EEE 51 Handout 5

vi1

vo2

vid

L. Alarcn, updated March 2, 2015

vod

+
+

vi2

vo1

Figure 5.1: A fully-dierential voltage amplifier.

Dierential Circuits

The circuits we have covered so far have input and output small signal voltages that are referenced to (or referred
to) the small signal ground. These circuits are called single-ended circuits. In certain cases, we want to amplify
the dierence between two signals. Circuits that operate on the dierence between two signals are called dierential
circuits. In this section, we will look at the reasons why one would choose dierential circuits over single-ended circuits,
and the costs associated with using these dierential circuits.

5.1

Dierential Signals and Gain Definitions

Consider two voltages referred to ground, v1 and v2 . If these two voltages are independent, then any change in v1
will not aect v2 . We can say that v1 and v2 are orthogonal to each other. Thus, in order to completely describe this
system of two independent voltages, we need specify both v1 and v2 .
Just like changing coordinate axes, we can use a dierent set of orthogonal quantities to describe these two voltages.
One such set of quantities is the the dierential voltage, vd , and the common-mode voltage, vc , defined as
vd = v1

(5.1)

v2

v1 + v2
(5.2)
2
Note that vd and vc are also orthogonal with respect to each other, since we can change the dierence between v1 and
v2 a , while maintaining their average, and vice-versa. From Eqs. 5.1 and 5.2, we can also get the inverse relationships
vc =

v1 = vc +

vd
2

(5.3)

vd
(5.4)
2
Consider a fully-dierential voltage amplifier, given in Fig. 5.1. A fully-dierential amplifier amplifies the dierential input voltage, and produces a dierential output voltage. However, since we have four quantities, we can define
four distinct voltage gains.
The voltage gain between the dierential input voltage to the dierential output voltage is called the dierentialmode gain, and is defined as
v2 = vc

Adm =

vod
vid

vo1
vi1

vo2
vi2

(5.5)

1
2 (vo1
1
2 (vi1

+ vo2 )
+ vi2 )

(5.6)

=
vic =0

We can also define the common-mode gain as

Acm =

voc
vic

=
vid =0

It is also possible for an amplifier to convert the input dierential voltage into a common-mode output voltage. Thus,
the dierential-mode to common-mode gain is
Adm

cm

voc
vid

(5.7)
vic =0

and the gain from the common-mode input voltage to the dierential-mode output voltage is defined as
Acm

dm

vod
vic

(5.8)
vid =0

Thus, the total dierential output voltage can be expressed as

a In

some texts, v1 and v2 are also referred to as v + and v , such that vd = v +

and vc =

1
2

v+ + v

Voltage [V]

Voltage [V]

EEE 51 Handout 5

0
v1
v2

L. Alarcn, updated March 2, 2015

0
v1
v2

vd
vc

2
0

vd

10

vc

2
15

10

Time

Time

(a) Ideal

(b) In the presence of common-mode noise

15

Figure 5.2: Dierential vs. single-ended signals.

vod = Adm vid + Acm

dm

vic

(5.9)

voc = Acm vic + Adm

cm

vid

(5.10)

and the total common-mode output voltage is

Why would we want to use dierential signals (voltage or current) instead of single-ended signals? Consider the
case when v1 = A cos (!t) + B and v2 = A cos (!t + 180 ) + B. We can express the dierential voltage vd as
vd = v1
and the common-mode voltage is

v2 = A cos (!t) + B

( A cos (!t) + B) = 2A cos (!t)

(5.11)

v1 + v2
A cos (!t) + B + ( A cos (!t) + B)
=
=B
(5.12)
2
2
Fig. 5.2a shows the plot of v1 , v2 , vd , and vc for A = 1 V, and B = 1 V.
Now consider the case when some random noise voltage gets coupled into the two voltages, v1 and v2 , such that
vc =

v10 = v1 + vnoise

(5.13)

v20 = v2 + vnoise

(5.14)

We can still calculate the dierential and common-mode voltages as

vd0 = v10

v20 = v1 + vnoise

v2

vnoise = v1

v2 = 2A cos (!t)

(5.15)

v10 + v20
v1 + vnoise + v2 + vnoise
=
= B + vnoise
(5.16)
2
2
Notice that as long as any noise or interference appears on both v1 and v2 , it is not seen in the dierential voltage,
vd0 ! All signals that are common to both v1 and v2 will appear as part of the common-mode signal, vc0 , as seen in
Fig. 5.2b. Thus, a dierential amplifier that only amplifies the dierential signal, and rejects the common-mode will
be immune to this common-mode noise or interference. One metric of how well an amplifier amplifies the dierential
signal and at the same time rejects the common-mode signal is the common-mode rejection ratio, defined as
vc0 =

CMRR =

Adm
Acm

(5.17)

Another advantage of using dierential amplifiers is the inherent generation of both the inverting and non-inverting
output. If an inverting amplifier is needed, one can simply re-label the output terminals of the amplifier in Fig. 5.1,
such that vo1 becomes vo2 and vice versa.

EEE 51 Handout 5

VCC

VCC

RL

RL
vo1

iC1
vi1

vo2

iC2

Q1

L. Alarcn, updated March 2, 2015

Q2
x

vBE1

vi2

vBE2
Itail

Figure 5.3: The BJT dierential pair.

5.2

The BJT Dierential Pair

How do we build dierential circuits? One very important dierential circuit building block is the BJT dierential pair
(or the emitter-coupled pair) with a resistor load, shown in Fig. 5.3. In order to understand how the BJT dierential
pair works, let us first look at its large-signal characteristics.
If we write the KVL equation around the input loop that includes the base terminals of both transistors, we get
Vi1

VBE1 + VBE2

(5.18)

Vi2 = 0

Assuming that Q1 and Q2 are identical,

Vi1

Vi2 = Vid = VBE1

VBE2 = VT ln

Rearranging Eq. 5.19, we get

IC1
IS

Vid

Writing the KCL equation at node x,

IC1 = IC2 e VT

VT ln

IC2
IS

= VT ln

IC1
IC2

(5.19)

(5.20)

IC1 + IC2
(5.21)

Using Eqs. 5.20 and 5.21, we can get expressions for the collector currents of both transistors in terms of the input
dierential voltage as
Itail = IE1 + IE2 =

IC1 =

Itail
1+e

Vid
VT

Itail

(5.22)

(5.23)
V
+ id
1 + e VT
Based on Eqs. 5.22 and 5.23, the behavior of the collector currents as the input dierential voltage is varied is shown
in Fig. 5.4a.
When we increase the input dierential voltage, Vid , we increase IC1 . But since the tail current source ensures that
the sum of the two collector currents are constant, and equal to Itail , any increase in IC1 will force IC2 to decrease by
exactly the same amount. Also note that even if Vi1 and Vi2 varies, as long as they are equal, i.e. Vid = 0, both IC1
and IC2 will always be equal to Itail
2 .
Thus, even if the common-mode input voltage changes, for two perfectly matched transistors with an ideal tail
current source, (1) the two collector currents will only be influenced by the input dierential voltage, and (2) the
collector currents will change in a purely dierential manner, meaning that if IC1 increases by I, or IC1 = Itail
2 + I,
Itail
then IC2 = Itail
I,
and
the
common-mode
current
of
will
not
change.
2
2
IC2 =

EEE 51 Handout 5

BJT Differential Amplifier

Differential Output Voltage

0.8

0.5
Vod [V]

Collector Currents [mA]

BJT Differential Pair

Collector Currents

0.6
0.4
0.2

IC1

IC2

0.5

0
Vid [V]

0
0.5
1
0.5

0.5

0
Vid [V]

(a) Collector currents

0.5

(b) Output voltage

Figure 5.4: BJT dierential pair large signal characteristics for

5.2.1

L. Alarcn, updated March 2, 2015

= 200, Itail = 1 mA, and RL = 1 k.

The BJT Dierential Amplifier

The collector currents are then converted to an output voltage by the two load resistors. Thus, the dierential pair
composed of the Q1 , Q2 and the tail current, when loaded with RL , can be considered a rudimentary fully dierential
amplifier. The output voltages are then
Vo1 = VCC

RL IC1

(5.24)

Vo2 = VCC

RL IC2

(5.25)

Solving for the dierential output voltage, Vod , we get

Vod = Vo1

Vo2 = RL (IC2

(5.26)

IC1 )

Combining Eqs. 5.22, 5.23, and 5.26, we get

1

Vid
2 VT

(5.27)
V
Vid
+ id
1 + e VT
1 + e VT
Eq. 5.27 is then the large signal dierential transfer characteristic of the BJT dierential amplifier since it relates the
dierential output voltage, Vod , and the dierential input voltage, Vid , and is plotted in Fig. 5.4b.
The maximum output dierential voltage we can get out of the BJT dierential amplifier is equal to
Vod = Itail RL

= Itail RL tanh

Vod,max = Itail RL

(5.28)

This is the dierential output when |Vid | is large enough such that all the tail current is flowing only on one side of
the dierential circuit.
5.2.2

The Common-Mode Signal Revisited

In order to simplify some of the analysis, but without loosing generality, we can assume that the input signals going
into our dierential amplifiers are of the form
vi1 =

V
cos (!t) + Vcm
2

vi2 =

V
cos (!t) + Vcm
2

(5.29)
(5.30)

resulting in
vid = vi1
vic =

vi2 = V cos (!t)

vi1 + vi2
= Vcm
2
4

(5.31)
(5.32)

EEE 51 Handout 5

L. Alarcn, updated March 2, 2015

Thus, we can think of the common-mode input as a DC oset where, on top of which, we add our dierential signal.
Notice that vi1 and vi2 are purely dierential signals since if vi1 increases by V , vi2 will decrease by the same amount,
relative to the common-mode voltage Vcm .
5.2.3

The Common-Mode Input Range

Note that Eqs. 5.19, 5.20, 5.22, 5.23, and 5.27 assume the transistor is operating in the forward-active region. In order
to check the BJT operating region, we need to get the collector-emitter voltage. From Fig. 5.3, we see that
VCE1 = VCC

IC1 RL

(5.33)

VX

where VX is the voltage across the tail current source. Note that for a collector current, IC1 , we get

IC1
VBE1 = VT ln
IS

(5.34)

Therefore, we can express VX as

VX = VI1

(5.35)

VBE1

Thus, combining Eqs. 5.33 and 5.35, we get

VCE1 = VCC

IC1 RL

VI1 + VT ln

VCE2 = VCC

IC2 RL

VI2 + VT ln

and similarly

For the case when there is no dierential input,

IC1
IS

(5.36)

IC2
IS

(5.37)

vi1 = VI1 = vi2 = VI2 = vic = Vcm

(5.38)

This implies that

Itail
(5.39)
2
since the left and right side of the dierential amplifier is the same, the tail current splits equally between these two
sides. Thus, Eq. 5.36 becomes

Itail RL
Itail
VCE1 = VCC
Vcm + VT ln
> VCE,sat
(5.40)
2
2 IS
IC1 = IC2 =

It is very important to note that as long as the transistors are in the forward-active region, the amplifier can
accept a range of common-mode input voltages, and still have IC1 = IC2 = Itail
2 . As the common-mode input voltage
is changed, the collector currents will remain the same, as enforced by the tail current source. Since the collector
currents remain the same, the base-emitter voltages will also remain the same. Thus, as the common-mode input
voltage increases, the voltage at node x will increase with itb .
Using Eq. 5.40, we can then calculate the maximum common-mode input voltage as

Itail RL
Itail
Vcm < VCC
VCE,sat + VT ln
= Vcm,max
(5.41)
2
2 IS

If the tail current source is not ideal and has a required minimum voltage, Vmin , then using Eq. 5.35, the minimum
common-mode input voltage can then be expressed as

Itail
Vcm > Vmin + VT ln
= Vcm,min
(5.42)
2 IS

Eqs. 5.41 and 5.42 defines the common-mode input range of the dierential amplifier in Fig. 5.3. The common-mode
input range is defined as the range of common-mode inputs that the amplifier can tolerate and still maintain proper
transistor operating regions.
Unlike single-ended amplifiers and circuits, where the input DC voltages can drastically change transistor bias
currents, dierential amplifiers have the advantage of being able to tolerate a relatively large range of input DC
voltages, while maintaining transistor bias currents.
b Readers will recognize that the path from v
i1 to node x is a common-collector or emitter-follower path, and it should be no surprise
that node x will try to follow vi1 .

EEE 51 Handout 5

VDD

VDD

RL

RL
vo1

iD1
vi1

vo2

M1

L. Alarcn, updated March 2, 2015

iD2
M2

vGS1

vi2

vGS2
Itail

Figure 5.5: The MOSFET dierential pair.

5.3

The MOSFET Dierential Amplifier

We can use MOSFETs to build dierential amplifier, as seen in Fig. 5.5. Once again, we can write the KVL equation
for the input loop as

Vid =

VT H +

Vi1

Vi2 = Vid = VGS1

VGS2

ID1
k

VT H +

ID2
k

(5.43)
r

ID1
k

ID2
k

(5.44)

and again applying KCL at node x, we get

Itail = ID1 + ID2

(5.45)

Using Eqs. 5.44 and 5.45 to solve for the drain currents, we get
r
Itail
k
2 Itail
Itail
ID1 =
+ Vid
Vid2 =
+ I
(5.46)
2
2
k
2
r
Itail
k
2 Itail
Itail
ID2 =
Vid
Vid2 =
I
(5.47)
2
2
k
2
Note that for Eqs. 5.46 and 5.47, ID1,max = ID2,max = Itail and ID1,min = ID2,min = 0, as dictated by the tail current
source. However, increasing or decreasing Vid in Eqs. 5.46 and 5.47 can result in currents larger than the maximum
or currents below the minimum current. This means that at a certain dierential input voltage, one transistor will
cut-o, while the other will carry all of Itail . This condition occurs when
r
Itail
k
2 Itail
2
I=
= Vid,max
Vid,max
(5.48)
2
2
k
Solving for Vid,max , we get
r
Itail
Vid,max =
(5.49)
k
Thus, as long as |Vid | Vid,max , Eqs. 5.46 and 5.47 are valid. However, if the input dierential voltage is outside this
range, then for Vid > 0, ID1 = Itail and ID2 = 0, and for Vid < 0, ID1 = 0 and ID2 = Itail , as seen in Fig. 5.6a.
The dierential output voltage is then
r
2 Itail
Vod = Vo1 Vo2 = RL (ID2 ID1 ) = RL k Vid
Vid2
(5.50)
k
Using Eqs. 5.49 and 5.50, we can calculate the maximum value of the dierential output voltage as
r
2 Itail
2
Vod,max = RL k Vid,max
Vid,max
= RL Itail
(5.51)
k
6

EEE 51 Handout 5

MOS Differential Amplifier

Differential Output Voltage

0.8

0.5
Vod [V]

Drain Currents [mA]

MOS Differential Pair

Drain Currents

0.6
0.4
0.2

ID1

ID2

0.5

L. Alarcn, updated March 2, 2015

0
Vid [V]

0
0.5
1
0.5

0.5

(a) Drain currents

0
Vid [V]

0.5

(b) Output voltage

Figure 5.6: MOSFET dierential pair large signal characteristics with VT H = 1 V, k = 100 mA
V2 , using RL = 1 k, a
tail current of 1 mA, and a supply voltage of 5 V.
which is expected since the maximum dierential voltage appears when all the current is already on one side of the
dierential pair, resulting in zero current on the other side, as seen in Fig. 5.6b.
5.3.1

Common-Mode Input Range

The drain-source voltage of transistor M1 can be expressed as

VDS1 = VDD

ID1 RL

(5.52)

VX

We can then express VX as

VX = VI1

(5.53)

VGS1

Thus, to prevent M1 from going into the linear region,

VDS1 = VDD

ID1 RL

VI1 + VGS1 > VGS1

VT H

(5.54)

If we set the dierential input to zero and apply only the common-mode input, VI1 = VI2 = Vcm , we get
VDD

Itail RL
2

Vcm >

VT H

(5.55)

Therefore,
Itail RL
+ VT H = Vcm,max
(5.56)
2
The common-mode input must also be large enough to support the minimum voltage requirement, Vmin , of the tail
current source, thus
Vcm < VDD

VX = Vcm

VGS1 > Vmin

(5.57)

(5.58)

Thus,
Vcm > Vmin + VGS1 = Vmin + VT H +

5.4

Itail
= Vcm,min
2k

Small Signal Analysis

After obtaining the quiescent DC currents of the simple dierential amplifier, we can now determine the corresponding
small signal two-port characteristics. The small signal equivalent circuit of the BJT dierential amplifier in Fig. 5.3
is shown in Fig. 5.7.
Let us analyze the small signal behavior of the dierential amplifier in two steps. First, we will look at the amplifiers
response to purely dierential signals, then we will look at the response to purely common-mode signals. Since the
small signal equivalent circuit is linear, we can get the total behavior of the dierential amplifier by superposition.
7

EEE 51 Handout 5

RL
vi1

RL
vo1

+
r

vbe1

gm vbe1

L. Alarcn, updated March 2, 2015

vo2

ro

vi2

+
ro

gm vbe2

vbe2

vx
ix1

ix2
Rtail

Figure 5.7: The small signal equivalent circuit of the BJT dierential amplifier in Fig. 5.3.
5.4.1

The Dierential Half Circuit

If we only have purely dierential signals, then this means that for an input dierential voltage, vid ,
vi1 = +

vid
2

(5.59)

vi2 =

vid
2

(5.60)

such that
vid = vi1

vi2

(5.61)

vi1 + vi2
=0
(5.62)
2
Eqs. 5.59 and 5.60 mathematically models the fact that if the inputs are purely dierential inputs, then a small change
in vi1 would be accompanied by the same change in vi2 but in the opposite direction.
Writing out the KVL expression for the input loop, we get
v
v
id
i2
vi1 vbe1 + vbe2 vi2 = +
vbe1 + vbe2
=0
(5.63)
2
2
thus,
vid = vi1 vi2 = vbe1 vbe2
(5.64)
vic =

Note that vx is the midpoint between + v2id and v2id . Thus, for any purely dierential input, vid , and if the left and
right sides of the circuit are perfectly matched, then we will always get
(5.65)

vx = 0

Since vx is always zero for purely dierential inputs, then node x can be considered a virtual ground node. Therefore,
we can redraw the small signal equivalent circuit in Fig. 5.7, and obtain the dierential small signal equivalent circuit
in Fig. 5.8.
By making node x a virtual ground, we have eectively decoupled the left and right sides of the dierential small
signal equivalent circuit. Thus, we can solve for the dierential small signal two-port parameters using either the left
or right side of the circuit in Fig. 5.8.
Using the left half circuit, we can calculate the dierential mode gain as
Adm =

+ v2od
vod
=
vid =
+ 2
vid

gm (ro k RL )

(5.66)

If we apply a test voltage, + v2id , at the input, we get

iid =

+ v2id
r

(5.67)

EEE 51 Handout 5

RL
+ v2id

L. Alarcn, updated March 2, 2015

RL

+ v2od

vod
2

vid
2

+
r

vbe1

+
gm vbe1

ro

ro

gm vbe2

vbe2

vx = 0
ix1

ix2

Figure 5.8: The dierential small signal equivalent circuit of the amplifier in Fig. 5.3.
Thus, the input resistance can be expressed as
Rid =

vid
= 2 r
iid

(5.68)

Similarly, if we zero out the input, and apply a test voltage, + v2od , at the output, we get
+ v2od
ro k R L

(5.69)

vod
= 2 (ro k RL )
iod

(5.70)

iod =
The output resistance is then
Rod =

We would get exactly the same expressions if we used the right half circuit of Fig. 5.8.
It is important to node that while we can consider node x as a virtual ground, no small signal current flows from
node x to the small signal ground. Instead, all the current going into node x from the left half circuit is exactly the
same current going out of node x into the right half circuit. Thus,
ix1 =

ix2

(5.71)

This is consistent with purely dierential mode inputs, since any small signal increase in voltage or current on the
left side would correspond to a decrease of equal magnitude on the right side. This is true for the open circuit from
node x to ground in Fig. 5.7, but it is also true even if we add any resistance to ground (e.g. if we use a tail current
source with finite output resistance, Rtail ), since vx = 0.
5.4.2

The Common-Mode Half Circuit

If we only apply a purely common-mode input, vic , such that

vic = vi1 = vi2

(5.72)

the dierential input component will be

vid = vi1

vi2 = 0

(5.73)

So if the left side of the dierential amplifier is perfectly matched to the right side, then the output dierential voltage
will also be zero, hence
vo1 = vo2 = voc

(5.74)

This also means that there will be no current flowing from the left side to the right side (or vice versa) since every
single node on the left side will have the same voltage as the corresponding node on the right, thus
ix1 = ix2 = 0

(5.75)

Extending this idea to the whole circuit, any connection from the left side and the right side would have zero
current, isolating the left side from the right. This allows us to calculate the common-mode small signal parameters
using only one side of the circuit in Fig. 5.7.
To solve for the common-mode gain, we first write out the KCL equation at node x,

EEE 51 Handout 5

RL
vi1

RL
vo1

+
r

vbe1

gm vbe1

L. Alarcn, updated March 2, 2015

vo2

ro

vi2

+
ro

gm vbe2

vbe2

vx
ix1

ix2

2Rtail

2Rtail

Figure 5.9: The common-mode small signal equivalent circuit of the BJT dierential amplifier in Fig. 5.3.

vx

vic
r

vx

voc
ro

gm (vic

vx ) = 0

(5.76)

and recognizing the that the current passing through r is the same current passing through RL , we get
voc
vic vx
=
RL
r

(5.77)

Using Eqs. 5.76 and 5.77, we can then express voc as

voc = vic

RL
RL + ro + r (1 + gm ro )

(5.78)

Thus, the small signal common-mode gain is

Acm =
Assuming thatgm ro

1 and ro

voc
RL
=
vic
RL + ro + r (1 + gm ro )

(5.79)

RL

r g m ro

(5.80)

RL , we get
Acm

RL
RL

0
ro
g m g m ro

If the tail current source is not ideal, but instead has an output resistance Rtail , breaks the even symmetry of the
small signal model, making it hard to distinguish the left side of the circuit in Fig. 5.8 from the right side. To restore
even symmetry, we can decompose Rtail into two parallel resistors, each with resistance value 2Rtail , as shown in Fig.
5.9. Since we have even symmetry once again, and ix1 = ix2 = 0, then we can solve for the common-mode gain using
only either the left or right half circuit.
If we take the left half circuit, and recognizing that this is exactly the same as the equivalent circuit of an emitter
degenerated common-emitter amplifier, with RE = 2Rtail , then the common-mode gain can be expressed as
Acm =

g m RL
1 + 2 gm Rtail

(5.81)

Note that since the common-mode source has to supply the input currents of both the left and right half circuits,
the common-mode input resistance is half that of the input resistance of the common-emitter amplifier with emitter
degeneration. Thus,
Ric =

vic
vic
r (1 + 2 gm Rtail )
=
=
iic,lef t + iic,right
2iic
2

(5.82)

As expected, the output resistance will also be half of the emitter-degenerated amplifier output resistance since for
the same output test voltage, we get twice the output current, one for each half circuit. Thus,
Roc =

voc
voc
ro (1 + 2 gm Rtail )
=
=
ioc,lef t + ioc,right
2ioc
2

10

(5.83)

EEE 51 Handout 5

iod

+
+

vid Rid

Roc

iic
vod

Adm vid

ioc

+
vic

+
+

Rod

iid

L. Alarcn, updated March 2, 2015

Ric

(a) Dierential-mode

voc

Acm vic

(b) Common-mode

Figure 5.10: The small signal model of the BJT dierential amplifier.
v1

1:1

+ v2d

vi1

vid

vod

vic

vi2
balun

vd

+ v2d

vc

vo2

+ v2d

voc

vo1
balun

1:1

+ v2d

v2

(a) Dierential signal conversion

(b) Equivalent circuit

Figure 5.11: The balun.

In summary, dierential amplifiers process the dierential- and common-mode signals dierently. We can then
think of dierential amplifiers as two distinct amplifiers, one processing the dierential-mode signal, and the other,
manipulating the common-mode input, as shown in Fig. 5.10.
Note that the small signal analysis for MOSFET dierential amplifiers is exactly the same as the analysis of its
BJT counterpart. The only dierence would be the expressions used to determine the transistor small signal two-port
parameters, leading to r ! 1.

5.5

The Balun

In many situations, it is necessary to convert single-ended signals into dierential signals, and vice versa. For example,
the dierential component of the input could be generated separately from the common-mode DC input component,
also known as an unbalanced pair. From the unbalanced pair, we want to generate balanced two wires whose
dierence contains the dierential information, and whose average contains the common-mode information. Fig.
5.11a shows a system that uses a balanced-unbalanced converter, or a balun, to convert from the (vd , vc ) coordinate
system to the (v1 , v2 ) coordinate system an vice-versa.
Fig. 5.11b shows a very simple balun implementation using two ideal transformers. Note that the circuit in Fig.
5.11b is bidirectional. Given vd and vc , it generates v1 and v2 , realizing Eqs. 5.3 and 5.4, and if given v1 and v2 , the
balun generates vd and vc , as described in Eqs. 5.1 and 5.2.

5.6

Dierential to Single-Ended Conversion

In some cases, the circuits driven by our amplifiers can only accept single-ended signals referred to ground. We still
however, want to be able to transfer the dierential output signal to the load circuit. Simply connecting one dierential
output to ground is normally not a good idea since the output node usually has some non-zero DC output level.
Dierential input, single-ended output amplifiers, whose symbol is shown in Fig. 5.12a, are a class of amplifiers
that allows us to drive single-ended loads. A relatively straightforward implementation of such an amplifier, seen in
Fig. 5.12b, simply takes one side of the dierential amplifier output, as the terminal used to drive the single-ended
load.
Using our dierential half circuit analysis, we get

11

EEE 51 Handout 5

L. Alarcn, updated March 2, 2015

VCC

VCC

RL

RL

iC1
vi1
+

vi1

Q1

Q2
x

vBE1

vo

vid

iC2

vo

vi2

vBE2
Itail

vi2

(a) Symbol

(b) A simple implementation

Figure 5.12: A single-ended output dierential input amplifier.

VCC

VCC

iin

IIN
VOU T + vout
IOU T + iout

Q2

Q1

Figure 5.13: The simple BJT current mirror with small signal input current, iin .

vo =

gm (ro k RL )

The gain is then

Av =

v
id
2

vo
gm (ro k RL )
=
vid
2

(5.84)

(5.85)

As expected, the single-ended gain is only half the fully dierential gain, since we are only using one half of the
dierential amplifiers capacity. This method of driving single-ended loads, however, is not very ecient, since we are
not only getting half the gain of a common-emitter amplifier, but also comsuming twice the current for the same gm .
An alternative way to generate a single-ended signal from a fully dierential amplifier is through the use of current
mirrors.
5.6.1

The Current Mirror Revisited

Before we use current mirrors for dierential-to-single-ended signal conversion, we need another look at their small
signal behavior. If we add a small signal current, iin , on top of the DC current, IIN , at the input of our current mirror,
as shown in Fig. 5.13, how much of that would make it to the output?
We can easily derive the small signal equivalent circuit of the current mirror, as seen in Fig. 5.14 . Assuming
g m ro
1 and that and ro are relatively large, calculating the base-emitter voltage of both transistors, we get

1
iin
vbe1 = vbe2 = iin
k ro2 k r1 k r2
(5.86)
gm2
gm2
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EEE 51 Handout 5

+
iin ro2

gm2 vbe2

L. Alarcn, updated March 2, 2015

vbe2

r2 r1

iout
gm1 vbe1

vbe1

ro1

+
vout

Figure 5.14: Small signal quivalent of the circuit in Fig. 5.13.

VCC

VCC

Q3

Q4

iC1

iC2

vi1

Q1

vo

vi2

Q2
x
Itail

Figure 5.15: Dierential to single-ended conversion using current mirrors.

Thus, if we assume that IC1 IC2 , then the small signal output current is
gm1
iin iin
gm2

iout gm1 vbe1 =

(5.87)

This very simple analysis shows that the current mirror is not only a mirror for DC input currents, but is also a
mirror for small signal input currents. We will use this property to make our dierential-to-single-ended conversion
more ecient in terms of gain.
5.6.2

Current Mirror Loads

Fig. 5.15 shows a dierential amplifier, but instead of resistors, the load is a PNP current mirror, where the output,
vo , is a single-ended signal.
Since the amplifier in Fig. 5.15 no longer exhibits any symmetry, we cannot apply our half circuit analysis
techniques, and we will need to perform the analysis on the whole small signal equivalent circuit, shown in Fig. 5.16.
If we once again assume that gm ro
1, and that and ro are relatively large, we can simplify the small signal
equivalent circuit in Fig. 5.16, as shown in Fig. 5.17. For purely dierential inputs, node x will still be at virtual
ground, and vbe1 = + v2id and vbe2 = v2id . Note that
vbe3 =

gm1

vid
1

= vbe4
2 gm3

(5.88)

By shorting the output to ground, no current will pass through ro2 and ro4 , thus we can calculate the eective
transconductance of the amplifier by first calculating the output short circuit current, io , as
io = gm4 vbe4 + gm2 vbe2 =

gm4 gm1

vid
1

2 gm3

vid
2

(5.89)

If gm1 = gm2 = gm and gm3 = gm4 , we will get

io =
Thus, the eective circuit transconductance is

gm vid

Gm =

13

gm

(5.90)

(5.91)

EEE 51 Handout 5

ro3

gm3 vbe3

r3

vbe3

r4

vbe4

L. Alarcn, updated March 2, 2015

gm4 vbe4

ro4

vo
vi1

+
r1

vi2

+
gm1 vbe1

vbe1

ro1

ro2

gm2 vbe2

vbe2

r2

vx
ix1

ix2
Rtail

Figure 5.16: The small signal equivalent circuit of the amplifier in Fig. 5.15.

1
gm3

gm4 vbe4

vbe3 =vbe4

ro4

vo
+ v2id

+
r1

vbe1

vid
2

+
gm1 vbe1

ro2

gm2 vbe2

vbe2

r2

vx
ix1

ix2

Figure 5.17: Simplified dierential small signal equivalent of the circuit in Fig. 5.16.

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EEE 51 Handout 5

L. Alarcn, updated March 2, 2015

If we zero out the input, then by inspecting the circuit in Fig. 5.17, we can see that all the dependent current sources
will be turned o (zero current), thus the output resistance is
Ro = (ro2 k ro4 )

(5.92)

The overall gain from the dierential input to the single-ended output is
Av =

vo
=
vid

Gm Ro = gm (ro2 k ro4 )

(5.93)

We can easily see that with the current mirror load, we will be able to achieve the same gain as the fully dierential
amplifier. Note that by using a current mirror as the dierential amplifier load allows us to redirect the small signal
current of the left half circuit to the output, where it combines constructively with the current generated by the right
half circuit.

15