SPI2016 Tutorial Slides

Introduction to Power Integrity
SPI 2016
by Steve Sandler - Picotest CEO
Steve@picotest.com - +1-480-375-0075
and
Heidi Barnes – Keysight Technologies
heidi_barnes@keysight.com +1-707-577-2110
POWER INTEGRITY BASICS IN 3.5 HOURS
Electronics are increasingly more sensitive to the quality of power, while also placing
greater demands on the power system design. Lower voltages, higher currents, and
faster speeds all drive challenges.
What you’ll gain today…

• An understanding of what power integrity is and the “Rules of Engagement”
• The four main components of a power distribution system
• How power related ‘noise’ degrades system performance and what to do about it
• Why flat PDN impedance is important and how to achieve it
• Introduction to Power Integrity measurements and simulation
MORE INTERACTIVE = MORE GAIN!
Copyright © 2016 Picotest.com, All Rights Reserved 2

And Just a Bit About Steve
• 38 Years Experience (1977-present)
• AEi Systems – Founder and CTO (1995-)
• Picotest – Founder and Managing Director (2010-)
Experience: Space Shuttle, Space Station, GPS, Large Hadron

Collider and many other military and commercial projects
Primarily focused on RF, Analog, and Distributed Power Systems
I enjoy writing lecturing lab time and making pizza

And Just a Bit About Heidi
• 30 Years Experience (1986-present)
High Speed Digital
RF/uW Packaging
Sensors and Instrumentation
• BS EE California Institute of Technology, 1986

• 2012 –Present
Keysight EEsof EDA Tools
Signal Integrity and Power Integrity
I enjoy writing simulating measuring and all forms of H20

WHAT IS POWER INTEGRITY?
This is not just about keeping voltages within limits!!!

Perspective – Ultra-Low Noise Oscillator
http://www.ko4bb.com/~bruce/CrystalOscillators.h
tml
Ultra-Low Phase Noise Crystal Oscillator without the power supply
Courtesy http://www.ko4bb.com/~bruce/CrystalOscillators.html

And With the Power Related Stuff
Ripple stripper
Noise averaging
Amp bias with voltage bias with
4 stages of noise
reduction
3 filtering stages
Current reg
There’s much more
for reduced
modulation
circuitry dedicated
to the power and
bias than to the
oscillator!
Power / bias
Oscillator
Courtesy http://www.ko4bb.com/~bruce/CrystalOscillators.html

A Simple Power Distribution Network (PDN)
INPUT FILTER REGULATOR PCB CAPACITORS
INPUT DECOUPLING
EMI FILTER VRM PLANES / CABLES r LOAD
POWER CAPACITORS
SIMPLE POWER SYSTEM
IT’S ALL ABOUT THE LOAD

AND CONTINUING INTO THE LOAD
BOND MORE ICs /
DEVICES
WIRES
CAPS PINS MORE ICs /
DEVICES
PERFORMANCE
DIE
MORE ICs /
IC / DEVICE BJT DEVICES
LOAD
PI is about delivering the APPROPRIATE power
quality here.

So What Are the Fundamental “Noise” Paths?
Input Single Power Distribution Path
Feedthru Load induced (∆I∙ ∆Z)
Filter Planes/Traces Regulator Planes/Traces Load

LNA
Z VRM Z VCO
interconnect interconnect
ADC
INPUT FPGA
CPU
Filter MEMORY
Related
USB3
Internal ripple and/or
Turn−on overshoot is a frequently
noise including DC
overlooked noise signal

The PDN Seen as a Series of Networks
Passive Network Active Network Passive Network
1 2 3 4 5 6
Planes/Traces
Filter Planes/Traces Load
INPUT Z
LNA
Z
VRM interconnect
VCO
Vref
interconnect
ADC
FPGA
CPU
MEMORY
Vref is a dominant noise source, USB3
though it is not generally accessible
Low noise is obtained by:

• Minimizing interaction between network ports [2,3] and [4,5]
• Maximizing isolation between network ports [1,2], [3,4] and [5,6]
• Minimizing self generated noise within each network

The VRM is the Foundation
Freq
ShutterStock footage by Paul Herron

The VRM is Also a Noise Hub
Active Network
[4,3] = PSRR (power supply rejection ratio)
3 4
[3,3] = Input Impedance (can be negative!)
[4,4] = Output Impedance (R-L network)
[3,4] = Reverse Transfer
VRM
[Vref,4] = Turn on Overshoot and Noise Path Vref
The VRM also generates internal noise. The VRM is an ACTIVE

This can be comprised of switching network, meaning that it
ripple, spike noise, modulation noise, has a feedback loop, which
shot and flicker noise, etc. is important to consider.

All of the Noise Paths are Related
Reverse Transfer - (S12) Output Impedance - (S22)
Iin/Iout
Port 1 VRM Port 2
Iin Iout
Vin
IN OUT Vout
RTN
Output Noise/Spikes
PSRR - (S21)
Input Impedance - (S11)

Input impedance can be NEGATIVE!
Power Supply
Rejection Ratio

All Are Related to Impedance
The degree of peaking for the plots on the left look

greater due to the different y-axis scaling used

If All are Related, Why Choose Impedance?
Modern circuits are DENSE… ..and continuously shrinking
6 Output 2013 eGaN
Power Supply 2014 LDO
8.5mm
12mm2
8.5mm More Power Supplies

72mm2
AND, as we said, all
The output capacitor is one place that performance paths are
is almost always available to measure related to impedance
(miniscule though it may be)

The PDN Highway
VRM Planes
Loads

Impedance is Combinations of Rs, Ls, and Cs
L C
R R

These Can be Active or Passive Elements
There is little difference in the impact of active and passive elements other than where to
go to improve performance.
Voltage regulators usually

result in active inductors
𝑅𝑜 + 𝑅𝑗
𝐿=
𝑎 𝐺+2
Ro = Bulk regulator resistance

Rj = Dynamic regulator resistance
a = Control loop pole
G = DC control loop gain
And conversely, current regulators (and electronic loads) usually result in active capacitors

Source = Interconnect = Load
VRM – Simply Defined PDN
𝐿 This is why RF instruments are 50Ω
Load 𝑍𝑜 = =1 source, 50Ω cable, and 50Ω load
𝐶
FLAT
𝑅1 = 𝑅2 = 𝑍𝑜
𝑍𝑜
𝑄=
𝑅1 + 𝑅2
What happens when they DON’T match?
And what does that have to do with PI?

When They Don’t Match
2Ω MAX 2Ω MAX
.01Ω Source and 2Ω LOAD
1Ω Source and 1Ω LOAD
1Ω MAX
1.99Ω Source and .01Ω LOAD

Adding Parasitic Inductance and Decoupling
4.5Ω MAX
2Ω MAX
1Ω MAX
1Ω Source and 1Ω LOAD

1.99Ω Source and 0.01Ω LOAD
0.01Ω Source and 1.99Ω LOAD

Really Simple Demonstration
TR1/Ohm
10 4
Load 10 3
Open
10 2 Match
10 1 Short
10 0
105 106 107
f/Hz
OPEN : |Mag(Impedance)|
VRM MATCH : |Mag(Impedance)|
SHORT : |Mag(Impedance)|
1m 50Ω COAX cable

A Simple ADS-PCB Demonstration
50Ω PCB trace 10 5
1
f/Hz TR1/Ohm 1
Load
10 4 Cursor 1 10.065M 2.694 𝜔C 709.7
TR1/Ohm
VRTS3
Training 10 3 Open
Demo 10 2 Match
Board 2.7
10 1 Short
10 0
10 -1 𝜔𝐿
10 -2
105 106 107
f/Hz
microstrip Quick Tip: |Mag(Impedance)|
OPEN
MATCH : |Mag(Impedance)|
1
SHORT : |Mag(Impedance)| 𝐿
𝑍𝑜 = 709.7 ∗ 2.7 ∙ 𝜔𝐿 = = 43.8Ω
𝜔C 𝐶
VRM

Simulation Tricks The PCB Layout
Simulations in the frequency domain are very fast:
Results can be expressed in S, Y, or Z values Distributed Models: Electrical Delay and Parasitics
Transmission Line
Algorithmic Model
or Z = V when AC stimulus is 1 Amp
S-Parameter
Behavioral Model
EM Simulated
Copyright © 2016 Keysight Technologies, All Rights Reserved 25

L/C Parallel Resonance Problem in the PDN Design
𝑓𝑟𝑒𝑠𝑜𝑛𝑎𝑛𝑐𝑒
70.79 kHz
126 m𝛺
𝐿 50𝑛𝐻
𝑍𝑜 = = = 22.4𝑚Ω
𝐶 100𝑢𝐹
𝑄=
𝑍𝑜 22.4𝑚Ω
= = 5.6
𝑍𝑝𝑒𝑎𝑘 = 𝑍𝑜 ∙ 𝑄 = 125𝑚Ω
𝑅 4𝑚Ω
𝑓≅
1
≅
1
≅ 71𝑘𝐻𝑧
ΔV=ΔI∙Zpeak=250mVpp
2𝜋 𝐿𝐶 2𝜋 50𝑛𝐻 ∙ 100𝑢𝐹

L-C Series Resonance Problem with Capacitors
Impedance Curve Series C-R-L Impedance vs. Frequency
 1 
Capacitor Z  ESRcap   j  ESLcap  j 
Model   C 
Voltage and current are in phase at fcap
1
f cap 
2 ESLcap  C
phase of I phase of V
Damping factor (D) expresses the leads V leads I
sharpness of the transition from C to L.
Higher D =slower phase change at f0
1 ESR cap C f cap

D  V in phase with I
2Q 2 ESLcap
(Pure resistance)

Adding a Decoupling Capacitor at the Load
10 5
TR1/Ohm
10 4
10 3
10 2
10 1
10 0
10 -1
10 -2 Load
105 106 107
f/Hz Load
OPEN 15nF : |Mag(Impedance)|
This is the “R” for frequencies above
21MHz. The “L” above 21MHz is the
MATCH 15nF : |Mag(Impedance)|
ESL of the decoupling capacitor PLUS
SHORT 15nF : |Mag(Impedance)|
PCB and interconnect inductance

An Actual Circuit Clock and buffer
The Picotest VRTS3

training board includes an 10nF cap
example with a VRM
connected to a clock.
Added PCB
Several output capacitor inductance
choices are available to
highlight the impedance
issues.
output caps

Harmonic Comb Example
Injecting the Harmonic Comb signal at the Clock
capacitor shown earlier reveals the impedance
resonance
Clock and buffer Sensitivities identified by interrogating with the comb
10nF cap

Focus on the Load NOT the VRM
In this example, a 7MHz resonance
in the PDN shows up as clock jitter.
Reducing the VRM impedance

increases jitter at 7MHz.
Trace resonance at 10nF cap
High ESR
VRM stability
Low ESR

with multiple impedance resonances with flat impedance
Multiple resonances can

accumulate into a rogue wave
How to Design for Power Integrity:

Finding Power Delivery Noise Problems
The same transient load step stimulus
Resulted in these very different voltage
www.youtube.com/watch?v=oL6qjhJH_m4&list=P
Ltq84kH8xZ9HIYgBYDsP7TbqBpftidzI8&index=6
transients…

Determining the Target Impedance
There are many sources of noise and
noise sources are additive
∞ ∞
𝟒
∆𝑰𝒇 ∙ 𝒁𝒇 ≈ ∆𝑽 − 𝑽𝒏 100uV 50kHz noise=23dB degradation
𝝅
𝒇=𝟎 𝒏=𝟎
The total noise budget for this FPGA is 30mVpk
Oscillators, sensors, ADC’s and DAC’s

are often sensitive to uVs of noise

Measuring

Reasons We Make Measurements
• To obtain unavailable data
• Because the manufacturer’s data is erroneous or lacks
sufficient detail
• To compare devices or topologies
• To troubleshoot non-functional or under performing
hardware
• To validate or verify design performance (as in ATP)
• To obtain statistics regarding tolerances

Recipe for a High Fidelity Measurement
 Correct instrument/Domain
 Correct probe and connections
 Correct measurement method and technique
 Correct measurement frequency range
 Correct calibration
And KNOW what you expect to see!

Relating Bandwidth and Rise Time
0.34966 0.34966
𝐵𝑊(𝑇𝑟𝑖𝑠𝑒10 ) = 𝑇𝑟𝑖𝑠𝑒10 (𝐵𝑊) =
90 𝑇𝑟𝑖𝑠𝑒10 90 𝐵𝑊
90
This is true for all single order systems (1-pole)

which includes many oscilloscopes
Though some oscilloscopes stretch this slightly

higher – up to 0.4/Trise
The bandwidth of most instruments is only a

few percent greater than the specified
bandwidth in order to minimize noise

Cascading Rise Times
Direct connection
P2101 Probe
Tr=34.79ps
Tr=276.94ps
𝑛 𝑇𝑟𝑖𝑠𝑒𝑝𝑟𝑜𝑏𝑒 = 276.94𝑝𝑠 2 − 34.79𝑝𝑠 2 = 275.75𝑝𝑠

𝑇𝑟𝑖𝑠𝑒 = 2
𝑇𝑟𝑖𝑠𝑒 = 2
𝑇𝑟𝑖𝑠𝑒 + 𝑇 2
𝑟𝑖𝑠𝑒 + 𝑇 2
𝑟𝑖𝑠𝑒
0.35
𝑛 𝑠𝑖𝑔𝑛𝑎𝑙 𝑠𝑐𝑜𝑝𝑒 𝑝𝑟𝑜𝑏𝑒 𝐵𝑊𝑝𝑟𝑜𝑏𝑒 = = 1.27𝐺𝐻𝑧
𝑖=1 275.75𝑝𝑠

Probes - Voltage
• This simple circuit is the basic Reference
Plane
representation of a voltage probe
• The circuit impedance interacts with the
probe impedance and can result in
undesirable responses
• The probe loading impedance forms a
divider with the circuit impedance and
probe interconnects

Probes - Voltage
• This comparison shows the transient
response to a fast step using ¼ inch leads
(blue) and a 3.5 inch ground clip (red)
• A series resistor can also be used to damp the
probe ringing
• The addition of the damping resistor flattens
the response and eliminates the ringing
• The simulated AC response is shown in the
figure with and without a 91Ω series resistor
using ¼ inch leads (blue) and a 3.5 inch
ground clip (red)

Selecting a Voltage Probe
• In order to minimize the interaction between the probe and the circuit:
1. The probe’s loading impedance should be greater than sum of the circuit impedance
2. The probe connection impedance should be up to at least the minimum acceptable
measurement bandwidth
• The probe impedance needs to be 4x-10x

the circuit impedance
• Often a 50 Ohm unity gain probe is the
best choice

1 Port and 2 Port Transmission Line Probes
• Can be used to assess impedance, stability, PDN, and circuit sensitivity to the power supply
• Each port is precisely 50Ω to match the cable and instrument up to more than 1GHz
• Unity gain probes offer the best SNR
• Bidirectional – sends stimulus and or receives stimulus

Choosing the Right Probe

Linear vs. Log Scales

Bode Plots
• The open loop Bode plot of the AD820 opamp shows a gain margin of 4dB and a phase
margin of 28.889 degrees, which matches the GM and PM derived using the Nyquist plot
• The phase shift falls below 0 degrees indicating at least one more pole
• The stability margin can’t be determined from the Bode plot
https://www.picotest.com/blog/wp
-content/uploads/2016/01/Killing-
the-Bode-Plot-Final.pdf

Nyquist Plot and Stability Margin
• The gain margin is assessed as the length
along the horizontal axis between the
unstable point and the loop gain curve
• The phase margin is assessed as the

angle formed by the horizontal axis and
the unity gain length connection from
(0,0) to the loop gain curve
• The stability margin (0.3066) is less stable than

either the GM (0.371) or PM (0.500)

Measuring Low ESR Capacitors Touchstone Impedance file
# Hz Z RI R 50
[Number of Ports] 1
[Number Of Frequencies] 201
Polymer [Network Data]
!freq ReZ11 ImZ11
Capacitor 1000.00
1047.128548
0.121123
0.111947
-1.537176
-1.468758
1096.478196 0.104285 -1.403602
1148.153621 0.097308 -1.341032
1202.264435 0.090883 -1.280776
1258.925412 0.085359 -1.224046
Export 1318.256739 0.079624 -1.169881
1380.384265 0.075118 -1.117441
1445.439771 0.070178 -1.067565
1513.561248 0.066014 -1.020212
PICOTEST KEYSIGHT 1584.893192 0.061078 -0.974788
1659.586907 0.058686 -0.930364
J2160A ENA5061B
DUT
Measured
Model

Measuring Impedance
Method is chosen primarily by impedance magnitude
Impedance (Ohms)
APPROXIMATE Measurement Ranges
 1-port reflection 0.5Ω-2.5kΩ

 2-port shunt thru 250uΩ-25Ω *
1-port
 2-port series thru 25Ω-1MΩ VNA
 3-port voltage/current 1mΩ-2kΩ
3-port 2-port
 Impedance adapters 0.1 Ω-400kΩ
FRA VNA*
Most Power Integrity Measurements
*Shunt Thru
use the 2-port shunt thru method

Freq (Hz)
* Later we’ll show how to extend this range

1-Port Reflect vs 2-Port Shunt Through
2-Port Shunt is a 4-wire sensing method that increases sensitivity
Current Density at 1MHz

220uF Aluminum Polymer
𝑆21
Port 1 𝑍𝑠ℎ𝑢𝑛𝑡 = 25 ∙
1 − 𝑆21
Injects
Current
1-port reflection
2-port shunt thru Port 2

Measures
Voltage

Connecting low frequency DC Blocks at the VNA input
2-Port Impedance isolates the 50 Ohm instrument loading from the circuit
J2130A or P2130A
Measurement 2-Port
1 2
Gnd
Probe
𝑆21 J2102A
𝑍𝐷𝑈𝑇 = 25 ∙
1 − 𝑆21
DC Blockers
Common Mode
Coaxial Transformer
-- Ground Loops
In some cases, a 2-port
probe can be used,
1mΩ measurement with and without simplifying the
connections and getting
coaxial transformer into small spaces

Separating PCB Mounting L from CESL
MEASURED
Shorting the Capacitor Pads to Simulate/Measure the PCB Mounting Inductance
0805 Mounting Inductance
IMPEDANCE (OHMS)
PCB EM MODEL + TUNED C-L-R MODEL LPCB_0805 = 548 pH Current Density at 10 MHz
IDEAL 2-PORT SHUNT THROUGH Lshort = 362pH
FREQUENCY (Hz)

2-Port Extended Range 𝑍𝐷𝑈𝑇(𝑚𝑖𝑛) =
𝑅𝑆 2 + 100 ∙ 𝑅𝑆 + 2500
2 ∙ 𝑅𝑆 − 5 ∙ 107
Impedance Measurement 9.6 ∙ 108 ∙ 𝑅𝑆 + 4.8 ∙ 1010

𝑍𝐷𝑈𝑇(𝑚𝑎𝑥) =
𝑅𝑆 + 8 ∙ 107
0.1uF with RS=200Ω

RS=200Ω can measure approximately 1mΩ to 4kΩ
(50 + 𝑅𝑆) 𝑆21
𝑍= ∙
2 1 − 𝑆21

NISM – Non-Invasive Stability Measurement
12
101
-10
Impedance reflects the stability
-20
100
margin (and so do all other
TR1/dB
TR2
-30 10-1 closed loop measurements)
-40 10-2
TPS40222 Buck Regulator
-50
10-3
102 103 104 105 106
f/Hz 150
1 2
60 TR1: Mag(Gain) TR2: |QTg(Gain)|
100
40
50
20
TR1/dB
TR2/°
0
A 5-V Input, 1.6-A Output, Non-Synchronous
0
Buck Converter
-20 -50
-40 -100
http://www.ti.com/lit/ug/slvu153/slvu153.pdf
-60
-150
102 103 104 105 106
f/Hz
TR1: Mag(Gain) TR2: Unwrapped Phase(Gain)

Power Supply Noise Density and Instrument Noise Floor
Noise Density
𝑁𝑜𝑖𝑠𝑒 = 𝑁𝑜𝑖𝑠𝑒_𝐷𝑒𝑛𝑠𝑖𝑡𝑦 ∙ 𝑅𝐵𝑊
Noise amplitude measurement using an Measuring noise density directly
oscilloscope spectrum option and various
Resolution Bandwidth (RBW)
dBmV Volts BW V/SQRT(BW)

-31.97 2.52E-05 4577.6 3.73E-07
-22.03 7.92E-05 36621.1 4.14E-07
-41.16 8.75E-06 572.2 3.66E-07
Noise density measurement
-46.04 4.99E-06 143.1 4.17E-07

-57.65 1.31E-06 8.9 4.39E-07 Measurement noise floor
-64.63 5.87E-07 2.2 3.96E-07
Average 4.01E-07

Clocks Make Great Noise Meters
Achieving the optimum performance from
the load is dependent getting the power Higher linear reg
right at the load. This often means the best impedance yields
measurements should be made in the system Higher mid-band
noise Linear
The noise at the load is regulator
generally computed as PCB resonance
𝑛𝑜𝑖𝑠𝑒𝑖2
𝑖=1
Switching POL has spurs
But lower impedance is
But noise sources can be Better in mid-band
directly additive

Power Supply Sensitivity
Modulating a clock to determine power supply sensitivity
Signal Generator
100uV 50kHz noise=23dB degradation

23dB
40dB attenuator Line Injector
Oscillators, sensors, ADC’s and DAC’s

Clock output are often sensitive to uV’s of noise
Clock power supply To E5052B
Measurement port

Reading the Impedance Measurement
Actual Computer Server Motherboard
Flat=resistor
Rising=inductor
Falling=capacitor

And Reconstructing It For Simulation
The flatness could be greatly
improved by increasing the
decoupling capacitance while
slightly increasing the ESR
36uF 2mΩ
VRM/Bulk Cap Decoupling
90uF 3mΩ

Designing a Flat Impedance VRM (and PDN)

Designing the Flat Impedance VRM
Using a current mode switching
Choose a controller with an external compensation pin VRM allows Rout to be easily set
by the the DC error amp gain
Not easy to control DC resistance

Pole often unknown in an LDO
Series resistor is often required
Output capacitance
and ESR are critical
Comp R1, R2 and PGfs set Rout

Power stage Gfs (PGfs)
is often unknown 𝑅1
𝑅𝑜𝑢𝑡 =
Internal pole and slope compensation set effective inductance 𝑅2 ∙ 𝑃𝐺𝑓𝑠

Four Step Design Process to Flat Impedance
Noise Budget = DC regulation + Ripple + IRdrop +
1. Create a noise budget Startup Overshoot/Step load excursion + Noise
2. Set impedance level using noise (rail voltage
deviation) budget
3. Set the VRM output resistance equal to the
desired impedance level (tolerances!)
4. At each node, cancel excess inductance with a
capacitor. Capacitor ESR must be equal to the
desired impedance
𝐿
𝐶= 2
Quick Tips 𝑍𝑑𝑒𝑠𝑖𝑟𝑒𝑑
• Minimizing inductance reduces capacitor size
• Higher bandwidth, locate regulator closer to the load, wide planes thinner PCB dielectric
• There’s a lot of variation in voltage regulators, choose wisely – lower output inductance wins
• Ferrite beads are VERY inductive and as a rule should be avoided like the plague
• Linear regulator inductance varies inversely with load current - assess at the lowest operating current

Vcomp (V)
1.761
1.771
Iout (A)
0.00
0.10
Determining Power Stage Transconductance
1.783 0.20
Measurements are often surprising. LM25116 Evaluation Board
1.796 0.30
1.807
1.818
0.40
0.50
Using a 10mΩ resistor should result in
1.830 0.60 PGfs of 10 and it does not … .
1.844 0.70
1.859 0.80
1.872 0.90
1.883 1.00
Power Stage Gfs
1.910 1.25 8.00
1.935 1.50
1.969 1.75 7.00 y = 8.7258x - 15.402
1.986 2.00
6.00 R² = 0.9995
LOAD CURRENT
2.016 2.24
2.052 2.50 5.00
2.087 2.75
2.119 3.00 4.00
Slope=PGfs
𝑷𝑮𝒇𝒔 can also be computed from
2.179 3.50
2.234 4.00 3.00
2.291
2.347
4.50
5.00
2.00 an Rout measurement
2.400 5.50 1.00 𝑅1
2.455 6.00
0.00 𝑃𝐺𝑓𝑠 =
2.564 7.00 𝑅2 ∙ 𝑅𝑜𝑢𝑡
2.616 7.50 1.700 1.900 2.100 2.300 2.500 2.700
2.649 7.80
2.660 7.90
VCOMP

Choosing the Output Capacitor
𝐿 Undersized output capacitor reveals the inductance
𝐶= resulting from the internal pole and slope compensation
2
𝑍𝑑𝑒𝑠𝑖𝑟𝑒𝑑 Cap ESL
The capacitor is chosen to match the +3dB=68kHz/35mΩ

desired impedance and to counteract the
inductor
𝟏
𝑪𝒐𝒖𝒕 = = 𝟕𝟐𝒖𝑭
𝟐𝝅(𝟔𝟖𝒌𝑯𝒛)(𝟑𝟓𝒎𝜴) Rout
𝑪𝒆𝒔𝒓 = 𝑹𝒐𝒖𝒕 = 𝟐𝟓𝐦𝜴

Cap ESR
Polymer capacitors tend to have flat
ESR vs. frequency which works best in
these applications

Case Study – Integrated Switch Step-Down
• A state space average model was constructed in
ADS from several measurements. LM20143
Rfeedback
• A number of potential output capacitors were
Demo Board
selected and measured then converted to Output
Touchstone files for co−simulation. cap
USB input
• Four capacitors were chosen to create 4 different
flat resistance VRMs
• Each of the 3 solutions was constructed and

measured. The TI LM20143 Evaluation board was
also measured.
• The measured impedance results were converted to

touchstone files using the BodeFile converter so that Load
they can be displayed along with the simulation
result Measurement ports

SIMULATED vs MEASURED
IMPEDANCE (OHMS) REFERENCE DESIGN
FREQUENCY (Hz)
SIMULATED vs MEASURED
IMPEDANCE (OHMS)
IMPROVED
DESIGN
9mΩ + 4.2nH
FREQUENCY (Hz)
VRM PDN Capacitors AC Sweep
Impedance Model for Z Flat Z at lower frequencies reduces
the package/ DUT anti-resonance
at higher frequencies!
IMPEDANCE (OHMS)
(OHMS)
Reference Design does VRM Impedance Package
not fit an R/L Model!
AC Sweep Decoupling
IMPEDANCE
VRM PDN Capacitors
Impedance Model for Z
R/L model assumes a FREQUENCY (Hz)

flat PDN design!

VRM PDN Capacitors AC Sweep
Impedance Model for Z
Many VRMs can be tuned for Flat Z.
So how do we choose the right one?
IMPEDANCE (OHMS)
IMPROVED DESIGN FREQUENCY (Hz)

State 1: SW1 = On and SW2= Off
Vc SW1 Cin RDS_SW1

Lout
Cin SW2
DCR_Lout
Cout
STATE SPACE AVERAGED MODEL

State 2: SW1 = Off and SW2= On
𝐷𝑢𝑡𝑦 = 𝑇𝑜𝑛_𝑆𝑊1 ∙ 𝐹𝑠𝑤 Lout
𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛 ∙ 𝐷𝑢𝑡𝑦 RDS_SW2

DCR_Lout
Cout
𝑉𝑐
𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛 ∙
𝑉𝑟𝑎𝑚𝑝

State 1: SW1 = On and SW2= Off
Vc SW1
Iout
Lout
Cin SW2 Cin
Cout
STATE SPACE AVERAGED MODEL

State 2: SW1 = Off and SW2= On
𝐷𝑢𝑡𝑦 = 𝑇𝑜𝑛_𝑆𝑊1 ∙ 𝐹𝑠𝑤 Lout
𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛 ∙ 𝐷𝑢𝑡𝑦 Iout Cout

𝑉𝑐
𝐼𝑜𝑢𝑡 = 𝑘
𝑅𝑖

Nominal Impedance is the same, Nominal PSRR is very different between
Voltage Mode is very sensitive to tolerances Current Mode and Voltage Mode
𝑅𝑖
𝑹𝒐𝒖𝒕_𝑪𝑴 = 𝑉𝑜 (𝑎𝑐)
1 + 𝐴𝑣 PSRR =
𝐷𝐶𝑅𝐿𝑜 + 𝑅𝐷𝑆𝑜𝑛𝑏𝑜𝑡 + 𝑅𝐷𝑆𝑜𝑛𝑡𝑜𝑝 − 𝑅𝐷𝑆𝑜𝑛𝑏𝑜𝑡 ∙
𝑉𝑜 𝑉𝑖𝑛 (𝑎𝑐)
𝑹𝒐𝒖𝒕_𝑽𝑴 = 𝑉𝑖𝑛
𝑉𝑖𝑛 Power Supply Rejection Ratio (PSRR)
1 + 𝐴𝑣 ∙
𝑉𝑟𝑎𝑚𝑝
IMPEDANCE (OHMS)
DCR_Lout +/- 45% Voltage Mode
PSRR (dB)
Voltage Mode Current Mode
Current Mode
FREQUENCY (Hz) FREQUENCY (Hz)

SERIES FEEDBACK SHUNT FEEDBACK
𝑅3 ∙ (𝐺𝑚 ∙ 𝑅2 − 1) 𝑅3 ∙ 𝐺𝑚 ∙ 𝑅2𝑠ℎ𝑢𝑛𝑡
𝐴𝑣_𝑠𝑒𝑟𝑖𝑒𝑠 = = 3.215 𝐴𝑣_𝑠ℎ𝑢𝑛𝑡 = = 3.215
𝑅1 + 𝑅3 + 𝐺𝑚 ∙ 𝑅1 ∙ 𝑅3 𝑅1 + 𝑅3
R2 R1 R2
R1
𝛿𝐴𝑣_𝑠ℎ𝑢𝑛𝑡
= 6.3 ∙ 103
𝛿𝐴𝑣_𝑠𝑒𝑟𝑖𝑒𝑠 𝛿𝐺𝑚
= 2.58 ∙ 103
𝛿𝐺𝑚
R3 R3 Gm
Gm
Error Amp Out (volts)

Gfs Error Amp

Min = 1.4 e-3
Nominal = 1.7 e-3
Max = 2.0 e-3
Frequency (Hz) Frequency (Hz) Gfs Error Amp

Voltage Mode with Shunt Feedback
Voltage Mode Series vs Shunt Voltage Mode Series vs Shunt

Error Amp Gain Slope (dB)
Output Impedance (Ohms)

SERIES
SHUNT
SHUNT
SERIES
FREQUENCY (Hz) FREQUENCY (Hz)

Monte Carlo Distribution of VRM Tolerances
Tolerance Distribution
DCR_Lo=30m 7%+0.4%/degC=50%
Transconductance Error Amplifier Gm=10%
Vin=10%
Vramp=10% (Gslope comp)
Lout=25%
Monte Carlo of Voltage Mode vs Current Mode
Output Impedance (ohms)

Cbulk_ESR=20% Output Impedance (ohms)
Cbulk_ESL=20% Voltage Mode Current Mode
Series Feedback Series Feedback
Frequency (Hz) Frequency (Hz)

Model + Measured Co-Simulation
Measurement Based State Space Averaged Model ... measured

capacitor impedance
+ =
Incredible Fidelity!

The Final Results
Undersized capacitor
reveals the effective
VRM inductance
SIMULATED
MEASURED
TI Evaluation Board
390uF/91K

Selecting the Decoupling Capacitors for Flat PDN
How to select the right de-coupling capacitors to
insure stable low noise performance at minimal cost.
Aluminum Bulk Cap only
1st Decoupling cap
1st and 2nd Decoupling cap
FLAT PDN = Guaranteed Stability

Is Target Impedance Really this Simple?
Target Impedance Calculation
( Power _ Supply _ Voltage)  ( Allowed _ Ripple)
Z Target 
Current
Example:
4A 3.3 V 2A
3.3 V Power Plane
VRM
V 
(3.3V )  (5%)
 82.5m
Z Target  Z Target(3.3V)
I 2A
“Target Impedance is the goal that designers should hit!!!”

Spectral Content of the Sink
Digital Switching Spectral Content
• Edge speeds determine the di/dt maximum for Ldi/dt Dynamic Switching Load Response
ripple voltage.
• I(t) waveform determines the spectral content, digital
patterns have a wide bandwidth (peaks at odd harmonics) ON
p
PRBS OFF n
OFF
p
SINE
ON n

Another Example: 1 Volt, 40 Amps
Equivalent Series Resistance (ESR) causes a voltage drop (droop) in the supply
when the Load draws power from the capacitors in the PDN.
Max ESR to prevent Supply Voltage Droop & Kick

Example Bulk C ESR
VSupply  ( PCTdroop  0.5) I Load  40 A
ESRmax_ripple  PCTtransient  100%
I Load  PCTtransient
VSupply  1V
ESRmax_ripple  estimated maximum parallel capacitor ESR in Ohms
PCTdroop  10%
I DUT  average DUT supplycurrent in Amps
PCTtransient  expected transient current as a percentage of I DUT
110  0.5
VSupply  supply voltage in Volts ESRmax_ripple   1.25 mΩ VLoad  VCap  ( I Load  ESRcap )
0.5  PCTdroop  amount of allowable supplydroop across the ESR cap 40 100
Note: ½ of Voltage Droop caused by ESR and ½ by Capacitor Discharging only valid for simple RC model!

How to Select the PDN Capacitors
Limited Bandwidth Requires Multiple Values Effective ESL is Limited by PCB Mounting
300pH
100nF 10nF
1.5nH
4.7uF 100pH
Paralleling ceramics is important for meeting target Z

A capacitor becomes an inductor above fcap,
so it is important to find ways to lower the
x1 Note: impedance at higher frequencies
x10 Parallel ceramics of the
same value have n x C, 1
x100 f cap 
ESL/n and ESR/n and 2 ESL  C
the fcap does not change

Not All Capacitors are Created Equal – Bulk Caps
*Datasheets specify a maximum so this table shows actual measured data for some of the capacitors.
For a given capacitor that meets Dmin, use them in parallel to achieve CTotal
and ESRmax for the ripple target of the Load.

Ceramic Decoupling Capacitors
PACKAGE ESL
External resistors can be used with standard 1206 ~ 1 nH
ceramic capacitors with slightly higher inductance
47uF 0805 ~ .6 nH
but much better selection and lower cost 0603 ~ .5 nH
0402 ~ .4 nH
47uF
10 -1
TR1
Ceramic + Rs
10 -2
Ceramic
Rs =10mΩ
104 105 106 107
f/Hz
47uF 6.3V 1206 : |Mag(Gain)|
47uF 6.3V 10m : |Mag(Gain)|
Convert measurement to Touchstone or RLC

Ceramic Decoupling Capacitors
ESR controlled ceramic
capacitors such as the
TDK’s YNA series can be
used or external resistance
can be used with standard
ceramic capacitors, though
with higher inductance

Tuning for Flat Z Requires Measured Models
R-L-C Lumped Model in

Blue
S-Parameter Measured
Model in Red
RLC model has difficulty

capturing the high
frequency characteristics.
Xilinx WP411 Jan. 30, 2012 Simulating Power Integrity Using S-Parameter Models

PCB Footprints for Ceramic vs Bulk Capacitors
Ceramic Caps
Lower ESL helps Bandwidth
Loop Inductance Bulk Tantalum and Electrolytic
+ - Via in Pad Via on Side
Lowest L Low L Higher ESL is Okay
Highest Density
C and ESR are
more important
then ESL
L 𝐿𝑠𝑙𝑜𝑝𝑒
𝐶= 2
𝑍𝑑𝑒𝑠𝑖𝑟𝑒𝑑
L increases
Bus Bar Design
with + and – Flexibility for adding different
via separation V1 V3
types of capacitors to tune the
Gnd PDN after assembly based on
V2 measured data.

Ceramic Capacitor Placement
Banks of different size and value caps around the
The Lplane of a buried capacitive layer
edge of the Package along with small caps placed
at the top of the board with topside
directly on the BGA vias provide the lowest
decoupling capacitors is lower then
inductance for high current applications.
Lvia for long PCB Board vias.
0805 / 1206 Designs have even

DUT Lplane
alternated the + and
0603 / 0402 – terminals of High
adjacent capacitors dK
0402 / 0201 Layer
to lower the
Inductance. Less Lvia Simple
mutual inductance. Design
Ideal
+ - Dual
Lvia
Top and
Bottom
- + Capacitors at the bottom

always have the inductance
of the Via in the path.

Example High Layer Count PCB for ATE
36 Layer PCB , 260 mils 3M ECM
High Dielectric
Ground Plane
Power Return Power Plane

Via Via
2.5 mil FR4
3M ECM
11 um

Start at the VRM to Design for Flat PDN
𝐿𝑠𝑙𝑜𝑝𝑒
𝐶= 2
DeCap1 DeCap2 𝑍𝑑𝑒𝑠𝑖𝑟𝑒𝑑
No DeCaps vs. With DeCaps
2
𝑍𝑑𝑒𝑠𝑖𝑟𝑒𝑑
𝐿𝑠𝑙𝑜𝑝𝑒

Co-Simulated Results With Decoupling Capacitors
The decoupling capacitors can be
converted to RLC models or the
Simulation with Touchstone Bulk
Touchstone files can be combined
capacitor only
directly in a mix and match
selection.
Here we are showing a large signal Touchstone measurement with

simulation combined with a Touchstone 47uF 10mΩ decoupling
Touchstone capacitor on one trace.
The measured Touchstone result is

then combined with touchstone
decoupling capacitors to see the Touchstone measurement with
flatness with and without the Touchstone 47uF without 10mΩ
external 10mΩ external resistor.

Advanced Topics
What is SI and PI Co-Simulation and why do I care about PCB EM Simulation?
Modern Applications
with Multiple PDNs
Xilinx Kintex VCU105 Board:
Power Planes
15 Major Power Distribution
Networks (PDN)
16 Layer PCB

SI with PI, PI with SI, and SI PI Co-Simulation
SI PI
SI and PI
It’s All About the Load – Target Z
Signal Integrity Drives PI Target Z
ADS SI Pro + Channel Simulation
SI simulation with injected noise
Max timing jitter and ripple calculation to set Target Z
Measure Supply Induced

• Amplitude Ripple
• Timing Jitter

The PI Eco-System VRM + PDN + Load
Kill the Rogue Waves with Flat Z
PI only Simulation with SI Requirements
ADS PI Pro + Transient Simulation
VRM – Control Loop Stability, Active Z
PDN – PCB and Capacitor Passive Parasitics

IR Drop, PDN Z, and Plane Resonances
Sink – Dynamic Broadband Load

PI Min/Max Ripple Includes DC IR Drop Tolerances
DC Simulation Result – Voltage Drop (Compliance)
With 5% Margin Voltage drop is passing

Power Net : VCC1v2_FPGA
Sink-1: Controller
Sink-1
VRM : MAX15303
Sink : 2-5

Additional EM - Field Data
AC Field Simulation Power Plane Cavity Resonances
Electric Field 100 MHz
Objective : Evaluates electromagnetic coupling between geometries to

improve component, via, and capacitor placement

PI Analysis Setup : Transient ( Dynamic IR Drop)
PDN impedance seen from the IC (U1)

The VRM provides 1.2 Volt, the IC pulls 0.8 A Ampere and a 5% tolerance on the supply voltage is allowed. That results in a target
impedance of 0.075 Ohm. We can look at what that implies in the time domain assuming the IC sink would draw current at a frequency
of respectively 10 and 100 MHz

PDN Transient Load Simulation - Dynamic IR Drop
10 MHz
Without Decaps With Decaps
Vcc + 5% Margin
Vcc - 5% Margin

What the Netlist Doesn’t Tell You –
PCB PDN Design
 Signal Net S-Parameters
 PDN Impedance
SI and PI Co-EM Simulation
 PCB Resonances
ADS SI Pro EM Simulation  PCB Coupling Power, Ground, Signal
SI Only Power Aware SI + PI

SI and PI Co-EM Simulation
Power and Signal Nets in

the same EM simulation
Write Channel scheme of DDR4 SI/PI co-simulation analysis
100
Copyright © 2015 Keysight Technologies, All Rights Reserved
SI and PI Co-EM Simulation: S-Parameters
Simulation with Decaps ( includes Power Plane)
Power Plane
Data Signals

SI and PI Co-Simulation with Power Aware Models
Power Aware SI Simulation Dynamic Load Response

Power Aware IBIS v5.0 Models
www.ibis.org
Example
• IBIS (Input/output Buffer Information Specification) models are behavioral using IBIS Model
I-V and V-t look-up tables that make simulations extremely fast.
• IBIS buffer macromodels are commonly applied for system-level SI simulations

instead of transistor-level netlists. Simulation time, memory consumption, and
convergence issues are all dramatically reduced versus transistor-level
simulation.
Micron EDY4016AABG-DR-F
• Power-Aware IBIS v5.0 models are used to represent the non ideal power
effects. There are two BIRDs related to the power awareness of the IBIS v5.0
models
- The first power aware BIRD is 95.6 : Power Integrity Analysis using IBIS
- The second power aware BIRD is 98.3. : Gate Modulation Effect

Power Aware IBIS SI Simulation : Approach-1
• SSN analysis with a separate EM simulations for the PDN model and the signal lines
• The only coupling between the PDN and the Signal lines is through the IBIS model, not the PCB layout.
PDN EM S-Parameter Model

PI-AC in PIPro
Power DQ Signals S-Parameter Model

Aware IBIS Power
Aware IBIS
PI- SI in SIPro
Copyright © 2016 Keysight Technologies, All Rights Reserved

104
Power Aware IBIS SI Simulation : Data Signal (DQ0) with
and without PDN impedance attached
SI Only Simulation ( no PDN effect) in simulation Power Aware SI Simulation with PDN effects in the simulation
0
Eye Diagram without the effect of the PDN Eye Diagram with PDN ( Power Aware SI)
Eye is more open

Power Aware IBIS with SI/PI Coupled EM Model : Approach-2
• Taking both Power Nets and Signal Nets in a single EM simulation.
EM Model with Power and Signal Nets

Power Power Nets
Aware IBIS
Power
Aware IBIS
Signal Net

Power Aware SI (Approach-2 ): Transient Test Bench Sim Result

Important to Lay the Groundwork for SI and PI Co-Simulation
- Start simple and build the complexity
ADS SI Pro + Channel Simulation What the Netlist ADS SI Pro EM Simulation
It is all about the Load Doesn’t Tell You!
SI only Simulation SI and PI Co-EM
with added PI Noise Simulation
Crosstalk
Flat PDN Deisgn ADS PI Pro + Transient Simulation Simulating the ADS PI Pro + SI Pro + Transient
Kills the Rogue Wave PDN Eco-System
PI only Simulation Power Aware
with SI Requirements IBIS SI and PI
Co-Simulation

Thanks for Sharing Your Time Today
Want to learn more
It was a pleasure speaking with you today. We hope you found this about Power Integrity?
tutorial session to be helpful and look forward to your feedback so that
we can continue to improve our lectures.
We’ll be answering questions and performing simulation demos at the

Keysight booth, so feel free to stop by.
Feel free to contact Steve at Steve@Picotest.com or

through LinkedIn and feel free to join the Picotest
LinkedIn Group - Power Integrity for Distributed Systems

Definitions
Power Integrity – The quality of the power delivered from the supply through the PDN to the loads
VRM – Voltage Regulator Module - Either a linear or switching regulator, supplies power to a system or load
PDN - Power Distribution Network - How power gets from VRMs to ICs
Resonance – A peak in the PDN impedance profile (impedance vs. frequency)
PSRR – Power Supply Rejection Ratio
Rogue Wave – Changes in the power required by the load are not DC, they occur in steps. Those steps can line up and
reinforce one another resulting in large voltage excursions on the line
ADS – Keysight’s (formerly Agilent) simulator
Noise Budget – The voltage deviation as determined by the needs of the loads (usually must be less than the absolute
maximum for the ICs being driven but other performance factors (e.g. frequency content) are important too). Noise Budget =
DC regulation + Ripple + IRdrop + Step load excursion/Startup Overshoot + Noise
Gfs – The ratio of the change in output current resulting from a change in input voltage
Reverse Transfer – The change in input current for a change in output current
VNA – Vector Network Analyzer, used for measuring impedances, s-parameters, gain/phase, Bode plots, non-invasive stability
NISM – Non-Invasive Stability Measurement, a method of determining the phase margin from an output impedance test
FRA – Frequency Response Analyzer, used for measuring gain/phase, Bode plots
BOL/ EOL – Beginning of Life/End of Life

ADS Simulation Workspaces
DesignCon 2016 Power Integrity Boot Camp with Hands-On ADS Labs
www.keysight.com\find\eesof-sipi-resources
Youtube Video: How to Design for Power Integrity: PDN Rogue Waves
www.keysight.com\find\eesof-how-to-pdn-roguewave
Youtube Video: How to Design for Power Integrity: Selecting a VRM

www.keysight.com\find\eesof-how-to-vrm

References
1. http://www.edn.com/design/pc-board/4429719/PCB-characteristics-affect-PDN-performance
2. http://www.edn.com/design/test-and-measurement/4413192/Target-impedance-based-solutions-for-
PDN-may-not-provide-a-realistic-assessment
3. http://www.edn.com/design/test-and-measurement/4433242/Match-impedances-when-making-
measurements
4. http://www.edn.com/design/power-management/4440087/3/Design-a-VRM-with-perfectly-flat-output-
impedance-in-5-seconds-or-less
5. http://www.edn.com/electronics-blogs/impedance-measurement-rescues/4439664/Rogue-waves-can-
ruin-your-power
6. http://www.edn.com/electronics-blogs/impedance-measurement-rescues/4438578/The-inductive-nature-
of-voltage-control-loops
7. http://powerelectronics.com/community/why-pdn-measured-using-vna-and-not-oscilloscope
8. http://electronicdesign.com/boards/how-measure-ultra-low-impedances
9. http://www.digikey.com/Web%20Export/Supplier%20Content/TDK_445/PDF/tdk-tech-report-esr-
control.pdf?redirected=1
10. http://www.cei.se/media/48264/cei%20europe%20course%2056.pdf
11. http://www.ece.gatech.edu/research/labs/hppdl/Epsilon2010/publications/2010/madhavan_emc.pdf
12. http://packetmicro.com/docs/Power_Integrity_Probing_with_Keysight_VNA.pdf
13. http://electronicdesign.com/boards/what-s-difference-between-signal-integrity-and-power-integrity

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Introduction to Power Integrity

What you’ll gain today…

MORE INTERACTIVE = MORE GAIN!

Copyright © 2016 Picotest.com, All Rights Reserved 2

Experience: Space Shuttle, Space Station, GPS, Large Hadron

I enjoy writing lecturing lab time and making pizza

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• BS EE California Institute of Technology, 1986

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This is not just about keeping voltages within limits!!!

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Ultra-Low Phase Noise Crystal Oscillator without the power supply

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INPUT FILTER REGULATOR PCB CAPACITORS

SIMPLE POWER SYSTEM

IT’S ALL ABOUT THE LOAD

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Filter Planes/Traces Regulator Planes/Traces Load

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Low noise is obtained by:

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ShutterStock footage by Paul Herron

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The VRM also generates internal noise. The VRM is an ACTIVE

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Input Impedance - (S11)

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The degree of peaking for the plots on the left look

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8.5mm More Power Supplies

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Voltage regulators usually

Ro = Bulk regulator resistance

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1.99Ω Source and .01Ω LOAD

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1Ω Source and 1Ω LOAD

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Simulations in the frequency domain are very fast:

or Z = V when AC stimulus is 1 Amp

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1 ESR cap C f cap

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The Picotest VRTS3

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Clock and buffer Sensitivities identified by interrogating with the comb

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Reducing the VRM impedance

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Multiple resonances can

How to Design for Power Integrity:

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The total noise budget for this FPGA is 30mVpk

Oscillators, sensors, ADC’s and DAC’s