Vlsidesign 120218133449 Phpapp02 PDF

VLSI DESIGN
Reference Material
By
Verilog Course Team
Where Technology and Creativity Meet
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Preface
The India Semiconductor Association (ISA), an Indian semiconductor
industry organization, has briefed growth, trends and forecasts for the Indian
semiconductor market in collaboration with a U.S. consulting company Frost
& Sullivan.
The report titled as "ISA-Frost & Sullivan 2007/2008 Indian Semiconductor
Market Update."
According to the report, total semiconductor consumption in India (total value
of semiconductors used for devices marketed in India) was $2.69 billion
(USD) in 2006. The $2.69 billion represents 1.09% of the global
semiconductor market. Of the total semiconductor consumption in India,
consumption by local Indian set manufacturers accounted for $1.26 billion.
The overall Indian semiconductor consumption will grow at an average rate of
26.7% per year in 2006 through 2009. Based on the actual consumption in
2006, the overall Indian semiconductor consumption is forecast to be $5.49
billion in 2009. This represents 1.62% of the global semiconductor market in
2009.
Semiconductor consumption by local Indian set manufacturers is predicted to
increase at 35.8% per year in 2006 through 2009 and amount to $3.18 billion
in 2009.
This material is the result of the Verilog Course Teams practical experience
both in Design/Verification and Training. Many of the examples illustrated
throughout the material are real designs models. With Verilog Course Teams
training experience has led to step by step presentation, which addresses
common mistakes and hard-to-understand concepts in a way that eases
learning.
Verilog Course Team invites suggestion and feedbacks from both students and
faculty community to improve the quality, content and presentation of the
material.
VLSI DESIGN
UNIT-I CMOS TECHNOLOGY
1. An overview of silicon semiconductor technology
1.1 The Fabrication of a Semiconductor Device
1.1.2 Wafer Fabrication
1.1.3 Assembly
1.2 Basic CMOS Technology
1.2.1 A Basic n-well CMOS Process
1.2.2 A Basic p-well CMOS Process
13
1.2.3 Twin-Tub (Twin-Well) CMOS Process
13
1.2.4 Silicon On Insulator (SOI) Process
14
1.3 INTERCONNECT
18
1.3.1 Metal Interconnect
18
1.3.2 Polysilicon/Refractory Metal Interconnect
19
1.3.3 Local Interconnect
20
1.4 CIRCUIT ELEMENTS
21
1.4.1 Resistors
21
1.4.2 Capacitors
21
1.4.3 Electrically Alterable ROMs
23
1.4.4 Bipolar Transistors
24
1.4.5 LatchUp
26
1.4.5.1 The Physical Origin of Latchup
26
1.4.5.2 Latchup Triggering
28
1.4.6 Latchup Prevention
29
1.5. LAYOUT DESIGN RULES
30
1.5.1 Layer Representations
31
1.5.2 CMOS n-well Rules
32
1.5.3 Scribe Line
34
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1.5.4 SOI Rules
34
1.5.5 Layer Assignments
35
1.6 PHYSICAL DEISGN
35
1.6.1 Basic Concept
35
1.6.2 CAD Tools sets
37
1.6.3 Physical Design-The Inverter
38
1.6.4 Physical Design-The NOR
38
1.6.5 Physical Design-The NAND
39
1.7 DESIGN STRATEGIES
39
1.7.1 Structured Design Strategies
40
1.7.2 Hierarchy
40
UNIT 2 MOS TRANSISTOR THEORY

2 .1 NMOS ENHANCEMENT TRANSISTOR
41
2.2 PMOS ENHANCEMENT TRANSISTOR
45
2.3 THRESHOLD VOLTAGE
45
2 . 3 . 1 Threshold Voltage Equations
46
2.4 BODY EFFECT
48
2.5 MOS Device Design Equations
48
2.5.1 Basic DC Equations
48
2.5.2 Second Order Effects
50
2.5.2.1 Threshold Voltage-Body Effect
51
2.5.2.2 Subthreshold Region
51
2.5.2.3 Channel-length Modulation
52
2.5.2.4 Mobility Variation
52
2.6 MOS MODELS
53
2.7 SMALL SIGNAL AC CHARACTERISTICS
54
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2.8THE COMPLEMENTARY CMOS INVERTER
DC CHARACTERISTICS
55
2.8.1 n/p ratio
61
2.8.2 Noise Margin
62
2.9 THE TRANSMISSION GATE
64
2.10 THE TRISTATE INVERTER
68
UNIT 3 SPECIFIFCATION OF VERILOG HDL

3. HISTORY OF VERILOG
69
3.1 BASIC CONCEPTS
69
3.1.1 Hardware Description Language
69
3.1.2 VERILOG Introduction
69
3.1.3 VERILOG Features
70
3.1.4 Design Flow
70
3.1.5 Design Hierarchies
73
3.1.5.1 Bottom up Design
73
3.1.5.2 Top-Down Design
74
3.1.6 Lexical Conventions
74
3.1.6.1 Whitespace
75
3.1.6.2 Comments
75
3.1.6.3 Identifiers and Keywords
76
3.1.6.4 Escaped Identifiers
76
3.1.7 Numbers in Verilog
76
3.1.7.1 Integer Numbers
77
3.1.7.2 Real Numbers
77
3.1.7.3 Signed and Unsigned Numbers
77
3.1.8 Strings
78
3.1.9 Data types
79
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3.1.9.1 Data Types Value set
79
3.1.9.2 Nets
79
3.1.9.3 Vectors
80
3.1.9.4 Integer, Real and Time Register Data Types
80
3.1.9.5 Arrays
81
3.1.9.6 Memories
82
3.1.9.7 Parameters
82
3.1.9.8 Strings
82
3.2 MODULES
83
3.2.1 Instances
84
3.3 PORTS
84
3.3.1 Port Declaration
85
3.3.2 Port Connection Rules
85
3.3.3 Ports Connection to External Signals
86
3.4 GATE DELAYS
87
3.4.1 Rise, Fall, and Turn-off Delays
87
3.4.2 Min/Typ/Max Values
88
3.5 MODELING CONCEPTS
89
3.6 SWITCH LEVEL MODELING
90
3.6.1 Switch level primitives
91
3.6.2 MOS switches
92
3.6.3 CMOS Switches
93
3.6.4 Bidirectional Switches
94
3.6.5Power and Ground
95
3.6.6 Resistive Switches
95
3.8 Delay Specification on Switches
96
3.8.1 MOS and CMOS switches
96
3.8.2 Bidirectional pass switches
97
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3.9 GATE LEVEL MODELING
101
3.9.1 Gate Types
101
3.10 BEHAVIORAL AND RTL MODELING
108
3.10.1 Operators
108
3.10.1.1 Arithmetic Operators
108
3.10.1.2 Relational Operators
109
3.10.1.3 Bit-wise Operators
110
3.10.1.4 Logical Operators
112
3.10.1.5 Reduction Operators
113
3.10.1.6 Shift Operators
114
3.10.1.7 Concatenation Operator
115
3.10.1.8 Replication Operator
116
3.10.1.9 Conditional Operator
116
3.10.1.10 Equality Operators
117
3.10.2 Operator Precedence
119
3.10.3 Timing controls
119
3.10.3.1 Delay-based timing control
119
3.10.3.2 Event based timing control
122
3.10.3.3 Level-Sensitive Timing Control
124
3.10.4 Procedural Blocks
124
3.10.5 Procedural Assignment Statements
125
3.10.6 Procedural Assignment Groups
126
3.10.7 Sequential Statement Groups
128
3.10.8 Parallel Statement Groups
128
3.10.9 Blocking and Nonblocking assignment
129
3.10.10 assign and deassign
130
3.10.11 force and release
131
3.10.12 Conditional Statements
131
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3.10.12.1 The Conditional Statement if-else
131
3.10.12.2 The Case Statement
132
3.10.12.3 The casez and casex statement
134
3.10.13 Looping Statements
136
3.10.13.1 The forever statement
136
3.10.13.2 The repeat statement
136
3.10.13.3 The while loop statement
137
3.10.13.4 The for loop statement
138
3.11 DATA FLOW MODELING AND RTL
139
3.11.1 Continuous Assignment Statements
139
3.11.2 Propagation Delay
141
3.12 STRUCTURAL GATE LEVEL DESCRIPTION
141
3.12.1 2 to 4 Decoder
141
3.12.2 Comparator
142
3.12.3 Priority Encoder
144
3.12.4 D-latch
144
3.12.5 D Flip Flop
145
3.12.6 Half adder
145
3.12.7 Full adder
146
3.12.8 Ripple Carry Adder
146
UNIT 4 CMOS CHIP DESIGN

4.1 INTRODUCTION TO CMOS
148
4.2 LOGIC DESIGN WITH CMOS
149
4.2.1 COMBITIONAL LOGIC
149
4.2.2 INVERTER
150
4.2.3 The NAND Gate
151
4.2.4 The NOR Gate
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152
VLSI DESIGN
4.3 TRANSMISSION GATES
153
4.3.1Multiplexers
153
4.3.2 Lathes
153
4.4 CMOS CHIP DESIGN OPTIONS
154
4.4.1 ASIC
154
4.4.2 Uses of ASICs
155
4.4.3 Full Custom ASICs
155
4.4.5 Semi-Custom ASICs
156
4.4.6 Standard- Cell-Based ASIC
156
4.4.7 Gate Array Asic
157
4.4.8 Channeled Gate Array
158
4.4.9 Channelless Gate Array
158
4.4.10 Structured Gate Array
159
4.5 PROGRAMMABLE LOGIC
159
4.5.1 Programmable Logic Structures
160
4.5.2 Programmable of PALs
161
4.5.3 Fusible Links
161
4.5.4 UV-erasable EPROM
161
4.5.5 EEPROM
161
4.5.6 Programmable Interconnect
162
4.6 ASIC DESIGN FLOW
163
UNIT-5 CMOS TEST METHODS

5.1 THE NEED FOR TESTING
165
5.1.1 Functionality Tests
166
5.2 MANUFACTURING TEST PRINCIPLS
166
5.2.1 FAULT MODELS
167
5.2.1.1 Stuck-At-Faults
167
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5.2.1.2 Short-Circuit and Open-Circuit Faults
168
5.2.2 Observability
170
5.2.3 Controllability
171
5.2.4 Fault Coverage
171
5.2.5 Automatic Test Pattern Generation (Atpg)
171
5.2.6 Fault Grading And Fault Simulation
177
5.2.7 Delay Fault Testing
178
5.2.8 Statistical Fault Analysis
179
5.2.9 Fault Sampling
180
5.3 DESIGN STRATEGIES FOR TEST
180
5.3.1 Design for Testability
180
5.3.2 Ad-Hoc Testing
181
5.3.3 Scan-Based Test Techniques
184
5.3.3.1 Level Sensitive Scan Design (LSSD)
185
5.3.3.2 Serial Scan
187
5.3.3.3 Partial Serial Scan
188
5.3.3.4 Parallel Scan
190
5.3.4 Self-Test Techniques
191
5.3.4.1 Signature Analysis and BILBO
191
5.3.4.2 Memory Self-Test
193
5.3.4.3 Iterative logic array testing
194
5.3.5 IDDQ testing
194
5.4 CHIP-LEVEL TEST TECHNIQUES
194
5.4.1 Regular Logic Array
194
5.4.2 Memories
195
5.4.3 Random Logic
196
5.5 SYSTEM-LEVEL TEST TECHNIQUES
196
5.5.1 Boundary Scan
196
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5.5.1.1 Introduction
196
5.5.1.2 The Test Access Port (TAP)
197
5.5.1.3 The Test Architecture
197
5.5.1.4 The TAP controller
198
5.5.1.5 The Instruction Register (IR)
198
5.5.1.6 Test-Data Registers
199
5.5.1.7 Boundary Scan Registers
199
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UNIT-I
An overview of silicon semiconductor technology
Silicon in its pure or intrinsic state is a semiconductor, having a bulk electrical
resistance somewhere between that of a conductor and an insulator. The
conductivity of silicon can be varied over several orders of magnitude by
introducing impurity atoms onto silicon crystal lattice. These dopants may either
supply free electrons or holes. Impurity elements that use electrons are referred to
as acceptors, since they accept some of the electrons already in the silicon,
leaving vacancies or holes. Similarly, donor elements provide electrons. Silicon
that contains a majority of donors is known as n-type and that which contains a
majority are brought together, the region where the silicon changes from n-type
and p-type materials are brought together, the region where the silicon changes
from n-type to p-type is called a junction. By arranging junctions in certain
physical structures and combining these with other physical structures, various
semiconductor devices may be constructed. Over the years, silicon semiconductor
processing has evolved sophisticated techniques for building these junctions and
other structures having special properties.
An integrated circuit is a small but sophisticated device implementing several
electronic functions. It is made up of two major parts: a tiny and very fragile
silicon chip (die) and a package which is intended to protect the internal silicon
chip and to provide users with a practical way of handling the component. The
various steps in manufacturing processes of transistor both in front-end and
back-end is taken as example, because it uses the MOS technology. Actually,
this technology is used for the majority of the ICs manufacturing companies.
1.1 The Fabrication of a Semiconductor Device
The manufacturing phase of an integrated circuit can be divided into two steps.
The first, wafer fabrication, is the extremely sophisticated and intricate process of
manufacturing the silicon chip. The second, assembly, is the highly precise and
automated process of packaging the die. Those two phases are commonly known
as Front-End and Backend. They include two test steps:
Wafer probing and Final test.
The flow chart is shown in figure 1.1.
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Figure 1.1 Manufacturing Flow Chart of an Integrated Circuit

1.1.2 Wafer Fabrication (Front-End)
Identical integrated circuits, called die, are made on each wafer in a multi-step
process. Each
step adds a new layer to the wafer or modifies the existing one. These layers form
the elements of the individual electronic circuits. The main steps for the
fabrication of a die are summarized in the following table. Some of them are
repeated several times at different stages of the process. The order given here
doesn't reflect the real order of fabrication process.
PhotoMasking
This step shapes the different components. The

principle is quite simple (see drawing on next page).
Resin is put down on the wafer which is then exposed
to light through a specific mask. The lighten part of
the resin softens and is rinsed off with solvents
(developing step).
Etching
This operation removes a thin film material. There are

two different methods: wet (using a liquid or soluble
compound) or dry (using a gaseous compound like
oxygen or chlorine).
Diffusion
This step is used to introduce dopants inside the

material or to grow a thin oxide layer onto the wafer.
Wafers are inserted into a high temperature furnace
(up to 1200 C) and doping gazes penetrate the
silicon or react with it to grow a silicon oxide layer.
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Ionic
Implantation
It allows to introduce a dopant at a given depth into

the material using a high energy electron beam.
Metal
Deposition
It allows the realization of electrical connections

between the different cells of the integrated circuit
and the outside. Two different methods are used to
deposit the metal: evaporation or sputtering.
Passivation
Wafers are sealed with a passivation layer to prevent

the device from contamination or moisture attack.
This layer is usually made of silicon nitride or a
silicon oxide composite.
Back-lap
Its the last step of wafer fabrication. Wafer thickness

is reduced (for microcontroller chips, thickness is
reduced from 650 to 380 microns), and sometimes a
thin gold layer is deposited on the back of the wafer.
Initially, the silicon chip forms part of a very thin (usually 650 microns), round
silicon slice: the raw wafer. Wafer diameters are typically 125, 150 or 200 mm (5,
6 or 8 inches). However raw pure silicon has a main electrical property: it is an
isolating material. So some of the features of silicon have to be altered, by means
of well controlled processes. This is obtained by "doping" the silicon.
Dopants (or doping atoms) are purposely inserted in the silicon lattice, hence
changing the features of the material in predefined areas: they are divided into
N and P categories representing the negative and positive carriers they hold.
Many different dopants are used to achieve these desired features: Phosphorous,
Arsenic (N type) and Boron (P type) are the most frequently used ones.
Semiconductors manufacturers purchase wafers predoped with N or P impurities
to an impurity level of.1 ppm (one doping atom per ten million atoms of silicon).
There are two ways to dope the silicon. The first one is to insert the wafer into a
furnace. Doping gases are then introduced which impregnate the silicon surface.
This is one part of the manufacturing process called diffusion (the other part being
the oxide growth). The second way to dope the silicon is called ionic
implantation. In this case, doping atoms are introduced inside the silicon using an
electron beam. Unlike diffusion, ionic implantation allows to put atoms at a given
depth inside the silicon and basically allows a better control of all the main
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parameters during the process. Ionic implantation process is simpler than

diffusion process but more costly (ionic implanters are very expensive machines).
Figure 1.2 Diffusion and Ionic Implantation Processes

PhotoMasking (or masking) is an operation that is repeated many times during
the process. This operation is described in figure 1.3. This step is called
photomasking because the wafer is masked in some areas (using a specific
pattern), in the same way one masks out or protects the windscreens of a car
before painting the body. But even if the process is somewhat similar to the
painting of a car body, in the case of a silicon chip the dimensions are measured
in tenth of microns. The photoresist will replicate this pattern on the wafer. The
exposed part of the photoresist is then rinsed off with a solvent (usually
hydrofluoric or phosphoric acid).
Figure 1.3 Photo Masking Process

Metal deposition is used to put down a metal layer on the wafer surface. There
are two ways to do that. The process shown in the figure 1.4, is called sputtering.
It consists first in creating a plasma with argon ions. These ions bump into the
target surface (composed of a metal, usually aluminium) and rip metal atoms from
the target. Then, atoms are projected in all the directions and most of them
condense on the substrate surface.
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Figure 1.4 Metal Deposition Process

Etching process is used to etch into a specific layer the circuit pattern that has
been defined during the photomasking process. Etching process usually occurs
after deposition of the layer that has to be etched. For instance, the poly gates of a
transistor are obtained by etching the poly layer. A second example is the
aluminium connections obtained after etching of the aluminum layer.
Figure 1.5 Etching Process

Photomasking, ionic implantation, diffusion, metal deposition, and etching
processes are repeated many times, using different materials and dopants at
different temperatures in order to achieve all the operations needed to produce the
requested characteristics of the silicon chip. The resolution limit (minimal line
size inside the circuit) of current technology is 0.35 microns. Achieving such
results requires very sophisticated processes as well as superior quality levels.
Backlap is the final step of wafer fabrication. The wafer thickness is reduced
from 650 microns to a minimum of 180 microns (for smartcard products).
Wafer fabrication takes place in an extremely clean environment, where air
cleanliness is one million times better than the air we normally breathe in a city,
or some orders of magnitude better than the air in a heart transplant operating
theatre. Photomasking, for example, takes place in rooms where theres maximum
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one particle whose diameter is superior to 0.5 micron (and doesnt exceed 1
micron) inside one cubic foot of air.
All these processes are part of the manufacturing phase of the chip itself. Silicon
chips are grouped on a silicon wafer (in the same way postage stamps are printed
on a single sheet of paper) before being separated from each other at the
beginning of the assembly phase.
Wafer Probing. This step takes place between wafer fabrication and assembly. It
verifies the functionality of the device performing thousands of electrical tests, by
means of special microprobes. Wafer probing is composed of two different tests:
1. Process parametric test: This test is performed on some test samples and
checks the wafer fabrication process itself.
2. Full wafer probing test: This test verifies the functionality of the finished
product and is performed on all the dies. The bad dies are automatically marked
with a black dot so they can be separated from good die after the wafer is cut. A
record of what went wrong with the non-working die is closely examined by
failure analysis engineers to determine where the problem occurred so that may be
corrected. The percentage of good die on an individual wafer is called its yield.
Figure 1.6 Description of the Wafer Probing Operation

1.1.3 Assembly (Back-End)
Figure 1.7
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The first step of assembly is to separate the silicon chips: this step is called die
cutting (figure 1.7). Then, the dies are placed on a lead frame: the leads are the
chip legs (which will be soldered or placed in a socket on a printed circuit board.
On a surface smaller than a baby's fingernail we now have thousands (or millions)
of electronic components, all of them interconnected and capable of implementing
a subset of a complex electronic function. At this stage the device is completely
functional, but it would be impossible to use it without some sort of supporting
system. Any scratch would alter its behavior (or impact its reliability), any shock
would cause failure. Therefore, the die must be put into a ceramic or plastic
package to be protected from the external world.
Figure 1.8 Description of The Assembly Process
Figure 1.9 Wire Bonding

Wires thinner than a human hair (for microcontrollers the typical value is 33
microns) are required to connect chips to the external world and enable electronic
signals to be fed through the chip. The process of connecting these thin wires
from the chips bond pads to the package lead is called wire bonding.
The chip is then mounted in a ceramic or plastic package. The package not only
protects the chip from external shocks, but also makes the whole device easier to
handle. These packages come in a variety of shapes and sizes depending on the
die itself and the application in which it will be used.
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Figure 1.10 Wire Bonding Operation

Products are then marked with a traceability code which is used by the
manufacturer and the user to identify the function of the device (and its date of
fabrication). At the end of the assembly process, the integrated circuit is tested by
automated test equipment. Only the integrated circuits that passed the tests will be
packed and shipped to their final destination.
Figure 1.11 Different Kinds of Plastic Packages

1.2 Basic CMOS Technology
Complementary metaloxidesemiconductor (CMOS) (pronounced "seemoss), is a major class of integrated circuits. CMOS technology is used in
microprocessors, microcontrollers, static RAM, and other digital logic circuits.
CMOS technology is also used for a wide variety of analog circuits such as image
sensors, data converters, and highly integrated transceivers for many types of
communication. Frank Wanlass got a patent on CMOS in 1967 (US Patent
3,356,858).
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CMOS is also sometimes referred to as complementary-symmetry metal

oxidesemiconductor. The words "complementary-symmetry" refer to the fact
that the typical digital design style with CMOS uses complementary and
symmetrical pairs of p-type and n-type metal oxide semiconductor field effect
transistors (MOSFETs) for logic functions.
Two important characteristics of CMOS devices are high noise immunity and low
static power consumption. Significant power is only drawn when the transistors in
the CMOS device are switching between on and off states. Consequently, CMOS
devices do not produce as much waste heat as other forms of logic, for example
transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices
without p-channel devices. CMOS also allows a high density of logic functions on
a chip.
The four main CMOS technologies are;
n-well process.
p-well process.
twin-tub process.
Silicon on insulator.
1.2.1 A Basic n-well CMOS Process
The basic process steps for pattern transfer through lithography, and having gone
through the fabrication procedure of a single n-type MOS transistor, the
generalized fabrication sequence of n-well CMOS integrated circuits, as shown in
figure. 1.12 In the following figures, some of the important process steps involved
in the fabrication of a CMOS inverter will be shown by a top view of the
lithographic masks and a cross-sectional view of the relevant areas. The n-well
CMOS process starts with a moderately doped (with impurity concentration
typically less than 1015 cm-3) p-type silicon substrate. Then, an initial oxide layer
is grown on the entire surface. The first lithographic mask defines the n-well
region. Donor atoms, usually phosphorus, are implanted through this window in
the oxide.
Figure 1.12
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Once the n-well is created, the active areas of the nMOS and pMOS transistors
can be defined. Figures 1.13 through 1.18 illustrate the significant milestones that
occur during the fabrication process of a CMOS inverter.
Following the creation of the n-well region, a thick field oxide is grown in the
areas surrounding the transistor active regions, and a thin gate oxide is grown on
top of the active regions. The thickness and the quality of the gate oxide are two
of the most critical fabrication parameters, since they strongly affect the
operational characteristics of the MOS transistor, as well as its long-term
reliability.
Polysilicon Gate Connections

Figure 1.13
The polysilicon layer is deposited using chemical vapor deposition (CVD) and
patterned by dry (plasma) etching. CVD Chemical Reactions
SiH4(gas) + O2(gas) SiO2(solid) + 2H2 (gas)

SiH4(gas) + H2(gas) +SiH2(gas) 2H2(gas) + PolySilicon (solid)
Figure 1.14
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Isolation layer
Figure 1.15
The created polysilicon lines will function as the gate electrodes of the nMOS and
the pMOS transistors and their interconnects. Also, the polysilicon gates act as
self-aligned masks for the source and drain implantations that follow this step.
Using a set of two masks, the n+ and p+ regions are implanted into the substrate
and into the n- well, respectively. Also, the ohmic contacts to the substrate and to
the n-well are implanted in this process step.
Figure 1.16
An insulating silicon dioxide layer is deposited over the entire wafer using CVD.
Then, the contacts are defined and etched away to expose the silicon or
polysilicon contact windows. These contact windows are necessary to complete
the circuit interconnections using the metal layer, which is patterned in the next
step.
Figure 1.17
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Metal (aluminum) is deposited over the entire chip surface using metal
evaporation, and the metal lines are patterned through etching.
Figure 1.18
Since the wafer surface is non-planar, the quality and the integrity of the metal
lines created in this step are very critical and are ultimately essential for circuit
reliability. The composite layout and the resulting cross-sectional view of the
chip, showing one nMOS and one pMOS transistor (built-in n-well), the
polysilicon and metal interconnections. The final step is to deposit the passivation
layer (for protection) over the chip, except for wire-bonding pad areas. The
patterning process by the use of a succession of masks and process steps is
conceptually summarized in Figure. 1.19. It is seen that a series of masking steps
must be sequentially performed for the desired patterns to be created on the wafer
surface. An example of the end result of this sequence is shown as a cross-section
on the right.
Figure 1.19
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1.2.2 A Basic p-well CMOS Process

N-well processes have emerged in popularity in recent years. Prior to this p-well
process was one of the most commonly available forms of CMOS. Typical p-well
fabrication steps are similar to an n-well process, except that a p-well is
implemented rather than an n-well. The first masking step defines the p-well
regions. This is followed by a low-dose boron implant driven in by a hightemperature step for the formation of the p-well. The well depth is optimized to
ensure against n-substrate to n+ diffusion breakdown, without compromising pwell to p+ separation.
The next steps are to define the devices and other; to grow field oxide; contact
cuts; and metallization. A p-well mask is used to define the p-channel transistors
and Vss contacts. Alternatively, an n-plus mask to define the n-channel
transistors, because the masks usually are the complement of each other. P-well
process are preferred in circumstances where the characteristics of the n- and ptransistors are required to be more balanced than that achievable in an n-well
process. Because the transistor that resides in the native substrate tends to have
better characteristics, the p-well process has better p devices than an n-well
process. Because p-devices inherently have lower gain than n-devices, the n-well
process exacerbates this difference while a p-well process moderates the
difference.
1.2.3 Twin-Tub (Twin-Well) CMOS Process
Twin-tub technology provides the basis for separate optimization of the nMOS
and pMOS transistors, thus making it possible for threshold voltage, body effect
and the channel transconductance of both types of transistors to be tuned
independently. Generally, the starting material is a n+ or p+ substrate, with a
lightly doped epitaxial layer on top. This epitaxial layer provides the actual
substrate on which the n-well and the p-well are formed.
Figure 1.20 Twin-well CMOS process cross section

Since two independent doping steps are performed for the creation of the well
regions, the dopant concentrations can be carefully optimized to produce the
desired device characteristics. The aim of epitaxy is to grow high-purity silicon
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layers of controlled thickness with accurately determined dopant concentration

distributed homogenously throughout the layer.
The electrical properties of this layer are determined by the dopant and its
concentration in the silicon. The process sequence, which is similar to the n-well
process apart from the tub formation where both p-well and n-well are utilized,
entails the following steps,
Tub formation.
Thin-oxide construction.
Source and drain implantations.
Contact cut definition.
Metallization.
In the conventional n-well CMOS process, the doping density of the well region is
typically about one order of magnitude higher than the substrate, which, among
other effects, results in unbalanced drain parasitics. The twin-tub process (figure
1.20) also avoids this problem.
1.2.4 Silicon On Insulator (SOI) Process
Silicon on insulator technology (SOI) refers to the use of a layered siliconinsulator-silicon substrate in place of conventional silicon substrates in
semiconductor manufacturing, especially microelectronics, to reduce parasitic
device capacitance and thereby improve performance. SOI-based devices differ
from conventional silicon-built devices in that the silicon junction is above an
electrical insulator, typically silicon dioxide or (less commonly) sapphire. The
choice of insulator depends largely on intended application, with sapphire being
used for radiation-sensitive applications and silicon oxide preferred for improved
performance and diminished short channel effects in microelectronics devices.
The insulating layer and topmost silicon layer also vary widely with application.
The first implementation of SOI was announced by IBM in August 1998. Rather
than using silicon as the substrate, the technologies have sought to use an
insulating substrate to improve process characteristics such as latchup and speed.
Hence the emergence of Silicon On Insulator (SOI) technologies. SOI CMOS
processes have several potential advantages over the traditional CMOS
technologies. These include closer packing of p- and n- transistors, absence of
latchup problems, and lower parasitics substrate capacitances. In the SOI process
a thin layer of single-crystal silicon film is epitaxially grown on an insulator such
as sapphire or magnesium aluminium spinal. Alternatively, the silicon may be
grown on SiO2 that has been in turn grown on silicon. This option has proved
more popular in recent years due to the compatibility of the starting material with
conventional silicon CMOS fabrication. Various masking and doping techniques
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(figure 1.21) are then used to form p-channel and n-channel devices. Unlike the
more conventional CMOS approaches, the extra steps in well formation do not
exist in the technology.
The steps used in typical SOI CMOS process are as follows. A thin film (7-8 m)
of very lightly doped n-type Si is grown over an insulator, Sapphire or SiO2 is
commonly used insulator (figure 1.21 a).
An anisotropic etch is used away the Si except where a diffusion area (n or p)
will be needed. The etch must be anisotropic since the thickness of the Si is much
greater than the spacing desired between the Si islands: (figure 1.21 b, c).
The p-islands are formed next by masking the n-islands with a photoresist. A
p-type dopant, boron, for example is then implanted. It is masked by the
photoresist, but forms p-islands at the unmasked islands. The p-islands will
become the n-channel devices (figure 1.12 d).
The p-islands are then covered with a photoresist and an n-type dopantphosphorus, for example is implanted to form the n-islands. The n-islands will
become the p-channel devices (figure 1.12 e).
A thin gate oxide (around 100-250 A) is grown over all of the Si structures,
this is normally done by thermal oxidation.
A polysilicon film is deposited over the oxide. Often the polysilicon is doped
with phosphorus to reduce its resistivity (figure 1.12f).
The polysilicon is then patterned by photomasking and is etched. This defines
the polysilicon layer in the structure (figure 1.12 g).
The next step is to form the n-doped source and drain of the n-channel devices
in the p-islands. The n-islands are covered with a photoresist and an n-type
dopant, normally phosphorus is implanted. The dopant and an n-type dopant,
normally phosphorus is implanted. The dopant will be blocked at the n-islands by
the photoresist, and it will be blocked from the gate region of the p-islands by the
polysilicon. After this step the n-channel devices are complete (figure 1.12 h).
The p-channel devices are formed next by masking the p-islands and
implanting a p-type dopant such as boron. The polysilicon over the gate of the nisland will block the dopant from the gate, thus forming the p-channel devices
(figure 1.12 i).
A layer of phosphorus glass or some other insulator such as silicon dioxide is
then deposited over the entire structure.
The glass is etched as contact cut locations. The metallization layer is formed
next by evaporating aluminum over the entire surface and etching it to leave only
the desired metal wires. The aluminium will flow through the contact cuts to
make contact with the diffusion or polysilicon regions (figure 1.12 j).
A final passivation layer of phosphorus glass is deposited and etched over
bonding pad locations (not shown in figure).
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Because the diffusion regions extend to the insulating substrate, only sidewall
areas associated with source and drain diffusion contribute to the parasitic
junction capacitance. Since sapphire and SiO2 are extremely good insulators,
leakage currents between transistors and substrate and adjacent devices are almost
eliminated.
In order to improve the yield, some processes use preferential etch in which he
island edges are tapered. Thus aluminium or poly runners can enter and leave the
islands with a minimum step height. This is contrasted to fully anisotropic etch
in which the undercut is brought to zero, as shown in figure 1.13.An isotropic
etch is also shown in the same diagram for the comparison.
Figure 1.12 SOI Process Flow
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The advantages of SOI technology are as follows,

Due to absence of wells, transistor structures denser than bulk silicon are
feasible. Also direct n-to-p connections may be made.
Lower substrate capacitances provide the possibility for faster circuits.
No field-inversion problems exist( insulating substrate)
There is no latchup because of the isolation of the n-and p-transistors by the
insulating substrate.
Because there is no conducting substrate, there are no body-effect problems.
However the absence of a backside substrate contact could lead to odd device
characteristic such as the kink effect in which the drain current increases
abruptly at around 2 to 3 volts.
Some of the disadvantages are,
Due to absence of substrate diodes, the inputs are somewhat more difficult to
protect. Because device gains are lower, I/O structures have to be larger.
Single crystal sapphire, spinel substrate, and silicon SiO2 are considerably
more expensive than silicon substrate and their processing techniques tend to be
less developed than bulk silicon techniques.
Figure 1.13 Classification of Etching processes
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1.3 INTERCONNECT
The most important additions for CMOS logic processes are additional signaland power-routing layers. This eases the routing (especially automated
netting) of logic signals between modules and improves the power and clock
distribution to modules. Improved mutability is achieved through additional
layers of metal or by improving the existing polysilicon interconnection
layer.
1.3.1 Metal Interconnect
A second level of metal is almost mandatory for modern CMOS digital. A
third layer is becoming common and is certainly required for leading-edge
high-density, high-speed chips. Normally, aluminum is used for the metal
layers. I f some form of planarization is employed the second-level metal
pitch can be the same as the first. As the vertical topology becomes more
varied, the width and spacing of metal conductors has to increase so that
the conductors do not thin and hence break at vertical topology jumps (step
coverage).
Contacting the second-layer metal to the first-layer metal is achieved by a
via, as shown in figure 1.14. If further contact to diffusion or polysilicon is
required, a separation between the via and the contact cut is usually
required. This requires a first-level metal tab to bridge between metal2 and
the lower-l e v e l conductor. It is important to realize that in contemporary
processes first level metal must be involved in any contact to underlying
areas. A number of contact geometries are shown in figure 1.15.
Figure 1.14 Two-level metal process cross section

Processes usually require metal borders around the via on both levels of
metal although some process require none. Processes may have no
restrictions on the placement of via with respect to underlying layers
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(figure 1.15a) or they may have to be placed inside (figure 1.15b) or

outside (figur e1.15c) the underlying polysilicon or diffusion areas.
Aggressive processes allow the stacking of vias on top of contacts, as
shown in figure 1.15 (d).
Figure 1.15 Two-level metal /via contact geometrics

Consistent with the relatively large thickness of the intermediate isolation
layer, the vias might be larger than contact cuts and second-layer metal
may need to be thicker and require a larger via overlap although modern
processes strive for uniform pitches on metal I and metal2.
The process steps for a two-metal process are briefly as follows:
The oxide below the first-metal layer is deposited by atmospheric
chemical vapor deposition (CVD).
The second oxide layer between the two metal layers is applied in a
similar manner.
Depending on the process, removal of the oxide is accomplished using
a plasma etcher designed to have a high rate of vertical ion bombardment.
This allows fast and uniform etch rates. The structure of a via etched
using such a method is shown in figure1.14.
1.3.2 Polysilicon/Refractory Metal Interconnect
The polysilicon layer used for the gates of transistors is commonly used
as i t interconnect layer. However, the sheet resistance of doped
polysilicon is between 20 and 40/square. If used as a long distance
conductor, a polysilicon wire can represent a significant delay.
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One method to improve this that requires no extra mask levels is to

reduce the polysilicon resistance by combining it with a refractory metal.
Three such approaches are illustrated in figure 1.16.In figure 1.16(a)
a silicide (e.g., silicon and tantalum) is used as the gate material. Sheet
resistances of the order of 1 to 5/square may be obtained. This is called
the, silicide gate approach.
Figure 1.16 Refractory metal interconnect

Silicides are mechanically strong and may be dry ached in plasma
reactors. Tantalum silicide is stable throughout standard processing and
has the advantage that it may be retrofitted into existing process lines.
Figure 1.16(b) uses a sandwich of silicide upon polysilicon, which is
commonly called the polycide approach. Finally, the silicide/polysilicon
approach may he extended to include the formation of source and d r a i n
r e g i o n s u s i n g t h e s i l i c i d e . This is called the salicide process (Self
Aligned SILICIDE) (figur e 1.16c). The effect of all of these processes
is to reduce the "second layer " interconnect resistance, allowing the gate
material to be used as a moderate long-distance interconnect. This is
achieved by minimum perturbation of an existing process. An increasing
trend in process is to use the salicide approach to reduce the resistance of
both gate and source/drain conductors.
1.3.3 Local Interconnect
The silicide itself may be used as a "local interconnect" layer for
connection within c e l ls . T i N i s u sed as a n example. Local
interconnect allows a direct connection between polysilicon and
diffusion, thus alleviating the need for area intensive contacts and metal.
Figure 1.17 shows a portion (p-devices only) of a six transistor SRAM
cell that uses local interconnect. The local interconnect has been used to
make the polysilicon-to-diffusion connections within the cell, thereby
alleviating the need to use metal (and contacts). Metal2 (not shown) bit
lines run over the cell vertically. Use of local i n t e r c o n n e c t in this RAM
reduced the cell area by 25%.
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Figure 1.17 Local interconnect as used in a RAM cell

In general, local interconnect if available can be used to complete intracell
routing, leaving the remaining metal layers for global wiring.
1.4 CIRCUIT ELEMENTS

1.4.1 Resistors
Polysilicon, if left undoped, is highly resistive. This property is used to build
resistors that are used in static memory cells. The process step is achieved by
preventing the resistor areas from being implanted during normal
processing. Resistors in the tera- (10 12 ) region are used. A value of
3T results in a standby current of 2A for a 1 Mbit memory.
For mixed signal CMOS (analog and digital), a resistive metal such as
nichrome may be added to produce high-value, high-quality resistors. The
resistor accuracy might be further improved by laser trimming the result
resistors on each chip to some predetermined test specification. In this
process a high-powered laser vaporizes areas of the metal resistor until it
meets a measurement constraint. Sheet resistance values in the K/square
are normal. The resistors have excellent temperature stability and long-term
reliability.
1.4.2 Capacitors
Good quality capacitors are required for switched-capacitor analog circuits
while small high-value/area capacitors are required for dynamic memory
cells. Both types of capacitors are usually added by using at least one extra
layer of polysilicon, although the process techniques are very different.
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Polysilicon capacitors for analog applications are the most straightforward.

A second thin-oxide layer is required in order to have an oxide sandwich
between the two polysilicon layers yielding a high-capacitance/unit area.
Figure 1.18 shows a typical polysilicon capacitor. The presence of this,
second oxide can also be used to fabricate transistors. These may differ,
characteristics from the primary gate oxide devices. For memory capacitors
recent processes have used three dimensions to increase the
capacitance/area.
Figure 1.18 Polysilicon Capacitor

One
popular
structure
is
the
trench
capacitor,
which has evolved considerably over the years to push memory densities to
64Mbits and beyond. A typical trench structure is shown in figure 1.19(a).
The sides of the trench are doped n+ and coated with a thin 1Onm oxide.
Sometimes oxynitride is used because its high dielectric constant increases
capacitance.
Figure 1.19 Dynamic memory capacitors

The trench is filled with a polysilicon plug, which forms the bottom plate of
the cell storage capacitor. This is held at VDD /2 via a metal connection at the
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edge of the array. The sidewall n+ forms the other side of capacitor and one
side of the pass transistor that is used to enable data onto the bit lines. The
bottom of the trench has a p+ plug that forms a channel stop region to isolate
adjacent capacitors. The trench is 4m deep and has a capacitance of 90fF.
Rather than building a trench, figure 1.19(b) shows a fintype- capacitor used
in a 64-Mb DRAM. The storage capacitance is 20 to 30 fF. The fins have the
additional advantage of reducing the bit capacitance by shielding the bit
lines. The fabrication of 3D-process structures such as these is a constant
reminder of the skill, perseverance, and ingenuity of the process engineer.
1.4.3 Electrically Alterable ROMs
Electrically alterable/erasable R O M ( E A R O M / E E P R O M ) i s added to
CMOS processes to yield permanent but reprogrammable s to r ag e to a
process. This is usually added by adding a polysilicon layer. Figure 1.20
shows a typical memory structure, which consists o f a stacked-gate
s t r u c t u r e . The normal gate is left floating, while a control gate is placed
above the floating gate. A very thin oxide called the tunnel oxide
separates the floating gate from the source, drain, and substrate.
Figure 1.20 EEPROM technology

This is usually 10 nm thick. Another thin oxide separates the control gate
from the floating gate. By controlling the control-gate, source, and drain
voltages, the thin tunnel oxide between the floating gate and the drain of
the device is used to allow electrons to "tunnel" to or from the floating
gate to turn the cell or on, respectively, using Fowler-Nordheim tunneling.
Alternatively, by setting the appropriate voltages on the terminals, "hot
electrons" can be induced to charge the floating gate, thereby
programming the transistor. In non-electrically alterable versions of the
technology, the p r o cess can be reversed by illuminating the gate with UV
light. In these the chips are usually housed in glass-lidded packages.
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1.4.4 Bipolar Transistors

The addition of the bipolar transistor to the device repertoire forms the
basis for BiCMOS processes. Adding an npn-transistor can markedly aid in
reducing the delay times of highly loaded signals, such as memory word
lines microprocessor busses. Additionally, for analog applications bipolar
transistors may be used to provide better performance analog functions than
MOS alone. To get merged bipolar/CMOS functionality,
Figure 1.21 Typical mixed signal BiCMOS process cross section
Figure 1.22 BiCMOS process steps for the cross section shown in
figure 1.21
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MOS transistors can add to a bipolar process or vice versa. In past days,
MOS processes always had to have excellent gate oxides while bipolar
processes had to have precisely controlled diffusions.
A BiCMOS process has to have both. A mixed signal BiCMOS process
cross section is shown in figure 1.21. This process features both npn- and
pnp-transistors in addition to pMOS and nMOS transistors. The major
processing steps are summarized in figure 1.22, showing the particular
device to which they correspond. The base layers of the process are similar
to the process shown in figure 1.12. The starting material is a lightlydoped p-type substrate into which antimony or arsenic are diffused to
form an n+ buried layer. Boron is diffused to form a buried p + layer. An ntype epitaxial layer 4.0 m thick is then grown. N-wells and p-wells are then
diffused so that they join in the middle of the epitaxial layer. This
epitaxial layer isolates the pnp-transistor in the horizontal direction, while
the buried n+ layer isolates it vertically. The npn-transistor is junctionisolated. The base for the pnp is then ion-implanted using phosphorous. A
diffusion step follows this to get the right doping profile. The npncollector is formed by depositing phosphorus before LOCOS. Field
oxidation is carried out and the gate oxide is grown. Boron is then used to
form the p-type base of the npn transistor.
Following the threshold adjustment of the pMOS transistors, the
polysilicon gates are defined. The emitters of the npn-transistors employ
polysilicon rather than a diffusion. These are formed by opening windows
and depositing polysilicon. The n+ and p+ source/drain implants are then
completed. This step also dopes the npn-emitter and the extrinsic bases of
the npn- and pnp-transistors (extrinsic because this is the part of the base
that is not directly between collector and emitter).
Following the deposition of PSG, the normal two-layer metallization steps
are completed. Representative of a high-density digital BiCMOS process
is that represented by the cross section shown in figure 1.23. The buriedlayer-epitaxial layer-well structure is very similar to the previous
structure. However because this is a 0.8m process, LDD structures must
be constructed for the p-transistors and the n-transistors. The npn is formed
by a double-diffused sequence in which both base and emitter are formed
by impurities that diffuse out of a covering layer of polysilicon. This
process, intended for logic applications, has only an npn-transistor. The
collector of the npn is connected to the n-well, which is in turn connected
to the VDD supply. Thus all npn-collectors are commoned. A typical npntransistor with a 0.8m-square emitter has a current gain of 90 and an ft. of
15 GHz.
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Figure 1.23 Digital BiCMOS process cross section

1.4.5 LatchUp
If every silver lining has a cloud, then the cloud that has plagued CMOS is
a parasitic circuit effect called "latchup." The result of this effect is the
shorting of the VDD and Vss lines, usually resulting in chip selfdestruction or at least system failure with the requirement to power down.
This effect was a critical factor in the lack of acceptance of early CMOS
processes, but in cur-rent processes it is controlled by process innovations
and well-understood circuit techniques.
1.4.5.1 The Physical Origin of Latchup
The source of the latchup effect may be explained by examining the
process cross section of a CMOS inverter, shown in figure 1.24(a), on
which is overlaid an equivalent circuit. The schematic depicts, in addition
to the expected nMOS and pMOS transistors, a circuit composed of an
npn-transistor, a pnp-transistor, and two resistors connected between the
power and ground rails (figure 1.24b). Under the right conditions, this
parasitic circuit has the VI characteristic shown in figure 1.24(c), which
indicates that above some critical voltage (known as the trigger point) the
circuit "snaps" and draws a large current while maintaining a low voltage
across the terminals (known as the holding voltage). This is, in effect, a
short circuit. As mentioned, the bipolar devices and resistors shown in
figure 1.24 (b) are parasitic, that is an unwanted byproduct of producing
pMOS and nMOS transistors. From the figure 1.24(a) reveals how these
devices are constructed. The figure shows a cross-sectional view of a
typical (n-well) CMOS process. The (vertical) pnp-transistor has its
emitter formed by the p+ source/drain implant used in the pMOS
transistors. Note that either the drain or source may act as the emitter
although the source is the only terminal that can maintain the latchup
condition. The base is formed by the n-well, while the collector is the p-
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substrate. The emitter of the (lateral) npn-transistor is the n+ source/drain

implant, while the base is the p-substrate and the collector is the n-well. In
addition, substrate resistance R substrate and well resistance R well are due to
the resistivity of the semiconductors involved.
Figure 1.24 The origin model, and VI characteristics of CMOS Latchup

Consider the circuit shown in figure 1.24(b). If a current is drawn from the
npn-emitter, the emitter voltage becomes negative with respect to the base until
the base emitter voltage is approximately 0.7 volts. At this point the npntransistor turns on and a current flows in the well resistor due to common emitter
current amplification. This raises the base emitter voltage of the pnptransistor, which turns on when the pnp Vbe = - 0 . 7 volts. This in turn
raises the npn base voltage causing a positive feedback condition, which
has the characteristic shown in figure 1.24(c). At a certain npn-baseemitter voltage, called the trigger point, the emitter voltage suddenly
"snaps back" and enters a stable state called the ON state. This state will
persist as long as the voltage across the two transistors is greater than the
holding voltage shown in the figure. As the emitter of the npn is the
source/drains of the n-transistor, these terminals are now at roughly 4
volts. Thus there is about 1 volt across the CMOS inverter, which will
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most likely cause it to cease operating correctly. The current drawn is

usually destructive to metal lines supplying the latched up circuitry.
1.4.5.2 Latchup Triggering
For latchup to occur the parasitic npn-pnp circuit has to be triggered and
the holding state has to be maintained. Latchup can be triggered by
transient cur-rents or voltages that may occur internally to a chip during
power-up or externally due to voltages or currents beyond normal
operating ranges. Radiation pulses can also cause latchup. Two distinct
methods of triggering are possible, lateral triggering and vertical
triggering.
Lateral triggering occurs when a current flows in the emitter of the lateral
npn-transistor. The static trigger point is set by
I ntrigger ~
where
V pnp-on
npn R well
(1.1)
V pnp _ on~ 0.7 volts the turn-on voltage of the vertical pnp-transistor
anpn = common base gain of the lateral npn-transistor
Rwell = well resistance.
Vertical triggering occurs when a sufficient current is injected into the
emitter of the vertical-pnp transistor. Similar to the lateral case, this
current is multiplied by the common-base-current gain, which causes a
voltage drop across the emitter base junction of the npn transistor due to
the resistance, R substrate . When the holding or sustaining point is entered, it
represents a stable operating point provided the current required to stay in
the state can he maintained.
Current has to be injected into either the npn- or pnp-emitter to initiate
latchup. During normal circuit in internal circuitry this may occur due to
supply voltage transients, but this is unlikely. However, these conditions
may occur at the I/O circuits employed on a CMOS chip, where the
internal circuit voltages meet the external world and large currents can
flow. Therefore extra precautions need to be taken with peripheral CMOS
circuits.
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a
Figure 1.25 Externally included latchup

Figure 1.25(a) illustrates an example where the source of an nMOS output
transistor experiences undershoot with respect to Vss due to some external
circuitry. When the output dips below Vss by more than 0.7V, the drain of
the nMOS output driver is forward biased, which initiates latchup. The
complementary case is shown in figure 1.25(b) where the pMOS output
transistor experiences an overshoot more than 0.7V beyond VDD . Whether
or not in these cases latchup occurs depends on the pulse widths and
speed of the parasitic transistors.
1.4.6 Latchup Prevention
For latchup to occur an analysis of the circuit in figure 1.25(b) finds the
following inequality has to be true
npnpnp> 1+ (npn+1 ) I Rsubstrate +I Rwellpnp)
I
DD - I Rsubstrate
(1.2)
Where
I
Rsubstrate == Vbe npn

R
substrate
Rwell =
Vbe pnp
Rwell
IDD =total supply current
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This equation yields the keys to reducing latchup to the point where it
should never occur under normal circuit conditions. Thus, reducing the
resistor values and reducing the gain of the parasitic transistors are the
basis for eliminating latchup.
Latchup may be prevented in two basic ways:
Latchup resistant CMOS processes.

Layout techniques.
A popular process option that reduces the gain of the parasitic transistors
is the use of silicon starting-material with a thin epitaxial layer on top of a
highly doped substrate. This decreases the value of the substrate resistor
and also provides a sink for collector current of the vertical pnp-transistor.
As the epi layer is thinned, the latchup performance improves until a point
where the up-diffusion of the substrate and the down-diffusion of any
diffusions in subsequent high-temperature procession steps thwart
required device doping profiles. The so-called retrograde well structure is
also used. This well has a highly doped area at the bottom of the well,
whereas the top of the well is more lightly doped. This preserves good
characteristics for the pMOS (or nMOS in p-well) transistors but reduces
the well resistance deep in the well. A technique linked to these two
approaches is to increase the holding voltage above the VDD supply. This
guarantees that latchup will not occur.
It is hard to reduce the betas of the bipolar transistors to meet the condition set above. Nominally, for a 1 n-well process, the vertical pnp has a
beta of 10-100, depending on the technology. The lateral npn-currentgain which is a function of n+ drain to n-well spacing , i s b e t w e e n 2
and 5.
1.5 LAYOUT DESIGN RULES

Layout rules, also referred to as design rules, can be considered as a prescription for preparing the photomasks used in the fabrication of
integrated circuits. The rules provide a necessary communication link
between circuit designer and process engineer during the manufacturing
phase. The main objective associated with layout rules is to obtain a
circuit with optimum yield (functional circuits versus nonfunctional
circuits) in as small an area as possible without compromising reliability
of the circuit.
In general, design rules represent the best possible compromise between
performance and yield. The more conservative the rules are, the more
likely it is that the circuit will function. However, the more aggressive the
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rules are, the greater the probability of improvements in circuit

performance. This improvement may be at the expense of yield.
Design rules specify to the designer certain geometric constraints on the
layout artwork so that the patterns on the processed wafer will preserve
the topology and geometry of the designs. It is important to note that
design rules do not represent some hard boundary between correct and
incorrect fabrication. Rather, they represent a tolerance that ensures very
high probability of correct fabrication and subsequent operation. For
example, one may find that a layout that violates design rules may still
function correctly, and vice versa. Nevertheless, any significant or
frequent departure (design-rule waiver) from design rules will seriously
prejudice the success of a design.
Two sets of design-rule constraints in a process relate to line widths and
interlayer registration. If the line widths are made too small, it is possible
for the line to become discontinuous, thus leading to an open circuit wire.
On the other hand, if the wires are placed too close to one another, it is
possible for them to merge together; that is, shorts can occur between two
independent circuit nets. Furthermore, the spacing between two
independent layers may be affected by the vertical topology of a process.
The design rules primarily address two issues:
(1) The geometrical reproduction of features that can be reproduced by
the mask- making and litho-graphical process and
(2) The interactions between different layers.
There are several approaches that can be taken in describing the design
rules. These include 'micron' rules stated at some micron resolution, and
lambda () based rules. Micron designs rules are usually given as a list
of minimum feature sizes and spacings for all masks required in a given
process.
1.5.1 Layer Representations
The advances in the CMOS processes are generally complex and
somewhat inhibit the visualization of all the mask levels that are used in
the actual fabrication process. Nevertheless the design process can be
abstracted to a manageable number of conceptual layout levels that
represent the physical features observed in the final silicon wafer. At a
sufficiently high conceptual level all CMOS processes use the following
features:
Two different substrates.
Doped regions of both p- and n-transistor-forming material.
Transistor gate electrodes.
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Interconnection paths.
Interlayer contacts.
The layers for typical CMOS processes are represented in various figures
in terms of:
A color scheme proposed by JPL based on the Mead-Conway colors.
Other color schemes designed to differentiate CMOS structures
(e.g., the colors as used on the from cover of this hook)
Varying stipple patterns.
Varying line styles.
Some of these representations are shown in below table.
1.5.2 CMOS n-well Rules

In this section a version of n-well rules based on the MOSIS CMOS
Scalable Rules and compares those with the rules for a hypothetical
commercial 1 CMOS process shown in below table. The MOSIC rules
are expressed in terms of . These rules allow some degree of scaling
between processes as, in principal, we only need to reduce the value of and
the designs will be valid in the next process down in size. Unfortunately, history
has shown that processes rarely shrink uniformly. Thus industry usually uses the
actual micron-design rules and codes designs in terms of these dimensions, or
uses symbolic layout systems to target the design rules exactly. At this time, the
amount of polygon pushing is usually constrained to a number of frequently used
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standard cells or memories, where the effort expended is amortized over many
designs. Alternatively, the designs are done symbolically, thus relieving the
designer of having to deal directly with the actual design rules.
The rules are defined in terms of:
Feature sizes.
Separations and overlaps.
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1.5.3 Scribe Line

The scribe line is specifically designed structure that surrounds the
completed chip and is the point at which the chip is cut with a diamond
saw. The construction of the scribe line varies from manufacturer to
manufactures
1.5.4 SOI Rules
SOI rules closely follow bulk CMOS rules except the n+ and p+ regions
can abut. This allows some interesting and latch circuits. A spacing rule
between the poly and island edges. This can be caused by thin or faculty
oxide covering over the islands.
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1.5.5 Layer Assignments

The below table lists the MOSIS Scalable CMOS design-rule layer
assignments for the Caltech Intermediate Form (CIF) and Calma stream
format.
1.6. PHYSICAL DEISGN

1.6.1 Basic Concept
Figure 1.26 shows part of the design flow, the physical design steps, for
an ASIC (omitting simulation, test, and other logical design steps that
have already been covered). Some of the steps in Figure 1.26 might be
performed in a different order from that shown. For example, depending
on the size of the system, perform system partitioning before any design
entry or synthesis. There may be some iteration between the different
steps too. First to apply system partitioning to divide a microelectronics
system into separate ASICs.
In floorplanning sizes estimate and set the initial relative locations of the
various blocks in our ASIC (sometimes we also call this chip planning).
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At the same time to allocate space for clock and power w i r i n g a n d

decide on the location of the I/O and power pads. Placement defines the
location of the logic cells within the flexible blocks and sets aside space for
the interconnect to each logic cell. Placement for a gate-array or standardcell design assigns each logic cell to a position in a row.
Figure 1.26 Part of ASIC Design Flow

For an FPGA, placement chooses which o f the fixed logic resources on the
chip are used for which logic cells. Floorplanning and placement are
closely related and are sometimes combined in a single CAD tool.
Routing makes the connections between logic cells. Routing is a hard
problem by itself is normally split into two distinct steps, called global
and local routing. Global routing determines where the interconnections
between the placed logic cells and blocks will be situated. Only the routes
to he used by the interconnections within the wiring areas.
Global routing is sometimes called loose routing for this reason. Local
routing joins the logic cells with interconnections. Information on which
interconnections areas to use comes from the global router. Only at this
stage o f layout d, finally decide on the width, mask layer, and exact
location of the interconnections local routing is also known as detailed
routing.
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1.6.2 CAD Tools sets

In order to develop a CAD tool it is necessary to convert each of the
physical do steps to a problem with well-defined goals and objectives. The
goals for each physical design step are the things to achieve. The
objectives for each step things to meet goals. Some examples of goals and
objectives for each of the ASIC physical design steps are as explained
below,
System partitioning
Goal: Partition a system into a number of ASICs.
Objectives: Minimize the number of external connections between the
ASICs. Keep each ASIC smaller than a maximum size.
Floorplanning
Goal: Calculate the sizes of all the blocks and assign them locations.
Objective: Keep the highly connected blocks physically close to each
other.
Placement
Goal: Assign the interconnect areas and the location of all the logic
cells within the flexible blocks.
Objectives: Minimize the ASIC area and the interconnect density.
Global routing
Goal: Determine the location of all the interconnect.
Objective: Minimize the total interconnect area used.
Detailed routing
Goal: Completely route all the interconnect on the chip.
Objective: Minimize the total interconnect length used.
There i s no magic recipe involved in the choice o f the ASIC physical
design steps. These steps have been chosen simply because, as tools and
techniques have developed historically, these steps proved to be the
easiest way to split up the larger problem if ASIC physical design.
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1.6.3 Physical Design-The Inverter
1.6.4 Physical Design-The NOR
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1.6.5 Physical Design-The NAND
1.7 DESIGN STRATEGIES

The economic viability of an IC is in large part affected by the productivity
that can be brought to hear on the design. This in turn depends on the
efficiency with which the design may be converted from concept to
architecture, to logic and memory, to circuit and hence to a physical layout.
A good VLSI design system should provide for consistent in all three
description domains (behavioral, structural and physical) and at all relevant
levels of abstraction (architecture, RTL, logic, circuit). The means by which
this is accomplished may be measured in various terms that differ in
importance based on the application. These design parameters may be
summarized in terms of
Performance-speed, power, function, flexibility.

Size of die (hence cost of die).
Time to design (hence cost of engineering and schedule).
Ease of test generation and testability (hence cost of engineering and
schedule).
Design is a continuous trade-off to achieve adequate results for all of the
above parameters. As such, the tools and methodologies used for a
particular chip will be a function of these parameters. Certain end results
have to be met (i.e., the chip must conform to performance specifications),
but other constraints may be a function of economics (i.e., size of die
affecting yield) or even subjectivity (i.e., what one designer finds easy,
another might find incomprehensible).
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Given that the process of designing a system on silicon is complicated, the

role of good VLSI-design aids is to reduce this complexity, increase
productivity, and assure the designer of a working product. A good method
of simplifying the approach to a design is by the use of constraints and
abstractions. By using constraints the tool designer has some hope of
automating procedures and taking a lot of the "legwork" out of a design. By
using abstractions, the designer can collapse details and arrive at a simpler
concept with which to deal.
1.7.1 Structured Design Strategies
The successful implementation of almost any integrated circuit requires an
attention to the details of the engineering design process. Over the years a
number of structured design techniques have been developed to deal with
both complex hardware and software projects. Not surprisingly the
techniques have a great deal of commonality. Rigorous application of these
techniques can drastically alter the amount of effort that has to be expended
on a given project and also in all likehood, the chances of a successful
conclusion. Whether under consideration is a small chip designed by a
single designer or a large system designed by a team of designers, the basic
principles of structured design will improve the prospects of success.
1.7.2 Hierarchy
The use of hierarchy, or "divide and conquer," involves dividing a module
into submodules and then repeating this operation on the submodules until
the complexity of the submodules is at an appropriately comprehensible
level of detail. This parallels the software case where large programs are
split into smaller and smaller sections until simple subroutines, with well
defined functions and interfaces can be written. A design may be expressed
in terms of three domains. A "parallel hierarchy" in each domain to
document the design. For instance, an adder may have a subroutine that
models the behavior, a gate-connection diagram that specifies the circuit
structure, and a piece of layout that specifies the physical nature of the
adder. Composing the adder into other structures can proceed in parallel for
all three domains, with domain-to-domain comparisons ensuring that the
representations are consistent. At a system level, the use of hierarchy
allows one to specify single designer projects, at which level the schedule
is proportional to the number of available personnel.
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MOS TRANSISTOR THEORY
UNIT-2
2.1 NMOS ENHANCEMENT TRANSISTOR
The structure for an n-channel enhancement-type transistor, shown in
figure 2.1, consists of a moderately doped p-type silicon substrate into
which two heavily doped n+ regions, the source and the drain, are
diffused. Between these two regions there is a narrow region of p-type
substrate called the channel, which is covered by a thin insulating layer of
silicon dioxide (SiO 2 ), called gate oxide. Over this oxide layer is a
polycrystalline silicon (polysilicon) electrode, referred to as the gate.
Polycrystalline silicon is silicon that is not composed of a single crystal.
Since the oxide layer is an insulator, the DC current from the gate to
channel is essentially zero. Because of the inherent symmetry of the
structure, there is no physical distinction between the drain and source
regions. Since SiO 2 has relatively low loss and high dielectric is strength,
the application of high gate fields is feasible.
In operation, a positive voltage is applied between the source and the
Drain (Vdy ). With zero gate bias (Vs = 0), no current flows from source to
drain because they are effectively insulated from each other by the two
reversed biased pn junctions shown in figure 21 (indicated by the diode
symbols). However, a voltage applied to the gate, which is positive with
respect to 'he source and the substrate, produces an electric field E across
the substrate, which attracts electrons toward the gate and repels holes. If
the gate voltage is sufficiently large, the region under the gate changes
from p-type to n-type (due to accumulation of attracted electrons) and
provides a conduction path between the source and the drain.
Figure 2.1 Physical structure of an nMOS transistor

Under such a condition, the surface of the underlying p-type silicon is
said to be inverted. The term n-channel is applied to the structure. This
concept is further illustrated by figure 2.2(a), which shows the initial
distribution of mobile positive holes in a p-type silicon substrate of MOS
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structure for a voltage, V gs , much less than a voltage, Vt, which is the
threshold voltage. This is termed the accumulation mode. As V gs is raised
above Vt in potential, the holes are repelled causing a depletion region
under the gate. Now the structure is in the depletion mode (figure 2.2b).
Raising Vgs further above Vt. results in electrons being attracted to the
region of the substrate under the gate. A conductive layer of electrons in
the p substrate gives rise to the name inversion mode (figure 2.2c).
Figure 2.2 Accumulation, Depletion and Inversion modes in an MOS

structure
The difference between a pn junction that exists in a bipolar transistor or
diode (or between the source or drain and substrate) and the inversion
layer substrate junction is that in the pn junction, the n-type conductivity
is brought about by a metallurgical process; that is, the electrons are
introduced into the semiconductor by the introduction of donor ions. In
an inversion layer substrate junction, the n-type layer is induced by the
electric field E applied to the gate. Thus, this junction, instead of being a
metallurgical junction, is a field-induced junction.
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Electrically, an MOS device therefore acts as a voltage-controlled switch

that conducts initially when the gate-to-source voltage, V gs , is equal to
the threshold voltage, Vt. When a voltage V d s is applied between source
and drain, with Vgs . = Vt , the horizontal and vertical components of the
electrical held due to the source-drain voltage and gate-to-substrate
voltage interact, causing conduction to occur along the channel. The
horizontal component of the electric field associated with the drain-tosource voltage (i.e., V ds > 0) is responsible for sweeping the electrons in
the channel from the source toward the drain. As the voltage from drain
to source is increased, the resistive drop along the channel begins to
change the shape of the channel characteristic. This behavior is shown in
figure 2.3. At the source end of the channel, the full gate voltage is
effective in inverting the channel. However, the drain end of the channel,
only the difference between the gate and n voltages is effective. When
the effective gate voltage (V gs . Vt) is greater than the drain voltage, the
channel becomes deeper as V g s is increased. This is termed the
Figure 2.3 nMOS device behavior under the influence of different terminal
voltages
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"linear," "resistive," "nonsaturated," or "unsaturated" region, where the

channel current Ids is a function of both gate and drain voltages. If Vds >
Vgs Vt, then Vgd < Vt (Vgd is the gate to drain voltage), and the channel
becomes pinched off- the channel no longer reaches the drain. This is
illustrated in figure 2.3(c). However, in this case, conduction is brought
about by a drift mechanism of electrons under the influence of the positive
drain voltage. As the electrons leave the channel, they are injected into the
drain depletion region and are subsequently accelerated toward the drain.
The voltage across the pinched-off channel tends to remain fixed at (V gs V t ). This condition is the "saturated" state in which the channel current
is controlled by the gate voltage and is almost independent of the drain
voltage. For the fixed drain-to-source voltage and fixed gate voltage, the
factors influence the level of drain current, Ids , flowing between source
and drain are:
the
the
the
the
the
the
distance between source and drain

channel width
threshold voltage V,
thickness of the gate-insulating oxide layer
dielectric Constant of the insulator
carrier (electron or hole) mobility
The normal conduction characteristics of an MOS transistor can be categorized as follows:

"Cut-off' region: where the current flow is essentially zero
(accumulation region).
"Nonsaturated" region: weak inversion region where the drain
current is dependent on the gate and the drain voltage (with respect to
the substrate).
"Saturated" region: channel is strongly inverted and the drain
current flow is ideally independent of the drain-source voltage
(strong inversion region).
An abnormal conduction condition called avalanche breakdown or
punch-through can occur if very high voltages are applied to the drain.
Under these circumstances, the gate has no control over the drain
current.
2.2 PMOS ENHANCEMENT TRANSISTOR

As discussed in previous topic toward nMOS; a reversal of n-type and ptype regions yields a p-channel MOS transistor. This is illustrated by
figure 2.4. Application of a negative gate voltage (w.r.t. source) draws
holes into the region below the gate, resulting in the channel changing
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from n-type to p-type. Thus, similar to nMOS, a conduction path is

created between the source and the drain. In this instance, how-ever,
conduction results from the movement of holes (versus electrons) in the
channel. A negative drain voltage sweeps holes from the source through
the channel to the drain.
Figure 2.4 Physical structure of a pMOS transistor
2.3 THRESHOLD VOLTAGE

The threshold voltage, Vt, for an MOS transistor can be defined as the
voltage applied between the gate and the source of an MOS device below
which he drain-to-source current Ids , effectively drops to zero. The word
effectively is used because the drain current never really is zero but
drops to a very small value that may be deemed insignificant for the
current application .In general, the threshold voltage is a function of a
number of parameters including the following
Gate conductor material.

Gate insulation material.
Gate insulator thickness-channel doping.
Impurities at the silicon-insulator interface.
Voltage between the source and the substrate, V sb
In addition, the absolute value of the threshold voltage decreases with an

increase in temperature. This variation is approximately - 4 mV/C for
high substrate doping levels, and - 2 mV/C for low doping levels.
2 . 3 . 1 Threshold Voltage Equations
Threshold voltage, Vt, may be expressed as
(2.1)
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where V t_mos., is the ideal threshold voltage of an ideal MOS capacitor and
V fb is what is termed the flat-band voltage. Vt_mos is the threshold where
there is no work function difference between the gate and substrate
materials. The MOS threshold voltage, V t-mos , is calculated by
considering the MOS capacitor structure that forms the gate of the MOS
transistor (see for e x a mp l e or 3 ). The ideal threshold voltage may be
expressed as
(2.2)
where
is the oxide capacitance
and
which is called the bulk charge
term.
The symbol b is the bulk potential, a term that accounts for the doping of
the substrate. It represents the difference between the Fermi energy level
of the doped semiconductor and the Fermi energy level of the intrinsic
semiconductor. The intrinsic level is midway between the valence-band
edge and the conduction band edge of the semiconductor. In a p type
semiconductor the Fermi level is closer to the valence hand, while in an
n-type
se miconductor it is closer to the conduction band. NA is the
density of carriers in the doped semiconductor substrate, and N i is the
carrier concentration in intrinsic silicon .N i is equal to 1.45 x 10 10 cm -3 at
3000K. The lowercase k is Boltzmanns constant (1.380 x 10-23 J/K).T is
the temperature (K) and q is th e electronic charge (1.602 x10 -1 9
Coulomb). The expression kT / q equals 0.02586 Volts at 300 0K. The term
Cox is the permittivity of silicon (1.06 x 10-12 Farads/cm). The term C o x is
the gate-oxide capacitance, which is inversely proportional to the gateoxide thickness (t ox ).The threshold voltage, V t-mos is positive for ntransistors and negative for p-transistors. The flatband voltage,V fb , is
given by
Vfb=ms-(Qfc/Cox)
(2.3)
The term V fb is the flat-band voltage. The term Qfc represents the fixed
charge due to surface states that arise due to imperfections in the siliconoxide interface and doping. The term ms is the work function difference
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between the gate material and the silicon substrate ( gate - si ), which may
the calculated for an n + gate over a p substrate as follows
(2.4a)
and T is the temperature (K). For an n+ poly gate on an n-substrate
(2.4b)
From these equations it may be seen that for a given gate and substrate
material the threshold voltage may be varied by changing the doping
concentration o f the substrate (NA ), the oxide capacitance (C ox ), or the
In addition, the temperature variation
surface state charge (Q fc .).
mentioned above may be seen.
It is often necessary to adjust the native (original) threshold voltage of an
MOS device. Two common techniques used for the adjustment of the
threshold voltage entail varying the doping concentration at the siliconinsulator interface through ion implantation or using different insulating
material for gate. The former approach introduces a small doped region
at the oxide/substrate interface that adjusts the flat-band voltage by
varying the Q fc term in equation (2.3). In the latter approach for
instance, a layer of silicon nitride (Si 3 N 4 ) is combined with a layer of
silicon dioxide resulting in an effective relative permittivity of about 6,
which is substantially larger than the dielectric constant SiO 2 .
Consequently, for the same thickness as an insulating layer consisting of
only silicon dioxide, the dual dielectric process will be electrically
equivalent to a thinner layer of SiO 2 leading to a higher C ox value.
2.4 BODY EFFECT

In general, all devices comprising an MOS device are made on a common
substrate. As a result, the substrate voltage of all devices is normally
equal. (In some analog circuits this may not be true.) However, in
ranging the devices to form gating functions it might be necessary to connect several devices in series as shown in figure. 2.5. This may result
in an increase in source-to-substrate voltage as we proceed vertically
along the series chain (V sb1 =0, V sb2 0).
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Under normal conditions that is, when V gs >V t the depletion-layer width
remains constant and charge carriers are pulled into the channel from the
source. However, as the substrate bias V sb (Vsource-Vsubstrate) is increased,
the width of the channel substrate depletion layer also increases, resulting
in an increase in the density of the trapped carriers in the depletion laver.
For charge neutrality to hold, the channel charge must decrease. The
resultant effect is that the substrate voltage, Vsb , adds to the channelsubstrate junction potential. This increases the gate-channel voltage
drop. The overall effect is an increase in the threshold voltage
V t (V t2 -V t1 )
Figure 2.5 The effect of substrate bias on series-connected n-transistors
2.5 MOS DEVICE DESIGN EQUATIONS

2.5.1 Basic DC Equations
The MOS transistors have three regions of operation:
Cutoff or subthreshold region.

Nonsaturation or linear region.
Saturation region.
The ideal (first order, Shockley) equations describing the behavior of an

nMOS device in the three regions are:
The cutoff region:
Ids=0
Vgs Vt
(2.5a)
The nonsaturation, linear or triode region:
The saturation region:
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Ids=(/2)(Vgs-Vt)2
(2.5c)
where Ids is the drain-to-source current, Vgs is the gate-to-source voltage, Vt is the
device threshold, and is the MOS transistor gain factor. The last factor is dependent on both the process parameters and the device geometry, and is given by
=(/tox)(W/L)
(2.6)
where is the effective surface mobility of the carriers in the channel, is the
permittivity of the gate insulator, tox is the thickness of the gate insulator, W is the
width of the channel, and L is the length of the channel. The gain factor thus
consists of a process dependent factor /tox, which contains all the process terms
that account for such factors as doping density and gate-oxide thickness and a
geometry dependent term (W/L), which depends on the actual layout dimensions
of the device. The process dependent factor is sometimes written as Cox, where
C ox = / t o x is the gate oxide capacitance. The geometric terms in Eq. (2.6) are
illustrated in figure 2.6 in relation to the physical MOS structure.
Figure 2.6 Geometric terms in the MOS device equation
Figure 2.7 VI characteristics for n- and p-transistors
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The voltage-current characteristics of the n- and p-transistors in the non-saturated

and saturated regions are represented in figure 2.7 (with the SPICE circuit for
obtaining these characteristics for an n-transistor). Note that we use the absolute
value of the voltages concerned to plot the characteristics of the p- and ntransistors on the same axes. The boundary between the linear and saturation
regions corresponds to the condition | Vds| = | Vgs - Vt | and appears as a dashed
line in figure 2.7. The drain voltage at which the device becomes saturated is
called Vdsat, or the drain saturation voltage. In the above equations that is equal
to Vgs-Vt
2.5.2 Second Order Effects
Equation 2.5 represents the simplest view of the MOS transistor DC voltage
current equations. There have been many research papers published on more
detailed and accurate models that have been created to fill a variety of
requirements, such as accuracy, computational efficiency, and the conservation
of charge. The circuit simulation program SPICE and its commercial and
proprietary derivations generally use a parameter called LEVEL to specify which
model equation, are LEVEL1 models build on those defined in Eq. (2.5) and
include some important second order effects. LEVEL 2 models calculate the
currents based on physics. LEVEL 3 is a semiempirical approach that relies on
parameters selected on the basis of matching the equations to real circuits. The
MOS device equations in terms of the LEVEL 1 parameters used in SPICE will
be covered here.
First the term /tox(Cox) is defined as the p r o ce s s gain factor. In SPICE
this is referred to as KP. Depending on the vintage of the process and the type of
transistor, KP may vary from 10-100 pA/V2. In addition, it is not unusual to
expect a variation of 10%-20% in KP within a given process as a result of
variations in starting materials and variation in SiO2 growth.
2.5.2.1 Threshold Voltage-Body Effect
The threshold voltage Vt is not constant with respect to the voltage difference
between the substrate and the source of the MOS transistor. This is known as the
substrate-bias effect or body effect. The expression for the threshold voltage
may be modified to incorporate Vsb, the difference between the source and the
substrate.
(2.7)
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where Vsb is the substrate bias, Vto is the threshold voltage for Vsb=0 , and is
the constant that describes the substrate bias effect. The term b is defined in Eq
2.2. Typical values for lie in the range of 0.4 to 1.2. It may be expressed as
(2.8)
in which q is the charge on an electron, ox, is the dielectric constant of the silicon
dioxide, si; is the dielectric constant of the silicon substrate, and NA is the doping
concentration density of the substrate. The term is the SPICE parameter called
GAMMA. Vto is the parameter VTO, N A is he parameter NSUB, and s=2b is
PHI, the surface potential at the onset of strong inversion. Thus the threshold
shifts by approximately half a volt with the source at 2.5 volts for these process
parameters. The type of CMOS process can have a large impact on this
parameter for both n- and p-transistors. The increase in threshold voltage leads to
lower device currents, which in turn leads to slower circuits.
2.5.2.2 Subthreshold Region
The cutoff region described by Eq. (2.5a) is also referred to as the subthreshold
region where Ids increases exponentially with Vds and Vgs. Although the value of
Ids is very small (I ds =0), the finite value of Ids may be used to advantage to
construct very low power circuits or it may adversely affect circuits such as
dynamic-charge storage nodes. As an approximation, Level 1 SPICE models set
the subthreshold current to 0.
2.5.2.3 Channel-length Modulation
The simplified equations that describe the behavior of an MOS device assume that
the carrier mobility is constant, and do not take into account the variations in
channel length due to the changes in drain-to-source voltage, Vds . For long
channel lengths, the influence of channel variation is of little consequence.
However, as devices are scaled down, this variation should be taken into
account. When an MOS device is in saturation, the effective channel length
actually is decreased such that
Leff=L-Lshort
(2.9)
where
The reduction in channel length increases the (W/L) ratio, thereby increasing
as the drain voltage increases. Thus rather than appearing as a constant current
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source with infinite output impedance, the MOS device has a unite output
impedance. An approximation that takes this behavior into account is
represented by the following equation:
(2.10)
Where k is the process gain factor /tox and is an empirical channel-length
modulation factor having a value in the range 0.02V-1 to 0.005V-1
2.5.2.4 Mobility Variation
The mobility , describes the ease with which carriers drift in the substrate
material. It is defined by
=average carrier drift velocity (V)/ Electric Field (E)
(2.11)
If the velocity, V, is given in cm/sec, and the electric field, E, in V/cm, the
mobility has the dimensions cm2/V-sec. The mobility may vary in a number of
ways. Primarily, mobility varies according to the type of charge carrier.
Electrons (negative-charge carriers) in silicon have a much higher mobility than
holes (positive-charge carriers), resulting in n-devices having higher currentproducing capability than the corresponding p-devices. Mobility decreases with
increasing doping-concentration and increasing temperature. The temperature
variation becomes less pronounced as the doping density increases. In SPICE is
specified by the parameter UO.
2.6 MOS MODELS

In the previous section the ideal equations that describe the behavior of
MOS transistors. While these incorporate some non ideal effects (channellength modulation, threshold-voltage variation), they may not accurately
model a specific device in a particular process. That is especially true for
devices that have very small dimensions (gate lengths, gate widths, oxide
thicknesses) as the modeling process becomes increasingly 3D in nature.
Parameter
nMOS
pMOS
Units
Description
VTO
0.7
0.7
Volt
Threshold voltage
KP
8x10-5
2.5x10-
A/V2
Transconductance
coefficient
GAMMA
0.4
0.5
V0.5
Bulk threshold
parameter
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PHI
0.37
0.36
volt
Surface potential
at strong
inversion
LAMBDA
0.01
0.01
Volt-1
Channel length
modulation
parameter
LD
0.1 x
10-6
0.1x10-
Meter
Lateral diffusion
TOX
2x10-8
2x10-8
Meter
Oxide thickness
NSUB
2x1016
4x1016
1/cm3
Substrate doping
density
Table 2.1 SPICE DC Parameters

Researchers have developed and refined a wide range of MOS models in
an effort to predict more accurately the performance of MOS devices before
they are fabricated for varying design scenarios. For instance, one might
predict DC currents very accurately from raw process parameters, thus
helping predict the behavior of an as yet untested device. However, because
of the complexity of the model, it might not be appropriate for a fast
execution time model that might be needed for digital simulation purposes.
In that case, a model based on parameters measured from an actual process
might be appropriate.
Depending on the particular circuit level simulator that may be available,
a wide variety of MOS simulation models may be used. For instance in one
commercial circuit simulators there are over 10 different MOS models.
Many semiconductor vendors expend a great deal of effort to model the
device they manufacture. Many times these efforts are aimed at internal
circuit simulators and proprietary models. Most CMOS digital foundry
operation have been standardized on the LEVEL 3 models in SPICE as
the level of circuit modeling that is required for CMOS digital system
design. Table 2.1 is a summary of the main SPICE DC parameters that are
used in Levels 1, 2, and 3 with representative values for a 1 n-well CMOS
process.
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2.7 SMALL SIGNAL AC CHARACTERISTICS

The MOS transistor can be represented by the simplified (Vsb = 0) small
signal equivalent model shown in figure 2.8 when biased appropriately. Here
the MOS transistor is modeled as a voltage-controlled current source (g m ),
an output conductance (g ds ), and the interelectrode capacitances. These
values may be used, for instance, to calculate voltage amplification factors
(gain) or bandwidth characteristics when considered along with other circuit
elements.
Figure 2.8 Small signal model for an MOS transistor

The output conductance (gds ) in the linear region can be obtained by differentiating Eq. (2.5b) with respect to Vds, which results in an output drainsource conductance of
g ds =((V gs - V t )-2 V ds )
(Vgs-Vt)
(2.12)
Note that consistent with Eq. (2.5b), Vds must be small compared to V gs for
the MOS device to be in a linear operating regime. On rearrangement, the
channel resistance R c is approximated by
Rc(linear) =1/ (Vgs-Vt)
(2.13)
which indicates that it is controlled by the gate-to-source voltage. The

relation defined by Eq. (2.13) is valid for gate to source voltages that
maintain constant mobility in the channel. In contrast, in saturation [i.e.,
V ds (V gs - Vt)], the MOS device behaves like a current source, the current
being almost independent of Vds . This may be verified from Eq. (2.5c)
since
(2.14)
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In practice, however, due to channel shortening (Eq. 2.9) and other

effects, the drain-current characteristics have some slope. This slope
defines the g ds of the transistor. The output conductance can be decreased
by lengthening the channel (i.e., L).
The transconductance g m expresses the relationship between output
current I ds and the input voltage V gs and is defined by
(2.15)
It is used to measure the gain of an MOS device. In the linear region g m
given by
(2.16)
g m(linear) =V ds
and in the saturation region by
g m(sat) = (Vgs-Vt)
(2.17)
Since transconductance must have a positive value, the absolute value is

used for voltages applied to p-type devices.
2.8 THE COMPLEMENTARY CMOS INVERTER DC

CHARACTERISTICS
A complementary CMOS inverter is realized by the series connection of a
p and an n-device, as shown in figure 2.11. In order to derive the DCtransfer characteristics for the inverter (output voltage, Vout , as a function
of the inverter Vin), from the Table 2.1, which outlines various regions of
operation for the n- and p-transistors. In this table, V tn is the threshold
voltage of the n channel device, and Vtp, is the threshold voltage of the pchannel device. The objective is to find the variation in output voltage
(V out ) for changes in the input voltage (V in ).
Figure 2.9 A CMOS inverter (with substrate connections)
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The graphical representation of the simple algebraic equations described

by Eq. (2.5) for the two inverter transistors shown in figure 2.12(a). The
absolute value of the p-transistor drain current I ds inverts this
characteristic. This allows the VI characteristics for the p-device to he
reflected about the x-axis (figure. 2.12b). This step is followed by taking
the absolute value of the p-device, Vds , and superimposing the two
characteristics yielding the resultant curves shown in Fig. 2.12(c).
Table 2.2 Relations Between Voltages for the Three Regions Of Operation Of
A CMOS Inverter
The input/output transfer curve may now be determined by the points of
common V gs intersection in figure 2.10(c). Thus, solving for V inn = V i n p
and I dsn =I dsp gives the desired transfer characteristics of a CMOS inverter
as illustrated in figure 2.13. The switching point is typically designed to
be 50 percent of the magnitude of the supply voltage: = V DD /2. During
transition, both transistors in the CMOS inverter are momentarily "ON,"
resulting in a short pulse of current drawn from the power supply. This is
shown by the dotted line in figure 2.11
The operation of the CMOS inverter can be divided into five regions
(figure 2.13). The behavior of n- and p-devices in each of the regions may
be found by using Table 2.2.
Region A. This region is defined by 0<V in <V tn in which the n-device is
cut off (Idsn = 0), and the p-device is in the linear region.
Since Idsp=- Idsp the drain-to-source current I dsp
for the p-device is also zero.
But for V dsp = Vout - V DD ,
with V dsp = 0, the output voltage is
V out = V DD
(2.18)
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Figure 2.10 Graphical derivation of CMOS inverter characteristic

Region B. This region is characterized by V tn < Vin < V DD /2 in which the
p-device is in its nonsaturated region (Vds 0) while the n-device is in
saturation. The equivalent circuit for the inverter in this region can be
represented by a resistor for the p-transistor and a current source for the
n-transistor as shown in figure 2.12(a).
The saturation current I dsn for the n-device is obtained by setting
V gs =V in . This result in
Where
n=(n/tox)(Wn/Ln)
and
Vtn=threshold voltage of n-device
n =mobility of electrons
Wn=channel width of n-device
Ln=channel length of n-device
The current for the p-device can be obtained by noting that
Vgs=Vin-VDD
and
Vds=Vout-VDD
and therefore
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Idsp=-p (Vin-VDD-Vtp)(Vout-VDD)- (Vout-VDD)2/2
(2.19)
Where
p=(p/tox)(Wp/Lp)
and
Vtp=threshold voltage of p-device
p =mobility of electrons
Wp=channel width of p-device
Lp=channel length of p-device
Substituting I dsp =-I dsn
The output voltage V out can be expressed as
(2.20)
Figure 2.11 CMOS inverter DC transfer characteristic and operating

regions
Figure 2.12 Equivalent circuits for operating regions of a CMOS

inverter
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Region C. In this region both the n and p device are in saturation. This is
represented by schematic in figure 2.12(b) which shows two current
sources in series. The saturation currents for the two devices are given by
With
I dsp =-( p /2)(V in -V DD -V tp ) 2

I dsn =-( n /2)(V in -V tn ) 2
I dsp = -I dsn
This yields
(2.21)
By setting n= p and V tn =-V tp
We obtain
(2.22)
V in =V DD /2
Which implies that region C exists only for one value of V in . The possible
values of V out in this region can be deduced as follows
n-channel: V in -V out <V tn
V out >V in -V tn
p-channel : V in -V out >V tp
V out <V in -V tp
Combining the two inequalities results in
V in -V tn < V out < V in -V tp
(2.23)
This indicates that with V in =V DD /2, V out varies within the range shown.
An MOS device in saturation behaves like an ideal current source with
drain-to-source current being independent of V ds In reality, as V ds
increases, I ds also increases slightly thus region C has a finite slope. The
significant factor to be noted is that in region C we have two current
sources in series, which is an unstable condition. Thus a small input
voltage has a large effect at the output. This makes the output transition
very steep, which contrasts with the equivalent nMOS inverter
characteristic. The relation defined by equation is particularly useful since
it provides the basis for defining the gate threshold V inv , which
corresponds to the state where V out =V in . This region also defines the
gain of the CMOS inverter when used as a small signal amplifier.
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Region D. This region is described by V DD /2 < V in V DD +V tp . The pdevice is in saturation while the n-device is operating in its nonsaturated
region. This condition is represented by equivalent circuit shown in
figure. The two currents may be written as
I dsp = (- p /2)(V in -V DD -V tp ) 2
and
I dsn = n (V in -V tn )V out -(V out 2 /2)
with I dsp =-I dsn

The output voltage becomes
(2.24)
Region E. This region is defined by input condition V in V DD -V tp , in
which the p-device is cut off (I dsp =0), and the n-device is in the linear
mode. Here , V gsp =V in -V DD, which is more positive than V tp .
Regi
on
Condition
p-device
n-device
Output
0 V in <V tn
Nonsatura
ted
Cutoff
V out =V D
D
V tn V in <V DD /
2
Nonsatura
ted
Saturated
equation
V in =V DD /2
Saturated
Saturated
V out f(V
in )
V DD /2<V in V
DD -|V tp |
Saturated
Nonsatura
ted
Equatio
n
V in >V DD -|V tp |
Cutoff
Nonsatura
ted
V out =V S
S
Table2.3 summary of CMOS inverter operation
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The output in this region is Vout=0

(2.25)
From the transfer curve of figure 2.13 it may be seen that the transition
between the two states is very steep. This characteristic is very desirable
because the noise immunity is maximized. For convenience, the
characteristics associated with the five regions are summarized in Table
2.3.
2.8.1 n/p ratio
In order to explore the variations of the transfer characteristics as a function of
n/p, the transfer curve for several values of n/p are plotted in figure 2.15. The
gate-threshold voltage Vinv where Vin=Vout is dependent on n/p . Thus for a
given process, if we want to change n/p we need to change the channel
dimensions, i.e., channel-length L and channel-width W. from figure it can be
seen that as the ratio n/p is decreased the transition region shifts from left to
right ; however, the output voltage transition remains sharp. For the CMOS
inverter a ratio of
n/p=1
(2.26)
may be desirable since it allows a capacitive load to charge and discharge in equal
times by providing equal current-source and sink capabilities. For inverter transfer
curve is also plotted for Wn/Wp .This shows a relative shift to the left compared
with ratioed case because the p-device has inherently lower gain.
Figure 2.13 Influence of n/p on inverter DC transfer characteristic

Temperature also has an effect on the transfer characteristic of an inverter. As the
temperature of an MOS device is increased, the effective carrier mobility
decreases. This results in a decrease in , which is related to temperature T by
T-1.5
(2.27)
Therefore
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Ids T
-1.5
(2.28)
Since the voltage characteristics depend on the ratio n/p, and the mobility of
both holes and electrons are similarly affected, this ratio is independent of
temperature to a good approximation. Both Vtn and Vtp decrease slightly as
temperature increases, and the extent of region A is reduced while the extent of
region E increases. Thus the overall transfer characteristics of figure shift to the
left as temperature increases. If the temperature rises by 500C, the threshold drop
by 200mV each. This would cause a 0.2V shift in the input threshold of the
inverter.
2.8.2 Noise Margin
Noise margin is a parameter closely related to the input-output voltage
characteristics. This parameter allows us to determine the allowable noise
voltage on the input of a gate so that the output will not be affected. The
specification most commonly used to specify noise margin is in terms of
two parameters the LOW noise margin, NM L
and the HIGH noise
margin NM H . NM L is defined as the difference in magnitude between the
maximum LOW output voltage of the driving gate and the maximum input
LOW voltage recognized by the driven gate. Thus
NM L =| V ILmax - V OLmin |
(2.29)
The value of NM H is the difference in magnitude between the minimum

HIGH output voltage of the driving gate and the minimum input HIGH
voltage recognized by receiving gate. Thus
NM H =| V OHmin - V IHmin |
(2.30)
where
V IHmin =minimum HIGH input voltage
VILmax =maximum LOW input voltage
VOHmin =minimum HIGH output voltage
VOLmax =maximum LOW output voltage
Figure 2.14 Noise margin definitions
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Generally it is desirable to have VIH =VIL and for this to be a value that is midway
in the logic swing, VOL to VOH . This implies that the transfer characteristics
should switch abruptly, that is, there should be high gain in the transition region.
For the purpose of calculating noise margins, the transfer characteristic of a
typical inverter and the definition of voltage levels VIL, VOL, VIH , VOH are shown
in figure 2.15. To determine VIL note that the inverter is in region B of operation,
where the p-device is in its linear region while the n-device is in saturation. The
VIL is found by using the unity gain point at the VOL end of the characteristic. For
the inverter shown the NML is 2.3 volts while the NMH is 1.7 volts.
Note that if either NML or NMH for a gate are reduced, then the gate may be
susceptible to switching noise that may be present on the inputs. Apart from
considering a single gate, one must consider the net effect of noise sources and
noise margins on cascaded gates in assessing the overall noise immunity of a
particular system. This is the reason to keep track of noise margins.
Figure 2.15 CMOS inverter noise margins
2.9 THE TRANSMISSION GATE

The transistor connection for a complementary switch or transmission gate is
reviewed in figure 2.18. It consists of an n-channel transistor and a p-channel
transistor with separate gate connections and common source and drain connections. The control signal is applied to the gate of the n-device, and its
complement is applied to the gate of the p-device. The operation of the transmission gate can be best explained by considering the characteristics of both the
n-device and p-device as pass transistors individually. We will address this by
treating the charging and discharging of a capacitor via a transmission gate.
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Figure 2.16 Transistor connection for CMOS transmission gate

nMOS Pass Transistor:
Referring to figure2.17 (a), the load capacitor Cload is initially discharged (i.e.,
V out = VSS). With S = 0 (Vss) (i.e.,Vgs= 0 volts), I ds = 0, then Vout = VSS
irrespective of the state of the input Vin. When S = 1 (V DD ), and V in = 1, the pass
transistor begins to conduct and charges the load capacitor toward VDD, i.e.,
initially Vgs, = VDD . Since initially Vin is at a higher potential than Vout the current
flows through the device from left to right . As the output voltage approaches
VDD-Vin, the n-device begins to turn off. Load capacitor, Cload, will remain
charged when S is changed back to 0. Therefore the output voltage Vout, remains
at VDD-Vtn(Vdd). V (tnVdd) is the n-transistor body affected threshold of logic one is
degraded as it passes through the gate. With Vin=0,S=1, and Vout=VDD-VtnVdd, the
pass transistor begins to conduct and discharge the load capacitor toward VSS,
i.e., Vgs=VDD. Since initially Vin is at a lower potential than Vout , the current flows
through the device from right to left. As the output voltage approaches VSS, the n
device current diminishes. Because Vout falls to VSS, the transmission of a logic
zero is not degraded.
pMOS Pass Transistor:
Once again a similar approach can be taken in analyzing the operation of a pMOS
pass transistor as shown in figure 2.17(b). With -S =1 (S = 0), Vin = V DD , and
Vout = VSS, the load capacitor Cload remains unchanged. When -S = 0 (S = 1),
current begins to flow and charges the load capacitor toward VDD. However,
when Vin= VSS and Vout= VDD ,the load capacitor discharges through the p-device
until Vout=Vtp(Vss), at which point the transistor ceases conducting. Thus
transmission of a logic zero is somewhat degraded through the p-device. The
resultant behavior of the n-device and p-device are shown in Table 2.4. By
combining the two characteristics we can construct a transmission gate that can
transmit both a logic one and a logic zero without degradation. As can be deduced
from the discussion so far, the operation of the transmission gate requires both the
true and the complement version of the control signal.
DEVICE
TRANSMISSION OF 1 TRANSMISSION OF 0
n
poor
good
p
good
poor
Table2.4 Transmission Gate Characteristics
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The overall behavior can be expressed as:
S=0(-S=1);
n-device =off
p-device =off
Vin=VSS, Vout=Z
Vin=VDD, Vout=Z
Where Z refers to a high impedance state and
S=1(-S=0);
n-device =on
p-device =on
Vin=VSS, Vout=VSS
Vin=VDD, Vout=VDD
Vin
a
Figure2.17 nMOS and PMOS transistor operation in transmission
gate
The transmission gate is a fundamental and ubiquitous component in MOS
logic. It finds use as a multiplexing element, a logic structure, a latch
element, and an analog switch. The transmission gate acts as a voltage
controlled resistor connecting the input and the output. Figure 2.18(a)
shows a typical circuit configuration for a transmission gate in which the
output is connected to a capacitor and the input to an inverter. The control
input is shown turning the transmission gate on. That is, the gate of the nchannel transmission gate switch is changing from 0 1 and the gate of
the p-channel is changing from 1 0. First consider the case where the
control input changes rapidly, the inverter input is low (V S S ), the inverter
output is high (V DD ), and the capacitor on the transmission gate output is
discharged (V SS ). The currents that flow in this situation may be modeled
by circuit shown in figure 2.18(b) in which the currents in the pass
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transistors are monitored. In reality, the capacitor charge would be

exponential, but a linear ramp serves to show what happens to the pass
transistor currents. As V out rises, the p-transistor current follows a constant
V gs of -5 volts. That is, it starts out in saturation and transitions to the
nonsaturated case when |V gsp -V tp |<|V dsp |. The n-transistor is always in the
saturated region as V dsn =V gsn and V gsn -V tn < V dsn . When V out reaches a V tn
delow V DD , the n-transistor turns off. Thus there are three regions of
operation:
Figure 2.18 Transmission gate output characteristic for control input

changing
Region A. n saturated, p saturated (V out < |V tp |)
Region B. n saturated, p nonsaturated (|V tp |<V out <V DD -V tn )
Region C. n off, p saturated (V DD -V in <V out )
In region A, approximately the p-current as a constant current while the ncurrent varies quadradically with V out . Hence the total current is roughly
linear with V in . In region B both currents yield a sum that varies almost
linearly with V out . Finally in region C the p-current varies linearly with
V out . Thus the transmission gate acts as a resistor, with contributions to its
resistance from both n and p transistors. This can be seen in figure (Idn5+Idp5).
Similar simulations may be carried out for Vin=VSS and Vout=VDDVSS.
Another operation mode that the transmission gate encounters in lightly loaded
circuits is where the output closely follows the input, such as shown in figure
2.19(a). Figure 2.19(b) shows a model of this while figure 2.19 (c) shows the
SPICE circuit used to model this condition including current monitoring voltage
sources. Figure 2.19(d) shows the n and p pass transistor currents for Vout-Vin=0.1 volts. It can be seen that again there are three regions of operation:
Region A. n nonsaturated, p off
Region B. n nonsaturated, p nonsaturated
Region C. n off, p nonsaturated
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The total current decreases in magnitude as Vin increases until Vin=|Wtp(bodyaffected)|. Here the p-transistor turns on and in this case slows the decrease of
current. When Vin>VDD-Vtn(body-affected), the current starts to increase in magnitude
as the p current continues to increase while the n transistor is off. In this
simulation the p and n gains were matched. For the region |Vtp|<Vin<VDD-Vtn, the
transmission gate will have a roughly constant resistance. The effect of having
only one polarity transistor in the transmission gate is also seen. If only an ntransistor is used, the output will rise to an n threshold below VDD as current stops
flowing at this point. Similarly, with a single p-transistor, the output would fall to
a p threshold above VSS, as current stops flowing in the p-transistor at this point.
Note also that as either the p or n current approaches zero, the speed of any
circuit would be prejudiced. If the surrounding circuitry can deal with
these imperfect high and low values, then single polarity transmission
gates may be used. Figure 2.20, shows a plot of the transmission gate
"on" resistance for the test circuit shown in figure 2.19(c).
Figure 2.19 Transmission gate output characteristic for switched

input changing
Figure 2.20 Resistance of a transmission gate for conditions in Figure 2.19
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2.10 THE TRISTATE INVERTER

By cascade a transmission gate with an inverter the tristate inverter shown in
figure 2.21(a) is constructed. when C=0 and C=1 , the output of the inverter is in
a tristate condition. When C=1 and and -C=0 the output Z is equal to the
complement of A. The connection between the n and p transistors may be omitted
and the operation remains substantially the same. Figure 2.21(c) shows the
schematic icon that represents the tristate inverter. For the same n and p devices,
this inverter is approximately half the speed of the inverter shown in figure 2.9.
Figure 2.21 Tristate inverter
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SPECIFICATION USING VERILOG HDL
UNIT 3
HISTORY OF VERILOG
Verilog was started in the year 1984 by Gateway Design Automation Inc as a
proprietary hardware modeling language. It is rumored that the original language
was designed by taking features from the most popular HDL language of the time,
called HiLo, as well as from traditional computer languages such as C. At that
time, Verilog was not standardized and the language modified itself in almost all
the revisions that came out within 1984 to 1990.
Verilog simulator first used in 1985 and extended substantially through 1987. The
implementation of Verilog simulator sold by Gateway. The first major extension
of Verilog is Verilog-XL, which added a few features and implemented the
infamous "XL algorithm" which is a very efficient method for doing gate-level
simulation.
Later 1990, Cadence Design System, whose primary product at that time included
thin film process simulator, decided to acquire Gateway Automation System,
along with other Gateway products., Cadence now become the owner of the
Verilog language, and continued to market Verilog as both a language and a
simulator. At the same time, Synopsys was marketing the top-down design
methodology, using Verilog. This was a powerful combination.
In 1990, Cadence organized the Open Verilog International (OVI), and in 1991
gave it the documentation for the Verilog Hardware Description Language. This
was the event which "opened" the language.
3.1 BASIC CONCEPTS

3.1.1 Hardware Description Language
Two things distinguish an HDL from a linear language like C:
Concurrency:
The ability to do several things simultaneously i.e. different code-blocks
can run concurrently.
Timing:
Ability to represent the passing of time and sequence events accordingly
3.1.2 VERILOG Introduction
Verilog HDL is a Hardware Description Language (HDL).

A Hardware Description Language is a language used to describe a digital
system; one may describe a digital system at several levels.
An HDL might describe the layout of the wires, resistors and transistors
on an Integrated Circuit (IC) chip, i.e., the switch level.
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It might describe the logical gates and flip flops in a digital system, i.e.,
the gate level.
An even higher level describes the registers and the transfers of vectors of
information between registers. This is called the Register Transfer Level
(RTL).
Verilog supports all of these levels.
A powerful feature of the Verilog HDL is that you can use the same
language for describing, testing and debugging your system.
3.1.3 VERILOG Features

Strong Background:
Supported by OVI, and standardized in 1995 as IEEE std 1364
Industrial support:
Fast simulation and effective synthesis (85% were used in ASIC
foundries by EE TIMES)
Universal :
Allows entire process in one design environment (including
analysis and verification)
Extensibility :
Verilog PLI that allows for extension of Verilog capabilities
3.1.4 Design Flow

The typical design flow is shown in figure 3.1,
Design Specification
Specifications are written first-Requirement/needs about the project

Describe the functionality overall architecture of the digital circuit to be
designed.
Specification: Word processor like Word, Kwriter, AbiWord and for drawing
waveform use tools like wave former or test bencher or Word.
RTL Description
Conversation of Specification in coding format using CAD Tools.
Coding Styles:
Gate Level Modeling
Data Flow Modeling
Behavioral Modeling
RTL Coding Editor : Vim, Emacs, conTEXT, HDL TurboWriter
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Figure 3.1 VLSI Design Flow
I0
I1
I2
Out
I3
S0
S1
Figure 3.2 Black Box View of 4:1 MUX
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Functional Verification &Testing
Comparing the coding with the specifications.

Testing the Process of coding with corresponding inputs and outputs.
If testing fails once again check the RTL Description.
Simulation: Modelsim, VCS, Verilog-XL,Xilinx.
Figure 3.3 Simulation Output View of 4:1 MUX Using Modelsim Wave form
Viewer
Logic Synthesis
Conversation of RTL description into Gate level -Net list form.
Description of the circuit in terms of gates and connections.
Synthesis: Design Compiler, FPGA Compiler, Synplify Pro, Leonardo
Spectrum, Altera and Xilinx.
Figure 3.4 Synthesis of 4:1 MUX Using Leonardo Spectrum

Logical Verification and Testing
Functional Checking of HDL coding by simulation and synthesis. If fails
check the RTL description.
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Floor Planning Automatic Place and Route

Creation of Layout with the corresponding gate level Net list.
Arrange the blocks of the net list on the chip
Place & Route: For FPGA use FPGA' vendors P&R tool. ASIC tools
require expensive P&R tools like Apollo. Students can use LASI, Magic
Physical Layout
Physical design is the process of transforming a circuit description into the
physical layout, which describes the position of cells and routes for the
interconnections between them.
Layout Verification
Verifying the physical layout structure.
If any modification once again check Floor Planning Automatic Place and
Route and RTL Description.
Implementation
Final stage in the design process.
Implementation of coding and RTL in the form of IC.
Figure 3.5 Layout view of a system

3.1.5 Design Hierarchies
3.1.5.1Bottom up Design
The Traditional method of electronic design is bottom up. Each design is
performed at the gate level using the standard gates .With increasing complexity
of new designs this approach is nearly impossible to maintain. It gives way to new
structural, hierarchical design methods. Without these new design practices it
would be impossible to handle the new complexity
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Figure 3.6 Bottom Up Design

3.1.5.2 Top-Down Design
A real top down design allows early testing, easy change of different
technologies, a structured system design and offers many other advantages. But it
is very difficult to follow a pure top-down design. Due to this fact most designs
are mix of both the methods. Implementing some key elements of both design
styles
Figure 3.7 Top-Down Design

3.1.6 Lexical Conventions
The basic lexical conventions used by Verilog HDL are similar to those in the C
programming language. Verilog contains a stream of tokens. Tokens can be
comments, delimiters, numbers, strings, identifiers, and keywords. Verilog HDL
is a case-sensitive language. All keywords are in lower case.
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3.1.6.1 Whitespace
White space can contain the characters for blanks, tabs, newlines, and form feeds.
These characters are ignored except when they serve to separate other tokens.
However, blanks and tabs are significant in strings.
White space characters are:
Blank spaces (\b)
Tabs(\t)
Carriage returns(\r)
New-line (\n)
Form-feeds (\a)
Example
3.1.6.2 Comments
Comments can be inserted in the code for readability and documentation. There
are two forms to introduce comments.
Single line comments begin with the token // and end with a carriage
return
Multi line comments begin with the token /* and end with the token */
Example
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3.1.6.3 Identifiers and Keywords

Identifiers are names used to give an object, such as a register or a function or a
module, a name so that it can be referenced from other places in a description.
Keywords are reserved to define the language constructs.
Identifiers must begin with an alphabetic character or the underscore
character (a-z A-Z _ )
Identifiers may contain alphabetic characters, numeric characters, the
underscore, and the dollar sign (a-z A-Z 0-9 _ $ )
Identifiers can be up to 1024 characters long.
Keywords are in lowercase.
Examples of legal identifiers
data_input mu
clk_input my$clk
i386
Examples of keywords
always
begin
end
3.1.6.4 Escaped Identifiers

Verilog HDL allows any character to be used in an identifier by escaping the
identifier. Escaped identifiers provide a means of including any of the printable
ASCII characters in an identifier (the decimal values 33 through 126, or 21
through 7E in hexadecimal).
Escaped identifiers begin with the back slash ( \ )

Entire identifier is escaped by the back slash.
Escaped identifier is terminated by white space (Characters such as
commas, parentheses, and semicolons become part of the escaped
identifier unless preceded by a white space)
Terminate escaped identifiers with white space, otherwise characters that
should follow the identifier are considered as part of it.
3.1.7 Numbers in Verilog

Numbers in Verilog can be specified constant numbers in decimal, hexadecimal,
octal, or binary format. Negative numbers are represented in 2's complement
form. When used in a number, the question mark (?) character is the Verilog
alternative for the z character. The underscore character (_) is legal anywhere in a
number except as the first character, where it is ignored.
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3.1.7.1 Integer Numbers

Verilog HDL allows integer numbers can be specified as
Sized or unsized numbers (Unsized size is 32 bits)

In a radix of binary, octal, decimal, or hexadecimal
Radix and hex digits (a,b,c,d,e,f) are case insensitive
Spaces are allowed between the size, radix and value
Integer numbers are represented as <size><base format> <number>

<size> is wrriten only in decimal and specifies the number of bits in the number.
Legal base formats are decimal (d or D), hexadecimal(h or H), binary (b or
B) and octal (o or O). the number is specified as consecutive digits from
0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f. only a subset of these digits is legal for a particular
base. Uppercase letters are legal for number specification.
4b1111 this is a 4-bit binary number
12habc this is a 12-bit hexadecimal number
16d255 this is a 16-bit decimal number
8o44-this is 8 bit octal number
3.1.7.2 Real Numbers
Verilog supports real constants and variables

Verilog converts real numbers to integers by rounding
Real Numbers can not contain 'Z' and 'X'
Real numbers may be specified in either decimal or scientific notation
< value >.< value >
< mantissa >E< exponent >
Real numbers are rounded off to the nearest integer when assigning to an
integer.
Example
Real
Number
1.2
0.6
3.5E6
Decimal
notation
1.2
0.6
3,500000.0
3.1.7.3 Signed and Unsigned Numbers

Verilog supports both types of numbers, but with certain restrictions. Like in C
language Verilog don't have int and unint types to say if a number is signed
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integer or unsigned integer. Any number that does not have negative sign prefix is
a positive number. Or indirect way would be "Unsigned".
Negative numbers can be specified by putting a minus sign before the size for a
constant number, thus they become signed numbers. Verilog internally represents
negative numbers in 2's complement format. An optional signed specifier can be
added for signed arithmetic.
Example
Number
32'hDEAD_BEEF
-14'h1234
Description
Unsigned
or
signed
positive number
Signed negative number
Example
module signed_number;
reg [31:0] a;
initial begin
a = 14'h1234;
$display ("Current Value of a = h", a);
a = -14'h1234;
a = 32'hDEAD_BEEF;
a = -32'hDEAD_BEEF;
#10 $finish;
end
endmodule
3.1.8 Strings
A string is a sequence of characters that are enclosed by double quotes. The
restriction on a string is that it must be contained on a single line, that is, without
a carriage return. It cannot be on multiple lines, Strings are treated as a sequence
of one-byte ASCII values.
Examples
hello Verilog world
a/b
aa+a
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3.1.9 Data types

Every signal has a data type associated with it:
Explicitly declared with a declaration in your Verilog code.

Implicitly declared with no declaration when used to connect structural
building blocks in your code. Implicit declaration is always a net type
"wire" and is one bit wide.
3.1.9.1 Data Types Value set

Verilog supports four values and eight strengths to model the functionality of real
hardware. The four levels are listed in table
Value level
0
1
x
z
Condition in hardware circuits

logic zero, false condition
logic one, true condition
unknown value
High impedance, floating state
3.1.9.2 Nets
Nets represent connections between hardware elements. Just as in real circuits,
nets have values continuously driven on them by the outputs of devices that they
are connected to.
Types of Nets
Each net type has a functionality that is used to model different types of hardware
(such as PMOS, NMOS, CMOS, etc)
Example
Net Data Type
wire, tri
wor, trior
wand, triand
tri0, tri1
supply0, supply1
Trireg
Functionality
Interconnecting wire - no special resolution
function
Wired outputs OR together (models ECL)
Wired outputs AND together (models opencollector)
Net pulls-down or pulls-up when not driven
Net has a constant logic 0 or logic 1 (supply
strength)
Retains last value, when driven by z (tristate).
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Register Data Types
Registers store the last value assigned to them until another assignment
statement changes their value.
Registers represent data storage constructs.
You can create regs arrays called memories.
Register data types are used as variables in procedural blocks.
A register data type is required if a signal is assigned a value within a
procedural block
Procedural blocks begin with keyword initial and always.
Example
Data Types
Functionality
reg
Unsigned variable
integer
time
real
Signed variable - 32 bits

Unsigned integer - 64 bits
Double precision floating point variable
3.1.9.3 Vectors
Nets or reg data types can be declared as vectors. If bit width is not specified, the
default is scalar (1-bit).Vectors can be declared at [high#: low#] or [low#: high#],
but the left number in the squared brackets is always the most significant bit of
the vector.
Examples
wire a // scalar net variable default
wire [7:0]bus; // 8-bit bus
wire [31:0] busA, busB, busC; // 3 buses of 32-bit width
reg clock // scalar register
busA[7]; // bit #7 of vector busA
bus [2:0] // three least significant bits of vector bus
3.1.9.4 Integer, Real and Time Register Data Types

Integer
An integer is a general purpose register data type used for manipulating
quantities. Integers are declared by the keyword integer. Although it is possible
to use reg as a general-purpose variable, it is more convenient to declare an
integer variable for purposes such as counting. The default width for an integer is
the host-machine word size, which is implementation specific but is at least 32
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bits. Registers declared as data type reg store values as unsigned quantities,
whereas integers store value as signed quantities.
Example
integer counter; // general purpose variable used as a counter
initial
counter=-1; // A negative one is stored in the counter
Real
Real number constants and real register data types are declared with the keyword
real. They can be specified in decimal notation (e.g., 5.12) or in scientific
notation (e.g., 5e6, which is 5x10^6). Real numbers cannot have a range
declaration, and their default value is 0. When a real value is assigned to an
integer, the real number is rounded off to the nearest integer.
Example
real delta; // define a real variable called delta
initial
begin
delta=4e10; // delta is assigned in scientific notation
delta=2.13 ; // delta is assigned a value 2.13
end
integer i; // define an integer i
Time
Verilog simulation is done with respect to simulation time. A special time register
data type is used in Verilog to store simulation time. A time variable is declared
with the keyword time. The width for time register data types is implementation
specific but is at least 64 bits. The system function $time is invoked to get the
current simulation time.
Example
time save_sim_time; // define a time variable save_sim_time
initial
save_sim_time=$time; // save the current simulation time
3.1.9.5 Arrays
Arrays are allowed in Verilog for reg, integer, time and vector register data types.
Arrays are not allowed for real variables. Arrays are accessed by
<array_name>[<subscript>]. Multidimensional arrays not permitted in Verilog.
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Example
integer count[7:0]; // an array of 8 count variables
reg bool[31:0]; // array of 32 one-bit Boolean register variables
integer matrix[4:0][4:0]; // illegal declaration Multidimensional array
3.1.9.6 Memories
In digital simulation, one often needs to model register files, RAMs and ROMs.
Memories are modeled in Verilog simply as an array of registers. Each element of
the array is known as a word. Each word can be one or more bits. It is important
to differentiate between n 1-bit registers and one n-bit register. A particular word
in memory is obtained by using the address as a memory array subscript.
Example
reg mem1bit[0:1023]; // memory mem1bit with 1K 1-bit words
reg [7:0]membyte[0:1023]; // memory membyte with 1K 8-bit words
3.1.9.7 Parameters
Verilog allows constants to be defined in a module by the keyword parameter.
Parameters cannot be used as variables. Parameter values for each module
instance can be overridden individually at compile time. This allows the module
instances to be customized.
Example
parameter port_id = 5; //Defines a constant port_id
parameter cache_line_width= 256; // Constant defines width of cache line
3.1.9.8 Strings
Strings can be stored in reg. The width of the register variables must be large
enough to hold the string. Each character in the string takes up 8 bits (1 byte).
If the width of the register is greater than the size of the string, Verilog fills bits
to left of the string with zeros. If the register width is smaller than the string
width, Verilog truncates the leftmost bits of the string. It is always safe to
declare that is slightly wider than necessary.
Example
reg [8*81:1] string_value; // declare a variable that is 18 bytes wide
initial
string_value=hello Verilog course team; // string can be stored in variable
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3.2 MODULES
A module in Verilog consists of distinct parts as shown in figure 1.8. A
module definition always begins with the keyword module. The module name,
port list, port declarations, and optional parameters must come first in a module
definition. Port list and port declarations are present only if the module has any
ports to interact with the external environment. The five components within a
module are;
variable declarations,
dataflow statements
instantiation of lower modules
behavioral blocks
tasks or functions.
These components can be in any order and at any place in the module definition.
The endmodule statement must always come last in a module definition. All
components except module, module name, and endmodule are optional and can
be mixed and matched as per design needs. Verilog allows multiple modules to be
defined in a single file. The modules can be defined in any order in the file.
Figure 3.8 Components of Verilog Module
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Example Module Structure :

module <module name>(<module_terminals_list>);
..
<module internals>
.
Endmodule
3.2.1 Instances
A module provides a template from which you can create actual objects. When a
module is invoked, Verilog creates a unique object from the template. Each object
has its own name, variables, parameters and I/O interface. The process of creating
objects from a module template is called instantiation, and the objects are called
instances. In Example below, the top-level block creates four instances from the Tflip-flop (T_FF) template. Each T_FF instantiates a D_FF and an inverter gate.
Each Instance must be given a unique name.
Example
// Define the top-level module called ripple carry
// counter. It instants 4 T-filpflops.
// four instances of the module T_FF are created. Each has a unique name.
// each instance is passed a set of signals
module ripple_carry_counter(q,clk,reset);
output [3:0]q;
input clk,reset;
T_FF tff0(q[0],clk,reset);
T_FF tff1(q[1],q[0],reset);
endmodule
// define the module T_FF. it instantiates a D-filpflop.
module T_FF(q,clk,reset);
output q;
input clk,reset;
wire d;
D_FF dff0(q,d,clk,reset);
not n1(d,q);
endmodule
3.3 PORTS
Ports provide the interface by which a module can communicate with its
environment. For example, the input/output pins of an IC chip are its ports. The
environment can interact with the module only through its ports. The internals
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of the module are not visible to the environment. This provides a very
powerful flexibility to the designer. The internals of the module can be
changed without affecting the environment as long as the interface is not
modified. Ports are also referred to as terminals.
3.3.1 Port Declaration
All ports in the list of ports must be declared in the module. Ports can be
declared as follows
Verilog Keyword
input
output
inout
Type of Port
Input port
Output port
Bidirectional port
Each port in the port list is defined as input, output, or inout, based on the
direction of the port signal.
3.3.2 Port Connection Rules
One can visualize a port as consisting of two units, one unit that is internal to
the module another that is external to the module. The internal and external
units are connected. There are rules governing port connections when modules
are instantiated within other modules. The Verilog simulator complains if any
port connection rules are violated. These rules are summarized in figure 1.9.
Figure 3.9 Port connection Rules

Inputs:
Internally must be of net data type (e.g. wire)

Externally the inputs may be connected to a reg or net data type
Internally may be of net or reg data type

Externally must be connected to a net data type
Internally must be of net data type (tri recommended)

Externally must be connected to a net data type (tri recommended)
Outputs:
Inouts:
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3.3.3 Ports Connection to External Signals

There are two methods of making connections between signals specified in the
module instantiation and ports in a module definition. The two methods cannot be
mixed.
Port by order list

Port by name
Port by order list

Connecting port by order list is the most intuitive method for most beginners. The
signals to be connected must appear in the module instantiation in the same order
as the ports in the ports list in the module definition.
Syntax for instantiation with port order list:
module_name instance_name (signal, signal...);
From the below example, notice that the external signals a, b, out appear in
exactly the same order as the ports a, b, out in the module defined in adder below.
Example
Port by name
For larger designs where the module have ,say 5o ports , remembering the order
of the ports in the module definition is impractical and error prone. Verilog
provided the capability to connect external signals to ports by the port names,
rather than by position.
Syntax for instantiation with port name:
module_name instance_name (.port_name(signal), .port_name (signal) );
From the below example, note that the port connections in any order as long as
the port name in the module definition correctly matches the external signal.
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Example
Another advantage of connecting ports by name is that as long as the port name is
not changed, the order of ports in the port list of a module can be rearranged
without changing the port connections in the module instantiations.
3.4 GATE DELAYS

In real circuits, logic gates have delays associated with them. Gate delays
allow the Verilog user to specify delays through the logic circuits. Pin-to-pin
delays can also be specified in Verilog.
3.4.1 Rise, Fall, and Turn-off Delays
There are three types of delays from the inputs to the output of a primitive gate
Rise delay
The rise delay is associated with a gate output transition to a 1 from another
value.
Fall delay
The fall delay is associated with a gate output transition to a 0 from another
value.
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Turn-off delay
The turn-off delay is associated with a gate output transition to the high
impedance value (z) from another value.
If the value changes to X, the minimum of the three delays is considered.
Three types of delay specifications are allowed. If only one delay is specified,
this value is used for all transitions. If two delays are specified, they refer to the
rise and fall delay values. The turn-off delay is the minimum of the two delays.
If all three delays are specified, they refer to rise, fall, and turn-off delay. If no
delays are specified, the default value is zero.
Example for Delay Specification
3.4.2 Min/Typ/Max Values

Verilog provides an additional level of control for each type of delay
mentioned. For each type of delay-rise, fall, and turn-off-three values, min, typ
and, max can be specified. Any one value can be chosen at the start of the
simulation. Min/ typ /max values are use to model devices whose delays vary
within a minimum and maximum range because of the IC fabrication process
variations.
Min value
The min value is the minimum delay value that the designer expects the gate
to have.
Typ value
The typ value is the typical delay value that the designer expects the gate to
have.
Max value
The max value is the maximum delay value that the designer expects the gate to
have.
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Min, typ, or max values can he chosen at Verilog run time. Method of
choosing a min/typ/max value may vary for different simulators or o p e r a t i n g
systems. (For Verilog-XLTM, the values are chosen by specifying options
+ m a x d e l a y , +typdelay, and +mindelays at run time. If no option
is specified, the typical delay value is the default). This allows the designers the
f l e x i b i l i t y of building three delay values for each transition into their
design. The designer can experiment with delay values without modifying the
design.
Examples of Min, Max and Typical Delay Values
3.5 MODELING CONCEPTS

Verilog is both a behavioral and a structural language. Internals of each module to
be defined at four levels of abstraction, depending on the needs of the design. The
module behaves identically with the external environment irrespective of the level of
abstraction at which the module is described. The internals of the module hidden
from the environment. Thus, the level of abstraction to describe a module can be
changed without any change in the environment. The levels are defined below
Behavioral or algorithmic level
This is the highest level of abstraction provided by Verilog HDL. A module can
be implemented in terms of the desired design algorithm without concern for the
hardware implementation details. Designing at this level is very similar to C
programming
Dataflow level
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At this level the module is designed by specifying the data flow. The designer is
aware of how data flows between hardware registers and how the data is
processed in the design.
Gate level
The module is implemented in terms of logic gates and interconnections
between these gates. Design at this level is similar to describing a design in
terms of a gate-level logic diagram.
Switch level
This is the lowest level of abstraction provided by Verilog. A module can be
implemented in terms of switches, storage nodes, and the interconnections
between them. Design at this level requires knowledge of switch-level
implementation details.
Verilog allows the designer to mix and match all four levels of abstractions in a
design. In the digital design community, the term register transfer level (RTL) is
frequently used for a Verilog description that uses a combination of behavioral and
dataflow constructs and is acceptable to logic synthesis tools.
If a design contains four modules, Verilog allows each of the modules to be written
at a different level of abstraction. As the design matures, most modules are replaced
with gate-level implementations.
,
Normally, the higher the level of abstraction, the more flexible and technology
Independent the design. As one goes lower toward switch-level design, the design
becomes technology dependent and inflexible. A small modification can cause a
significant number of changes in the design. Comparing the analogy with C
programming and assembly language programming. It is easier to program in higherlevel language such as C. The program can be easily ported to any machine.
However, if the design at the assembly level, the program is specific for that
machine and cannot be easily ported to another machine.
3.6 SWITCH LEVEL MODELING

Usually, transistor level modeling is referred to model in hardware
structures using transistor models with analog input and output signal
values. On the other hand, gate level modeling refers to modeling hard-ware
structures wing gate models with digital input and output signal values between
these two modeling schemes is referred to as switch level modeling. At this
level, a hardware component is described
at the transistor level, but transistors only exhibit digital behavior and their input,
and output signal values are only limited to digital values. At the switch level,
transistors behave as on-off switches- Verilog uses a 4 value logic value system,
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so Verilog switch input and output signals can take any of the four 0, 1, Z, and X
logic values.
3.6.1 Switch level primitives
Table 1.1 shows Verilog switch and pull primitives. Switches are unidirectional or
bidirectional and resistive or nonresistive. For each group those primitives that
switch on with a positive gate {like an NMOS transistor} and those that switch
on with a negative gate {like a PMOS transistor}. Switching on means that logic
values flow from input transistor to its input. Switching off means that the output
of a transistor is at Z level regardless of its input value.
A unidirectional transistor passes its input value to its output when it is switched
on. A bidirectional transistor conducts both ways. A resistive structure reduces the
strength of its input logic when passing it to its output. In addition to switch level
primitives, pull-primitives that are used as pull-up and pull-down resistors for tristate outputs.
Table 3.1
Figure 1.10 shows standard switches; pull primitives, and tri-state gates that
behave like nmos and pmos. Instantiations of these primitives and their
corresponding symbols are also shown. Cmos is a unidirectional transmission gate
with a true and complemented control lines. Nmos and pmos are unidirectional
pass gates representing NMOS and PMOS transistors respectively.
When such a resistive switch conducts, the strength of its output signal is one or
two levels below that of its input signal. Delay values for transition to 1, transition
to 0, and transition to Z can be specified in the #(to-1, to-0, to-z) format for
unidirectional switches. Bidirectional tran switches shown in figure are
functionally equivalent to unidirectional switches shown in the adjacent column
of this figure. When conducting, the two inout ports are connected and logic
values flow in both directions.
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3.6.2 MOS switches

Two types of MOS switches can be defined with the keywords nmos
and pmos. Keyword nmos is used to model NMOS transistors,
Keyword pmos is used to model PMOS transistors. The symbols for
nmos and pmos switches are shown in figure 3.11.
Figure 3.10
Figure 3.11 PMOS and NMOS Switches

In Verilog nmos and pmos switches are instantiated as shown in below,
nmos n1(out, data, control); // instantiate a nmos switch
pmos p1(out, data, control); // instantiate a pmos switch
Since switches are Verilog primitives, like logic gates, the name of the instance is
optional. Therefore, it is acceptable to instantiate a switch without assigning an
instance name.
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nmos (out, data , control); // instantiate nmos switch ; no instance name

pmos (out, data, control); // instantiate pmos switch; no instance name
Value of the out signal is determined from the values of data and control signals.
Logic tables for out are shown in table. Some combinations of data and control
signals cause the gates to output to either a 1 or 0 or to an z value without a
preference for either value. The symbol L stands for 0 or Z; H stands for 1 or z.
Table 3.2 Logic Tables of NMOS and PMOS

Thus, the nmos switch conducts when its control signal is 1. If control signal is 0,
the output assumes a high impedance value. Similarly a pmos switch conducts if
the control signal is 0.
3.6.3 CMOS Switches
CMOS switches are declared with the keyword cmos. A cmos device can be
modeled with a nmos and a pmos device. The symbol for a cmos switch is shown
in figure
Figure 3.12 CMOS switch

A CMOS switch is instantiated as shown in below,
cmos cl(out, data, ncontrol, pcontrol);//instantiate cmos gate
or
cmos (out, data, ncontrol, pcontrol); //no instance name given
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The ncontrol and pcontrol are normally complements of each other. When the
ncontrol signal is 1 and pcontrol signal is 0, the switch conducts. If ncontrol is
0 and pcontrol is 1, the output of the switch is high impedance value. The cmos
gate is essentially a combination of two gates: one nmos and one pmos. Thus
the cmos instantiation shown above is equivalent to the following.
nmos (out, data, ncontrol); //instantiate a nmos switch
pmos (out, data, pcontrol); //instantiate a pmos switch
Since a cmos switch is derived from nmos and pmos switches, it is possible
derive the output value from Table 1.2, given values of data, ncontrol, and
pcontrol signals.
3.6.4 Bidirectional Switches
NMOS, PMOS and CMOS gates conduct from drain to source. It is important to
have devices that conduct in both directions. In such cases, signals on either side
of the device can be the driver signal. Bidirectional switches are provided for
this purpose. Three keywords are used to define bidirectional switches: tran,
tranif0, and tranifl.
Symbols for these switches are shown in figure 3.13 below.
Figure 3.13 Bidirectional switches

The tran switch acts as a buffer between the two signals inoutl and inout2. Either
inoutl or inout2 can be the driver signal. The tranif0 switch connects the two
signals inoutl and inout2 only if the control signal is logical 0. If the control
signal is a logical 1, the nondriver signal gets a high impedance value z. The
driver signal retains value from its driver. The tranifl switch conducts if the
control signal is a logical 1.
These switches are instantiated as shown in below
tran tl(inoutl, inout2); //instance name tl is optional
tranifO (inoutl, inout2, control); //instance name is not specified
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tranifl (inoutl, inout2, control); //instance name is not specified
Bidirectional switches are typically used to provide isolation between buses or

signals.
3.6.5Power and Ground
The power (Vdd, logic 1) and Ground (Vss, logic 0) sources are needed when
transistor-level circuits are designed. Power and ground sources are defined with
keywords supplyl and supply0.
Sources of type supplyl are equivalent to Vdd in circuits and place a logical 1
on a net. Sources of the type supply0 are equivalent to ground or Vss and place
a logical o on a net. Both supplyl and supply0 place logical 1 and o
continuously on nets throughout the simulation.
Sources supply1 and supply0 are shown below,
supply1 vdd;
supply0 gnd;
assign a=vdd; // connect a to vdd
assign b=gnd; // connect b to gnd
3.6.6 Resistive Switches

MOS, CMOS, and bidirectional switches discussed before can be modeled
corresponding resistive devices. Resistive switches have higher source-to-drain
impedance than regular switches and reduce the strength of signals passing
through them. Resistive switches are declared with keywords that have x
prefixed to the corresponding keyword for the regular switch. Resistive have the
same syntax as regular switches
rnmos
rcmos
rtran
rpmos
rtranif0
rtranifl
There are two main differences between regular switches and resistive switches:
their source-to-drain impedances and the way they pass signal strengths.
Resistive devices have a high source-to-drain impedance. Regular to have a
low source-to-drain impedance.
Resistive switches reduce signal strengths when signals pass through them.
The changes are shown below. Regular switches retain strength levels of
signals from input to output. The exception is that if the input is of supply,
the output is of strength strong. Table 1.3 shows the strength reduction due
to resistive switches
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Input strength
supply
strong
pull
weak
large
medium
small
high
Output strength
pull
pull
weak
medium
medium
small
small
high
Table 3.3 Strength reduction by resistive switches

3.8 Delay Specification on Switches
3.8.1 MOS and CMOS switches
Delays can be specified for signals that pass through these switch-level elements.
optional and appear immediately after the keyword for the switch.
Switch element
Delay
specification
Pmos,nmos,rpmo
s,rnmos
Zero (no delay)

One (same
delay on all
transitions)
Examples
pmos
p1(out,data,control);
pmos#(1)
Two (rise,fall)
Three
(rise,fall,turnof
f)
Cmos,rcmos
Zero, one,two
or three delays
(same as
above)
nmos #(1,2)
nmos #(1,3,2)
cmos #(5)
c2(out,data,nctrl,pctrl);
cmos #(1,2)
c1(out,data,nctrl,pctrl);
Table 3.4 Delay Specification on NMOS and CMOS switches
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3.8.2 Bidirectional pass switches

Delay specification is interpreted slightly differently for bidirectional pass
switches. These switches do not delay signals passing through them. Instead, they
have turn-on and turn-off delays while switching. Zero, one, or two delays can b
specified for bidirectional switches, as shown in Table 3.5.
Switch
element
Delay
specification
tran, rtran
No
delay
specification
allowed
tranif1,rtranif1
Zero (no delay)
tranif0,rtranif0
One (both turn-on

and turn-off)
Two
(turn-on,
turn-off)
Examples
rtranif0
rt1(inout1,inout2,control);
tranif0#(3)
T(inout1,inout2,control);
tranif1#(1,2)
t1(inout1,inout2,control);
Table 3.5 Delay Specification for Bidirectional Switches

Example-CMOS Nor Gate
Verilog has a nor gate primitive, to design nor gate, using CMOS switches, the
gate and the switch-level circuit diagram for the nor gate is shown in Figure 1.14
Figure 3.14 Gate and Switch diagram for Nor gate
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Switch level Verilog for Nor gate

module my_nor(out, a, b);
output out;
input a,b;
wire c;
supply1 pwr;
supply0 gnd;
pmos (c,pwr,b);
pmos (out,c,a);
nmos (out, gnd, a);
nmos (out,gnd, b);
endmodule
Example-CMOS NAND
Figure 3.14 Switch diagram for NAND gate

module my_nand (Out,A,B);
input A,B;
ouput Out;
wire C;
supply1 Vdd;
supply0 Vss;
pmos (Out,A,Vdd)
pmos (Out,B,Vdd);
nmos (Out,A,C);
nmos(C,Vss,B);
endmodule
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Example -2-to-1 Multiplexer

A 2-to-1 multiplexer can be defined with CMOS switches. The circuit diagram for
the multiplexer is shown in figure 3.15
Figure 3.15 2-to-1 Multiplexer, using switches

The 2-to-1 multiplexer passes the input I0 to output OUT if S=0 and passes I1 to
OUT if S=1. The switch-level description for the 2-to-1 multiplexer is shown in
below
module my_mux(out, s, i0, i1);
output out;
input s,i0,i1;
wire sbar;
my_nor nt(sbar, s , s );
cmos (out, io , sbar, s);
cmos (out, i1, s, sbar);
endmodule
Example-Simple CMOS Flip-Flop

Combinatorial elements are designed in the previous examples. Let us now define
a memory element which can store a value. The diagram for a level-sensitive
CMOS flip-flop is shown in figure 3.16.
The switches C1 and C2 are CMOS switches. Switch C1 is open if clk=1, and
switch C2 is open if clk=0. Complement of the clk is fed to the ncontrol input of
C2. The CMOS inverters can be defined by using MOS switches as shown in
figure 3.17
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Figure 3.16 CMOS flip-flop
Figure 3.17CMOS inverter

The Verilog module description for the CMOS inverter from the switch-level
circuit from figure 3.17 is given below ,
module my_not(out,in);
output out;
input in;
supply1 pwr;
supply0 gnd;
pmos (out, pwr, in);
nmos (out, gnd, in);
endmodule
The CMOS flip-flop can be defined using the CMOS switches and my_hot
inverters. The Verilog description for the CMOS flip-flop is given below.
module cff(q, qbar, d, clk);
output q,qbar;
input d,clk;
wire e;
wire nclk;
my_not nt(nclk, clk);
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cmos (e, d, clk, nclk);

cmos (e, q, nclk, clk);
my_not nt1(qbar,e);
my_not nt2(q, qbar);
endmodule
3.9 GATE LEVEL MODELING

Verilog has built in primitives like gates, transmission gates, and switches. These
are rarely used in design (RTL Coding), but are used in post synthesis world for
modeling the ASIC/FPGA cells; these cells are then used for gate level
simulation. Also the output netlist format from the synthesis tool, which is
imported into the place and route tool, is also in Verilog gate level primitives.
3.9.1 Gate Types
A logic circuit can be designed by use of logic gates. Verilog supports logic gates
as predefined primitives. Theses primitives are instantiated like modules except
that they are predefined in Verilog and do not need a module definition. All
circuit can be designed by using basic gates. There are two classes of basic gates:
and/or gates and buf/not gates.
And/Or Gates
and/or gates have one scalar output and multiple scalar inputs. The first terminal in
the list of gate terminals is an output and the other terminals are inputs. The output
of a gate is evaluated as soon as one of the inputs changes. The and/or gates
available in Verilog are shown below.
and
or
nand nor
xor
xnor
The corresponding logic symbols for these gates are shown in figure 1.18. We
consider gates with two inputs.
These gates are instantiated to build logic circuits in Verilog. Examples of gate
Instantiations are shown below. In the below example, for all instances, OUT is
connected to the output out, and IN1 and IN2 are connected to the two inputs i1 and
i2 of the gate primitives.
Figure 1.18 Gates symbol
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The instance name does not need to be specified for primitives. More than two
inputs can be specified in gate instantiation Gates with more two inputs are
instantiated by simply adding more ports in the gate instantiation. Verilog
automatically instantiates the appropriate gate.
Example Gate Instantiation of And/Or gates
The truth tables for these gates are given below, assuming two inputs. Outputs of
gates with more than two inputs are computed by applying the truth table
iteratively.
Buf/Bufif1/Bufif0/Not/Notfif1/Notfif0 Gates
Buf/not gates have one scalar input and one or more scalar output. The lasts
terminal in the port list is connected to the input. Other terminals are connected
the outputs.
Bufif1, Bufif0, Notif1, Notifo gates propagate only if their control signal is
asserted. Such a situation is applicable when multiple drivers drive the signal.
These drivers are designed to drive the signal on mutually exclusive control.
They propagate z if their control signal is deasserted.
buf
bufif1
bufif1
not
notfif1
bufif0
__________________________________________
Figure 3.19 Gates But, Not, Bufif1, Bufif0, Notif1, Notifo
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Table 1.6Truth Table

Example Gate Instantiation of Buf/Not gates
From the above example, notice that theses gates can have multiple outputs but
exactly one inputs, which is the last terminal in the port list.
The truth tables for these gates are shown below.
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Examples
AND Gate from NAND Gate
Figure 3.20 Structural model of AND gate from two NANDS

module and_from_nand();
reg X, Y;
wire F, W;
// Two instantiations of the module NAND
nand U1(W,X, Y);
nand U2(F, W, W);
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// Testbench Code
initial begin
$monitor ("X = %b Y = %b F = %b", X, Y, F);
X = 0;
Y = 0;
#1 X = 1;
#1 Y = 1;
#1 X = 0;
#1 $finish;
end
endmodule
Simulation Output
X=0Y=0F=0
X=1Y=0F=0
X=1Y=1F=1
X=0Y=1F=0
D-Flip flop from NAND Gate
Figure 3.20 Structural model of D Flip-flop from NAND Gate

module dff_from_nand();
wire Q,Q_BAR;
reg D,CLK;
nand U1 (X,D,CLK) ;
nand U2 (Y,X,CLK) ;
nand U3 (Q,Q_BAR,X);
nand U4 (Q_BAR,Q,Y);
// Test bench
initial begin
$monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR);
CLK = 0;
D = 0;
#3 D = 1;
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#3 D = 0;
#3 $finish;
end
always #2 CLK = ~CLK;
endmodule
Simulation Output
CLK = 0 D = 0 Q = x Q_BAR = x
CLK = 1 D = 0 Q = 0 Q_BAR = 1
CLK = 1 D = 1 Q = 1 Q_BAR = 0
CLK = 0 D = 1 Q = 1 Q_BAR = 0
CLK = 1 D = 0 Q = 0 Q_BAR = 1
CLK = 0 D = 0 Q = 0 Q_BAR = 1
Multiplex from Primitives
Figure 3.20 Structural model of Multiplex from Primitives

module mux_from_gates ();
reg c0,c1,c2,c3,A,B;
wire Y;
//Invert the sel signals
not (a_inv, A);
not (b_inv, B);
// 3-input AND gate
and (y0,c0,a_inv,b_inv);
and (y1,c1,a_inv,B);
and (y2,c2,A,b_inv);
and (y3,c3,A,B);
// 4-input OR gate
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or (Y, y0,y1,y2,y3);
// Test bench
initial begin
$monitor (
"c0 = %b c1 = %b c2 = %b c3 = %b A = %b B = %b Y = %b",
c0, c1, c2, c3, A, B, Y);
c0 = 0;
c1 = 0;
c2 = 0;
c3 = 0;
A = 0;
B = 0;
#1 A = 1;
#2 B = 1;
#4 A = 0;
#8 $finish;
end
always #1 c0 = ~c0;
always #2 c1 = ~c1;
always #3 c2 = ~c2;
always #4 c3 = ~c3;
endmodule
Simulation Output
c0 = 0 c1 = 0 c2 = 0 c3 = 0 A = 0 B = 0 Y = 0
c0 = 1 c1 = 0 c2 = 0 c3 = 0 A = 1 B = 0 Y = 0
c0 = 0 c1 = 1 c2 = 0 c3 = 0 A = 1 B = 0 Y = 0
c0 = 1 c1 = 1 c2 = 1 c3 = 0 A = 1 B = 1 Y = 0
c0 = 0 c1 = 0 c2 = 1 c3 = 1 A = 1 B = 1 Y = 1
c0 = 1 c1 = 0 c2 = 1 c3 = 1 A = 1 B = 1 Y = 1
c0 = 0 c1 = 1 c2 = 0 c3 = 1 A = 1 B = 1 Y = 1
c0 = 1 c1 = 1 c2 = 0 c3 = 1 A = 0 B = 1 Y = 1
c0 = 0 c1 = 0 c2 = 0 c3 = 0 A = 0 B = 1 Y = 0
c0 = 1 c1 = 0 c2 = 1 c3 = 0 A = 0 B = 1 Y = 0
c0 = 0 c1 = 1 c2 = 1 c3 = 0 A = 0 B = 1 Y = 1
c0 = 1 c1 = 1 c2 = 1 c3 = 0 A = 0 B = 1 Y = 1
c0 = 0 c1 = 0 c2 = 0 c3 = 1 A = 0 B = 1 Y = 0
c0 = 1 c1 = 0 c2 = 0 c3 = 1 A = 0 B = 1 Y = 0
c0 = 0 c1 = 1 c2 = 0 c3 = 1 A = 0 B = 1 Y = 1
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3.10 BEHAVIORAL AND RTL MODELING

Verilog provides designers the ability to describe design functionality in an
algorithmic manner. In other words, the designer describes the behavior of the
circuit. Thus, behavioral modeling represents the circuit at a very high level of
abstraction. Design at this level resembles C programming more than it resembles
digital circuit design. Behavioral Verilog constructs are similar to C language
constructs in many ways. Verilog is rich in behavioral constructs that provide the
designer with a great amount of flexibility.
3.10.1 Operators
Verilog provided many different operators types. Operators can be,
Arithmetic Operators
Relational Operators
Bit-wise Operators
Logical Operators
Reduction Operators
Shift Operators
Concatenation Operator
Replication Operator
Conditional Operator
Equality Operator
3.10.1.1 Arithmetic Operators
These perform arithmetic operations. The + and - can be used as either

unary (-z) or binary (x-y) operators.
Binary: +, -, *, /, % (the modulus operator)
Unary: +, - (This is used to specify the sign)
Integer division truncates any fractional part
The result of a modulus operation takes the sign of the first operand
If any operand bit value is the unknown value x, then the entire result
value is x
Register data types are used as unsigned values (Negative numbers are
stored in two's complement form)
Example
module arithmetic_operators();
initial begin
$display (" 5 + 10 = %d", 5 + 10);
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$display (" 5 - 10 = %d", 5 - 10);

$display (" 10 - 5 = %d", 10 - 5);
$display (" 10 * 5 = %d", 10 * 5);
$display (" 10 / 5 = %d", 10 / 5);
$display (" 10 / -5 = %d", 10 / -5);
$display (" 10 %s 3 = %d","%", 10 % 3);
$display (" +5
= %d", +5);
$display (" -5
= %d", -5);
#10 $finish;
end
endmodule
Simulation Output
5 + 10 = 15
5 - 10 = -5
10 - 5 = 5
10 * 5 = 50
10 / 5 = 2
10 / -5 = -2
10 % 3 = 1
+5
= 5
-5
= -5
3.10.1.2 Relational Operators

Relational operators compare two operands and return a single bit 1or 0. These
operators synthesize into comparators. Wire and reg variables are positive Thus (3b001) = = 3b111 and (-3d001)>3d1 10, however for integers -1< 6
Operator
Description
a<b
a less than b
a>b
a greater than b
a <= b
a less than or equal to b
a >= b
a greater than or equal to b
The result is a scalar value (example a < b)

0 if the relation is false (a is bigger than b)
1 if the relation is true ( a is smaller than b)
x if any of the operands has unknown x bits (if a or b contains X)
Note: If any operand is x or z, then the result of that test is treated as false (0)
Example
module relational_operators();
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VLSI DESIGN
initial begin
$display (" 5 <= 10 = %b", (5 <= 10));
$display (" 5 >= 10 = %b", (5 >= 10));
$display (" 1'bx <= 10 = %b", (1'bx <= 10));
$display (" 1'bz <= 10 = %b", (1'bz <= 10));
#10 $finish;
end
endmodule
Simulation Output
5 <= 10 = 1
5 >= 10 = 0
1'bx <= 10 = x
1'bz <= 10 = x
3.10.1.3 Bit-wise Operators

Bitwise operators perform a bit wise operation on two operands. This take each
bit in one operand and perform the operation with the corresponding bit in the
other operand. If one operand is shorter than the other, it will be extended on the
left side with zeroes to match the length of the longer operand.
Operator
~
&
|
^
^~ or ~^
Description
negation
and
inclusive or
exclusive or
exclusive nor (equivalence)
Computations include unknown bits, in the following way:

-> ~x = x
-> 0&x = 0
-> 1&x = x&x = x
-> 1|x = 1
-> 0|x = x|x = x
-> 0^x = 1^x = x^x = x
-> 0^~x = 1^~x = x^~x = x
When operands are of unequal bit length, the shorter operand is zero-filled
in the most significant bit positions.
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Example
module bitwise_operators();
initial begin
// Bit Wise Negation
$display (" ~4'b0001
= %b", (~4'b0001));
$display (" ~4'bx001
= %b", (~4'bx001));
$display (" ~4'bz001
= %b", (~4'bz001));
// Bit Wise AND
$display (" 4'b0001 & 4'b1001 = %b", (4'b0001 & 4'b1001));
$display (" 4'b1001 & 4'bx001 = %b", (4'b1001 & 4'bx001));
$display (" 4'b1001 & 4'bz001 = %b", (4'b1001 & 4'bz001));
// Bit Wise OR
$display (" 4'b0001 | 4'b1001 = %b", (4'b0001 | 4'b1001));
$display (" 4'b0001 | 4'bx001 = %b", (4'b0001 | 4'bx001));
$display (" 4'b0001 | 4'bz001 = %b", (4'b0001 | 4'bz001));
// Bit Wise XOR
$display (" 4'b0001 ^ 4'b1001 = %b", (4'b0001 ^ 4'b1001));
$display (" 4'b0001 ^ 4'bx001 = %b", (4'b0001 ^ 4'bx001));
$display (" 4'b0001 ^ 4'bz001 = %b", (4'b0001 ^ 4'bz001));
// Bit Wise XNOR
$display (" 4'b0001 ~^ 4'b1001 = %b", (4'b0001 ~^ 4'b1001));
$display (" 4'b0001 ~^ 4'bx001 = %b", (4'b0001 ~^ 4'bx001));
$display (" 4'b0001 ~^ 4'bz001 = %b", (4'b0001 ~^ 4'bz001));
#10 $finish;
end
endmodule
Simulation Output
~4'b0001
= 1110
~4'bx001
= x110
~4'bz001
= x110
4'b0001 & 4'b1001 = 0001
4'b1001 & 4'bx001 = x001
4'b1001 & 4'bz001 = x001
4'b0001 | 4'b1001 = 1001
4'b0001 | 4'bx001 = x001
4'b0001 | 4'bz001 = x001
4'b0001 ^ 4'b1001 = 1000
4'b0001 ^ 4'bx001 = x000
4'b0001 ^ 4'bz001 = z000
4'b0001 ~^ 4'b1001 = 0111
4'b0001 ~^ 4'bx001 = x111
4'b0001 ~^ 4'bz001 = x111
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3.10.1.4 Logical Operators

Logical operators return a single bit 1 or 0. They are the same as bit-wise operators
only for single bit operands. They can work on expressions, integers or groups of
bits, and treat all values that are nonzero as 1. Logical operators are typically
used in conditional (if ... else) statements since they work with expressions.
Operator
Description
!
logic negation
&&
logical and
||
logical or
Expressions connected by && and || are evaluated from left to right

Evaluation stops as soon as the result is known
The result is a scalar value:
-> 0 if the relation is false
-> 1 if the relation is true
-> x if any of the operands has x (unknown) bits
Example
module logical_operators();
initial begin
// Logical AND
$display ("1'b1 && 1'b1 = %b", (1'b1 && 1'b1));
$display ("1'b1 && 1'b0 = %b", (1'b1 && 1'b0));
$display ("1'b1 && 1'bx = %b", (1'b1 && 1'bx));
// Logical OR
$display ("1'b1 || 1'b0 = %b", (1'b1 || 1'b0));
$display ("1'b0 || 1'b0 = %b", (1'b0 || 1'b0));
$display ("1'b0 || 1'bx = %b", (1'b0 || 1'bx));
// Logical Negation
$display ("! 1'b1
= %b", (! 1'b1));
$display ("! 1'b0
= %b", (! 1'b0));
#10 $finish;
end
endmodule
Simulation Output
1'b1 && 1'b1 = 1
1'b1 && 1'b0 = 0
1'b1 && 1'bx = x
1'b1 || 1'b0 = 1
1'b0 || 1'b0 = 0
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VLSI DESIGN
1'b0 || 1'bx = x
! 1'b1
=0
! 1'b0
=1
3.10.1.5 Reduction Operators

Reduction operators operate on all the bits of an operand vector and return a singlebit value. These are the unary (one argument) form of the bit-wise operators.
Operator
Description
&
and
~&
nand
|
or
~|
nor
^
xor
^~ or ~^
xnor
Reduction operators are unary.

They perform a bit-wise operation on a single operand to produce a single
bit result.
Reduction unary NAND and NOR operators operate as AND and OR
respectively, but with their outputs negated.
-> Unknown bits are treated as described before
Example
module reduction_operators();
initial begin
// Bit Wise AND reduction
$display (" & 4'b1001 = %b", (& 4'b1001));
$display (" & 4'bx111 = %b", (& 4'bx111));
$display (" & 4'bz111 = %b", (& 4'bz111));
// Bit Wise NAND reduction
$display (" ~& 4'b1001 = %b", (~& 4'b1001));
$display (" ~& 4'bx001 = %b", (~& 4'bx001));
$display (" ~& 4'bz001 = %b", (~& 4'bz001));
// Bit Wise OR reduction
$display (" | 4'b1001 = %b", (| 4'b1001));
$display (" | 4'bx000 = %b", (| 4'bx000));
$display (" | 4'bz000 = %b", (| 4'bz000));
// Bit Wise OR reduction
$display (" ~| 4'b1001 = %b", (~| 4'b1001));
$display (" ~| 4'bx001 = %b", (~| 4'bx001));
$display (" ~| 4'bz001 = %b", (~| 4'bz001));
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// Bit Wise XOR reduction

$display (" ^ 4'b1001 = %b", (^ 4'b1001));
$display (" ^ 4'bx001 = %b", (^ 4'bx001));
$display (" ^ 4'bz001 = %b", (^ 4'bz001));
// Bit Wise XNOR
$display (" ~^ 4'b1001 = %b", (~^ 4'b1001));
$display (" ~^ 4'bx001 = %b", (~^ 4'bx001));
$display (" ~^ 4'bz001 = %b", (~^ 4'bz001));
#10 $finish;
end
endmodule
Simulation Output
& 4'b1001 = 0
& 4'bx111 = x
& 4'bz111 = x
~& 4'b1001 = 1
~& 4'bx001 = 1
~& 4'bz001 = 1
| 4'b1001 = 1
| 4'bx000 = x
| 4'bz000 = x
~| 4'b1001 = 0
~| 4'bx001 = 0
~| 4'bz001 = 0
^ 4'b1001 = 0
^ 4'bx001 = x
^ 4'bz001 = x
~^ 4'b1001 = 1
~^ 4'bx001 = x
~^ 4'bz001 = x
3.10.1.6 Shift Operators

Shift operators shift the first operand by the number of bits specified by the second
operand. Vacated positions are filled with zeros for both left and right shifts
(There is no sign extension).
Operator
Description
<<
left shift
>>
right shift
The left operand is shifted by the number of bit positions given by the
right operand.
Verilog Course Team

VLSI DESIGN
The vacated bit positions are filled with zeroes
Example
module shift_operators();
initial begin
// Left Shift
$display (" 4'b1001 << 1 = %b", (4'b1001 << 1));
$display (" 4'b10x1 << 1 = %b", (4'b10x1 << 1));
$display (" 4'b10z1 << 1 = %b", (4'b10z1 << 1));
// Right Shift
$display (" 4'b1001 >> 1 = %b", (4'b1001 >> 1));
$display (" 4'b10x1 >> 1 = %b", (4'b10x1 >> 1));
$display (" 4'b10z1 >> 1 = %b", (4'b10z1 >> 1));
#10 $finish;
end
endmodule
Simulation Output
4'b1001 << 1 = 0010
4'b10x1 << 1 = 0x10
4'b10z1 << 1 = 0z10
4'b1001 >> 1 = 0100
4'b10x1 >> 1 = 010x
4'b10z1 >> 1 = 010z
3.10.1.7 Concatenation Operator

The concatenation operator combines two or more operands to form a larger
vector.
Concatenations are expressed using the brace characters { and }, with
commas separating the expressions within.
->Example: + {a, b[3:0], c, 4'b1001} // if a and c are 8-bit numbers, the
results has 24 bits
Unsized constant numbers are not allowed in concatenations.
Example
module concatenation_operator();
initial begin
// concatenation
$display (" {4'b1001,4'b10x1} = %b", {4'b1001,4'b10x1});
#10 $finish;
end
Verilog Course Team

VLSI DESIGN
endmodule
Simulation Output
{4'b1001,4'b10x1} = 100110x1
3.10.1.8 Replication Operator

Replication operator is used to replicate a group of bits n times. Say you have a 4
bit variable and you want to replicate it 4 times to get a 16 bit variable: then we
can use the replication operator.
Operator
Description
{n{m}}
Replicate value m, n times
Repetition multipliers (must be constants) can be used:

-> {3{a}} // this is equivalent to {a, a, a}
Nested concatenations and replication operator are possible:
-> {b, {3{c, d}}} // this is equivalent to {b, c, d, c, d, c, d}
Example
module replication_operator();
initial begin
// replication
$display (" {4{4'b1001}}
= %b", {4{4'b1001}});
// replication and concatenation
$display (" {4{4'b1001,1'bz}} = %b", {4{4'b1001,1'bz}});
#10 $finish;
end
endmodule
Simulation Output
{4{4'b1001}
= 1001100110011001
{4{4'b1001,1'bz} = 1001z1001z1001z1001z
3.10.1.9 Conditional Operator

Conditional operator is like those in C/C++. They evaluate one of the two
expressions based on a condition. It will synthesize to a multiplexer (MUX).
->cond_expr ? true_expr : false_expr
The true_expr or the false_expr is evaluated and used as a result
depending on what cond_expr evaluates to (true or false).
Example
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VLSI DESIGN
module conditional_operator();
wire out;
reg enable,data;
// Tri state buffer
assign out = (enable) ? data : 1'bz;
initial begin
$display ("time\t enable data out");
$monitor ("%g\t %b
%b %b",$time,enable,data,out);
enable = 0;
data = 0;
#1 data = 1;
#1 data = 0;
#1 enable = 1;
#1 data = 1;
#1 data = 0;
#1 enable = 0;
#10 $finish;
end
endmodule
Simulation Output
time
0
1
2
3
4
5
6
enable data out

0
0 z
0
1 z
0
0 z
1
0 0
1
1 1
1
0 0
0
0 z
3.10.1.10 Equality Operators

There are two types of Equality operators. Case Equality and Logical Equality.
Operator
a === b
a !== b
a == b
a != b
Description
a equal to b, including x and z (Case equality)
a not equal to b, including x and z (Case inequality)
a equal to b, result may be unknown (logical equality)
a not equal to b, result may be unknown (logical
equality)
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VLSI DESIGN
Operands are compared bit by bit, with zero filling if the two operands do
not have the same length
Result is 0 (false) or 1 (true)
For the == and != operators, the result is x, if either operand contains an x
or a z
For the === and !== operators, bits with x and z are included in the
comparison and must match for the result to be true
Note: The result is always 0 or 1
Example
module equality_operators();
initial begin
// Case Equality
$display (" 4'bx001 === 4'bx001 = %b", (4'bx001 === 4'bx001));
$display (" 4'bx0x1 === 4'bx001 = %b", (4'bx0x1 === 4'bx001));
$display (" 4'bz0x1 === 4'bz0x1 = %b", (4'bz0x1 === 4'bz0x1));
$display (" 4'bz0x1 === 4'bz001 = %b", (4'bz0x1 === 4'bz001));
// Case Inequality
$display (" 4'bx0x1 !== 4'bx001 = %b", (4'bx0x1 !== 4'bx001));
$display (" 4'bz0x1 !== 4'bz001 = %b", (4'bz0x1 !== 4'bz001));
// Logical Equality
$display (" 5
== 10
= %b", (5
== 10));
$display (" 5
== 5
= %b", (5
== 5));
// Logical Inequality
$display (" 5
!= 5
= %b", (5
!= 5));
$display (" 5
!= 6
= %b", (5
!= 6));
#10 $finish;
end
endmodule
Simulation Output
4'bx001 === 4'bx001 = 1
4'bx0x1 === 4'bx001 = 0
4'bz0x1 === 4'bz0x1 = 1
4'bz0x1 === 4'bz001 = 0
4'bx0x1 !== 4'bx001 = 1
4'bz0x1 !== 4'bz001 = 1
5
== 10
=0
5
== 5
=1
5
!= 5
=0
5
!= 6
=1
Verilog Course Team

VLSI DESIGN
3.10.2 Operator Precedence

Operator
Unary, Multiply, Divide,
Modulus
Add, Subtract, Shift
Relation, Equality
Reduction
Logic
Conditional
Symbols
!, ~, *, /, %
+, - , <<, >>
<,>,<=,>=,==,!=,===,!==
&, !&,^,^~,|,~|
&&, ||
?:
3.10.3 Timing controls

Various behavioral timing control constructs are available in Verilog. In Verilog,
if there are no timing control statements, the simulation time does not advance.
Timing controls provide a way to specify the simulation time at which procedural
statements will execute.
There are three methods of timing control:
Delay based timing control
Event based timing control
Level-sensitive timing control
3.10.3.1 Delay-based timing control
Delay-based timing control in an expression specifies the time duration between
when the statement is encountered and when it is executed. Delays are specified
by the symbol #. Syntax for the delay-based timing control statement is shown
below
<delay>
::= #<NUMBER>
||= #<identifier>
||= #<mintypmax_expression> <,<mintypmax_expression>>*)
Delay-based timing control can be specified by a number, identifier, or a

mintypmax_expression. There are three types of delay control for procedural
assignments
Regular delay control
Intra-assignment delay control
Zero delay control
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VLSI DESIGN
Regular delay control

Regular delay control is used when a non-zero delay is specified to the left of a
procedural assignment. Usage of regular delay control is shown below example,
module clk_gen ();
reg clk, reset;
initial begin
$monitor ("TIME = %g RESET = %b CLOCK = %b", $time, reset, clk);
clk = 0;
reset = 0;
#2 reset = 1;
#5 reset = 0;
#10 $finish;
end
always
#1 clk = !clk;
endmodule
Simulation Output
TIME = 0 RESET = 0 CLOCK = 0
Intra-assignment delay control

Instead of specifying delay control to the left of the assignment, it is possible to
assign a delay to the right of the assignment operator. Usage of intra-assignment
delay control is shown in below example,
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VLSI DESIGN
module intra_assign();
reg a, b;
initial begin
$monitor("TIME = %g A = %b B = %b",$time, a , b);
a = 1;
b = 0;
a = #10 0;
b = a;
#20 $display("TIME = %g A = %b B = %b",$time, a , b);
$finish;
end
endmodule
Simulation output
TIME = 0 A = 1 B = 0
TIME = 10 A = 0 B = 0
TIME = 30 A = 0 B = 0
Difference between the intra-assignment delay and regular delay

Regular delays defer the execution of the entire assignment. Intra-assignment
delays compute the right-hand-side expression at the current time and defer the
assignment of the computed value to the left-hand-side variable. Intra-assignment
delays are like using regular delays with a temporary variable to store the current
value of a right-hand-side expression.
Zero delay control
Zero delay control is a method to ensure that a statement is executed last, after all
other statements in that simulation in that simulation time are executed. This is
used to eliminate race conditions. However, if there are multiple zero delay
statements, the order between them is nondeterministic. Usage of zero delay
control is shown in below example,
initial
begin
x=0;
y=0;
end
initial
begin
#0 x=1;
#0 y=1;
End
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VLSI DESIGN
Above four statements x=0,y=0,x=1,y=1 are to be executed at simulation time 0.

However since x=1 and y=1 have #0, they will be executed last. Thus, at the end
of time 0,x will have value 1 and y will have value 1.
3.10.3.2 Event based timing control
An event is the change in the value on a register or a net. Events can be utilized
to trigger execution of a statement or a block of statements. There are four types
of event-based timing control
Regular event control

Named event control
Event OR control
Level-sensitive timing control
Regular event control

The @ symbol is used to specify an event control. Statements can be executed on
changes in signal value or at a positive or negative transition of the signal value.
The keyword posedge is used for a negative transition as shown in below
example,
module edge_wait_example();
reg enable, clk, trigger;
always @ (posedge enable)
begin
trigger = 0;
// Wait for 5 clock cycles
repeat (5) begin
@ (posedge clk) ;
end
trigger = 1;
end
//Test bench
initial begin
$monitor ("TIME : %g CLK : %b ENABLE : %b TRIGGER : %b",
$time, clk,enable,trigger);
clk = 0;
enable = 0;
#5 enable = 1;
#1 enable = 0;
#10 enable = 1;
#1 enable = 0;
#10 $finish;
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VLSI DESIGN
end
always
#1 clk = ~clk;
endmodule
Simulation Output
TIME : 0 CLK : 0 ENABLE : 0 TRIGGER : x
TIME : 5 CLK : 1 ENABLE : 1 TRIGGER : 0
Named event control

Verilog provides the capability to declare an event and then trigger and recognize
the occurrence of that event. The event does not hold any data. A named event is
declared by the keyword event. An event is triggered by the symbol. The
triggering of the event is recognized by the symbol @.
Example
event received_data;
always @(posedge clock)
begin
if (last_data_packet)
received_data;
end
always @(received_data)
data_buf={data_pkt[0],data_pkt[1]};
Verilog Course Team

VLSI DESIGN
Event OR control
Sometimes a transition on any one of multiple signals or events can trigger the
execution of a statement or a block of statements. This is expressed as an OR of
events or signals. The list of events or signals expressed as an OR is also known
as a sensitivity list. The keyword or is used to specify multiple triggers as shown
in below example,
always @(reset or clock or d)
begin
if(reset)
q=1b0;
else if (clock)
q=d;
end
3.10.3.3 Level-Sensitive Timing Control

Verilog allows a level-sensitive timing control, that is, the ability to wait for a
certain condition to be true before a statement or a block of statements is
executed. The keyword wait is used for level-sensitive constructs.
Example
always
wait (count_enable) #20 count=count+1;
From the above example, the value of count_enable is monitored continuously. If

count_enable is 0, the statement is not entered. If it is logical 1, the statement
count=count+1 is executed after 20 time units. If count_enable stays at 1, count
will be incremented every 20 time units.
3.10.4 Procedural Blocks
Verilog behavioral code is inside procedure blocks, but there is an exception:
some behavioral code also exist outside procedure blocks. We can see this in
detail as we make progress.
There are two types of procedural blocks in Verilog:
initial: initial blocks execute only once at time zero (start execution at
time zero).
always: always blocks loop to execute over and over again; in other
words, as the name suggests, it executes always.
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VLSI DESIGN
Example initial
module initial_example();
reg clk,reset,enable,data;
initial begin
clk = 0;
reset = 0;
enable = 0;
data = 0;
end
endmodule
In the above example, the initial block execution and always block execution
starts at time 0. Always block waits for the event, here positive edge of clock,
whereas initial block just executed all the statements within begin and end
statement, without waiting.
Example always
module always_example();
reg clk,reset,enable,q_in,data;
always @ (posedge clk)
if (reset) begin
data <= 0;
end else if (enable) begin
data <= q_in;
end
endmodule
In an always block, when the trigger event occurs, the code inside begin and end
is executed; then once again the always block waits for next event triggering. This
process of waiting and executing on event is repeated till simulation stops.
3.10.5 Procedural Assignment Statements
Procedural assignment statements assign values to reg, integer, real, or

time variables and cannot assign values to nets (wire data types)
You can assign to a register (reg data type) the value of a net (wire),
constant, another register, or a specific value.
Example - Bad procedural assignment

module initial_bad();
reg clk,reset;
wire enable,data;
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VLSI DESIGN
initial begin
clk = 0;
reset = 0;
enable = 0;
data = 0;
end
endmodule
Example - Good procedural assignment

module initial_bad();
reg clk,reset;
wire enable,data;
initial begin
clk = 0;
reset = 0;
enable = 0;
data = 0;
end
endmodule
3.10.6 Procedural Assignment Groups

If a procedure block contains more than one statement, those statements must be
enclosed within
Sequential begin - end block
Parallel fork - join block
When using begin-end, we can give name to that group. This is called named
blocks.
Example - "begin-end"
module initial_begin_end();
initial begin
$monitor(
"%g clk=%b reset=%b enable=%b data=%b",
$time, clk, reset, enable, data);
#1 clk = 0;
#10 reset = 0;
#5 enable = 0;
#3 data = 0;
#1 $finish;
end
endmodule
Verilog Course Team

VLSI DESIGN
Begin : clk gets 0 after 1 time unit, reset gets 0 after 11 time units, enable after 16
time units, data after 19 units. All the statements are executed sequentially.
Simulator Output
0 clk=x reset=x enable=x data=x
1 clk=0 reset=x enable=x data=x
11 clk=0 reset=0 enable=x data=x
16 clk=0 reset=0 enable=0 data=x
19 clk=0 reset=0 enable=0 data=0
Example - "fork-join"
module initial_fork_join();
initial begin
$monitor("%g clk=%b reset=%b enable=%b data=%b",
$time, clk, reset, enable, data);
fork
#1 clk = 0;
#10 reset = 0;
#5 enable = 0;
#3 data = 0;
join
#1 $display ("%g Terminating simulation", $time);
$finish;
end
endmodule
Fork: clk gets its value after 1 time unit, reset after 10 time units, enable after 5
time units, data after 3 time units. All the statements are executed in parallel.
Simulator Output
0 clk=x reset=x enable=x data=x
1 clk=0 reset=x enable=x data=x
3 clk=0 reset=x enable=x data=0
5 clk=0 reset=x enable=0 data=0
10 clk=0 reset=0 enable=0 data=0
11 Terminating simulation
3.10.7 Sequential Statement Groups

The begin - end keywords:
Group several statements together.
Cause the statements to be evaluated sequentially (one at a time)
Verilog Course Team

VLSI DESIGN
-> Any timing within the sequential groups is relative to the previous
statement.
-> Delays in the sequence accumulate (each delay is added to the previous
delay)
-> Block finishes after the last statement in the block.
Example sequential
module sequential();
reg a;
initial begin
$monitor ("%g a = %b", $time, a);
#10 a = 0;
#11 a = 1;
#12 a = 0;
#13 a = 1;
#14 $finish;
end
endmodule
Simulator Output
0a=x
10 a = 0
21 a = 1
33 a = 0
46 a = 1
3.10.8 Parallel Statement Groups

The fork - join keywords:
Group several statements together.

Cause the statements to be evaluated in parallel (all at the same time).
-> Timing within parallel group is absolute to the beginning of the group.
-> Block finishes after the last statement completes (Statement with
highest delay, it can be the first statement in the block).
Example Parallel
module parallel();
reg a;
initial
fork
$monitor ("%g a = %b", $time, a);
Verilog Course Team

VLSI DESIGN
#10 a = 0;
#11 a = 1;
#12 a = 0;
#13 a = 1;
#14 $finish;
join
endmodule
Simulator Output
0a=x
10 a = 0
11 a = 1
12 a = 0
13 a = 1
3.10.9 Blocking and Nonblocking assignment

Blocking assignments are executed in the order they are coded, hence they are
sequential. Since they block the execution of next statement, till the current
statement is executed, they are called blocking assignments. Assignment are made
with "=" symbol.
Example a = b;
Nonblocking assignments are executed in parallel. Since the execution of next
statement is not blocked due to execution of current statement, they are called
nonblocking statement. Assignments are made with "<=" symbol.
Example a <= b;
Note: Correct way to spell 'nonblocking' is 'nonblocking' and not 'non-blocking'.
Example - blocking and nonblocking
module blocking_nonblocking();
reg a,b,c,d;
// Blocking Assignment
initial begin
#10 a = 0;
#11 a = 1;
#12 a = 0;
#13 a = 1;
end
initial begin
#10 b <= 0;
#11 b <= 1;
#12 b <= 0;
#13 b <= 1;
end
Verilog Course Team

VLSI DESIGN
initial begin
c = #10 0;
c = #11 1;
c = #12 0;
c = #13 1;
end
initial begin
d <= #10 0;
d <= #11 1;
d <= #12 0;
d <= #13 1;
end
initial begin
$monitor("TIME = %g A = %b B = %b C = %b D = %b",$time, a, b, c, d);
#50 $finish;
end
endmodule
Simulator Output
TIME = 0 A = x B = x C = x D = x
TIME = 10 A = 0 B = 0 C = 0 D = 0
TIME = 11 A = 0 B = 0 C = 0 D = 1
TIME = 12 A = 0 B = 0 C = 0 D = 0
TIME = 13 A = 0 B = 0 C = 0 D = 1
TIME = 21 A = 1 B = 1 C = 1 D = 1
TIME = 33 A = 0 B = 0 C = 0 D = 1
TIME = 46 A = 1 B = 1 C = 1 D = 1
3.10.10 assign and deassign

The assign and deassign procedural assignment statements allow continuous
assignments to be placed onto registers for controlled periods of time. The assign
procedural statement overrides procedural assignments to a register. The deassign
procedural statement ends a continuous assignment to a register.
3.10.11 force and release
Another form of procedural continuous assignment is provided by the force and
release procedural statements. These statements have a similar effect on the
assign-deassign pair, but a force can be applied to nets as well as to registers.
One can use force and release while doing gate level simulation to work around
reset connectivity problems. Also can be used insert single and double bit errors
on data read from memory.
Verilog Course Team

VLSI DESIGN
3.10.12 Conditional Statements

3.10.12.1 The Conditional Statement if-else
if - else statement controls the execution of other statements. In programming
language like c, if - else controls the flow of program. When more than one
statement needs to be executed for an if condition, then we need to use begin and
end as seen in earlier examples.
Syntax : if
if (condition)
statements;
Syntax : if-else
if (condition)
statements;
else
statements;
Syntax : nested if-else-if
if (condition)
statements;
else if (condition)
statements;
................
................
else
statements;
Example- simple if
module simple_if();
reg latch;
wire enable,din;
always @ (enable or din)
if (enable) begin
latch <= din;
end
endmodule
Example- if-else
module if_else();
reg dff;
wire clk,din,reset;
if (reset) begin
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VLSI DESIGN
dff <= 0;
end else begin
dff <= din;
end
endmodule
Example- nested-if-else-if
module nested_if();
reg [3:0] counter;
reg clk,reset,enable, up_en, down_en;
// If reset is asserted
if (reset == 1'b0) begin
counter <= 4'b0000;
// If counter is enable and up count is asserted
end else if (enable == 1'b1 && up_en == 1'b1) begin
counter <= counter + 1'b1;
// If counter is enable and down count is asserted
end else if (enable == 1'b1 && down_en == 1'b1) begin
counter <= counter - 1'b1;
// If counting is disabled
end else begin
counter <= counter; // Redundant code
end
3.10.12.2 The Case Statement

The case statement compares an expression to a series of cases and executes the
statement or statement group associated with the first matching case:
case statement supports single or multiple statements.

Group multiple statements using begin and end keywords.
Syntax of a case statement is given below,
case ()
< case1 > : < statement >
< case2 > : < statement >
.....
default : < statement >
endcase
Verilog Course Team

VLSI DESIGN
Example- case
module mux (a,b,c,d,sel,y);
input a, b, c, d;
input [1:0] sel;
output y;
reg y;
always @ (a or b or c or d or sel)
case (sel)
0 : y = a;
1 : y = b;
2 : y = c;
3 : y = d;
default : $display("Error in SEL");
endcase
endmodule
Example- case without default

module mux_without_default (a,b,c,d,sel,y);
input a, b, c, d;
input [1:0] sel;
output y;
reg y;
always @ (a or b or c or d or sel)
case (sel)
0 : y = a;
1 : y = b;
2 : y = c;
3 : y = d;
2'bxx,2'bx0,2'bx1,2'b0x,2'b1x,
2'bzz,2'bz0,2'bz1,2'b0z,2'b1z : $display("Error in SEL");
endcase
endmodule
Example- case with x and z

module case_xz(enable);
input enable;
always @ (enable)
case(enable)
Verilog Course Team

VLSI DESIGN
1'bz : $display ("enable is floating");

1'bx : $display ("enable is unknown");
default : $display ("enable is %b",enable);
endcase
endmodule
3.10.12.3 The casez and casex statement

Special versions of the case statement allow the x ad z logic values to be used as
"don't care":
casez : Treats z as don't care.
casex : Treats x and z as don't care.
Example- casez
module casez_example();
reg [3:0] opcode;
reg [1:0] a,b,c;
reg [1:0] out;
always @ (opcode or a or b or c)
casez(opcode)
4'b1zzx : begin // Don't care about lower 2:1 bit, bit 0 match with x
out = a;
$display("@%0dns 4'b1zzx is selected, opcode %b",$time,opcode);
end
4'b01?? : begin
out = b; // bit 1:0 is don't care
$display("@%0dns 4'b01?? is selected, opcode %b",$time,opcode);
end
4'b001? : begin // bit 0 is don't care
out = c;
$display("@%0dns 4'b001? is selected, opcode %b",$time,opcode);
end
default : begin
$display("@%0dns default is selected, opcode %b",$time,opcode);
end
endcase
Simulation Output - casez
@0ns default is selected, opcode 0000
@2ns 4'b1zzx is selected, opcode 101x
@4ns 4'b01?? is selected, opcode 0101
@6ns 4'b001? is selected, opcode 0010
Verilog Course Team

VLSI DESIGN
Example- casex
module casex_example();
reg [3:0] opcode;
reg [1:0] a,b,c;
reg [1:0] out;
always @ (opcode or a or b or c)
casex(opcode)
4'b1zzx : begin // Don't care 2:0 bits
out = a;
$display("@%0dns 4'b1zzx is selected, opcode %b",$time,opcode);
end
4'b01?? : begin // bit 1:0 is don't care
out = b;
$display("@%0dns 4'b01?? is selected, opcode %b",$time,opcode);
end
4'b001? : begin // bit 0 is don't care
out = c;
$display("@%0dns 4'b001? is selected, opcode %b",$time,opcode);
end
default : begin
$display("@%0dns default is selected, opcode %b",$time,opcode);
end
endcase
Simulation Output - casex
@2ns 4'b1zzx is selected, opcode 101x
@4ns 4'b01?? is selected, opcode 0101
@6ns 4'b001? is selected, opcode 0010
3.10.13 Looping Statements

Looping statements appear inside procedural blocks only; Verilog has four
looping statements like any other programming language.
forever
repeat
while
for
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3.10.13.1 The forever statement

The keyword forever is used to express this loop. The loop does not contain any
expression and executes continually, until the $finish task is encountered.
Normally we use forever statements in initial blocks.
Syntax: forever < statement >
One should be very careful in using a forever statement: if no timing construct is
present in the forever statement, simulation could hang. The code below is one
such application, where a timing construct is included inside a forever statement.
Example
module forever_example ();
reg clk;
initial begin
#1 clk = 0;
forever begin
#5 clk = !clk;
end
end
initial begin
$monitor ("Time = %d clk = %b",$time, clk);
#100 $finish;
end
endmodule
3.10.13.2 The repeat statement

The keyword repeat is used for thi sloop. The repeat construct executes the loop a
fixed number of times. A repeat construct cannot be used to loop on a general
logical expression. The repeat loop executes < statement > a fixed < number > of
times.
Syntax: repeat (< number >) < statement >
Example- repeat
module repeat_example();
reg [3:0] opcode;
reg [15:0] data;
reg
temp;
always @ (opcode or data)
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begin
if (opcode == 10) begin
// Perform rotate
repeat (8) begin
#1 temp = data[15];
data = data << 1;
data[0] = temp;
end
end
end
// Simple test code
initial begin
$display (" TEMP DATA");
$monitor (" %b %b ",temp, data);
#1 data = 18'hF0;
#1 opcode = 10;
#10 opcode = 0;
#1 $finish;
end
endmodule
3.10.13.3 The while loop statement

The keyword while is used to specify this loop. The while loop executes as long
as an < expression > evaluates as true. If the loop is entered when the whileexpression is false, the loop is not executed at all. This is the same as in any other
programming language.
Syntax: while (< expression >) < statement >
Example- while
module while_example();
reg [5:0] loc;
reg [7:0] data;
always @ (data or loc)
begin
loc = 0;
// If Data is 0, then loc is 32 (invalid value)
if (data == 0) begin
loc = 32;
end else begin
while (data[0] == 0) begin
loc = loc + 1;
data = data >> 1;
end
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end
$display ("DATA = %b LOCATION = %d",data,loc);
end
initial begin
#1 data = 8'b11;
#1 data = 8'b100;
#1 data = 8'b1000;
#1 data = 8'b1000_0000;
#1 data = 8'b0;
#1 $finish;
end
endmodule
3.10.13.4 The for loop statement

The for loop is the same as the for loop used in any other programming language.
Executes an < initial assignment > once at the start of the loop.
Executes the loop as long as an < expression > evaluates as true.
Executes a < step assignment > at the end of each pass through the loop.
Syntax: for (< initial assignment >; < expression >, < step assignment >) <
statement >
Note: Verilog does not have ++ operator as in the case of C language.
Example For
module for_example();
integer i;
reg [7:0] ram [0:255];
initial begin
for (i = 0; i < 256; i = i + 1) begin
#1 $display(" Address = %g Data = %h",i,ram[i]);
ram[i] <= 0; // Initialize the RAM with 0
#1 $display(" Address = %g Data = %h",i,ram[i]);
end
#1 $finish;
end
endmodule
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VLSI DESIGN
3.11 DATA FLOW MODELING AND RTL

For small circuits, the gate-level modeling approach works very well because the
number of gates is limited and the designer can instantiate and connects every
gate individually. Also, gate-level modeling is very intuitive to a designer with a
basic knowledge of digital logic design. However, in complex designs the number
of gates is very large. Thus, designers can design more effectively if they
concentrate on implementing the function at a level of abstraction higher than gate
level. Dataflow modeling provides a powerful way to implement a design.
Verilog allows a circuit to be designed in terms of the data flow between registers
and how a design processes data rather than instantiation of individual gates.
Dataflow modeling has become a popular design approach as logic synthesis tools
have become sophisticated. This approach allows the designer to concentrate on
optimizing the circuit in terms of data flow. For maximum flexibility in the design
process, designers typically use a Verilog description style that combines the
concepts of gate-level, dataflow, and behavioral design. In the digital design
community, the term RTL (Register Transfer Level) design is commonly used for
a combination of dataflow modeling and behavioral modeling.
3.11.1 Continuous Assignment Statements
A continuous assignment is the most basic statement in dataflow modeling, used
to drive a value onto a net. A continuous assignment replaces gates in the
description of the circuit and describes the circuit at a higher level abstraction. A
continuous assignment statement starts with the keyword assign. They represent
structural connections.
They are used for modeling Tri-State buffers.

They can be used for modeling combinational logic.
They are outside the procedural blocks (always and initial blocks).
The continuous assign overrides any procedural assignments.
The left-hand side of a continuous assignment must be net data type.
Syntax: assign (strength, strength) #(delay) net = expression;

Example - One bit Adder design using continuous assignment statement
module adder_using_assign ();
reg a, b;
wire sum, carry;
assign #5 {carry,sum} = a+b;
initial begin
$monitor (" A = %b B = %b CARRY = %b SUM = %b",a,b,carry,sum);
#10 a = 0;
b = 0;
#10 a = 1;
#10 b = 1;
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#10 a = 0;
#10 b = 0;
#10 $finish;
end
endmodule
Example - Tri-state buffer using continuous assignment statement

module tri_buf_using_assign();
reg data_in, enable;
wire pad;
assign pad = (enable) ? data_in : 1'bz;
initial begin
$monitor ("TIME = %g ENABLE = %b DATA : %b PAD %b",
$time, enable, data_in, pad);
#1 enable = 0;
#1 data_in = 1;
#1 enable = 1;
#1 data_in = 0;
#1 enable = 0;
#1 $finish;
end
endmodule
3.11.2 Propagation Delay

Continuous Assignments may have a delay specified; only one delay for all
transitions may be specified. A minimum: typical: maximum delay range may be
specified.
Example - Tri-state buffer
module tri_buf_using_assign_delays();
reg data_in, enable;
wire pad;
assign #(1:2:3) pad = (enable) ? data_in : 1'bz;
initial begin
$monitor ("ENABLE = %b DATA : %b PAD %b",enable, data_in,pad);
#10 enable = 0;
#10 data_in = 1;
#10 enable = 1;
#10 data_in = 0;
#10 enable = 0;
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#10 $finish;
end
endmodule
3.12 STRUCTURAL GATE LEVEL DESCRIPTION

3.12.1 2 to 4 Decoder
Digital circuit for 2 to 4 decoder
RTL Coding for 2 to 4 decoder

module decoder_2to4_gates (A0,A1,D0,D1,D2,D3);
input A0,A1;
output D0,D1,D2,D3;
wire n1,n2;
not i1 (n1,A0);
not i2 (n2,A1);
and a1 (D0,n1,n2);
and a2 (D1,n1,A1);
and a3 (D2,A0,n2);
and a4 (D3,A0,A1);
endmodule
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3.12.2 Comparator
Digital circuit for Comparator
RTL Coding for Comparator

module comparator(A,B,AEQB,ALTB,AGTB);
input [3:0]A,B;
output AEQB,ALTB,AGTB;
wire A3,A2,A1,A0;
wire B3,B2,B1,B0;
assign A3=A[3];
assign A2=A[2];
assign A1=A[1];
assign A0=A[0];
assign B3=B[3];
assign B2=B[2];
assign B1=B[1];
assign B0=B[0];
wire N1,N2,N3,N4,N5,N6,N7,N8;
wire N11,N12,N13,N14,N15,N16,N17,N18;
wire M1,M2,M3,M4;
wire M11,M12,M13,M14,M15,M16,M17,M18;
not
not
not
not
not
not
A11(N1,A3);
A12(N2,B3);
A13(N3,A2);
A14(N4,B2);
A15(N5,A1);
A16(N6,B1);
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not A17(N7,A0);
not A18(N8,B0);
and
and
and
and
and
and
and
and
A19(N11,B3,N1);
A20(N12,A3,N2);
A21(N13,B2,N3);
A22(N14,A2,N4);
A23(N15,B1,N5);
A24(N16,A1,N6);
A25(N17,B0,N7);
A26(N18,A0,N8);
nor A27(M1,N11,N12);
nor A28(M2,N13,N14);
nor A29(M3,N15,N16);
nor A30(M4,N17,N18);
and A31(M11,M1,N13);
and A32(M12,M1,N14);
and A33(M13,M1,M2,N15);
and A34(M14,M1,M2,N16);
and A35(M15,M1,M2,M3,N17);
and A36(M16,M1,M2,M3,N18);
and A37(AEQB,M1,M2,M3,M4);
or A38(ALTB,N11,M11,M13,M15);
or A39(AGTB,N12,M12,M14,M16);
endmodule
3.12.3 D-latch
Digital circuit for D-latch
RTL coding for D-latch

module d_latch( D,E,Q,Qbar);
input D,E;
output Q,Qbar;
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wire n1,n2,n3,n4;
not a11(n1,D);
and a12(n2,E,n1);
and a13(n3,E,D);
nor a14(Q,n2,Qbar);
nor a15(Qbar,n3,Q);
endmodule
3.12.4 D Flip Flop
Digital circuit for D Flip Flop

RTL coding for D Flip Flop
module d_flipflop( D,C,Q,Qbar);
input D,E;
output Q,Qbar;
wire n1,n2,n3,n4;
not a11(n1,D);
nand a12(n2,C,n1);
nand a13(n3,C,D);
nor a14(Qbar,n2,Q);
nor a15(Q,n3,Qbar);
endmodule
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3.12.5 Half Adder

Digital circuit for half adder
RTL coding for Half Adder

module half_adder(A,B,S,C);
input A,B;
output S,C;
xor a11(S,A,B);
and a12(C,A,B);
endmodule
3.12.6 Full Adder

Digital circuit for Full Adder
RTL coding for Full Adder

module full_adder(A,B,CIN,S,COUT);
input A,B,CIN;
output S,COUT;
wire n1,n2,n3,n4,n5,n6;
xor a11(n1,A,B);
xor a12(S,n1,CIN);
and a13(n2,n1,CIN);
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and a14(n3,A,B);
or a15(COUT,n2,n3);
endmodule
3.12.7 Ripple Carry Adder

Digital circuit for Ripple Carry Adder
RTL coding for Ripple Carry Adder Circuit

module ripple_carry_adder(ai,bi,cin,sum,carry);
input ai,bi,cin;
output sum,carry;
wire n1,n2,n3;
wire m1,m2,m3,m4,m5,m6,m7;
not a11(n1,ai);
not a12(n2,bi);
not a13(n3,cin);
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nand a14(m1,bi,cin);
nand a15(m2,cin,ai);
nand a16(m3,ai,bi);
nand a17(m4,ai,bi,cin);
nand a18(m5,n3,n2,ai);
nand a19(m6,n3,bin,n1);
nand a20(m7,cin,n2,n1);
nand a21(carry,m1,m2,m3);
nand a22(sum,m4,m5,m6,m7);
endmodule
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CMOS CHIP DESIGN
UNIT 4
4.1 INTRODUCTION TO CMOS
Over the past decade, Complementary Metal Oxide Semiconductor (CMOS)
technology has played an increasingly important role in the global integrated
circuit industry. Not that CMOS technology is that new. In fact, the basic
principle behind the MOS filed-transistor was proposed by J.Lilienfeld as early as
1925, and a similar structure closely resembling a modern MOS transistor was
proposed by O.Heli in 1935.
In VLSI design, a logic function is implemented by means of a circuit consisting
of one or more basic cells, such as NAND or NOR gates. The implementation can
be used as a library cell in the design phase. In CMOS circuits, it is possible to
implement complex Boolean functions by means of NMOS and PMOS
transistors. A cell is an interconnection of CMOS transistors. A CMOS cell is
depicted in Figure 4 .1. It consists of a row of PMOS transistors and a row of
NMOS transistors corresponding to the PMOS and NMOS sides of the circuit,
respectively. The automatic generation of standard CMOS logic cells has been
studied intensively during the last decade. The continuous progress in VLSI
technology presents new challenges in developing efficient algorithms for the
layout of standard CMOS logic cells. The cell generation techniques are classified
into random generation and regular style. A random cell generation technique
does not exploit any particular structure to produce the cells. It uses a general
technique, such as a hierarchical place-route algorithm. Random generation
methods produce compact and (if desired) high-performance layouts. However, it
takes a long time to design a cell. Regular generation techniques employ a
predefined structure to design a cell. Cells generated in this manner occupy more
area but can be designed faster. Traditional cell structures based on regularity are,
for example, PLAs, ROMs, and RAMs. The disadvantage of the ROM-based cell
is that it takes a lot of area, as it uses many redundant transistors.
Figure 4.1 CMOS
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4.2 LOGIC DESIGN WITH CMOS

4.2.1 COMBITIONAL LOGIC
If two N_SWITCHES are placed in series ,the compsoite switch constructed by
the action is closed (or ON) if both swicthes are closed(or ON)figure 4.2(a).This
yeilds an AND function. The corrresponding strcuture for P-SWITCHES is
shown in figure 4.2(b).The composite switch is closed if the onputes are set to 0.
When two N-SWITCHES are placced in parallel figure 4.2(c), the composite
switch is closed (if either input is as1).Thus ans OR function is created. The
switch shown in figure 4.2(d) is composed of two P-SWITCHES placed in
parellel.Incontrast to previous case ,if either input is a 0 the switch is closed.
By using combinations of these contrucitons, CMOS combination gates may be
constructed.
s1=0 s1=0
s2=0 s2=1
s1=1
s2=0
s1=1
s2=1
s1=0 s1=0 s1=1 s1=1

s2=0 s2=1 s2=0 s2=1
s1=0
s2=0
s1=0
s2=1
s1=1
s2=0
s1=1
s2=1
s1=0
s2=0
s1=0
s2=1
s1=1
s2=0
s1=1
s2=1
c
d
Figure 4.2 Connection and behavior of series and parallel of N-SWITHCES
and P-SWITCHES
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4.2.2 INVERTER
Table 4.1 outlines the truth table of required to implement a logical inverter.
INPUT
OUTPUT
0
1
1
0
Table 4.1 Inverter Truth Table
Figure 4.3 CMOS Inverter

If Vin is high (at or near Vdd ) the NMOS transistor will be turned on. The
voltage between the gate and substrate of the p-channel device is at or near zero.
The gate is at Vdd and so is the moat.Hence the upper transistor will be turned
off. The output will thus be low. If the input voltage is at or near ground (a low)
then the n-channel device is turned off. The voltage between the gate and
substrate of the p-channel device is now
- Vdd (The gate is 0 and the
substrate is at +Vdd ). If the PMOS transistor has a threshold voltage VT of, say, 2 V, then it will be turned on and the output will be high. Note however, that in
either state, high or low, there is no static current flowing through the inverter.
The transfer characteristics for this circuit. Are a little more complicated. First,
lets make sure that the voltages and currents defined. From the figure 4.4, Vgs-n
the n-channel gate-source voltage is just Vin. Vgs-p the gate-source voltage for
the p-channel device is Vin-VddId-n=Id-p=IdVds-P the drain source voltage for
the p-channel transistor can be written as Vds-n-Vdd.
Figure 4.4 Schematic of a CMOS inverter
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4.2.3 The NAND Gate

The two transistors Q1 and Q3 resemble the series-connected as a complementary
pair from the inverter circuit. Both are controlled by the same input signal (input
A), the upper transistor turning off and the lower transistor turning on when the
input is "high" (1), and vice versa. Transistors Q2 and Q4 from figure 4.5 are
similarly controlled by the same input signal (input B), and how they will also
exhibit the same on/off behavior for the same input logic levels. The upper
transistors of both pairs (Q1 and Q2) have their source and drain terminals
paralleled, while the lower transistors (Q3 and Q4) are series-connected. What this
means is that the output will go "high" (1) if either top transistor saturates, and
will go "low" (0) only if both lower transistors saturate.
Figure 4.5 Logic Schematic

The following sequence of illustrations shows the behavior of this NAND gate for
all four possibilities of input logic levels (00, 01, 10, and 11):
The pull-down tree is a series pair of N-switches with one end connected to Vdd
and the other end connected to the output.
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Figure 4.6 Behavior of NAND Gate

The output level of the structure ,given the logic levels on the control inputs
shown in the Table 4.2.
CONTROL INPUT A CONTROL INPUT B OUTPUT
0
0
Z
0
1
Z
1
0
Z
1
1
0
Table 4.2 Nand Gate Pull-down Truth Table
The pull-up tree is a parallel connection pair of P-SWITHCES with one end
connected to Vdd and the other end connected to NAND gate output.The level of
the output of the combined switch is shown in Table 4.3.
CONTROL INPUT A CONTROL INPUT B
OUTPUT
0
0
1
0
1
1
1
0
1
1
1
Z
Table 4.3 Nand Gate Pull-up Truth Table
The combined state of the ouput depends on the combination of the pull-up states
and the pull-down states
4.2.4 The NOR Gate
As compare with the NAND gate, transistors Q1 and Q3 work as a complementary
pair, as do transistors Q2 and Q4. Each pair is controlled by a single input signal.
If either input A or input B are "high" (1), at least one of the lower transistors (Q3
or Q4) will be saturated, thus making the output "low" (0). Only in the event of
both inputs being "low" (0) will both lower transistors be in cutoff mode and both
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upper transistors be saturated, the conditions necessary for the output to go "high"
(1). This behavior, of course, defines the NOR logic function.
Figure 4.7 Logic Schematic
4.3 TRANSMISSION GATES

4.3.1 Multiplexers
Complementary switches may be used to select between a number of inputs, thus
forming a multiplexer function. Figure 4.8(a) shows a connection diagram for a 2input multiplexer. As the switches have to pass 0s and 1s equally well.
Complementary switches with n-and p-transistors are used. Multiplexer are key
components in CMOS memory elements and data manipulation structures.
A
Output
S
B
Output
C
1
S
a
b
Figure 4.8 A 2-input CMOS multiplexer
4.3.2 Lathes
A structure called D latch using 2-input multiplexer and two inverter is shown in
Figure 4.9(a). It consist of a data input, D, a clock input, CLK, and output Q and
Q. When CLK=1, Q set to D and Q is set to D (the logical NOT of D) Figure
4.9(b).There are number of ways are used to indicate the logical NOT of a signal.
The form D is often used in texts. However, CAD systems due to the use of an
ASCII a feedback path around the inverter pair is established figure 4.9(c). This
causes the current state of Q to be stored. While CLK=0 the input D is ignored.
This is known as level-sensitive latch. That is the state of the output is dependent
on the level of the clock signal. The latch shown is a positive level-sensitive latch.
By reversing the control connection to the multiplexer, a negative level-sensitive
latch may be constructed.
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D
CMOS CHIP DESIGN

-Q
C
C
CLK
D
-Q
b
CLK=1
-Q
D
CLK=0
c
Q
Figure 4.9 A CMOS positive-level-sensitive D latch
4.4 CMOS CHIP DESIGN OPTIONS

4.4.1 ASIC
What is an ASIC?
Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is
custom designed for a specific application rather than a general-purpose chip such
as a microprocessor. The use of ASICs improves performance over generalpurpose CPUs, because ASICs are "hardwired" to do a specific job and do not
incur the overhead of fetching and interpreting stored instructions. However, a
standard cell ASIC may include one or more microprocessor cores and embedded
software, in which case, it may be referred to as a "system on a chip" (SoC).
A full custom ASIC chip is the most costly, and like standard cell ASICs, uses a
custom-designed mask for every layer in the chip. Unlike standard cells, designers
of a full custom device have total control over the size of every transistor forming
every logic gate, so they can "fine tune" each gate for optimum performance.
Thus, a full custom ASIC performs electronic operations as fast as it is possible to
do so, providing that the circuit design is efficiently architected.
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Today, full custom ASICs represent a small percentage of the ASIC market
because gate arrays, structured ASICs and standard cells turn circuit designs into
working chips much faster and at much less cost. Such chips have greatly
improved in speed over the years and provide the necessary performance for
many applications. The speed advantage of a full custom ASIC is not as relevant
as it was in the past. It is used primarily for devices such as microprocessors that
must run as fast as possible and will be produced in huge quantities.
Also promoting the decline of full custom ASICs are chip manufacturers that
make generic chips containing all the necessary functions for specific mass
market products such as DVDs, CDs, digital cameras, etc. An ASIC (Application
Specific Integrated Circuit) is a semiconductor device designed especially for a
particular customer (versus a Standard Product, which is designed for general use
by any customer). The two major categories of ASIC Technology are ArrayBased and Cell-Based (also referred to as Standard Cell). Array-Based ASICs
configure a customer's design at the metal layers, whereas Cell-Based ASICs are
uniquely fabricated at all layers of the silicon process including the diffusion
layers.
4.4.2 Uses of ASICs
To save chip area, ASIC technology integrates the logic and much of the memory
formerly distributed among multiple ICs, thus improving reliability, optimizing
PC Board space, and reducing component costs. In addition, the higher
integration and smaller size results in significantly better system performance.
ASICs were originally used solely to replace or consolidate TTL glue logic and
consisted of relatively low complexity logic. Improvements in design tools and
implementation software, in process technology, and in large pin count packages,
now integrate much more of the logic formerly distributed among numerous ICs
onto a single, very large scale System-On-a-Chip (SOC)
4.4.3 Full Custom ASICs
In a Full-custom ASIC all mask layers are customized show in figure 4.10.Full
Custom designs offer the highest performance and the smallest die size, with the
disadvantage if increased design time, higher complexity and costs, together with
the highest risks of failure .This design option only makes sense when either
libraries nor IP cores are available, or when very high performances are required.
Time after time, fewer projects are really full-custom, because of the very high
cost and the prohibitively slow time to market.
Most of the full-customs works are related library cell generation or minor parts
of a full design. Examples of full-custom IC specific parts are high voltage
(automobiles-avionic), analog processing and analog/digital communication
devices, sensors and transducers. Traditionally microprocessors and memories
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were exclusively full-custom, but industry is increasingly turning semicustom

ASIC techniques in these areas too.
Figure.4.10 In a Full-custom designs every layer must be designed
Figure 4.11 Application Specific components

4.4.5 Semi-Custom ASICs
In order to reduce the unaffordable cost of full custom in most projects, a wide
variety of design approaches have been developed to shorten design time , cut
down the costs , and automate the processes. These approaches are commonly
called semicustom. Semicustom designs are performed at the logic (gate) level.
As such, they lose some of the flexibility available from a full-custom fashion that
is the price paid for much easier design techniques. Semicustom solutions can be
further categorized into gate array and standard cell.
4.4.6 Standard- Cell-Based ASIC
Standard cells are logic components (e.g., gates, multiplexer, adders, flip flops)
previously designed and stored in a library. The standard cell areas (also called
flexible blocks) in a cell-based (cell-based IC or CBIC- a common term in Japan,
pronounced sea-bick) CBIC are built of rows of standard cells-like a wall built
of bricks. The standard cell areas may be used in combination with larger
predesigned cells, perhaps microcontroller or even microprocessor, known as
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megacells. Megacells are also called mega functions, full-custom blocks, systemlevel macros (SLMs), fixed blocks, cores, or Functional Standard Blocks (FSBs).
The ASIC designer defines only the placement of the standard cells and the
interconnect in a CBIC. However, the standard cells can be placed anywhere on
the silicon, this means that all mask layers of a CBIC are customized and are
unique to a particular customer. The advantage of CBIC is that designers save
time, money, and reduce risk by using a predesigned, pretested and pre
characterized standard-cell library. In addition each standard cell can be
optimized individually. During the design of the cell library each and every
transistor in every standard cell can be chosen to maximize speed or minimizing
area, for example. The disadvantages are time or expense of designing or buying
the standard-cell library and time needed to fabricate all layers of the ASIC for
each new design.
Figure 4.12 Typical Standard cell layouts

A designed is created using the library cells as inputs to CAD system; logic
schematic diagram or hardware description language (HDL) code description.
Next, further CAD tool automatically converts the design into a chip layout.
Standard cell designs are typically organized on the chip, rows of constant height
cells (figure 4.12). Together with logic level components cells, standard cell
systems typically offer-higher-level function such as multipliers and memory
arrays. This allows the use of predesigned (or automatically generated) high
level components to complete the design.
4.4.7 Gate Array Asic
Gate Arrays (Gas) are basically composed of continuous arrays of P- and n-type
transistors. The silicon vendor provides master or base wafers, to be then
personalized according to the interconnection information supplied by the
customers. Therefore, the designers supply the personated information that
defines the connections between transistors in the gate array. Although a gate
array standardized the chip at the geometry level, user interaction to gates, is
performed through an ad hoc CAD tool.
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The gate array also called masked gate array (MGA), or prediffused array) used
library components and macros that reduce the development time.
Three main types of gate array can be mentioned
Channel
Channelless and
Structured.
4.4.8 Channeled Gate Array

Figure 4.13 shows a channeled gate array. The important features of this type of
MGA are:
Only the interconnect is customized.
The interconnect uses predefined spaces between rows of base cells.
Manufacturing lead time is between two days and two weeks.
Figure 4 .13 Channel Gate Array

In channeled gate array, the interconnections are drawn within predefined spaces
(channels) between rows of logic cells.
4.4.9 Channelless Gate Array
Figure 4.14 shows a channelless gate array (also known as a channel-free gate
array, sea-of-gates array, or SOG array). The important features of this type of
MGA are:
Only some (the top few) mask layers are customized the interconnect.
Figure 4 .14 Channel Gate Array
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In a channelless (channelfree gate array o r sea-of-gates), there are no connections

channels, the connections are drawn with the upper metal layers, that is on the top
of the logic cells. In both cases, only some mask layers (the upper ones) must be
customized.
4.4.10 Structured Gate Array
An embedded gate array or structured gate array (also known as masterslice or
masterimage) combines some of the features of CBISCs and MGAs. One of the
disadvantages of the MGA is the fixed gate-array base cell. This makes the
implementation of memory, for example, difficult and inefficient. Figure 4.15
shows an structured gate array. The important features of this type of MGA are
the following,
Only the interconnect is customized.

Customs blocks (the same for each design) can be embedded.
Figure 4.15 Structured Gate Array

An embedded gate array gives the improved area efficiency and increased
performance of a CBIC but with the lower cost and faster turnaround of an MGA.
One disadvantage of an embedded gate array is that embedded function is fixed.
4.5 PROGRAMMABLE LOGIC

As the investment made in any chip designs is significant, designers search for
ways in which to amortize the design effort over a large number of devices. This
might results from a huge single market for one device or, more probably,
multiple smaller markets for a more adaptable device. The larger the unit volume
for a part lowest its cost will be the end user.
Programmability is one way to achieve a wider use for a particular part. This is
epitomized by the microprocessor. Often, though, the cost or speed of a
microprocessor may not meet system goals and an alternative solution is required.
In CMOS one may be divided this spectrum of Programmable devices into three
areas,
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Programmable Logic Structures.

Programmable Interconnect.
Reprogrammable Gate Arrays.
4.5.1 Programmable Logic Structures

The first broad classes of programmable CMOS devices are represented by the
programmable logic devices referred to as PALs (Programmable Array Logic,
Advanced Micro Devices, Inc.) or PLDs (Programmable Logic Devices).
Generally these devices are implemented as AND-OR plane devices as shown in
Figure 4.16.In the design shown a number of inputs feed vertical wires , which are
selectively connected to an AND-OG gate. Each AND-OR gate has a variable
number of products terms that feed the gate. This gate in turn feed an I/O cell,
which allows result into the AND-OR plane.PAL devices come in a large range of
sizes with a variable of inputs, outputs, product terms, and I/O cell complexity.
Figure 4.16 PAL architecture
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4.5.2 Programmable of PALs

The Programming of PALs is done in three ways,
Fusible links
UV-erasable EPROM
EEPROM-Electrically Erasable Programmable ROM
4.5.3 Fusible Links

A fusible links use a metal such platininium silicide or titatinium tungsten to form
links that are blown when a certain current is exceeded in the fuse. This is
normally accomplished by using a higher than normal programming voltage
applied to the device. This technology is normally used in conjunction with a
bipolar process (as opposed to a CMOS process) where the small devices can
readily sink the current needed to blow the fuses. Programming is a one- time
operation. As an alternative to current, a laser can be used to cut aluminum fuses
in normal CMOS technologies. Frequently this is used in redundant memory
technique where a spare column may be switched in to replace a failing one.
4.5.4 UV-erasable EPROM
UV-erasable memories typically use a floating gate structure. Here a floating gate
is interposed between the regular MOS transistor gate and the channel. To
program the cell, a voltage around 13-14 volts is applied to the control gate while
the drain of the transistor to be programmed is held at around 12 volts. This
results in the floating gate becoming charged negatively. This increases the
threshold of the transistor (to around 7 volts), thus rendering it permanently off
for all normal circuit voltage 9 maximum 5-6 volts). The process can be reversed
by illuminating the gate with UV light.
4.5.5 EEPROM
EEPROM (also written E2PROM and pronounced e-e-prom or simply e-squared),
which stands for Electrically Erasable Programmable Read-Only Memory, is a
type of non-volatile memory used in computers and other electronic devices to
store small amounts of data that must be saved when power is removed, e.g.,
calibration tables or device configuration. When larger amounts of static data are
to be stored (such as in USB flash drives) a specific type of EEPROM such as
Figure 4.17 EEPROM Structure
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flash memory is more economical than traditional EEPROM devices. EEPROM

technology allows the electrical programming and erasure of CMOS ROM cells.
This type of programming forms the most popular in use today for CMOS and is
the most likely encountered by the IC system designers in todays foundry
possesses.
4.5.6 Programmable Interconnect
In a PAL the device is programmed by changing the characteristics of the
switching element. An alternative would be to program the routing. This has been
demonstrated via a number of techniques including Laser Pantography, where a
laser lays down paths of metal under computer control. Commercially,
programmable routing approaches are represented by products from Actel,
QuickLogic, and other companies.
Metal
100 M
Polysilicon
Dielectric
ONO Layer
n+ diffusion
Metal
200-500 M
Polysilicon
Dielectric
after breakdown
n+ diffusion
Figure 4.18(a) Antifuse

The Actel Field Programmable Gate Array are based on an element called a
PLICE (Programmable Low-Impedance Circuit Element) or anti-fuse. An antifuse
is normally high resistance (>100 M). On application of appropriate
programming voltages, the antifuse is changed permanently to a low-resistance
structure (200-500). The structure of an antifuse is shown in figure 4.18(a). It
consists of an ONO (oxide-nitride-oxide) layer sandwiched between a polysilicon
layer on top and n+ diffusion on the bottom. The QuickLogic array is based on a
structure called a ViaLink, which consist of a sandwich of material between
metal1 and metal2.This is illustrated in figure 4.18(b).The on resistance of this
structure is somewhat lower than that in figure 4.18(a). One chip architecture that
uses the antifuse in shown in figure 4.19.Logic elements are arranged in rows
separated by horizontal interconnect. Interconnect permanently connected to the
logic elements passes vertically. Both horizontally and vertical segments are
segmented into variety of lengths. Segments may be joined by programming
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antifuse. Certain special logic elements are surrounded by I/O pads and
programming and diagnostic logic
Metal
Via
Sio2
metal
link
via
Sio2
Figure 4.18(b) ViaLink
Figure 4.19 Programmable Interconnect Model
4.6 ASIC DESIGN FLOW

Figure 4.20 shows the sequence of the steps to design an ASIC; we call this a
Design Flow. The steps are listed below with a brief description of the function of
each steps.
Design Entry: Enter the design into an ASIC design system, either using a
Hardware Description Language (HDL) or schematic entry
Logic Synthesis: Use an HDL (Verilog/VHDL) and a logic synthesis tool to
produce a netlist-a description of the logic cells and their constraints.
System Partitioning: Divide a large system into ASIC sized pieces.
Prelayout Simulation: Check to see if the design functions correctly.
Floorplanning: Arrange the blocks of the netlist on the chip.
Placement: Decide the collations of the cells and block.
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Routing: Make the connections between cells and blocks.

Extraction: Determine the resistance and capacitance of the interconnect.
Postlayout Simulation: Check to see the design still works with the added loads
of the interconnect.
Steps 1-4 are part of Logical Design. And steps 5-9 are part of Physical Design.
There is some overlap. For example, system portioning might be considered as
either logical or physical design. To put it another way, when performing system
partitioning the main factor to be consider include both logical and physical
factors.
Figure 4.20 ASIC Design Flow
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UNIT-5
5.1 THE NEED FOR TESTING
While in real estate the refrain is Location! the comparable advice in IC design
should be Testing! Testing! Testing! .While most problems in VLSI design has
been reduced to algorithm in readily available software, the responsibilities for
various levels of testing and testing methodology can be significant burden on the
designer.
The yield of a particular IC was the number of good die divided by the total
number of die per wafer. Due to the complexity of the manufacturing process not
all die on a wafer correctly operate. Small imperfections in starting material,
processing steps, or in photomasking may result in bridged connections or
missing features. It is the aim of a test procedure to determine which die are good
and should be used in end systems.
Testing a die can occur:

At the wafer level
At the packaged level
At the board level
At the system level
In the field
By detecting a malfunctioning chip at an earlier level, the manufacturing cost may

be kept low. For instance, the approximate cost to a company of detecting a fault
at the above level is:
Wafer $0.01- $.1
Packaged-chip $0.10-$1
Board $1-$10
System $10-$100
Field $100-$1000
Obviously, if faults can be detected at the wafer level, the cost of manufacturing is
kept the lowest. In some circumstances, the cost to develop adequate tests at the
wafer level, mixed signal requirements or speed considerations may require that
further testing be done at the packaged-chip level or the board level. A component
vendor can only test the wafer or chip level. Special systems, such as satelliteborne electronics, might be tested exhaustively at the system level.
Tests may fall into two main categories. The first set of tests verifies that the chip
performs its intended function; that is, that it performs a digital filtering function,
acts as a microprocessor, or communicates using a particular protocol. In other
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words, these tests assert that all the gates in the chip, acting in concert, achieve a
desired function. These tests are usually used early in the design cycle to verify
the functionality of the circuit. These will be called functionality tests. The second
set of tests verifies that every gate and register in the chip functions correctly.
These tests are used after the chip is manufactured to verify that the silicon in
intact. They will be called manufacturing tests. In many cases these two sets of
tests may be one and the same, although the natural flow of design usually has a
designer considering function before manufacturing concerns.
5.1.1 Functionality Tests
Functionality tests are usually the first tests a designer might construct as part of
the design process. For most systems, functionality tests involve proving that the
circuit is functionally equivalent to some specification. That specification might
be a verbal description, a plain-language textual specification, a description in
some high-level computer language such as C, FORTRAN, Pascal, or Lisp or in a
hardware-description language such as VHDL, ELLA, or Verilog or simply a
table of inputs and required outputs. Functional equivalence involves running a
simulator at some level on the two descriptions of the chip and ensuring for all
inputs applied that the outputs are equivalent at some convenient checkpoints in
time. The most detailed check might be on a cycle-by-cycle basis.
Functional equivalence may be carried out at various levels of the design
hierarchy. If the description is in a behavior language, the behavior at the system
level may be verifiable. For instance, in the case of a microprocessor, the
operating system might be booted and key programs might be run for the
behavioral description. However, this might be impractical for a gate-level model
and extremely impractical for a transistor-level model. The way out of this
impasse is to use the hierarchy inherent within a system to verify chips and
modules within chips.
5.2 MANUFACTURING TEST PRINCIPLES

A critical factor in all LSI and VLSI design is the need to incorporate methods of
testing circuits. This task should proceed concurrently with any architectural
considerations and not be left until fabricated parts are available.
Figure 5.1(a) shows a combinational circuit with n-inputs. To test this circuit
exhaustively a sequence of 2^n inputs must be applied and observed to fully
exercise the circuit. This combinational circuit is converted to a sequential circuit
with addition of m-storage registers, as shown in figure 5.1b the state of the
circuit is determined by the inputs and the previous state. A minimum of 2^ (n+m)
test vectors must be applied to exhaustively test the circuit. Clearly, this is an
important area of design that has to be well understood.
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Combinational
Logic
2^n inputs required to exhaustively test circuit

(a)
Combinational
Logic
n
n
m
m
Register
Clk
2^(n+m) inputs required to exhaustively test circuit

For n=25 m=50 1micro seconds/test, the test time is oner 1 billion years
(b)
Figure 5.1 The combinational explosion in test vectors

5.2.1 FAULT MODELS
5.2.1.1 Stuck-At-Faults
In order to deal with the existence of good and bad parts it is necessary to propose
a fault model, that is, a model for how faults occur and their impact on circuits.
The most popular model is called the stuck-at model. With this model, a faulty
gate input is modeled as a stuck at zero(stuck-at-0,S-A-0,SA0) or stuck at one
(Stuck-At-1,S-A-1,SA1). This model dates from board level designs where this
was determined to be an adequate set of models for modeling faults. Figure 5.2
illustrates how an S-A-0 or S-A-1 fault might occur. These faults most frequently
occur due to thin oxide shorts or metal-to-metal shorts.
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Figure 5.2 CMOS stuck-at faults

5.2.1.2 Short-Circuit and Open-Circuit Faults
Other models include stuck-open or shorted models. Two shorted faults are
shown in figure 5.3. Considering the faults shown in figure5.3, the short s1 is
modeled by an S-A-0 fault at input A, while short S2 modifies the function of the
gate. What becomes evident is that to ensure the most accurate modeling, faults
should be modeled at the transistor level, because it is only at this level that the
complete circuit structure is known. For instance, in the case of a simple NAND
gate, the intermediate node in the series n-pair is hidden by the schematic. What
this implies is that test generations must be done in such a way as to take account
of possible shorts and open circuits at the switch level. Although the switch level
may be the most appropriate level, expediency dictates that most existing systems
rely on Boolean logic representation of circuits and S-A-0 and S-A-1 fault
modeling.
A particular problem that arises with CMOS is that it is possible for a fault to
convert a combinational circuit into a sequential circuit. This is illustrated for the
case of a 2-input NOR gate in which one of the transistors is rendered ineffective
(stuck open or stuck closed) in figure 5.4.This might be due to a missing source,
drain or gate connection. If one of the n-transistors is stuck open, then the
function displayed by the gate will be
F= (not (A+B)) + (A. (not B).Fn)
Where Fn is the previous state of the gate. Similarly if the B n-transistors drain
connection is missing, the function is
F= (not (A+B)) + ((not A).B.Fn)
If either p-transistor is open, the node would be arbitrarily charged until one of the
n-transistors discharged the node. Thereafter it would remain at zero, bar charge
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leakage effects. This problem has caused researchers to search for new methods
of test generation to detect such behavior.
Figure 5.3 CMOS bridging faults
Figure 5.4 A CMOS open fault causes sequential faults
Currently debate ranges over whether an SA0/SA1 approach to testing is adequate for
testing CMOS. It is also possible to have switches exhibit a stuck-open or stuckclosed state. Stuck closed states can be detected by observing the static VDD current
(IDD ) while applying test vectors. Consider the gate fault shown in Figure 5.5 where a
p-transistor in a 2-input NAND gate is shorted. This could physically occur if stray
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metal overlapped the source and drain connection or if the source and drain diffusions
shorted. If the test vector 11 is applied to the A and B input and measure the static IDD
, the change to notice that it rises to some value determined by the ratios of the n
and p transistors. While the debate continues and test cycles are at a premium, the
SA0/SA1 model will suffice for some time to come.
Figure 5.5 A defect that Causes Static IDD current

5.2.2 Observability
The observability of a particular internal circuit node is the degree to which one
can observe that node at the outputs of an integrated circuit. This measure is of
importance when a designer/tester desires to measure the output of a gate within a
larger circuit to check that it operates correctly. Given a limited number of nodes
that may be directly observed, it is the aim of well-designed chips to have easily
observed gate outputs, and the adaption of some basic test design techniques can
aid tremendously in this respect. Ideally, one should be able to observe directly or
with moderate indirection every gate output within integrated circuit. While at one
time this aim was hindered by limited gate-count processes and a lack of design
methodology, current design practices and processes allow one to approach this
ideal.
5.2.3 Controllability
The controllability of an internal circuit node within a chip is measure of the case
of setting the node to a 1 or 0 state. This measure is of importance when assessing
the degree of difficulty of testing a particular signal within a circuit. An easily
controllable node would be directly settable via an input pad. A node with little
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controllability might require many hundreds or thousands of cycles to get it to

the right state. Often one finds it impossible to generate a test sequence to set a
number of poorly controllable nodes into the right state. It should be the aim of a
well-designed circuit to have all nodes easily controllable. In common with
observability, the adoption of some simple design for test techniques can aid
tremendously in this respect.
5.2.4 Fault Coverage
A measure of goodness of a test program is the amount of fault coverage it
archives; that is, for the vectors applied, what percentages of the chips internal
nodes were checked. Conceptually, the way in which the fault coverage is
calculated is as follows. Each circuit node is taken in sequence and held to 0(S-A0), and the circuit is simulated. Comparing the chip outputs with a known good
machines-a circuit with no nodes artificially set to 0 (or 1).When a discrepancy is
detected between the faulty machine and the good machine. The fault is marked
as detected and the simulation is stopped. This is repeated for setting the node to 1
(S-A-1).In turn. Every node is stuck at 1 and 0, sequentially. The total number of
nodes that, when set to 0 or 1, do result in the detection of the fault, divided by the
total number of nodes in the circuit, is called the percentage-fault coverage.
The above method of the fault analysis is called sequential fault grading. While
this might be practical for small circuits, or by using hardware simulation
accelerators on medium circuits, the time to complete the fault grading may be
very long. On average KN cycles assuming that, on average N/2 cycles are
needed to detect each fault need to be simulated, where K is the number of nodes
in the circuit and N is the length of test sequence. For K=1000 and N=12000, 12
million cycles are required. At 1ms per cycle, this yields 12,000 seconds or 3hrs
20 minutes. For K=100000 and `N=360,000, 3.6x10^9 cycles are required. At 1s
per cycle, 1040 years would be required to do sequential fault grading. To
overcome these long simulation times many ingenious techniques have been
invented to deal with fault simulation.
5.2.5 Automatic Test Pattern Generation (Atpg)
In IC industry, designers designed circuits, layout drafts people completed the
layout, and the test engineer wrote the tests . In many ways, the test engineers
were the Sherlock Holmes of the industry, reverse engineering circuits and
devising tests that would test the circuits in an adequate manner. For the longest
time, test engineers implored circuit designers to include extra circuitry to ease
the burden of test generation. As processes have increased in density and chips
increased in complexity, the inclusion of test circuitry has become less of an
overhead for both the designer and the manager worried about the cost of the die.
In addition, as tools have improved, more of the burden for generating tests has
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fallen on the circuit/logic designer. To deal with this burden, methods for
automatically generating tests have been invented. Collectively these are known
as ATPG, for Automatic Test Pattern Generation. In practice, one may find that
ATPG is of great use in the generation of test vectors or that for a variety of
reasons it is not applicable.
Most ATPG approaches have been based on simulation. A five-valued logic form
is commonly used to implement test generate algorithms. This consists of the
states 1, 0, D, D and X. 0 and 1 represent logical zero and logical one
respectively. X represents the unknown or DONT-CARE state. D represents a
logic 1 in a good machine and a logic 0 in a faulty machine while D represents a
logic 0 in a good machine and logic 1 in a faulty machine. The truth tables for
inverters, AND, and OR gates are shown in tables 5.1, 5.2, and 5.3.
A
Table 5.1 Inverter Z=NOT A
With the use of this five-valued logic by considering the circuit shown in fig5.6
where an S-A-0 fault is to be detected at node h. Alternatively call a circuit
machine, which is customary in test momentclature. Thus node h would have
value D. There are two objectives. The first is to propagate the D on node h to one
or more primary outputs (Pos). A primary output is a directly observable signal,
such as a pad or a scan output. This path to the primary output (or outputs) is
called the sensitized path. The second objective is to set node h to state D via a set
of primary inputs (PIs). A primary input is one that can be directly set via a pad or
some other means. The gate driving node h is the Gate Under test or GUT. From
node h we backtrack to the primary inputs (a, b, c, d, e) to find the necessary input
vector required to set node to a 1. Because the gate driving node h is an AND gate
from the above definition (a D is a 1 in a good machine), both inputs (f, g) have to
be set to 1 to set h to 1. Proceeding further toward the inputs, to assert node f as a
1, both nodes a and b have to be set to a 1. Because node g is driven by an OR
gate, either node c or node d need to be set to a 1 to assert node g.
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A
B
0
0
1
0
X
0
D
0
D
0
Table 5.2 2-input AND gate Z=A AND B

A
B
0
0
1
1
X
X
D
D
D
D
Table 5.3 2-input OR gate Z=A OR B

Thus a vector {a,b,c,d} of {1,1,1,0} or {1,1,0,1} is required to control node h. To
observe that node g has been set to a D, input node e has to be set to a 1. Thus the
resultant test vector is {a,b,c,d,e}={1,1,0,1,1} or {1,1,1,0,1}. If we are checking
for an S-A-1 fault at node h, we must be able to set it to 0. By similar reasoning to
that for the S-A-0 case the test vector would be {a,b,c,d,e}={0,1,X,X,1} or
{1,0,X,X,1} or {0,0,X,X,1} or [1,1,0,0,1]. Similarly, for other nodes a summary
of the vectors is as in table 5.4
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NODE TEST
h
S-A-0
h
S-A-1
f
S-A-0
f
S-A-1
g
S-A-0
g
S-A-1
VECTOR{a,b,c,d,e}
{1,1,0,1,1},{1,1,1,0,1}
0,1,X,X,1},{1,0,X,X,1},{0,0,X,X,1},{1,1,0,0,1}
{1,1,0,1,1},{1,1,1,0,1}
{0,0,0,1,1},{0,0,1,0,1}
{1,1,0,1,1},{1,1,1,0,1},{1,1,1,1,1}
{1,1,0,0,1}
Table 5.4 Node-vector Summary of D-algorithm
Figure 5.6 The D-algorithm sensitization step
Figure 5.7 Reconvergent fan-out with D notation
The next step is to collapse the vectors into least set that covers all nodes. A
possible set is [1,1,0,1,1],[0,0,1,0,1],[1,1,0,0,1].
The reason for using a five-valued logic is shown in figure5.7. Here an additional
AND gate and INVERT gate have been added to the circuit. From the figure 5.7
that a fault at node h is essentially unobservable. This circuit suffers from what is
called reconvergent fan-out. The usual basis for manual generation of tests by test
engineers and many current automatic test-pattern generation programs is the Dalgorithm(DALG), PODEM and PODEM-X are improved algorithms that are
more efficient than the original DALG and in addition treat error-correcting
circuits composed of XOR gates with reconvergent fan-out. Another ATPG
algorithm is called FAN and an improved efficiency algorithm dealing with
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tristate drivers called ZALG has been developed. Other work has concentrated on
dealing at a module level rather than the gate level. In basis these algorithms start
by propagating the D value on an internal node to a primary output. This is called
the D-propagation phase. The selection of which gates to pass through to the
output is guided by observability indexes assigned to gates. At any particular gate
input, the gate with the highest observability is selected. Once the D value is
observable at a primary output, the next step is to determine the primary input
values that are required to enable the fault to be observed and tested. This
proceeds by backtracking from the faulted signal and sensitized path-enables
toward the primary inputs. The selection of which path to proceed along toward
the inputs is aided by controllability indices assigned to nodes. This is known as
the backtrace step.
Controllabilities and observabilities can be assigned statically or dynamically. The
SCOAP algorithm is one method of assigning controllabilities and observabilites.
In the SCOAP system the following six testability measures are defined for each
circuit node:
CC0(n)-combinatorial 0 controllability of node 0

CC1 (n)-combinatorial 1 controllability of node n.
C0(n) combinatorial observability of node n
SC0(n)-sequential 0 controllability of node n
SC1(n) sequential 1 controllability of node n
S0 (n) sequential observability of node n.
The combinatorial measures are applied to the outputs of logic gates, while the
sequential measures apply to registers and other sequential modules. As an
example, for the AND gate shown in figure 5.8 the CC1 value is
CC1 (z) =CC1 (a) +CC1 (b) +1
Figure 5.8 NAND gate

That is, the 1-controllability of the output of the AND gate is the sum of the 1controllabilities of each input because each input has to be set to 1 to set the
output to 1. the 1 is added at the end because the AND gate represents one stage
of combinatorial logic. The sequential 1-controllability is given by
SC1 (z) =SC1 (a) +SC1 (b)
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The combinatorial 0-controllability is given by

CC0 (z) =min [CC0 (a), CC0 (b)] +1
This arises due to the fact that either a 0 on a or b forces a 0 at the output.
Therefore the easiest controllable input may be used. The sequential
controllability is given by
SC0 (z) =min [SC0 (a), SC0 (b)],
The combinatorial observability of a is given by

C0 (a) =C0 (z) +CC1 (b) +1;
That is, the observability of z added to the combinatorial 1-controllability of b.

This occurs because b has to be forced to a 1 to make a observable. The
sequential observability of a is given by
S0 (a) =S0 (z) +S0 (b)
Similar equations may be derived for other gate types. The SCOAP algorithm
proceeds by first calculating the circuit controllabilities by propagating
controllabilities from logic inputs. Following this, the observabilities are
propagated from the logic outputs. Figure 5.9(a) shows a logic circuit with the 1controllabities annotated. Figure 5.9(b) shows the observabilities.
Figure 5.9 SCOAP testability measure example (a) controllabilities (b)

observabilities
In cases of multiple fan-out, the minimum observability measure is used. The
presence of high controllability numbers a node that is difficult to control, while
the presence of high observability numbers indicates nodes that are difficult to
observe. As mentioned above, the testability measures are used to guide the
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selection of paths in the D-propagation and backtrace phase of the D-algorithm

based ATPG procedures.
Other testability measures, such as COP and LEVEL are also used. COP
testability measures are probabilistic in nature.
5.2.6 Fault Grading And Fault Simulation
Fault grading consists of two steps. First, the node to be faulted is selected.
Normally global nodes such as reset lines and clock lines are excluded because
faulting them can lead to unnecessary simulation. A simulation is run with no
faults inserted, and the results of this simulation are saved. Following this process,
in principle, each node or line to be faulted is set to 0 and then 1 and the test
vector is applied. If, and when, a discrepancy is detected between the faulted
circuit response and good circuit response, the fault is said to be detected and the
simulation is stopped, and the process is repeated for the next node to be faulted.
If the numbers of nodes to be faulted is K, and the average number of test vectors
is N, the number of simulation cycles Sk is approximately
SK =(2*(N/2)*k)+N
= K(N+1)=KN
This serial fault simulation process is therefore running K sets of the test vector
set. With a small vector set, simple circuit, or very fast simulator, this approach is
feasible. However, for large test sets and circuits, it is highly impractical.
To deal with this problem, a number of ideas have been developed to increase the
speed of fault simulation.
Parallel simulation is one method for speeding up simulation of multiple
machines. In this method m words in an n-bit computer are used to encode the
state of n machines for a 2^m state machine. Two n-bit words may be used to
encode n machines for a three-state simulation. More computer words may be
used to encode simulators with more states. Moreover this principle has been
extended to special-purpose hardware where the computer word length could be
optimized to deal with substantially more circuits in parallel. Now if M circuits
can be simulated in parallel, then
SK =KN/M
Concurrent simulation is currently the most popular method for software based
fault simulation. The technique uses a nonfaulted version of the circuit to create a
good machine model. Each fault creates a new faulty machine that is simulated
parallel with the good machine. Thus N+1 simulations mat have to be completed,
where N is the number of faults. Concurrent simulators rely on a number of
heuristics to reduce the amount of simulation. For instance, when a difference is
noted between a faulted machine and a good machine at an externally observable
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point, the faulty machine is dropped from the simulation queue and the fault is
detected. If the bad machines has an X or Z compared to a 1 or 0 for the good
machine, the fault is possible detect. Obviously, the more externally observable
nodes a circuit has, the quicker bad machines get dropped from the simulations.
Normally, only the good machine state is stored, with each node listing the fault
machines that differ with the good machine. The different state is often small,
which implies that there is a small amount of extra simulation to be done. In other
words most simulation for a faulty machine is exactly the same as the good
machine. This is what concurrent simulation exploits. Fault collapsing occurs
when two different faults result in the same faulty machine. This is noted, and one
of the faulty machines may be dropped. Some machines performs static fault
collapsing prior to simulation. For instance, an SA0 fault on the input of an
inverter is the same as an SA1 fault at the output of the same inverter. With some
fault simulators it is possible to create a fault dictionary.
This is a cross reference that maps an observed fault to a set of possible internal
faults. It is of use when the tester wishes to track down the actual internal failure
rather than just call the part. Apart from software based simulations, hardwarefault simulation accelerators that can provide a speedup over software based
simulators are also available.
5.2.7 Delay Fault Testing
The fault models we have dealt with to this point have neglected timing. Failures
that occur in CMOS could leave the functionality of the circuit untouched, but
affect the timing.
Figure 5.10 An example of a delay fault

For instance, consider the layout shown in figure5.10 for a high-power NAND
gate composed of paralleled n and p transistors. If the link illustrated was opened,
the gate would still function, but with increased pull-down time. In addition, the
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fault now becomes sequential because the detection of the fault depends on the
previous state of the gate and the simulation clock speed.
5.2.8 Statistical Fault Analysis
Conventional fault analysis can consume large CPU resources and take a long
time. An alternative to this is what is called statistical fault analysis. This method
of fault analysis relies on estimating the probability that a fault will be detected.
In summary, a fault free simulation is performed on a circuit in which some extra
statistics are gathered by a modified simulator on a per-input vector basis. These
are as follows
Zero-counterthe 0 count on each gate input when a 1->0 change of the

output is detected.
One counter the 1 count on each gate input when a 0->1 change of the
output detected.
Sensitization counter incremented if the input changes cause the output
to be sensitized.
Loop-counter used to detect and deal with feedback.
GATE TYPE
B1 (l)
B0(l)
AND
B1 (m).(C1(m)/C1(l))
B0(m).(S(l)-1(m))/C0(l)
OR
B1 (m).(S(l)-C0(m))/C1(l)
B0(m).C0(m)/C0(l)
NAND
B0 (m).C0(m)/C1(l)
B1(m).(S(l)-1(m))/C0(l)
OR
B0 (m).(S(l)-C1(m))/C1(l)
B1(m).(C1(m)/C0(l))
NOT
B0 (m)
B1(m)
Table 5.5 Statistical Fault Analysis 1 And 0 Observations

The one-controllability of line l is given by
C1 (l) = one-count/N
Where N is the number of vectors.
The zero-controllability is given by
C0 (l) =zero-count/N
The one-level sensitization probability is
S (l) = sensitization-count/N
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The observabilities are calculated by propagating from gate outputs to gate inputs.
For common gates, Jain and Agrawal derive the one-observabilites (B1) and zeroobservabilities (B0) for common gates as shown in table 5.5
Methods also exist to deal with fan-out where two observabilities must be
combined. Once these observability and controllability measures have been
determined, the probability of fault detection may be calculated as follows
D1 (l) =B0 (l).C0 (l)
Where D1 (l) is the probability of detection that line l is SA1
D0 (l) =B1 (l). C1 (l)
Where D0 (l) is the probability of detection that line l is SA0
From these values the fault coverage of the circuit mat be calculated. The results
of using this technique follow very closely the results generated by conventional
fault simulation.
5.2.9 Fault Sampling
Another approach to fault analysis is known as fault sampling. This is used in
circuits where it is impossible to fault every node in the circuit. Nodes are
randomly selected and faulted. The resulting fault-detection rate may be
statistically inferred from the number of faults that are detected in the fault set and
the size of the set. As with all probabilistic methods it is important that the
randomly selected faults be unbiased. Although this approach does not yield a
specific level of fault coverage, it will determine whether the fault coverage
exceeds a desired level. The level of confidence may be increased by increasing
the no of samples.
5.3 DESIGN STRATEGIES FOR TEST

5.3.1 Design for Testability
The key to designing circuits that are testable are the two concepts that introduced
called controllability and observability. Restated, controllability is the ability to
set (to 1) and reset (to 0) every node internal to the circuit. Observability is the
ability to observe either directly or indirectly the state of any node in the circuit.
The three main approaches to what is commonly called design for testability.
These may be categorized as:
Ad-hoc testing
Scan-based approaches
Self-test and built-in testing
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Following this, the application of these techniques to particular types of circuits.

In this treatment we will look at:
Random logic(multilevel standard-cell, two-level PLA)
Regular logic arrays (data paths)
Memories (RAM, ROM)
5.3.2 Ad-Hoc Testing

Ad-Hoc test techniques, as their name suggests, are collections of ideas aimed at
reducing the combinational explosion of testing. Common techniques involve:
Partitioning large sequential circuit
Adding test points
Adding multiplexers
Providing for easy state reset
Long counters are good examples of circuits that can be tested by ad-hoc
techniques. For instance imagine you have designed an 8-bit counter and want to
test it. Figure 5.11(a) shows a nave implementation in which the counter only has
a RESET and a CLOCK input, with the terminal count (TC) being observable.
The designer probably thought that a reset and 256 clock cycles, followed by the
observation of TC, would be adequate for testing purposes. Apart from the
nonobservability of the count value (Q<7:0>), the main problem is the number of
cycles required to test a single counter. Possible ad-hoc test techniques are shown
in figure 5.11(b) and figure 5.11(c). In figure 5.11(b), a parallel-load feature is
added to the counter. This enables the counter to be preloaded with appropriate
values to check the carry propagation within the counter. Another technique is to
reduce the length of each counter to, say, 4 bits, as shown in figure 5.11(c). This
is achieved by having the test signal block the carry propagate at every 4-bit
boundary. With this method 16 vectors exhaustively can test each 4-bit section.
The carry propagate between 4-bit sections may be tested with a few additional
vectors.
Another technique classified in this category is the use of the bus in a bus-oriented
system for test purposes. This is shown on figure 5.12(a) for a very simple
accumulator. Each registers has been made loadable from the bus and capable of
being driven onto the bus for testing purposes. A more general scheme is
illustrated in figure 5.12(b), where the normally inaccessible inputs are set and the
outputs are observed via the bus.
Frequently, multiplexers may be used to provide alternative signal paths during
testing. In CMOS transmission gate multiplexers provide low area and speed
overhead. Figure 5.13(a) shows a scheme called a design for autonomous test,
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which uses multiplexers. Figure 5.13(b) shows the circuit configured for normal
use, while figure 5.13(c) shows the circuit configuration to test module A.
Figure 5.11 Ad-hoc test techniques applied to a counter

Any design should always have a method of resetting the internal state of the chip
within a single cycle or at most a few cycles. Apart from making testing easier,
this also makes simulation faster because a few cycles are required to initialize the
chip.
In general, ad-hoc testing techniques represent a bag of tricks developed over the
years by designers to avoid the overhead of a systems approach to testing, which
will be described in the next section. While these general approaches are still
quite valid, process densities and chip complexities necessitate a structured
approach to testing.
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Figure 5.12 Bus-oriented test techniques

5.3.3 Scan-Based Test Techniques
A collection of approaches have evolved for testing that lead to a structured
approach to testability. The approaches stem from the basic tenets of
controllability and observability.
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Figure 5.13 Multiplexer based testing

5.3.3.1 Level Sensitive Scan Design (LSSD)
A popular approach is called Level Sensitive Scan Design or the LSSD approach,
introduced by IBM. This is based on two tenets. First, that the circuit is level
sensitive. The second principle of LSSD is that each register may be converted to
a serial shift register.
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The basic building block in LSSD is that Shift Register Latch or SRL. A block
level implementation of a polarity hold SRL is shown in figure 5.14(a). It consists
of two latches L1 and L2. L1 has a serial port data, I, and an enable, A. It also has
a data port, D, and an enable, C. when A is high, the value of L1 (T1) is set by the
value of I, while when C is high, L1 is set by D. A and C cannot be
simultaneously high. When signal B in L2 is high, T1 is passed to T2. A gatelevel implementation of the SRL is shown in figure 5.14(b) and 5.14(c). In normal
operation, the D input is the normal input to the register, while the T2 signal is the
output. L1 is the master while L2 is the slave. SRLs may be connected in series by
using the T2 output and the I input of successive latches. During normal system
operation, A is held low and C and B may be thought of as a two-phase
nonoverlapping clock. When data is to be loaded into the SRL or dumped out of
SRL, A and B are used as a two-phase shift clock.
Figure 5.14 A shift register latch

Figure 5.15(a) shows a typical LSSD scan system. An expanded view as shown in
figure 5.15(b). The first rank of SRLs have inputs driven from a preceding stage
and have outputs QA1, QA2 and QA3. These outputs feed a block of
combinational logic. The output of this logic block feeds a second rank of
SRLs with outputs QB1, QB2 and QB3. Figure 5.15(c) shows a typical clocking
sequence. Initially the shift-clk and C2 are clocked three times to shift data into
the first rank of SRLs (QA1-3). C1 is asserted, and then c2 is asserted, clocking
the output of the logic block into the second rank of SRLs (QB1-3), shift-clk and
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C2 are then clocked three times to shift QB1, QB2 and QB3 out via the serialdata-out line.
Figure 5.15 An LSSD scan chain: (a) basic architecture (b) example circuit
(c) example timing
Testing proceeds in this manner of serially clocking the data through the SRLs to
the right point in the manner of serially clocking the data through the SRLs to the
right point in the circuit, running a single system clock cycle and serially clocking
the data out for observation. In this scheme, every input to the combinational
block may be controlled and every output may be observed. In addition,
running a serial sequence of 1s and 0s through the SRLs can test them.
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5.3.3.2 Serial Scan

Level Sensitive Scan went to great pains to provide a hazard-free latching
scheme. Faster clock speeds and design for smaller overhead in the registers has
to led to simplifications in the SRL that give up a little on the hazard front but
retain the scan principle mentioned above. The hazard is moved inside the
register, which with careful design can be guaranteed to be race free for a
particular process and environment characteristics.
A schematic for a commonly used CMOS edge sensitive scan register is shown in
figure5.16. A MUX is added before the master latch in a conventional D register.
TE is the Test Enable pin and TI is the Test Input pin. When TE is enabled, T1 is
closed into the register by rising edge of CLK. Figure 5.17 shows some circuit
level diagram of CMOS SRL implementation. Figure 5.17(a) shows a frequently
used implementation, which uses transmission gates to implement the
multiplexers. The layout density overhead for this latch is minimal. In addition,
because the addition of the testability MUX places two transmissions gates in
series, the increase in delay is minimized. Two further implementation of the
input MUX are shown in figure 5.17(b) and 5.17(c). Figure 5.17(b) shows the
addition of only two transistors and s single control line. A register so
implemented does have the normal problems associated with used single-polarity
transmission gates. Alternatively, the checks may be gated, as shown in figure
5.17(c). While this minimizes transistors, it may lead to unacceptable hold-time
constraints on the register. Because the signals applied to the master latch are
delayed with respect to the main clock, the data has to be held for a longer time at
the input.
Figure 5.16 A typical CMOS scan-register
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Figure 5.17 Various CMOS scan-latch options

5.3.3.3 Partial Serial Scan
Quite often in a design, one may not find it area and speed-efficient to implement
scan registers in every location where a register is used. This occurs for instance
in signal-processing circuits where many pipeline registers might be used to
achieve high speed. If these are in the data-flow section of the chip, then one can
think of the logic that has to be tested as the logic with the pipeline registers
removed. In this case only the input and output registers need to be scannable.
This technique of testing is known as partial scan, and depends on the designer
making decisions about which registers need to be made scannable.
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Consider the design shown in figure 5.18. in a fault scan test strategy all registers
would have to be scannable. A partial scan design is shown in figure 5.18(a)
where only two registers have been made scannable (R6 and R3). In addition,
these registers have the ability to hold their state dependent on a HOLD control.
The part of the circuit that is being tested and monitored by the scan registers is
shown in figure 5.18(b). it may be proven that, by holding the vectors at the input
of the kernel for three clock cycles, the kernel may be represented by the
combinational-equivalent circuit shown in figure 5.18(c). This circuit may be used
by an ATPG program to generate test vectors.
Figure 5.18 The application of scan techniques to employ partial scan (a)
pipeline circuit (b) kernal of pipeline circuit (c) combinational equivalent of
kernal
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5.3.3.4 Parallel Scan

One can imagine that serial-scan chains can become quite long, and the loading
and unloading sequence can dominate testing time. An extension of serial scan is
called random-access or parallel scan.
The basic idea is shown in figure 5.19. Each register in the design is arranged on
an imaginary grid where registers on common rows receive common data lines
and registers in common columns receive common read and write signals. In the
figure, an array of 2-by-2 registers as shown. The D and Q signals of the registers
are connected to the normal circuit connections. Any registers output may be
observed by enabling the appropriate column read line and setting the appropriate
address on an output data multiplexer. Similarly, data may be written to any
register.
Figure 5.20 shows a D-register implementation called a Cross-Controlled Latch. It
consists of a normal CMOS master-slave edge-triggered register augmented by
two small n-transistors, N1 and N2. When test-write-enable is high, and clk is
low, the value of node Y (D) may be sensed on sense[i] via transistor N2. When
test-write-enable is low, probe[j] is high, and clk is high, the value on sense[i]
can be driven onto node Y. This is seen immediately at the output of the register.
The net effect on the register-timing parameters of the extra transistors is to
slightly increase the minimum clock-pulse width. The area impact for an ASIC
based register is around 3%.
The large amount of observable outputs are compressed using signature analysis.
The large number of observable outputs leads to very efficient concurrent-fault
simulation.
Figure 5.19 Parallel scan basic structure
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Figure 5.20 Parallel scan register (a cross-controlled latch)

5.3.4 Self-Test Techniques
Self-test and built-in test techniques, as their names suggest, rely on augmenting
circuits to allow them to perform operations on themselves that prove correct
operation.
5.3.4.1 Signature Analysis and BILBO
One method of incorporating a built-in test module is to use signature analysis or
cyclic-redundancy checking. This involves the use of a pseudo random sequence
generator (PRSG) to generate the input signals for a section of combinational
circuitry and then using signature analyzer to observe the output signals.
A PRSG implements a polynomial of some length N. It is connected from a linear
feedback shift register (LFSR), which is constructed, in turn from a number of 1bit registers connected in serial fashion as shown in figure 5.21. The outputs of
certain shift bits are XORed and fed back to the input of the LFSR to calculate the
required polynomial. For instance, in figure 5.21 the 3-bit shift register is
computing the polynomial f(x) =1+x+x^3. For an n-bit LFSR, the output will
cycle through 2^n-1 states before repeating the sequence. Tables for determining
suitable shift register (CFSR) includes the zero state, which may be required in
some test situations.
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Figure 5.21 Pseudo-random sequence generator (PRSG)

A signature analyzer is constructed by cyclically adding the outputs of a circuit to
a register or an LFSR if successive logic blocks are to be tested in a like manner.
A typical circuit is shown in fugre5.22 (a). As each test vector is run, the
incoming data is XORed with the contents of the LFSR. At the end of a test
sequence, the LFSR contains a number, known as the syndrome, which is a
function of the current output and all previous outputs. This can be compared with
the correct syndrome to determine whether the circuit is good or bad.
Signature analysis can be merged with the scan technique to create a structure
known as BIBLO for Built-In Logic Block Observation
Figure 5.22 Built-in logic block observation (BIBLO) (a) individual register
(b) use in a system
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A 3-bit register is shown with the associated circuitry. In mode D (C0=C1=1), the
registers act as conventional parallel registers. In mode A (C0=C1=0), the
registers act as scan registers. In mode C (C0=1, C1=0) the registers act as a
signature analyzer or pseudo-random sequence generator (PRSG). The registers
are reset if C0=0 and C1=1. Thus a complete test-generation and observation
arrangement can be implemented, as shown in Figure 5.22(b). In this case two
sets of registers have been added in addition to some random logic to effect the
test structure.
A chip set for FFT application was designed with local testing based on pseudorandom pattern generation and signature analysis. With a 28-bit pattern generator
and a 17-bit signature at 10MHz it took 26 seconds to test the part.
5.3.4.2 Memory Self-Test
Embedding self-test circuits for memories in higher-speed circuits not only may
be the way of testing the structures at speed but can save on the number of
external test vectors that have to be run. A typical read/write memory (RAM) test
program for an M-bit address memory might be as follows.
FOR i=0 to M-1 write (data)
FOR i=0 to M-1 read (data) then write (data)
FOR i=0 to M-1 read (data) then write (data)
FOR i=M-1 to 0 read (data) then write (data)
FOR i=M-1 to 0 read (data) then write (data)
data is 1 and data is 0 for a 1-bit memory or a selected set of patterns for an n-bit
word. For an 8-bit memory data might be x00, x55, x33, and x0F. An address
counter, some multiplexers, and a simple-state machine result in a fairly low
overhead self-test structure for read/write memories. The self-test consists of
256K cycles that input a checkerboard pattern to test for cell-to-cell interference.
This is followed by 256K cycles in which the data is read out. Then a
complemented checkerboard is written and read. A total of 1 million cycles
provide a test sufficient for system maintenance.
ROM memories may be tested by placing a signature analyzer at the output of the
ROM and incorporating a test mode that cycles through the contents of the ROM.
A significant advantage of all self-test methods is that testing mat be completed
when the part is in the field. With care, self-test may be performed during normal
system operation.
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5.3.4.3 Iterative logic array testing

Arrays of logic present an interesting problem to the test architect because the
replication can be used to advantage in reducing the number of tests. In addition,
by augmenting the logic extremely high fault coverage rates are possible. An
iterative logic array (ILA) is a collection of identical logic modules (such as an nbit adder). An ILA is C-testable if it can be tested with a constant number of input
vectors independent of the iteration count. An ILA is I-testable if a particular fault
that occurs in any module as a result of an applied input vector is identical for all
modules in the ILA. Assuming that only one module is faulty, the detection of a
fault may be made by using an equality test on the ILA outputs.
5.3.5 IDDQ testing
An increasingly popular method of testing for bridging faults is called is called
IDDQ or current-supply monitoring. This relies on the fact that when a
complementary CMOS logic gate is not switching, it draws no DC current. When
a bridging fault occurs, for some combination of input conditions a measurable
DC IDD will flow. Testing consists of applying the normal vectors, allowing the
signals to settle, and then measuring IDD. To be effective any circuits that draw
DC power such as pseudo-nMOS gates or analog circuits have to be disabled.
Because many circuits now require SLEEP modes to reduce power, this may not
be a substantial additional overhead. Because current measuring is slow, the tests
must be run slower than normal, thus increasing the test time,. However, this
technique gives a form of indirect massive observability at little circuit overhead.
5.4 CHIP-LEVEL TEST TECHNIQUES

In the past the design process was frequently divided between a designer who
designed the circuit and a test engineer who designed the test to apply to that
circuit. The advent of the ASIC, small design teams, the desire for reliable ICs,
and rapid times to market have all forced the test problem earlier in the design
cycle. In fact, the designer who is only thinking about what functionality has to be
implemented and not about how to test the circuit will quite likely cause product
deadlines to be slipped and in extreme cases precuts to be stillborn. In this section
some practical methods of incorporating test requirements into a design. This
discussion is structured around the main types of circuit structure that will be
encountered in a digital CMOS chip.
5.4.1 Regular Logic Array
Partial serial scan or parallel scan is probably the best approach for structures
such as datapaths. One approach that has been used in a Lisp microprocessor is
shown in figure 5.23. Here the input busses may be driven by a serially loaded
register. These in turn may be sourced onto a bus, and this bus may be loaded into
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a register that may be serially accessed. All of the control signals to the datapath
are also made scannable.
5.4.2 Memories
Memories may use the self-testing techniques mentioned in section 5.3.4.2.
alternatively, the provision of multiplexers on data inputs and addresses and
convenient external access to data outputs enables the testing of embedded
memories. It is a mistake to have memories indirectly accessible (i.e., data is
written by passing through logic, data is observed after passing through logic,
addresses cannot be conveniently sequenced). Because memories have to be
tested exhaustively, any overhead on writing and reading the memories can
substantially increase the test time and, probably more significantly, turn the
testing task into an effort inscrutability
Figure 5.23 Datapath test scheme
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5.4.3 Random Logic

Random logic is probably best tested via full serial scan or parallel scan.
5.5 SYSTEM-LEVEL TEST TECHNIQUES

Traditionally at the board level, bed-of-nails testers have been used to test
boards. In this type of a tester, the board under test is lowered onto a set of test
points that probe points of interest on the board. These may be sensed and driven
to test the complete board. At the chassis level, software programs are frequently
used to test a complete board set. For instance, when a computer boots, it might
run a memory test on the installed memory to detect possible faults.
The increasing complexity of boards and the movement to technologies like
Multichip Modules (MCMs) and surface-mount technologies resulted in system
designers agreeing on a unified scan-based methodology for testing chips at the
board(and system level). This is called Boundary Scan.
5.5.1 Boundary Scan
5.5.1.1 Introduction
The IEEE 1149 Boundary Scan architecture is shown in figure 5.24. In essence it
provides a standardized serial scan path through the I/O pins of an IC. At the
board level, ICs obeying the standard may be connected in a variety of series and
parallel combinations to enable testing of a complete board or, possibly,
collection of boards. The description here is a prcis of the published standard.
The standard allows for the following types of tests to be run in a unified testing
framework;
Figure 5.24 Boundary scan architecture
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Connectivity tests between components

Sampling and setting chip I/Os
Distribution and collection of self-test or built-in-test results
5.5.1.2 The Test Access Port (TAP)

The Test Access Port (TAP) is a definition of the interface that needs to be
included in an IC to make it capable of being included in a Boundary-Scan
architecture. The port has four or five single-bit connections, as follows
TCK (The Test Clock Input) used to clock tests into and out of chips.
TMS (The Test Mode Select) used to control test operations.
TDI (The Test data Input) used to input test data to a chip.
TDO (the Test Data Output) used to output test data from a chip.
It also has an optional signal
TRST (The Test Reset Signal) used to asynchronously reset the TAP
controller, also used if a power-up reset signal is not available in the chip
being tested.
The TDO signal is defined as a tristate signal that is only driven when the
TAP controller is outputting test data.
5.5.1.3 The Test Architecture
The basic test architecture that must be implemented on a chip is shown in figure
5.25 it consists of:
the TAP interface pins

a set of test-data registers to collect data from the chip
an instruction register to enable test inputs to be applied to the chip
a TAP controller, which interprets test instructions and controls the flow
of data onto and out of the TAP.
Data that is input via the TDI port may be fed to one or more test dat registers or
an instruction register. An output MUX selects between the instruction register
and the data registers to be output to the tristate TDO pin.
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Figure 5.25 TAP architecture

5.5.1.4 The TAP controller
The TAP controller is a 16-state FSM that proceeds from state to state based on
the TCK and TMS signals. It provides signals that control the test data registers,
and the instruction register. These include serial-shift-clocks and update clocks.
The state diagram shown in figure 5.26. The state adjacent to each state transition
is that of the TMS signal at the rising edge of TCK. The reader is referred to the
standard for complete descriptions of these states. It is probably best to
understand them by examining a typical test sequence. Starting initially in the
Test-Logic-Reset state, a low on TMS transitions the FSM to the Run-Test/Idle
mode. Holding TMS high for the next three TCK cycles places the FSM in the
Select-DR-Scan, Select-IR-Scan, and finally Capture-IR mode. In this mode two
bits are input to the TDI Port and shifted into the instruction register. Asserting
TMS for a cycle allows the instruction register to pause while serially loading to
allow tests to be carried out. Asserting TMS for two cycles, allows the FSM to
enter the Exit2-IR mode on exit from the Pause-IR state and then to enter the
Update-IR mode where the Instruction Register is updated with the new IR value.
Similar sequencing is used to load the data registers.
5.5.1.5 The Instruction Register (IR)
The instruction register has to be at least two bits long, and logic detecting the
state of the instruction register has to decode at least three instructions, which are
as follows;
BYPASS This instruction is represented by an IR having zeroes in it. It

is used to bypass any serial-data registers in a chip with a 1-bit register.
This allows specific chips to be tested in a serial-scan chain without
having to shift through the accumulated SR stages in all the chips
EXTEST This instruction allows for the testing of off-chip circuitry and
is represented by all ones in the IR.
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SAMPLE/PRELOAD This instruction places the boundary-scan registers

(i.e., at the chips I/O pins) in the DR chain, and samples or preloads the
chips I/Os
In addition to these instructions, the following are also recommended:
INTEST This instruction allows for single-step testing of internal

circuitry via the boundary-scan registers.
RUNBIST This instruction is used to run internal self-testing procedures
within a chip.
Further instructions may be defined as needed to provide other testing functions.

A typical IR bit is shown in figure 5.27
Figure 5.27 Instruction register bit implementation

5.5.1.6 Test-Data Registers
The test-data registers are used to set the inputs of modules to be tested, and to
collect the results of running tests. The simplest data-register configuration would
be a boundary-scan register (passing through all I/O pads) and a bypass register
(1-bit long). Figure 5.28 shows a generalized view of the data registers where one
internal data register has been added. A multiplexer under the control of the Tap
controller selects which particular data register is routed to the TDO pin.
5.5.1.7 Boundary Scan Registers
The boundary scan register is a special case of a data register. It allows circuitboard interconnections to be tested, external components tested, and the state of
chip digital I/Os to be sampled. Apart from the bypass register, it is the only data
register required in a Boundary Scan compliant part.
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Figure 5.28 TAP data registers
Figure 5.29 Boundary scan (a) input and (b) output cells
A single structure can be used for all I/O pad types, depending on the connections
made to the cell. It consists of two multiplexers and two edge-triggered registers.
Figure 5.29(a) shows this cell used as an input pad. Two register bits allow the
serial shifting of data through the boundary-scan chain and the local storage of a
data bit. This data bit may be directed to internal circuitry in the INTEST or
RUNBIST modes (Mode=1). When Mode=0, the cell is in EXTEST or
SAMPLE/PRELOAD mode. A further multiplexer under the control of shift DR
controls the serial/parallel nature of the cell. The signal ClockDR and UpdateDR
generated by the Tap Controller load the serial and parallel register, respectively.
An output cell is shown in figure 5.29(b). When Mode=1, the cell is in EXTEST,
INTEST, or RUNBIST modes, communicating the internal data to the output pad.
When Mode=0, the cell is in the SAMPLE/PRELOAD mode.
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Figure 5.30 Boundary scan tristate cell
Figure 5.31 Boundary scan bidirectional cell

Two output cells may be combined to form a tristate boundary-scan cell, as shown
in figure 5.30. The output signal and tristate-enable each have their own muxes
and registers. The Mode control is the same for the output-cell example. A
bidirectional pin combines an input and tristate cell, as shown in figure 5.31
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VLSI DESIGN

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1.1 The Fabrication of a Semiconductor Device

1.1.2 Wafer Fabrication

1.2 Basic CMOS Technology

1.2.1 A Basic n-well CMOS Process

1.2.2 A Basic p-well CMOS Process

1.2.3 Twin-Tub (Twin-Well) CMOS Process

1.2.4 Silicon On Insulator (SOI) Process

1.3.1 Metal Interconnect

1.3.2 Polysilicon/Refractory Metal Interconnect

1.3.3 Local Interconnect

1.4 CIRCUIT ELEMENTS

1.4.3 Electrically Alterable ROMs

1.4.4 Bipolar Transistors

1.4.5.1 The Physical Origin of Latchup

1.4.5.2 Latchup Triggering

1.4.6 Latchup Prevention

1.5. LAYOUT DESIGN RULES

1.5.1 Layer Representations

1.5.2 CMOS n-well Rules

1.5.3 Scribe Line

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1.5.5 Layer Assignments

1.6 PHYSICAL DEISGN

1.6.1 Basic Concept

1.6.2 CAD Tools sets

1.6.3 Physical Design-The Inverter

1.6.4 Physical Design-The NOR

1.6.5 Physical Design-The NAND

1.7 DESIGN STRATEGIES

1.7.1 Structured Design Strategies

UNIT 2 MOS TRANSISTOR THEORY

2.2 PMOS ENHANCEMENT TRANSISTOR

2.3 THRESHOLD VOLTAGE

2 . 3 . 1 Threshold Voltage Equations

2.4 BODY EFFECT

2.5 MOS Device Design Equations

2.5.1 Basic DC Equations

2.5.2 Second Order Effects

2.5.2.1 Threshold Voltage-Body Effect

2.5.2.2 Subthreshold Region

2.5.2.3 Channel-length Modulation

2.5.2.4 Mobility Variation

2.6 MOS MODELS

2.7 SMALL SIGNAL AC CHARACTERISTICS

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2.8.1 n/p ratio

2.8.2 Noise Margin

2.9 THE TRANSMISSION GATE

2.10 THE TRISTATE INVERTER

UNIT 3 SPECIFIFCATION OF VERILOG HDL

3.1 BASIC CONCEPTS