CMOS Analog Circuit Design (Allen-2016)

CMOS ANALOG CIRCUIT DESIGN LECTURES
Lecture Section Topic

Number Number
1 1.1-1.4 Introduction
2 2.1 Submicron CMOS Technology
3 2.1 Deep Submicron CMOS Technology
4 - Ultra-Deep Submicron CMOS and BiCMOS Technology
5 2.2 PN Junctions and CMOS Transistors
6 2.4 Capacitors
7 2.4 Resistors and Inductors
8 - Latchup and ESD
9 3.1 Large Signal MOSFET Model
10 3.2 MOSFET Capacitor Model and Large Signal Model Dependence
11 3.3 Small Signal Models, Noise, Passive Component Models
12 - Component Matching
13 3.6 Computer Models and Extraction of the Simple Large Signal Model
14 4.1 MOS Switch
15 4.3 Current Sinks and Sources
16 4.4-4.5 Current Mirrors and Simple References
17 4.6 Bandgap References
18 5.1 Inverting Amplifier
19 5.2 Differential Amplifier
20 5.3 Low Input Resistance Amplifiers – CG, Cascode and Current Amplifiers
21 5.4 Output Amplifiers
22 6.1-6.2 Compensation of Op Amps
23 6.3 Two-stage Op Amp Design
24 6.4-6.5 Cascode Op Amps
25 6.6 Simulation and Measurement of Op Amps
26 7.1 Buffered Op Amps
27 7.2 High Speed Op Amps
28 7.3 Differential-In, Differential-Out Op Amps
29 7.4 Low Noise and Low Power Op Amps
30 7.5 Low Voltage Op Amps
31 8.1 Open-Loop Comparators
32 8.2 Improved Open-Loop Comparators and Latches
33 8.3 High speed comparators
34 10.1 Characterization of DACs and Current Scaling DACs
35 10.2 Voltage, Charge Scaling and Serial DACs, Improved Resolution
36 10.3 Characterization of ADCs and Sample and Hold Circuits
37 10.4 Moderate Speed Nyquist ADCs
38 10.5 High Speed Nyquist ADCs
39 10.6 Oversampling ADCs – Part I
40 10.7 Oversampling ADCs – Part II
Lecture 01 – Introduction (7/6/15) Page 01-1
LECTURE 01 - INTRODUCTION TO CMOS ANALOG CIRCUIT

DESIGN
LECTURE ORGANIZATION
Outline
• Introduction
• What is Analog Design?
• Skillset for Analog IC Circuit Design
• Trends in Analog IC Design
• Notation, Terminology and Symbols
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
Pages 1-16
CMOS Analog Circuit Design © P.E. Allen - 2016

INTRODUCTION
Course Objective
This course teaches analog integrated circuit design using CMOS technology.
VDD
VPB1
I4 I5
SPECIFICATIONS
M4 M5
I1 I2 VPB2
I6 I7
vOUT
M6 M7
+
M1 M2 VNB2
vIN
- M8 M9 CL
VNB1 M3 I
3 M10 M11
070209-01

Course Prerequisites
• Basic understanding of electronics
- Active and passive components
- Large and small signal models
- Frequency response
• Circuit analysis techniques
- Mesh and loop equations
- Superposition, Thevenin and Norton’s equivalent circuits
• Integrated circuit technology
- Basics process steps
- PN junctions

Course Organization – Based on 3rd Ed. of CMOS Analog Circuit Design
Appendix E Chapter 9
Switched Capaci- D/A and A/D
tor Circuits Converters
Systems
Chapter 6 Chapter 7 Chapter 8

Simple CMOS & High Performance CMOS/BiCMOS
BiCMOS OTA's OTA's Comparators
Complex
Chapter 4 Chapter 5
CMOS CMOS
Subcircuits Amplifiers
Simple
Circuits
Chapter
Chapter10
2 Chapter
Chapter11
3
CMOS/BiCMOS
D/A and A/D CMOS/BiCMOS
Analog
Technology
Converters Modeling
Systems
Devices
Introduction
070209-02

References
1.) P.E. Allen and D.R. Holberg, CMOS Analog Circuit Design – 3rd Ed., Oxford
University Press, 2012.
2.) P.R. Gray, P.J. Hurst, S.H. Lewis and R.G. Meyer, Analysis and Design of Analog
Integrated Circuits – 4th Ed., John Wiley and Sons, Inc., 2001.
3.) B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc., 2001.
4.) R.J. Baker, H.W. Li and D.E. Boyce, CMOS Circuit Design, Layout, and
Simulation, IEEE Press, 1998.
5.) D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley and Sons,
Inc., 1997.
6.) K.R. Laker and W.M.C. Sansen, Design of Analog Integrated Circuits and Systems,
McGraw-Hill, Inc., 1994.
7.) R.L. Geiger, P.E. Allen and N.R. Strader, VLSI Techniques for Analog and Digital
Circuits, McGraw-Hill, Inc., 1990.
8.) A. Hastings, The Art of Analog Layout – 2nd Ed., Prentice-Hall, Inc., 2005.
9.) J. Williams, Ed., Analog Circuit Design - Art, Science, and Personalities,
Butterworth-Heinemann, 1991.
10.) R.A. Pease, Troubleshooting Analog Circuits, Butterworth-Heinemann, 1991.
Course Philosophy
This course emphasizes understanding of analog integrated circuit design.
Although simulators are very powerful, the designer must understand the circuit before
using the computer to simulate a circuit.

WHAT IS ANALOG DESIGN?

The Analog IC Design Process

What is Electrical Design?

Electrical design is the process of going from the specifications to a circuit solution. The
inputs and outputs of electrical design are:
L
W
W/L ratios
VDD
M6
Circuit or Analog M3 M4 Cc
vout
systems Integrated -
vin
M1 M2 CL
specifications Circuit Design +

VBias M5
M7
-
VSS
Topology
DC Currents Fig. 1.1-3
The electrical design requires active and passive device electrical models for
- Creating the design
- Verifying the design
- Determining the robustness of the design

Steps in Electrical Design

1.) Selection of a solution
- Examine previous designs
- Select a solution that is simple
2.) Investigate the solution
- Analyze the performance (without a computer)
- Determine the strengths and weaknesses of the solution
3.) Modification of the solution
- Use the key principles, concepts and techniques to implement
- Evaluate the modifications through analysis (still no computers)
4.) Verification of the solution
- Use a simulator with precise models and verify the
solution
- Large disagreements with the hand analysis and
computer verification should be carefully examined.

What is Physical Design?

Physical design is the process of representing the electrical design in a layout consisting
of many distinct geometrical rectangles at various levels. The layout is then used to
create the actual, three-dimensional integrated circuit through a process called
fabrication.
CIRCUIT LAYOUT FABRICATION
Blue Green Black Red Orange White
n+ p+ Metal Poly p-well n-substrate
Ground
+5V vout
M2
vout
vin
M2
(2.5V) (2.5V)
M1
M1 p+
p+
n+
te
n+
tra
bs
p-well
su
n-
n-substr
ate
031113-01
5V vin

What is the Layout Process?

1.) Inputs are the W/L values and the schematic (generally from schematic entry used for
simulation).
2.) A CAD tool is used to enter the various geometries. The designer must enter the
location, shape, and level of the particular geometry.
3.) During the layout, the designer must obey a set of rules called design rules. These
rules are for the purpose of ensuring the robustness and reliability of the technology.
4.) Once the layout is complete, then a process called layout versus schematic (LVS) is
applied to determine if the physical layout represents the electrical schematic.
5.) The next step is now that the physical dimensions of the design are known, the
parasitics can be extracted. These parasitics primarily include:
a.) Capacitance from a conductor to ground
b.) Capacitance between conductors
c.) Bulk resistance
6.) The extracted parasitics are entered into the simulated database and the design is re-
simulated to insure that the parasitics will not cause the design to fail.

Packaging†
Packaging of the integrated circuit is an important part of the physical design process.
The function of packaging is:
1.) Protect the integrated circuit
2.) Power the integrated circuit
3.) Cool the integrated circuit
4.) Provide the electrical and mechanical connection between the integrated circuit and
the outside world.
Packaging steps:
Attachment Connecting Encapsulating the
Dicing
of the chip to the chip to chip and lead
the wafer
a lead frame a lead frame frame in a package
031115-01
Other considerations of packaging:

• Speed
• Parasitics (capacitive and inductive)
†Rao Tummala, “Fundamentals of Microsystems Packaging,” McGraw-Hill, NY, 2001.

What is Test Design?

Test design is the process of coordinating, planning and implementing the
measurement of the analog integrated circuit performance.
Objective: To compare the experimental performance with the specifications and/or

simulation results.
Types of tests:
• Functional – verification of the nominal specifications
• Parametric – verification of the characteristics to within a specified tolerance
• Static – verification of the static (AC and DC) characteristics of a circuit or system
• Dynamic – verification of the dynamic (transient) characteristics of a circuit or system
Additional Considerations:
Should the testing be done at the wafer level or package level?
How do you remove the influence (de-embed) of the measurement system from the
measurement?
ANALOG INTEGRATED CIRCUIT DESIGN SKILLSET

Characteristics of Analog Integrated Circuit Design
• Done at the circuits level
• Complexity is high
• Continues to provide challenges as technology evolves
• Demands a strong understanding of the principles, concepts and techniques
• Good designers generally have a good physics background
• Must be able to make appropriate simplifications and assumptions
• Requires a good grasp of both modeling and technology
• Have a wide range of skills - breadth (analog only is rare)
• Be able to learn from failure
• Be able to use simulation correctly

Understanding Technology
Understanding technology helps the analog IC designer to know the limits of the
technology and the influence of the technology on the design.
Device Parasitics:
Connection Parasitics:
+5V
M2
M2 vout
vin vout vin
+5V
M1
M1
050304-01

Understanding Modeling
Modeling:
Modeling is the process by which the electrical properties of an electronic circuit or
system are represented by means of mathematical equations, circuit representations,
graphs or tables.
Models permit the predicting or verification of the performance of an electronic
circuit or system.
Electronic Equations, Prediction or

Circuits Circuit verification of
and representations, circuit or system
Systems graphs, tables performance
Electronic Modeling Process
030130-02
Examples:
Ohm’s law, the large signal model of a MOSFET, the I-V curves of a diode, etc.
Goal:
Models that are simple and allow the designer to understand the circuit performance.

Key Principles, Concepts and Techniques of Analog IC Design

• Principles mean fundamental laws that Techniques
are precise and never change. "Tricks"
(Webster – A comprehensive and

fundamental law, doctrine, or
assumption. The laws or facts of nature Concepts - Analog
underlying the working of an artificial Information IC Design
Analog
device.) that enhances Design
Process
design
• Concepts will include relationships,
“soft-laws” (ones that are generally true),
analytical tools, things worth
remembering. Principles (laws)
used in design 040511-01
(Webster – An abstract idea generalized
from particular instances.)
• Techniques will include the assumptions, “tricks”, tools, methods that one uses to
simplify and understand.
(Webster – The manner in which technical details are treated, a method of
accomplishing a desired aim or goal.)

Complexity in Analog Design

Analog design is normally done in a non-hierarchical manner and makes little use of
repeated blocks. As a consequence, analog design can become quite complex and
challenging.
How do you handle the complexity?
Systems Systems Level (ADC)
1.) Use as much hierarchy as possible.
2.) Use appropriate organization Circuits Level (op amps)
techniques.
3.) Document the design in an efficient
Circuits Block Level (amplifier)
manner.
4.) Make use of assumptions and
Sub-block Level (current sink)
simplifications.
5.) Use simulators appropriately.
Components Components (transistor)
031030-03

Assumptions
Assumptions:
An assumption is taking something to be true without formal proof. Assumptions in
analog circuit design are used for simplifying the analysis or design. The goal of an
assumption is to separate the essential information from the nonessential
information of a problem.
The elements of an assumption are:
1.) Formulating the assumption to simplify the problem without eliminating the
essential information.
2.) Application of the assumption to get a solution or result.
3.) Verification that the assumption was in fact appropriate.
Examples:
Neglecting a large resistance in parallel with a small resistance
Miller effect to find a dominant pole
Finding the roots of a second-order polynomial assuming the roots are real and
separated

WHERE IS ANALOG IC DESIGN TODAY?

Analog IC Design has Reached Maturity
There are established fields of application:
• Digital-analog and analog-digital conversion
• Disk drive controllers
• Modems - filters
• Bandgap reference
• Analog phase lock loops
• DC-DC conversion
• Buffers
• Codecs
• Etc.
Existing philosophy regarding analog circuits:
“If it can be done economically by digital, don’t use analog.”
Consequently:
Analog finds applications where speed, area, or power have advantages over a
digital approach.

Analog IC Design Challenges

Technology:
• Digital circuits have scaled well with technology
• Analog does not benefit as much from smaller features
- Speed increases
- Gain decreases
- Matching decreases
- Nonlinearity increases
- New issues appear such as gate current leakage
Analog Circuit Challenges:
• Trade offs are necessary between linearity, speed, precision and power
• As analog is combined with more digital, substrate interference will become worse

Digitally Assisted Analog Circuits

Use digital circuits which work better at
scaled technologies to improve analog
circuits that do not necessarily improve
with technology scaling.
Principles and Techniques:
• Open-loop vs. closed loop
- Open loop is less accurate but smaller  Faster, less power
- Closed-loop is more accurate but larger  Slower, more power
• Averaging
- Increase of accuracy  Smaller devices, more speed
• Calibration
- Accuracy increases  Increased resolution with same area
• Dynamic Element Matching
- Enhancement of component precision
• Doubly correlated sampling
- Reduction of dc influences (noise, offset)  Smaller devices, more speed
• Etc.
A New Paradigm for IC Design?

• Today’s Paradigm
– $ invested up front
– No guarantee that product will be profitable
– Requires a lot of overhead, support, and time
Potential market for IC is designed and IC is
an IC is identified fabricated marketed
150623-02
• New Paradigm (shaped by the internet)
– No $ invested until the product is sold

– The need for an IC is generated by potential consumer
– Opens the design space to a wide range of “designers”
– Massive markets not needed to make a product and profit
– Minimizes the time and overhead required to develop a product
– Design equivalent of crowd funding ➞ “crowd designing”
NOTATION, TERMINOLOGY AND SYMBOLOGY

Definition of Symbols for Various Signals
Signal Definition Quantity Subscript Example

Total instantaneous value of the signal Lowercase Uppercase qA
DC value of the signal Uppercase Uppercase QA
AC value of the signal Lowercase Lowercase qa
Complex variable, phasor, or rms value Uppercase Lowercase Qa
of the signal
Example:
Drain Current
Idm
id
ID iD
t
Fig. 1.4-1

MOS Transistor Symbols

D S
Enhancement Enhancement
G NMOS with G PMOS with
VBS = 0V. VBS = 0V.
S D
D S
Enhancement Enhancement
G B NMOS with G B PMOS with
VBS ¹ 0V. VBS ¹ 0V.
S D
D S
Simple Simple
G NMOS G PMOS
symbol symbol
S D

Other Schematic Symbols

+ + + +
V V V
- -
-
-
Differential amplifier,
op amp, or comparator Independent Independent
voltage sources current source
I2
+ + +
+
V1 AvV1 - V2 V1 GmV1
- - -
Voltage-controlled, Voltage-controlled,
voltage source current source
I1 I1 I2
RmI1 +- V2 AiI1
-
Current-controlled, Current-controlled,
voltage source current source

Three-Terminal Notation
QABC
A = Terminal with the larger magnitude of potential
B = Terminal with the smaller magnitude of potential
C = Condition of the remaining terminal with respect to terminal B
C = 0  There is an infinite resistance between terminal B and the 3rd terminal
C = S  There is a zero resistance between terminal B and the 3rd terminal
C = R  There is a finite resistance between terminal B and the 3rd terminal
C = X  There is a voltage source in series with a resistor between terminal B
and the 3rd terminal in such a manner as to reverse bias a PN
junction. IDSS
S D S D
Examples
D +
- G
VGS CDGS IDS BVDGO
+
G S G -
(a.) (b.) (c.)

(a.) Capacitance from drain to gate with the source shorted to the gate.
(b.) Drain-source current when gate is shorted to source (depletion device)
(c.) Breakdown voltage from drain to gate with the source is open- circuited to the gate.

SUMMARY
• Successful analog IC design proceeds with understanding the circuit before simulation.
• Analog IC design consists of three major steps:
1.) Electrical design  Topology, W/L values, component values and dc currents
2.) Physical design (Layout)
3.) Test design (Testing)
• Analog designers must be flexible and have a skill set that allows one to simplify and
understand a complex problem
• Analog IC design has reached maturity and is here to stay.
• The appropriate philosophy is “If it can be done economically by digital, don’t use
analog”.
• As a result of the above, analog finds applications where speed, area, or power result in
advantages over a digital approach.
• Deep-submicron technologies will offer exciting challenges to the creativity of the
analog designer.
• Paradigm for IC design might be changing which would influence analog IC design.

Lecture 02 – Submicron CMOS Technology (12/9/13) Page 02-1
LECTURE 02 - SUBMICRON CMOS TECHNOLOGY

Outline
• CMOS Technology
• Fundamental IC Process Steps
• Typical Submicron CMOS Fabrication Process
• Summary
Pages 18-33

CMOS TECHNOLOGY
Categorization of CMOS Technology
• Minimum feature size as a function of time:
1
Submicron Technology
Minimum Feature Size (µm)
Deep Submicron Technology
0.1
Ultra Deep Submicron Technology (Nanotechnology)
0.01
1985 1990 1995 2000 2005 2010 2020
Year 120327-01
• Categories of CMOS technology:

1.) Submicron technology – Lmin ≥ 0.35 microns
2.) Deep Submicron technology (DSM) – 0.1 microns ≤ Lmin ≤ 0.35 microns
3.) Ultra-Deep Submicron technology (UDSM) – Lmin ≤ 0.1 microns
Why CMOS Technology?

Comparison of BJT and MOSFET technology from an analog viewpoint:
Comparison Feature BJT MOSFET
Cutoff Frequency(fT) 100 GHz 50 GHz (0.25µm)
Noise (thermal about the same) Less 1/f More 1/f
DC Range of Operation 9 decades of exponential 2-3 decades of square law
current versus vBE behavior
Transconductance (Same current) Larger by 10X Smaller by 10X
Small Signal Output Resistance Slightly larger Smaller for short channel
Switch Implementation Poor Good
Capacitor Voltage dependent More options
Performance/Power Ratio High Low
Technology Improvement Slower Faster
Therefore,
• Almost every comparison favors the BJT, however a similar comparison made from
digital viewpoint would come up on the side of CMOS.
• Therefore, since large-volume mixed-mode technology will be driven by digital
demands, CMOS is an obvious result as the technology of availability.

FUNDAMENTAL IC PROCESS STEPS

Basic Steps for a CMOS Submicron Process
• Oxide growth
• Thermal diffusion
• Ion implantation
• Deposition
• Etching
• Epitaxy
Photolithography
Photolithography is the means by which the above steps are applied to selected
areas of the silicon wafer.
Silicon Wafer

Oxidation
Description:
Oxidation is the process by which a layer of silicon dioxide is grown on the
surface of a silicon wafer.
Original silicon surface tox
Silicon dioxide
0.44 tox Silicon substrate

Fig. 2.1-2
Uses:
• Protect the underlying material from contamination
• Provide isolation between two layers.
Very thin oxides (100Å to 1000Å) are grown using dry oxidation techniques.
Thicker oxides (>1000Å) are grown using wet oxidation techniques.
Diffusion
Diffusion is the movement of impurity atoms at the surface of the silicon into the
bulk of the silicon.
Always in the direction from higher
High Low
concentration to lower concentration. Concentration
Concentration
Fig. 150-04
Diffusion is typically done at high temperatures: 800 to 1400°C

ERFC Gaussian
N0 N0
N(x) t1 < t2 < t3 N(x) t1 < t2 < t3
NB NB
t3 t2 t3
t1 t2 t1
Depth (x) Depth (x)
Infinite source of impurities at the surface. Finite source of impurities at the surface.
Fig. 150-05

Ion Implantation
Ion implantation is the process by Path of
impurity
which impurity ions are accelerated to atom
a high velocity and physically lodged
into the target material. Fixed Atom
Fixed Atom
• Annealing is required to activate the Fixed Atom
Impurity Atom
impurity atoms and repair the physical
final resting place
damage to the crystal lattice. This step Fig. 150-06
is done at 500 to 800°C.
• Ion implantation is a lower temperature
process compared to diffusion. Concentration peak
N(x)
• Can implant through surface layers, thus it
is useful for field-threshold adjustment.
• Can achieve unique doping profile such as
buried concentration peak. NB
Generally implant first then use diffusion
to achieve the well or active area. 0 Depth (x) Fig. 150-07

Deposition
Deposition is the means by which various materials are deposited on the silicon
wafer.
Examples:
• Silicon nitride (Si3N4)
• Silicon dioxide (SiO2)
• Aluminum
• Polysilicon 120521-01
There are various ways to deposit a material on a substrate:

• Chemical-vapor deposition (CVD)
• Low-pressure chemical-vapor deposition (LPCVD)
• Plasma-assisted chemical-vapor deposition (PECVD)
• Sputter deposition
Material that is being deposited using these techniques covers the entire wafer
and requires no mask.

Etching
Etching is the process of selectively Mask
Film
removing a layer of material.
When etching is performed, the etchant Underlying layer
may remove portions or all of: (a) Portion of the top layer ready for etching.
a Selectivity
• The desired material
Mask
• The underlying layer Film c
• The masking layer b Anisotropy
Selectivity Underlying layer
Important considerations:
(b) Horizontal etching and etching of underlying layer.
• Anisotropy of the etch is defined as, Fig. 150-08
A = 1-(lateral etch rate/vertical etch rate)

• Selectivity of the etch (film to mask and film to substrate) is defined as,
film etch rate
Sfilm-mask = mask etch rate
A = 1 and Sfilm-mask =  are desired.

There are basically two types of etches:
• Wet etch which uses chemicals
• Dry etch which uses chemically active ionized gases.
Epitaxy
Epitaxial growth consists of the formation of a layer of single-crystal silicon on
the surface of the silicon material so that the crystal structure of the silicon is
continuous across the interfaces.
• It is done externally to the material as opposed to diffusion which is internal
• The epitaxial layer (epi) can be doped differently, even opposite to the material on
which it is grown
• It is accomplished at high temperatures using a chemical reaction at the surface
• The epi layer can be any thickness, typically 1-20 microns
Gaseous cloud containing SiCL 4 or SiH4

Si Si + Si Si
+ +
Si Si Si Si Si Si Si Si Si Si Si Si
+ +
- Si -
Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si
- Si Si Si Si Si Si Si
-
- -
Fig. 150-09
Photolithography
Components:
• Photoresist material
• Mask
• Material to be patterned (e.g., oxide)
Positive photoresist:
Areas exposed to UV light are soluble in the developer
Negative photoresist:
Areas not exposed to UV light are soluble in the developer
Steps:
1. Apply photoresist
2. Soft bake (drives off solvents in the photoresist)
3. Expose the photoresist to UV light through a mask
4. Develop (remove unwanted photoresist using solvents)
5. Hard bake (  100°C)
6. Remove photoresist (solvents)

Illustration of Photolithography - Exposure

Photomask
The process of exposing selective
areas to light through a photo-mask
is called printing.
Types of printing include:
• Contact printing
• Proximity printing
UV Light
• Projection printing
Photomask
Photoresist
Polysilicon
Fig. 150-10

Illustration of Photolithography - Positive Photoresist
Develop
Polysilicon
Photoresist Etch
Photoresist
Polysilicon
Remove
photoresist
Polysilicon
Fig. 150-11

TYPICAL SUBMICRON CMOS FABRICATION PROCESS

N-Well CMOS Fabrication Major Steps
1.) Implant and diffuse the n-well
2.) Deposition of silicon nitride
3.) n-type field (channel stop) implant
4.) p-type field (channel stop) implant
5.) Grow a thick field oxide (FOX)
6.) Grow a thin oxide and deposit polysilicon
7.) Remove poly and form LDD spacers
8.) Implantation of NMOS S/D and n-material contacts
9.) Remove spacers and implant NMOS LDDs
10.) Repeat steps 8.) and 9.) for PMOS
11.) Anneal to activate the implanted ions
12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass)
13.) Open contacts, deposit first level metal and etch unwanted metal
14.) Deposit another interlayer dielectric (CVD SiO2), open vias, deposit 2nd level metal
15.) Etch unwanted metal, deposit a passivation layer and open over bonding pads

Major CMOS Process Steps

Step 1 - Implantation and diffusion of the n-wells
n-well implant
SiO2
Photoresist Photoresist
p- substrate
Step 2 - Growth of thin oxide and deposition of silicon nitride

Si3N4
SiO2
n-well
p- substrate
070523-01

Major CMOS Process Steps – Continued

Step 3.) Implantation of the n-type field channel stop
n- field implant
Photoresist
Si3N4 Photoresist Pad oxide (SiO 2)
n-well
p- substrate
Step 4.) Implantation of the p-type field channel stop

p- field implant
Si3N4
Photoresist
n-well
p- substrate
070523-02


Step 5.) Growth of the thick field oxide (LOCOS - localized oxidation of silicon)
Si3N4
FOX FOX
n-well
p- substrate
Step 6.) Growth of the gate thin oxide and deposition of polysilicon. The thresholds
can be shifted by an implantation before the deposition of polysilicon.
Polysilicon
FOX FOX
n-well
p- substrate
070523-03


Step 7.) Removal of polysilicon and formation of the sidewall spacers
SiO2 spacer
Polysilicon
Photoresist
FOX FOX FOX
FOX
n-well
p- substrate
Step 8.) Implantation of NMOS source and drain and contact to n-well (not shown)
n+ S/D implant
Polysilicon
Photoresist
FOX FOX FOX
FOX
n-well
p- substrate
070523-04

Major CMOS Process Steps - Continued

Step 9.) Remove sidewall spacers and implant the NMOS lightly doped source/drains
n- S/D LDD implant
Polysilicon Photoresist
FOX FOX FOX
FOX
n-well
p- substrate
Step 10.) Implant the PMOS source/drains and contacts to the p - substrate (not shown),
remove the sidewall spacers and implant the PMOS lightly doped source/drains
LDD Diffusion
Polysilicon
FOX FOX FOX

FOX
n-well
p- substrate
070209-03

Step 11.) Anneal to activate the implanted ions
n+ Diffusion p+ Diffusion Polysilicon
FOX FOX FOX

n-well
p- substrate
Step 12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass)

n+ Diffusion p+ Diffusion Polysilicon
BPSG
FOX FOX FOX
n-well
p- substrate
070523-05

Major CMOS Process Steps - Continued

Step 13.) Open contacts, deposit first level metal and etch unwanted metal
CVD oxide, Spin-on glass (SOG) Metal 1
BPSG
FOX FOX FOX
n-well
p- substrate
Step 14.) Deposit another interlayer dielectric (CVD SiO 2), open contacts,
deposit second level metal
Metal 2
Metal 1
BPSG
FOX FOX FOX
n-well
p- substrate
070523-06


Step 15.) Etch unwanted metal and deposit a passivation layer and open
over bonding pads
Metal 2 Metal 1
Passivation protection layer
BPSG
FOX FOX FOX
n-well
p- substrate
070523-07
p-well process is similar but starts with a p-well implant rather than an n-well implant.

Approximate Side View of CMOS Fabrication

Passivation
Metal 4
Metal 3
Metal 2
2 microns
Metal 1
Polysilicon
Diffusion 070523-08

Planarization
Planarization attempts to minimize the variation in surface height of the wafer.
Planarization techniques
• Repeated applications of SOG Tungsten
Plug
• Resist etch-back – highest areas of oxide
are exposed longest to the etchant and
therefore erode away the most.
Influence of planarization on analog design:

+ Number of levels of metal and the metal integrity depends on planarization
+ Thin film components at the surface require good planarization
+ Without planarization, resistance of conductors increases
+ Planarization at the top level leads to less package induced stress (trimming?)
+ Planarized passivation helps printing when the depth of field is small.
- With planarization, the capacitance of the interdielectric isolation can vary (a good
reason to extract capacitance!)
- Significant difference in contact aspect ratio (deep versus shallow contacts)
Chemical Mechanical Polishing

CMP produces the required degree of planarization for modern submicron
technology.
Comments:
• Both chemical effect (slurry) and mechanical (pad pressure) take place.
• Although CMP is superior to SOG and resist etchback, large areas devoid of underlying
metal or poly produce low regions in the final surface.
• Challenge: Achieve a highly planarized surface over a wide range of pattern density.

Chemical Mechanical Polishing – Continued

Impact on analog design:
+ Makes the surface flatter
- Vias and plugs can become longer adding resistance
+ More uniform surface giving better metal coverage and foundation for thin film
components
- Thickness varies with pattern density
Examples of pattern fill:
Pattern density design rules are both local and global.

Silicide/Salicide Technology
Used to reduce interconnect resistivity by placing a low-resistance silicide such
as TiSi2, WSi2, TaSi2, etc. on top of polysilicon
Salicide technology (self-aligned silicide) provides low resistance source/drain
connections as well as low-resistance polysilicon.
Polysilicide Polysilicide
Metal Metal
Salicide
FOX FOX FOX FOX
Polycide structure Salicide structure 070523-09

SUMMARY
• Fabrication is the means by which the circuit components, both active and
passive, are built as an integrated circuit.
• Basic process steps include:
1.) Oxide growth 2.) Thermal diffusion 3.) Ion implantation
4.) Deposition 5.) Etching 6.) Epitaxy
• The complexity of a process can be measured in the terms of the number of
masking steps or masks required to implement the process.
• Major CMOS Processing Steps:
1.) Well definition
2.) Definition of active areas and substrate/well contacts (SiNi3)
3.) Thick field oxide (FOX)
4.) Thin field oxide and polysilicon
5.) Diffusion of the source and drains (includes the LDD)
6.) Dielectric layer/Contacts (planarization)
7.) Metallization
8.) Dielectric layer/Vias

Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-1
LECTURE 03 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGY

Outline
• Characteristics of a deep submicron CMOS technology
• Typical deep submicron CMOS technology
• Summary
New material

CHARACTERISTICS OF A DEEP SUBMICRON CMOS TECHNOLOGY

Isolation of Transistors
The use of reverse bias pn junctions to isolate transistors becomes impractical as the
transistor sizes decrease.

Use of Shallow Trench Isolation Technology

Shallow trench isolation (STI) allows closer spacing of transistors by eliminating the
depletion region at the surface.
Substrate Salicide Substrate Salicide

Well Salicide Decreased
spacing
ion h
Trench Isolation
lat nc
ow
Iso Tre
all
ow
Sh
a ll
Sh
n+ p+ p+ nn++ nnn+++
Shallow Shallow Shallow

Trench n-well Trench Trench
Isolation Isolation p-well Isolation
Substrate 070330-03
Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal

Comparison of STI and LOCOS

What are the differences between a LOCOS and STI technology?
Comments:
• If the n+ to p+ spacing is large, the Bird’s beak can be compensated using techniques
such as poly buffered LOCOS
• At some point as the n+ to p+ spacing gets smaller, the restricted bird’s beak leads to
undesirable stress effects in the transistor.
• An important advantage of STI is that it minimizes the heat cycle needed for n+ or p+
isolation compared to LOCOS. This is a significant advantage for any process where
there are implants before STI.

Shallow Trench Isolation (STI)

Nitride
1.) Cover the wafer with pad oxide and silicon nitride. (1) Silicon
2.) First etch nitride and pad oxide. Next, an anisotropic

(2)
etch is made in the silicon to a depth of 0.4 to 0.5 microns.
(3)
3.) Grow a thin thermal oxide layer on the trench walls.
(4)
4.) A CVD dielectric film is used to fill the trench.
(5)
5.) A chemical mechanical polishing (CMP) step is used to
polish back the dielectric layer until the nitride is reached.
The nitride acts like a CMP stop layer. (6)
6.) Densify the dielectric material at 900°C and strip the 060203-01
nitride and pad oxide.

Illustration of a Deep Submicron (DSM) CMOS Technology

Metal Layers
0.8mm M8
NMOS PMOS
Transistor Transistor M7
M6
Polycide 0.3mm M5 7mm
Polycide Sidewall Spacers
M4
Salicide Salicide M3
Salicide M2
M1
n+ n+ p+ p+
STI Source/drain STI Source/drain STI
extensions extensions
Deep p-well Deep n-well p-substrate
031211-02
In addition to NMOS and PMOS transistors, the technology provides:

1.) A deep n-well that can be utilized to reduce substrate noise coupling.
2.) A MOS varactor that can serve in VCOs
3.) At least 6 levels of metal that can form many useful structures such as inductors,
capacitors, and transmission lines.

Transistors
fT as a function of gate-source overdrive, VGS-VT (0.13µm):
Typical, 25°C
70
60 NMOS
Slow, 70°C
50
fT (GHz)
40 Typical, 25°C
30 PMOS Slow, 70°C
20
10
0
0 100 200 300 400 500
|VGS-VT| (mV) 030901-07
The upper frequency limit of the transistors varies with overdrive and process corners.
The NMOS transistor has an fT of 40GHz at low overdrives and increases to above
60GHz at the slow-high temperature corner with 0.5V overdrive.

Resistors
1.) Diffused and/or implanted resistors.
2.) Well resistors.
3.) Polysilicon resistors.
4.) Metal resistors.

Capacitors
Polysilicon-polysilicon
capacitors:
Metal-metal capacitors:
Protective Insulator Layer
Metal Via
Top
Vias connecting top Metal
Capacitor plate to top metal
dielectric Capacitor Top Metal Second level
Inter-
Vias connecting bottom from top metal
mediate
Capacitor bottom plate plate to lower metal Third level
Oxide
Layers Vias connecting bottom from top metal
plate to lower metal Fourth level
from top metal
060530-01
Inductors
Top view and cross-section of a planar inductor:
Top Metal
Top Metal
W
S Next Level
Metal
Vias Oxide
Next Level Oxide
Metal
D
Silicon Substrate
N turns
030828-01
D
Enhanced inductor removing the substrate†:
†
M. Raieszadeh, Integrated Inductors on Trenched Silicon Islands, MS Thesis, School of Electrical and Computer Engineering, Georgia Institute of Technology, April 2005

TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS

Major Fabrication Steps for a DSM CMOS Process
1.) p and n wells
2.) Shallow trench isolation
3.) Threshold shift and anti-punch through implants
4.) Thin oxide and gate polysilicon
5.) Lightly doped drains and sources
6.) Sidewall spacer
7.) Heavily doped drains and sources
8.) Siliciding (Salicide and Polycide)
9.) Bottom metal, tungsten plugs, and oxide
10.) Higher level metals, tungsten plugs/vias, and oxide
11.) Top level metal, vias and protective oxide

Starting Material
The substrate should be highly doped to act like a good conductor.
Substrate
Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal 060118-02

Step 1 - n and p wells

These are the areas where the transistors will be fabricated - NMOS in the p-well and
PMOS in the n-well.
Done by implantation followed by a deep diffusion.
n well implant and diffusion p well implant and diffusion
p+ n+
n-well p-well
Substrate

Step 2 – Shallow Trench Isolation

The shallow trench isolation (STI) electrically isolates one region/transistor from
another.
p+ n+
Trench Trench Trench
Isolation Isolation Isolation
n-well p-well
Substrate

Step 3 – Threshold Shift and Anti-Punch Through Implants

The natural thresholds of the NMOS is about 0V and of the PMOS is about –1.2V. An
p-implant is used to make the NMOS harder to invert and the PMOS easier resulting in
threshold voltages balanced around zero volts.
Also an implant can be applied to create a higher-doped region Source Drain
beneath the channels to prevent punch-through from the drain
Punch-through
depletion region extending to source depletion region.
120521-02
n+ anti-punch through implant p+ anti-punch through implant
p threshold implant p threshold implant
n+
n-well p-well
Substrate

Step 4 – Thin Oxide and Polysilicon Gates

A thin oxide is deposited followed by polysilicon. These layers are removed where they
are not wanted.
p+ n+
n-well p-well
Substrate

Step 5 – Lightly Doped Drains and Sources

A lightly-doped implant is used to create a lightly-doped source and drain next to the
channel of the MOSFETs.
Shallow p- Shallow p- Shallow n- Shallow n-

Implant Implant Implant Implant
p+ n+
n-well p-well
Substrate

Step 6 – Sidewall Spacers

A layer of dielectric is deposited on the surface and removed in such a way as to leave
“sidewall spacers” next to the thin-oxide-polysilicon-polycide sandwich. These sidewall
spacers will prevent the part of the source and drain next to the channel from becoming
heavily doped.
Sidewall Sidewall
Spacers Spacers
p+ n+
n-well p-well
Substrate

Step 7 – Implantation of the Heavily Doped Sources and Drains

Note that not only does this step provide the completed sources and drains but allows for
ohmic contact into the wells and substrate.
n+ p+ p+ n+ n+ p+
implant implant implant implant implant implant
n+ p+ p+ n+ nn++ p+
n-well p-well
Substrate

Step 8 – Siliciding (Salicide and Polycide)

This step reduces the resistance of the bulk diffusions and polysilicon and forms an
ohmic contact with material on which it is deposited.
Salicide = Self-aligned silicide
Polycide Polycide
Salicide Salicide Salicide

Salicide
n+ p+ pp++ n+ nn++ p+
n-well p-well
Substrate

Step 9 – Intermediate Oxide Layer

An oxide layer is used to cover the transistors and to planarize the surface.

Step 10- First-Level Metal

Tungsten plugs are built through the lower intermediate oxide layer to provide contact
between the devices, wells and substrate to the first-level metal.

Step 11 – Second-Level Metal

The previous step is repeated for the second-level metal.

Completed Fabrication
After multiple levels of metal are applied, the fabrication is completed with a thicker top-
level metal and a protective layer to hermetically seal the circuit from the environment.
Note that metal is used for the upper level metal vias. The chip is electrically connected
by removing the protective layer over large bonding pads.

Scanning Electron Microscope of a MOSFET Cross-section
Tungsten Plug
TEOS
SOG
Polycide
Sidewall
TEOS/BPSG Spacer
Poly
Gate
Fig. 2.8-20

Scanning Electron Microscope Showing Metal Levels and Interconnect
Metal 3
Aluminum
Vias
Metal 2
Tungsten
Plugs
Metal 1
Transistors Fig.180-11

SUMMARY
• DSM technology typically has a minimum channel length between 0.35µm and 0.1µm
• DSM technology addresses the problem of excessive depletion region widths in
junction isolation techniques by using shallow trench isolation
• DSM technology may have from 4 to 8 levels of metal
• Lightly doped drains and sources are a key aspect of DSM technology

Lecture 04 – UDSM and BiCMOS Technologies (3/10/14) Page 04-1
LECTURE 04 - ULTRA-DEEP SUBMICRON AND BiCMOS

TECHNOLOGIES
Outline
• Ultra-deep submicron CMOS technology
- Features
- Advantages
- Problems
• BiCMOS technology process flow
- CMOS is typical submicron (0.5 µm)
• Summary
New material

ULTRA-DEEP SUBMICRON (UDSM) CMOS TECHNOLOGY

USDM Technology
• Lmin ≤ 0.1 microns
• Minimum feature size less than 100 nanometers
• Today’s state of the art:
- 22 nm drawn length
- 5 nm lateral diffusion (12 nm gate length)
- 1 nm transistor gate oxide
- 8 layers of copper interconnect
• Specialized processing is used to increase drive capability and maintain low off
currents

65 Nanometer CMOS Technology

TEM cross-section of a 35 nm NMOS and PMOS transistors.†
NMOS: PMOS:
220 nm pitch
NMOS
These transistors utilize enhanced channel strains to

increase drive capability and to reduce off currents.
†P. Bai, et. Al., “A 65nm Lobic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and
0.57 µm2 SRAM Cell, IEEE Inter. Electron Device Meeting, Dec. 12-15, 2005.
UDSM Metal and Interconnects

Physical aspects:
Layer Pitch Thickness Aspect
(nm) (nm) Ratio
Isolation 220 230 -
Polysilicon 220 90 -
Contacted Gate Pitch 220 - -
Metal 1 210 170 1.6
Metal 2 210 190 1.8
Metal 3 220 200 1.8
Metal 4 280 250 1.8
Metal 5 330 300 1.8
Metal 6 480 430 1.8
Metal 7 720 650 1.8
Metal 8 1080 975 1.8

What are the Advantages of UDSM CMOS Technology?

Digital Viewpoint:
• Improved Ion/Ioff 70 Mbit SRAM chip:
• Reduced gate capacitance
• Higher drive current capability
• Reduced interconnect density
• Reduction of active power
Analog Viewpoint:
• More levels of metal
• Higher fT
• Higher capacitance density
• Reduced junction capacitance per gm
• More speed

What are the Disadvantages of UDSM CMOS Technology (for Analog)?

• Reduction in power supply resulting in reduced headroom
• Gate leakage currents
• Reduced small-signal intrinsic gains
• Increased nonlinearity (IIP3)
• Increased noise and poorer matching (smaller area)
Intrinsic gain and IP3 as a function of the gate overdrive for decreasing VDS:†
†Anne-Johan Annema, et. Al., “Analog Circuits in Ultra-Deep-Submicron CMOS,” IEEE J. of Solid-State Circuits, Vol. 40, No. 1, Jan. 2005, pp.
132-143.
What is the Gate Leakage Problem?

Gate current occurs in thin oxide devices due to direct tunneling through the thin oxide.
Gate current depends on:
1.) The gate-source voltage (and the drain-gate voltage)
iGS = K1vGS exp(K2vGS) and iGD = K3vGD exp(K4vGD)
2.) Gate area – NMOS leakage ≈ 6nA/µm2 and PMOS leakage ≈ 3nA/µm2
Unfortunately, the gate leakage current is nonlinear with respect to the gate-source and
gate-drain voltages. A possible model is:
- +
f(vGD) vGD f(vSG) vSG ggd gsg
+ -
+ -
f(vGS) vGS f(vDG) vDG ggs gdg
- +
NMOS PMOS NMOS PMOS

051205-03 Large Signal Models Small Signal Models
Base current cancellation schemes used for BJTs are difficult to apply to the MOSFET.

UDSM CMOS Technology Summary

• Increased transconductance and frequency capability
• Low power supply voltages
• Reduced parasitics
• Gate leakage causes challenges for analog applications of UDSM technology
- Can no longer use the MOSFET for capacitance
- Conflict between matching and gate leakage
• Other issues
- Noise
- Zero temperature coefficient behavior
- Etc.

BiCMOS TECHNOLOGY
Typical 0.5µm BiCMOS Technology
Masking Sequence:
1. Buried n+ layer 9. Base oxide/implant 17. Contacts
2. Buried p+ layer 10. Emitter implant 18. Metal 1
3. Collector tub 11. Poly 1 19. Via 1
4. Active area 12. NMOS lightly doped drain 20. Metal 2
5. Collector sinker 13. PMOS lightly doped drain 21. Via 2
6. n-well 14. n+ source/drain 22. Metal 3
7. p-well 15. p+ source/drain 23. Nitride passivation
8. Emitter window 16. Silicide protection
Notation used in the following slides:
BSPG = Boron and Phosphorus doped Silicate Glass (oxide)
Kooi Nitride = A thin layer of silicon nitride on the silicon surface as a result of the
reaction of silicon with the HN3 generated, during the field oxidation.
TEOS = Tetro-Ethyl-Ortho-Silicate. A chemical compound used to deposit conformal
oxide films.

n+ and p+ Buried Layers
Starting Substrate:
p-substrate 1mm
BiCMOS-01 5mm
n+ and p+ Buried Layers:

NPN Transistor PMOS Transistor NMOS Transistor
n+ buried layer p+ buried n+ buried layer p+ buried layer

layer
p-substrate 1mm
BiCMOS-02 5mm

Epitaxial Growth
p-type
n-well p-well n-well p-well
Epitaxial
Silicon
n+ buried layer p+ buried n+ buried layer
p+ buried layer
layer
p-substrate 1mm
BiCMOS-03 5mm
Comment:
• As the epi layer grows vertically, it assumes the doping level of the substrate beneath
it.
• In addition, the high temperature of the epitaxial process causes the buried layers to
diffuse upward and downward.

Collector Tub

Original Area of
CollectorTub Implant
Collector Tub n-well

p-well p-well p-type
Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-04 5mm
Comment:
• The collector area is developed by an initial implant followed by a drive-in diffusion to
form the collector tub.

Active Area Definition
Comment:
• The silicon nitride is use to impede the growth of the thick oxide which allows contact
to the substrate
• -silicon is used for stress relief and to minimize the bird’s beak encroachment

Field Oxide
NPN Transistor
FOX PMOS Transistor NMOS Transistor
FOX Field Oxide Field Oxide Field Oxide

Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-06 5mm
Comments:
• The field oxide is used to isolate surface structures (i.e. metal) from the substrate

Collector Sink and n-Well and p-Well Definitions

Collector Sink Anti-Punch Through Anti-Punch Through
Threshold Adjust Threshold Adjust
FOX

Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-07 5mm

Base Definition
NPN Transistor

Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-08 5mm

Definition of the Emitter Window and Sub-Collector Implant

Sacrifical Oxide
FOX

n-well
Sub-Collector Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-09 5mm

Emitter Implant
NPN Transistor
Emitter Implant PMOS Transistor NMOS Transistor
FOX
Sub-Collector Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-10 5mm
Comments:
• The polysilicon above the base is implanted with n-type carriers

Emitter Diffusion
NPN Transistor

n-well
Emitter Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-11 5mm
Comments:
• The polysilicon not over the emitter window is removed and the n-type carriers diffuse
toward the base forming the emitter

Formation of the MOS Gates and LD Drains/Sources
NPN Transistor

n-well
Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-12 5mm
Comments:
• The surface of the region where the MOSFETs are to be built is cleared and a thin gate
oxide is deposited with a polysilicon layer on top of the thin oxide
• The polysilicon is removed over the source and drain areas
• A light source/drain diffusion is done for the NMOS and PMOS (separately)

Heavily Doped Source/Drain
NPN Transistor

n-well
Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-13 5mm
Comments:
• The sidewall spacers prevent the heavy source/drain doping from being near the
channel of the MOSFET

Siliciding

Silicide TiSi2
FOX Silicide TiSi2 Silicide TiSi2

n-well
Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-14 5mm
Comments:
• Siliciding is used to reduce the resistance of the polysilicon and to provide ohmic
contacts to the base, emitter, collector, sources and drains

Contacts
Tungsten Plugs Tungsten Plugs Tungsten Plugs
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
FOX
FOX Field Oxide Field Oxide Field
FieldOxide
Oxide
n-well
Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-15 5mm
Comments:
• A dielectric is deposited over the entire wafer
• One of the purposes of the dielectric is to smooth out the surface
• Tungsten plugs are used to make electrical contact between the transistors and metal1

Metal1
Metal1 Metal1 Metal1

FOX
FOX Field Oxide Field Oxide Field

FieldOxide
Oxide
n-well
Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-16 5mm

Metal1-Metal2 Vias
Tungsten Plugs Oxide/

SOG/
Oxide
FOX

FieldOxide
n-well
Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-17 5mm

Metal2
Metal 2
Oxide/
SOG/
Oxide
FOX

FieldOxide
n-well
Epitaxial
Silicon

layer
p-substrate 1mm
BiCMOS-18 5mm

Metal2-Metal3 Vias
Comments:
• The metal2-metal3 vias will be filled with metal3 as opposed to tungsten plugs
Completed Wafer

Silicon-Germanium
Physical Perspective (130nm):
Electrical:
Max. voltage = 2V
 ≈ 300
fT ≈ 100 GHz

SUMMARY
• UDSM technology typically has a minimum channel length less than 0.1µm
• UDSM transistors utilize enhanced channel strains to increase drive capability and
reduce off currents
• Advantages of UDSM technology include:
- Smaller devices
- Higher speeds and transconductances
- Improved Ion/Ioff
• Disadvantages of UDSM technology include:
- Gate leakage currents
- Reduced small signal gains
- Increased nonlinearity
• BiCMOS technology
- Offers both CMOS transistors and a high performance vertical BJT
- CMOS is typically a generation behind
- Silicon germanium can be used to enhance the BJT performance

Lecture 05 – PN Junction and CMOS Transistors (8/5/14) Page 05-1
LECTURE 05 - PN JUNCTIONS AND CMOS TRANSISTORS

Outline
• pn junctions
• MOS transistors
• Layout of MOS transistors
• Parasitic bipolar transistors in CMOS technology
• High voltage CMOS transistors
• Summary
Pages 33-46 and 644-652

PN JUNCTIONS
How are PN Junctions used in CMOS?
• PN junctions are used to electrically isolate one semiconductor region from another
• PN diodes
• ESD protection
• Creation of the thermal voltage for bandgap purposes
• Depletion capacitors – voltage variable capacitors (varactors)
Components of a pn junction:
1.) p-doped semiconductor – a semiconductor having atoms containing a lack of
electrons (acceptors). The concentration of acceptors is NA in atoms per cubic
centimeter.
2.) n-doped semiconductor – a semiconductor having atoms containing an excess of
electrons (donors). The concentration of these atoms is ND in atoms per cubic
centimeter.

Abrupt PN Junction
Metal-semiconductor junction pn junction Metal-semiconductor junction
p+ semiconductor n semiconductor
Depletion Region
W 060121-02
p+ semiconductor n semiconductor
W1 0 x
W2
W1 = Depletion width on p side W2 = Depletion width on n side
1. Doped atoms near the metallurgical junction lose their free carriers by diffusion.
2. As these fixed atoms lose their free carriers, they build up an electric field, which
opposes the diffusion mechanism.
3. Equilibrium conditions are reached when:
Current due to diffusion = Current due to electric field

Influence of Doping Level on the Depletion Regions

Intuitively, one can see that the depletion regions are inversely proportional to the doping
level. To achieve equilibrium, equal and opposite fixed charge on both sides of the
junction are required. Therefore, the larger the doping the smaller the depletion region
on that side of the junction.
NA = 1015 ND = 1017
The equations that result are: 9.1nm
2(o -vD) 1
W1 =  910nm
 NA  NA
qNA1 + N 
 D
NA = 1019 ND = 1017
and
2(o -vD) 1 91nm
ND 
W2 = 0.91nm
 ND
qND1 +  p-side n-side
 N A 140310-01
Assume that vD = 0, o = 0.637V and ND = 1017 atoms/cm3. Find the p-side depletion
region width if NA = 1015 atoms/cm3 and if NA = 1019 atoms/cm3:
For NA = 1015 atoms/cm3 the p-side depletion width is 0.90 µm.
For NA = 1019 atoms/cm3 the p-side depletion width is 0.9 nm.
Graphical Characterization of the Abrupt PN Junction

Assume the pn junction is open-circuited. Impurity Concentration (cm -3)
ND
Cross-section of an ideal pn junction: x
xd 0
xp
xn NA
Impurity Concentration (cm -3)
qND
p+ semiconductor n semiconductor -W1
x
iD
0 W2
+ vD - -qNA
060121-03
Symbol for the pn junction: Electric Field (V/cm)

iD
Built-in potential, o: x
NAND +v -
o = Vt ln 2  , D E0
 ni  iD
Potential (V)
where
+v -
kT D Fig. 06-03 yo
Vt = q x
xd
ni is the intrinsic concentration of silicon. 060121-04

Reverse-Biased PN Junctions
Depletion region: xd
xd = xp + xn = W1 + W2 Influence
vD of vR on
xp = W1  vR depletion
iD region width
and - vR = 0V +
vR xd
xn = W2  vR
060121-05
- vR > 0V +
Breakdown voltage (BV):
In the reverse direction the current iD
can be written as,
-IR BV
iD = vD
 vR n Reverse Forward
1 - BV
  Bias Bias
060121-06

Breakdown Voltage as a Function of Doping

It can be shown that†:
si(NA + ND) 2
BV ≈ Emax
2qNAND
where Emax = 3x105 V/cm for silicon.
An example:
Assume that ND = 1017 atoms/cm3.
Find BV if NA = 1015 atoms/cm3 and if NA = 1019 atoms/cm3:
NA = 1015 atoms/cm3:
si2 1.04x10-12·9x1010
If NA << ND, then BV ≈ E = = 291V
2qNA max 2·1.6x10-19·1015
NA = 1019 atoms/cm3:
si2 1.04x10-12·9x1010
If NA >> ND, then BV ≈ E = = 2.91V
2qND max 2·1.6x10-19·1017
†
P. Allen and D. Holberg, CMOS Analog Circuit Design, 3rd ed., Oxford University Press, 2012
Depletion Capacitance
Physical viewpoint of the depletion capacitance:
d
xd
- +
- +
- +
- +
- +
- +
W1 W2 060204-01 + vD -
siA siA
Cj = d = W +W
1 2
siA Cj
=
2si(o-vD)  ND NA  Ideal
 
q(ND+NA)  NA + ND  Cj0 Gummel-
siqNAND 1 Poon Effect
=A 2(NA+ND) o-vD Reverse Bias
Cj0
=
v
yo D
vD 0
1-
o 060204-02

Forward-Biased PN Junctions
When the pn junction is forward-biased, the potential barrier is reduced and significant
current begins to flow across the junction. This current is given by:
 vD  Dppno Dnnpo qAD ni2 -VGO
iD = Isexp V  - 1 where Is = qA L + L  ≈ L N = KT exp V  3
  t   p n   t 
Graphically, the iD versus vD characteristics are given as:
ln(iD/Is)
Decade current
change/60mV
or
Octave current
change/18mV
vD
0V 060204-03

Graded PN Junctions
In practice, the pn junction is graded rather than abrupt.
Impurity
Concentration Impurity profile
approximates a
p+
constant slope
n+ p+
Intrinsic
x Concentration
x
0
Surface Junction
060204-04
The previous expressions become:

Depletion region widths- Depletion capacitance-
2si(o-vD)NDm   siqNAND m 1
W1 =  qN (N +N )   C j = A  
 A A D   1 m
2(NA+ND) o-vDm
2si(o-vD)NAm
 W  N
 
W2 =  qN (N +N )  
Cj0
D A D  

=
 v D m
1 - 
 o
where 0.33 m  0.5.

Metal-Semiconductor Junctions
Ohmic Junctions: A metal-semiconductor junction formed by a highly doped
semiconductor and metal.
Energy band diagram IV Characteristics
I
Vacuum Level 1
qfm Tunneling
Contact
qfs
qfB EC Resistance
EF V
EV
n-type metal Highly doped n-type 140809-02
semiconductor
Schottky Junctions: A metal-semiconductor junction formed by a lightly doped

semiconductor and metal.
Energy band diagram IV Characteristics
Current flow by thermionic emission
I
qfB EC (Forward Bias)

EF EC (Thermal Equilibrium)
EC (Reverse Bias)
EV (Forward Bias) V
EV (Thermal Equilibrium)
EV (Reverse Bias) 140809-01
CMOS Analog Circuit Design n-type metal Low Doped n-type semiconductor © P.E. Allen - 2016
MOS TRANSISTORS
Physical Structure of MOS Transistors in an n-well Technology
Substrate Salicide Substrate Salicide
Well Salicide
W W
n+ p+ p+ nn++ nnn+++
L L
Shallow Shallow
Trench Trench
Isolation n-well Isolation
p-well
Substrate 070322-02
Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal
Width (W) of the MOSFET = Width of the source/drain diffusion

Length (L) of the MOSFET = Width of the polysilicon gate between the S/D diffusions
Note that the MOSFET is isolated from the well/substrate by reverse biasing the
resulting pn junction

Enhancement MOSFETs
The channel of an enhancement MOSFET is formed when the proper potential is applied
to the gate of the MOSFET. This potential inverts the material immediately below the
gate to the same type of impurity as the source and drain forming the channel.
VGS=0V 0V<VGS<VT V <V (sat) VGS>VT
VDS<VDS(sat) DS DS VDS<VDS(sat)
S G D S G D S G D
VDS VDS VDS
Cutoff Weak Inversion Strong Inversion

060205-06
VT = Gate-bulk work function (MS) + voltage to change the surface potential (-2F)
+ voltage to offset the channel-bulk depletion charge (-Qb/Cox)
+ voltage to compensate the undesired interface charge (-Qss/Cox)
Qb0 Qss Qb - Qb0
VT = MS -2F - C - C - C = VT0 +   |-2F + vSB| - |-2F|
ox ox ox
where Qb0 Qss 2qsiNA
VT0 = MS - 2F - C - C ,  = and Qb ≈ 2qNAsi(|-2F+vSB|)
ox ox Cox
Depletion Mode MOSFET

The channel is diffused into the substrate so that a channel exists between the source and
drain with no external gate potential.
The threshold voltage for a depletion mode NMOS transistor will be negative (a negative
gate potential is necessary to attract enough holes underneath the gate to cause this
region to invert to p-type material).

Weak Inversion Operation

0V<VGS<VT VDS<VDS(sat)
Weak inversion operation occurs when the applied
gate voltage is below VT and occurs when the surface S G D
VDS
of the substrate beneath the gate is weakly inverted.
Regions of operation according to the surface Diffusion

potential, S. Current
Weak Inversion
S < F : Substrate not inverted 060205-07
F < S < 2F : Channel is weakly inverted (diffusion current)

2F < S : Strong inversion (drift current)
Drift current versus
log iD
diffusion current
Diffusion Current
in a MOSFET: Drift Current
10-6
10-12 VGS
0 VT

LAYOUT OF MOS TRANSISTORS

Layout of a Single MOS transistor:
L STI L
Well/Bulk Well/Bulk
Drain Drain
W W
n-well p-well
Gate Source Gate Source

060223-01
Comments:
• Make sure to contact the source and drain with multiple contacts to evenly distribute
the current flow under the gate.
• Minimize the area of the source and drain to reduce bulk-source/drain capacitance.

Diffusion and Etch Effects

• Poly etch rate variation – use dummy elements to prevent etch rate differences.
Dummy Dummy
Gate Gate
041027-03
• Do not put contacts on top of the gate for matched transistors.

• Be careful of diffusion interactions for diffusions near the channel of the MOSFET

Thermal and Stress Effects

• Oxide gradients – use common centroid geometry layout
• Stress gradients – use proper location and common centroid geometry layout
• Thermal gradients – keep transistors well away from power devices and use common
centroid geometry layout with interdigitated transistors
Examples of Common Centroid Interdigitated transistor layout:
DA SA/SB DB
DA SA/SB DB SA/SB DA
A B
Dummy Gate
Dummy Gate
Dummy Gate
Dummy Gate
A B B A GA GB
GB GA
B A
GA GB GB GA
Interdigitated, common centroid layout
DB SB/SA DA
041027-04
Cross-Coupled Transistors

MOS Transistor Layout

Photolithographic invariance (PLI) are transistors that exhibit identical orientation. PLI
comes from optical interactions between the UV light and the masks.
Source/Drain Implant
Simple illustration of PLI:
Photo- Photo-
resist resist
140810-01
Examples of the layout of matched MOS transistors:

1.) Examples of mirror symmetry and photolithographic invariance.
Mirror Symmetry Photolithographic Invariance

CMOS Analog Circuit Design 120328-02 © P.E. Allen - 2016
MOS Transistor Layout - Continued

2.) Two transistors sharing a common source and laid out to achieve both
photolithographic invariance and common centroid.
Metal 2 Metal 1
Via 1
120328-03

MOS Transistor Layout - Continued

3.) Compact layout of the previous example.
Metal 2
Via 1
Metal 1
120328-04

PARASITIC BIPOLAR TRANSISTORS IN CMOS TECHNOLOGY

A Lateral Bipolar Transistor VC B LC E LC
n-well CMOS technology: n+ p+ p+ p+
• It is desirable to have the lateral
STI STI
collector current much larger than the
vertical collector current. n-well
• Lateral BJT generally has good Substrate

060221-01
matching.
• The lateral BJT can be used as a Vertical STI Lateral Collector
Collector
photodetector with reasonably good
efficiency. Emitter
• Triple well technology allows the
current of the vertical collector to
avoid the substrate.
Base

A Field-Aided Lateral BJT

Use minimum channel length to VC B LC E LC
enhance beta:
ßF  50 to 100 depending on the n+ p+ p+ pp++
Keeps carriers from
process STI flowing at the surface STI
and reduces 1/f noise
n-well
Substrate
060221-02
Vertical STI Lateral Collector Emitter

Collector
Base

HIGH VOLTAGE CMOS TRANSISTORS

Extended Voltage MOSFETS
The electric field from the source to drain in the channel is shown below.
Electric
Field
Emax
Area = Vp Area = Vd
0
Distance, x
Pinch-off region xp xd
Channel
Source n+ Drain n+
Source Drain
depletion depletion
region region
Substrate depletion region
p - substrate
040920-01
The voltage drop from drain to source is,

VDS = Vp + Vd = 0.5(Emaxxp + Emaxxd) = 0.5Emax(xp + xd)
Emax and xp are limited by hot carrier generation and channel length modulation
requirements whereas these limitations do not exist for xd.
Therefore, to get extended voltage transistors, make xd larger.

High Voltage Architectures

The objective is to create a lightly doped, extended drain region where the high voltage
of the drain can drop down to a level that will not cause the gate oxide to breakdown.
LOCOS Architecture:
DSM Architecture:

Lateral DMOS (LDMOS) Using LOCOS CMOS Technology

The LDMOS structure is designed to provide sufficient lateral dimension and to prevent
oxide breakdown by the higher drain voltages.
One possible implementation using LOCOS technology:
• Structure is symmetrical about the source/bulk contact

• Channel is formed in the p region under the gates
• The lightly doped n region between the drain side of the channel and the n+ drain
contact (xd) increases the depletion region width on the drain side of the channel/drain
pn junction resulting in larger values of vDS.
• Drain voltage can be 20-100V depending on the spacing and doping.
Lateral DMOS (LDMOS) Using DSM CMOS Technology

Cross-section of an
NLDMOS using DSM
technology:
Differences between an NLDMOS and NMOS:

VS = 0V VG > VT VD > 0
• Asymmetry
Poly
• Non-uniform channel
STI STI
• Current flow (not all at the surface) Depletion
• No self-alignment (larger drain-gate overlap region
capacitance)
• Note the extended drift region on the drain side of the
channel 120624-03

SUMMARY
• pn junction usage in CMOS include:
- Electrical isolation, pn diodes, ESD protection, depletion capacitors
• Depletion region widths are inversely proportional to the doping
• Depletion region widths are proportional to the reverse bias voltage
• Ohmic metal-semiconductor junctions require a highly doped semiconductor
• MOSFETs can be:
- Enhancement – the applied gate voltage forms the channel
- Depletion – the channel is physically constructed in fabrication
• The threshold voltage of MOSFETs consists of the following components:
- Gate bulk work function (MS)
- Voltage to change the surface potential (-2F)
- Voltage to offset the channel-bulk depletion charge (-Qb/Cox)
- Voltage to compensate the undesired interface charge (-Qss/Cox)
• Weak inversion is MOSFET operation with the gate-source voltage less than the
threshold voltage
• Layout of the MOSFET is important to its performance and matching capabilities
• Extended drain regions lead to higher voltage capability MOSFETs
Lecture 06 – Capacitors (8/18/14) Page 06-1
LECTURE 06 - CAPACITORS
Outline
• Introduction
• pn junction capacitors
• MOSFET gate capacitors
• Conductor-insulator-conductor capacitors
• Deviation from ideal behavior in capacitors
• Summary
Pages 46-52 and 654-657

INTRODUCTION
Types of Capacitors for CMOS Technology
1.) PN junction (depletion) d
xd
capacitors - +
- +
- +
- +
- +
- +
W1 W2 060204-01 + vD -
G D,S,B
2.) MOSFET gate capacitors Cox
n+ n+ p+
Cjunction p-well
060207-01
3.) Conductor-insulator-conductor Top Conductor

Bottom
capacitors Dielectric Conductor
Insulating layer
060206-02

Characterization of Capacitors
What characterizes a capacitor?
1.) Losses in a capacitor characterized by the quality factor of a capacitor is a measure of
the imaginary to real part of the impedance or admittance
1
Q= = CRp
CRs
where Rp is the equivalent resistance in parallel with the capacitor, C, and Rs is the
electrical series resistance (ESR) of the capacitor, C.
2.) Parasitic capacitors to ground from each node of the capacitor.
3.) The density of the capacitor in Farads/area.
4.) The absolute and relative accuracies of the capacitor.
5.) The Cmax/Cmin ratio which is the largest value of capacitance to the smallest when
the capacitor is used as a variable capacitor (varactor).
6.) The variation of a variable capacitance with the control voltage.
7.) Linearity, q = Cv.

PN JUNCTION CAPACITORS
PN Junction Capacitors in a Well
Generally made by diffusion into the well.
Anode Cathode
Substrate
rD
Cj Cj Cw C VB
VA
n+ p+ n+ p+ Anode Rwj Cathode
Rwj Rwj Rw Rs
Depletion
n-well Region
p- substrate
Fig. 2.5-011
Layout:
Minimize the distance between the p+ and n+ diffusions. n+ diffusion
Two different versions have been tested. p+ dif-

1.) Large islands – 9µm on a side fusion
n-well
2.) Small islands – 1.2µm on a side
Fig. 2.5-1A
PN-Junction Capacitors – Continued

The anode should be the floating node and the cathode must be connected to ac ground.
Experimental data (Q at 2GHz, 0.5µm CMOS)†:
Cmax Cmin Qmin Qmax
4 120
3.5
100
Small Islands
CAnode (pF)
3 C
Large Islands Anode Cathode
2.5 80
QAnode
Small Islands R-X Cathode
2 60 Bridge Voltage
C
1.5 Anode Cathode
40
Large Islands
1 R-X Cathode
Bridge Voltage 20
0.5
0 0
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5
Cathode Voltage (V) Cathode Voltage (V) 060206-03
Terminal Small Islands (598 1.2µm x1.2µm) Large Islands (42 9µm x 9µm)
Under Test Cmax/Cmin Qmin Qmax Cmax/Cmin Qmin Qmax
Anode 1.23 94.5 109 1.32 19 22.6
Cathode 1.21 8.4 9.2 1.29 8.6 9.5
Electrons as majority carriers lead to higher Q because of their higher mobility.
The resistance, Rwj, is reduced in small islands compared with large islands  higher Q
†E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
MOSFET GATE CAPACITORS

MOSFET Gate Capacitor Structure
The MOSFET gate capacitors have the gate as one terminal of the capacitor and some
combination of the source, drain, and bulk as the other terminal.
In the model of the MOSFET gate capacitor shown below, the gate capacitance is really
two capacitors in series depending on the condition of the channel.
1
Cgate =
1 1
+
Cox Cj
S G D B G Channel Resistance
Cox
Cox S D
n+ n+ p+
Cjunction p-well Cjunction

060207-02 B Bulk Resistance

MOSFET Gate Capacitor as a function of VGS with D=S=B

G D,S,B Capacitance
Cox Cox Cox
n+ n+ Weak
p+
Accumulation Inv. Strong
Cjunction p-well Inversion
Depletion Moderate VG-VD,S,B

Operation: Inversion 060207-03
In this configuration, the MOSFET gate capacitor has 5 regions of operation as VGS is
varied. They are:
1.) Accumulation
2.) Depletion
3.) Weak inversion
4.) Moderate inversion
5.) Strong inversion
For the first four regions, the gate capacitance is the series 1
combination of Cox and Cj given as, C gate =
1 1
+
Cox Cj

Use of a 3 Segment Model to Explain the Gate Capacitor Variation

Region Channel R Cox and Cj Cgate 3-Segment Model
Accumulation Large In series and Cgate ≈ Cox

Cj > Cox
Depletion In series and Cgate ≈ 0.5Cox

Large
Cj ≈ Cox ≈ 0.5Cj
Weak Large In series and Cgate ≈ Cj

Inversion Cj < Cox
Moderate Moderate In series and Cj < Cgate <

Inversion Cj < Cox Cox
Strong Small In parallel and Cgate ≈ Cox

Inversion Cj < Cox

MOSFET Gate Capacitor as a function of VGS with Bulk Fixed (Inversion Mode)
G D,S B Capacitance
Cox Cox B=D= S Cox
n+ n+ p+ Inversion VT shift
Mode MOS if VBS ≠ 0
Cjunction p-well
0 VG-VD,S
060207-04
Conditions:
• D = S, B = VSS
• Accumulation region removed by connecting bulk to ground
• Nonlinear
• Channel resistance:
L
Ron = 12K '(V -|V |)
P BG T
• LDD transistors will give lower Q because of the increased series resistance

Inversion Mode NMOS Capacitor

Best results are obtained G D,S
when the drain-source are Shown in inversion mode
D,S
connected to ac ground. Bulk R C
Cov Cox Cov
sj j B
p+ n+ n+
Rd Cd Csi Cd Rd G
p- substrate/bulk Rsi n- LDD
Fig. 2.5-2
Experimental Results (Q at 2GHz, 0.5µm CMOS)†:
Cmax Cmin Qmax Qmin
4.5 38
VG = 2.1V RX 36 VG = 2.1V
RX
4 Meter Meter
VG VD,S 34 VG VD,S
3.5
CGate (pF)
32
VG = 1.8V
QGate
3 30
VG = 1.8V
28
2.5 VG = 1.5V
VG = 1.5V 26
2
24
1.5 22
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5
Drain/Source Voltage (V) Drain/Source Voltage (V) 070617-06
VG =1.8V: Cmax/Cmin ratio = 2.15 (1.91), Qmax = 34.3 (5.4), and Qmin = 25.8(4.9)
†E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
Accumulation Mode NMOS Gate Capacitor

G B Capacitance
Cox Cox
n+ Depletion
n+
Inversion Accumulation
VG-VD,S,B
060207-05
Conditions:
• Build the NMOS in a n-well or the PMOS in a p-well – channel is present with no bias
• Implements a variable capacitor with a larger transition region between the maximum
and minimum values.
• Reasonably linear capacitor for values of VG-VD,S,B > 0

Accumulation Mode Capacitor – Continued

Best results are Shown in depletion mode. G D,S
obtained when the D,S
drain-source are on Cov Cox Cov
Bulk Cw B
ac ground. p+ + n n+
Rs Rw Rd Rd G
Cd Cd
n- well
n- LDD
p- substrate/bulk Fig. 2.5-5
Experimental Results (Q at 2GHz, 0.5µm CMOS)†:

Cmax Cmin Qmax Qmin
4 45
RX
RX VG = 0.3V Meter
Meter VG
3.6 VD,S
VG = 0.9V VG VD,S 40
VG = 0.6V
CGate (pF)
3.2
QGate
VG = 0.6V
35
VG = 0.9V
2.8
2.4 VG = 0.3V 30
2 25
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5
Drain/Source Voltage (V) Drain/Source Voltage (V) 070617-07
VG = 0.6V: Cmax/Cmin ratio = 1.69 (1.61), Qmax = 38.3 (15.0), and Qmin = 33.2(13.6)
†
E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
CONDUCTOR-INSULATOR-CONDUCTOR CAPACITORS
Polysilicon-Oxide-Polysilicon (Poly-Poly) Capacitors
LOCOS Technology:
A very linear capacitor
with minimum bottom
plate parasitic.
DSM Technology:
A very linear capacitor with
small bottom plate parasitic.

Metal-Insulator-Metal (MiM) Capacitors

In some processes, there is a thin dielectric between a metal layer and a special metal
layer called “capacitor top metal”. Typically the capacitance is around 1fF/µm2 and is at
the level below top metal.
Metal Via
Top
Vias connecting top Metal
Capacitor plate to top metal
dielectric Capacitor Top Metal Second level
Inter-
Vias connecting bottom from top metal
mediate
Capacitor bottom plate plate to lower metal Third level
Oxide
Layers Vias connecting bottom from top metal
plate to lower metal Fourth level
from top metal
060530-01
Good matching is possible with low parasitics.

Metal-Insulator-Metal Capacitors – Lateral and Vertical Flux

Capacitance between conductors on the same level and use lateral flux.
Fringing field
Top view:
Metal Metal
Metal 3 + - + - Side view:
Metal 2 - + - +
Metal 1 + - + - Fig2.5-9
These capacitors are sometimes called fractal capacitors because the fractal patterns are
structures that enclose a finite area with a near-infinite perimeter.
The capacitor/area can be increased by a factor of 10 over vertical flux capacitors.
More Detail on Horizontal Metal Capacitors†

Some of the possible metal capacitor structures include:
1.) Horizontal parallel plate (HPP).
030909-01
2.) Parallel wires (PW):
Lateral View 030909-02

Top View
†R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors, IEEE J. of Solid-State Circuits, vol. 37, no. 3,
March 2002, pp. 384-393.
Horizontal Metal Capacitors - Continued

3.) Vertical parallel plates (VPP):
Vias
030909-03
4.) Vertical bars (VB):
Vias
030909-04
Lateral View Top View

Horizontal Metal Capacitors - Continued

Experimental results for a digital CMOS process with 7 layers of metal, Lmin =0.24µm,
tox = 0.7µm and tmetal = 0.53µm for the bottom 5 layers of metal. All capacitors = 1pF.
Structure Cap. Caver. Area Cap. Std.  fres. Q @ Break-
Density 2
(1 pF) (pF) (µm ) Enhanc Dev. Caver. (GHz) 1 GHz down
(aF/µm2) ement (fF) (V)
VPP 1512.2 1.01 670 7.4 5.06 0.0050 > 40 83.2 128
VB 1281.3 1.07 839.7 6.3 14.19 0.0132 37.1 48.7 124
HPP 203.6 1.09 5378 1.0 26.11 0.0239 21 63.8 500
MIM 1100 1.05 960.9 5.4 - - 11 95 -
Histogram of the capacitance distribution:
Result: The horizontal metal capacitors

have a matching accuracy that is
equivalent of the better capacitors – poly-
poly and MIM.

DEVIATION FROM IDEAL BEHAVIOR IN CAPACITORS

Capacitor Errors
1.) Dielectric gradients
2.) Edge effects
3.) Process biases
4.) Parasitics
5.) Voltage dependence
6.) Temperature dependence

Capacitor Errors - Oxide Gradients

Error due to a variation in dielectric thickness across the wafer.
Common centroid layout - only good for one-dimensional errors:
No common centroid layout Common centroid layout
2C C 2C C
060207-07
An alternate approach is to layout numerous repetitions and connect them randomly to

achieve a statistical error balanced over the entire area of interest.
Improved matching of three components, A, B, and C:

Capacitor Errors - Edge Effects

There will always be a randomness on the definition of the edge.
However, etching can be influenced by the presence of adjacent structures.
For example,
Matching of A and B are disturbed by the presence of C.
C
A B
Improved matching achieve by matching the surroundings of A and B.
C
A B

Process Bias on Capacitors

Consider the following two capacitors:
If L1 = L2 = 2µm, W2 = 2W1 = 4µm and

x = 0.1µm, the ratio of C2 to C1 can
be written as,
C2 (2-.2)(4-.2) 3.8
C1 = (2-.2)(2-.2) = 1.8 = 2.11 → 5.6% error in matching
How can this matching error be reduced?
The capacitor ratios in general can be expressed as,
1 - 2x
C2 (L2-2x)(W2-2x) W2 W2  W2 2x 2x W2 2x 2x
C1 = (L1-2x)(W1-2x) = W1 2x  W11 - W2 1 + W1   W11 - W2 + W1 
1 - W 
 1
Therefore, if W2 = W1, the matching error should be minimized. The best matching
results between two components are achieved when their geometries are identical.
Replication Principle
Based on the previous result, a way to minimize the matching error between two or more
geometries is to insure that the matched components have the same area to periphery
ratio. Therefore, the replication principle requires that all geometries have the same
area-periphery ratio.
Correct way to match
the previous capacitors
(the two C2 capacitors
are connected
together):
If L1 = L2 = 2µm, W2 = 2W1 = 2µm and x = 0.1µm, the ratio of C2 to C1 can be written

as,
C2 2(2-.2)(2-.2) 2·1.8
= = = 2 → 0% error in matching
C1 (2-.2)(2-.2) 1.8
The replication principle works for any geometry and includes transistors, resistors as
well as capacitors.

Capacitor Errors - Relative Accuracy

Capacitor relative accuracy is proportional to the area of the capacitors and inversely
proportional to the difference in values between the two capacitors.
For example,
0.04
Unit Capacitance = 0.5pF

0.03
Relative Accuracy
Unit Capacitance = 1pF
0.02
0.01
Unit Capacitance = 4pF
0.00
1 2 4 8 16 32 64
Ratio of Capacitors

How to Keep the Relative Accuracy Constant as Ratio Increases

The following scheme will tend to keep the relative accuracy constant as a function of
the ratio of capacitors. Of course the tradeoff for this accuracy is area.
1:2 2 2 1 1 2 2
4 4 4 4 1 1 4 4 4 4
1:4
4 4 4 4 1 1 4 4 4 4
4 4 4 4 4 4 4 4 1 1 4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4 1 1 4 4 4 4 4 4 4 4
1:8
4 4 4 4 4 4 4 4 1 1 4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4 1 1 4 4 4 4 4 4 4 4
120625-01

Capacitor Errors - Parasitics

Parasitics are normally from the top and bottom plate to ac ground which is typically the
substrate.
Top Plate
Top
plate Desired
parasitic Capacitor
Bottom
Bottom Plate plate
060702-08
parasitic
Top plate parasitic is 0.01 to 0.001 of Cdesired

Bottom plate parasitic is 0.05 to 0.2 Cdesired

Layout Considerations on Capacitor Accuracy

Decreasing Sensitivity to Edge Variation:
Fringing Fringing
Field Field
? ?
Sensitive to alignment errors in the Insensitive to alignment errors and the
upper and lower plates and loss of flux reaching the bottom plate is lar ger
capacitance flux (smaller capacitance). resulting in large capacitance. 060207-09
A structure that minimizes the ratio of perimeter to area (circle is best).

Bottom Plate
Top
Plate
060207-10 Reduced bottom plate parasitic.

Accurate Matching of Capacitors†

Accurate matching of capacitors depends on the following influence:
1.) Mismatched perimeter ratios
2.) Proximity effects in unit capacitor photolithography
3.) Mismatched long-range fringe capacitance
4.) Mismatched interconnect capacitance
5.) Parasitic interconnect capacitance
Long-range fringe capacitance:
Obviously there will be a tradeoff between matching and speed.
†M.J. McNutt, S. LeMarquis and J.L.Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE J. of Solid-State
Circuit, vo. 29, No. 5, May 1994, pp. 611-616.
Shielding
The key to shielding is to determine and control the electric fields.
Consider the following noisy conductor and its influence on the substrate:
Increased Parasitic Capacitance
Noisy Conductor Noisy Conductor Separate
Ground
Shield
Substrate Substrate
060118-10
Use of bootstrapping to reduce capacitor bottom plate parasitic:

Top Plate
2Cpar +1
Bottom Plate
Cpar
2Cpar Shield
Substrate Substrate
060316-02

Definition of Temperature and Voltage Coefficients

In general a variable y which is a function of x, y = f(x), can be expressed as a Taylor
series,
y(x)  y(x0) + a1(x- x0) + a2(x- x0)2+ a3(x- x0)3 + ···
where the coefficients, ai, are defined as,
df(x) | 1 d2f(x) |
a1 = dx x=x , a2 = 2 , ….
0 dx2 x=x0
The coefficients, ai, are called the first-order, second-order, …. temperature or voltage
coefficients depending on whether x is temperature or voltage.
Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a term
called fractional temperature coefficient, TCF, which is defined as,
1 df(T) |
TCF(T=T0) = f(T=T ) dT T=T parts per million/°C (ppm/°C)
0 0
or more simply,
1 df(T)
TCF = f(T) dT parts per million/°C (ppm/°C)
A similar definition holds for fractional voltage coefficient.
Capacitor Errors - Temperature and Voltage Dependence

MOSFET Gate Capacitors:
Absolute accuracy  ±10%
Relative accuracy  ±0.2%
Temperature coefficient  +25 ppm/C°
Voltage coefficient  -50ppm/V
Polysilicon-Oxide-Polysilicon Capacitors:
B Silicide A
Temperature coefficient  +25 ppm/C° Silicide
Thin depletion regions
Effective dielectric
Voltage coefficient  -20ppm/V thickness
Metal-Dielectric-Metal Capacitors: Shallow Trench Isolation

140310-03

Temperature coefficient  +40 ppm/C°
Voltage coefficient  -20ppm/V, 5ppm/V2
Accuracies depend upon the size of the capacitors.
SUMMARY
• Capacitors are made from:
- pn junctions (depletion capacitors)
- MOSFET gate capacitors
- Conductor-insulator-conductor capacitors
• Capacitors are characterized by:
- Q, a measure of the loss
- Density
- Parasitics
- Absolute and relative accuracies
• Deviations from ideal capacitor behavior include;
- Dielectric gradients
- Edge effects (etching)
- Process biases
- Parasitics
- Voltage and temperature dependence

Lecture 07 – Resistors and Inductors (3/10/14) Page 07-1
LECTURE 07 – RESISTORS AND INDUCTORS

Outline
• Resistors
• Inductors
• Summary
Pages 50-52, 652-654 and new material

RESISTORS
Types of Resistors Compatible with CMOS Technology
1.) Diffused and/or implanted resistors.
2.) Well resistors.
3.) Polysilicon resistors.
4.) Metal resistors.

Characterization of Resistors
1.) Value Area = A
Area = A
L nt L
R= A Curre L
Current 050217-02
AC and DC resistance
i
2.) Linearity Linear Resistor
Does V = IR?
Velocity saturation
Velocity saturation of carriers
v
Breakdown
3.) Power Voltage 060211-01
P = VI = I2R
4.) Current
Electromigration Metal 050304-04
5.) Parasitics
R R
R
Cp Cp
060210-01
Cp 2 2

MOS Resistors - Source/Drain Resistor

Metal First Level Metal
SiO2 p+
Tungsten Intermediate Tungsten
Plug Oxide Layer Plug
FOX FOX p+ p+
n- well L
STI STI
n-well
p- substrate
060214-02 Older LOCOS Technology

Diffusion: Ion Implanted:
10-100 ohms/square 500-2000 ohms/square
Absolute accuracy = ±35% Absolute accuracy = ±15%
Relative accuracy=2% (5µm), 0.2% (50µm) Relative accuracy=2% (5µm), 0.15% (50µm)
Temperature coefficient = +1500 ppm/°C Temperature coefficient = +400 ppm/°C
Voltage coefficient  200 ppm/V Voltage coefficient  800 ppm/V
Comments:
• Parasitic capacitance to substrate is voltage dependent.
• Piezoresistance effects occur due to chip strain from mounting.

Polysilicon Resistor
100-500 ohms/square (shielded)

Absolute accuracy = ±3 0%
Relative accuracy = 2% (5 µm)
Temperature coefficient = 500-1000 ppm/°C
Voltage coefficient  100 ppm/V
Comments:
• Used for fuzzes and laser trimming
• Good general resistor with low parasitics

N-well Resistor
Metal n+ First Level Metal
Tungsten Intermediate Tungsten
Plug Oxide Layer Plug
FOX FOX FOX n+ n+
n- well L
L STI STI
n-well
p- substrate
060214-04 LOCOS Technology p-substrate
1000-5000 ohms/square
Absolute accuracy = ±40%
Relative accuracy  5%
Temperature coefficient = 4000 ppm/°C
Voltage coefficient is large  8000 ppm/V
Comments:
• Good when large values of resistance are needed.
• Parasitics are large and resistance is voltage dependent
• Could put a p+ diffusion into the well to form a pinched resistor

Metal as a Resistor
Illustration: L1 L5 Second
A B
Inter- Level
mediate Metal
L2 Tungsten Plug Tungsten Plug L4 First
Oxide
Layers Level
L3 Metal
Salicide
Substrate
060214-05
Resistance from A to B = Resistance of segments L1, L2, L3, L4, and L5 with some
correction subtracted because of corners.
Sheet resistance:
50-70 m/ ± 30% for lower or middle levels of metal
30-40 m/ ± 15% for top level metal
Tj(°C) Tr(°C) Dt
Watch out for the current limit for metal resistors.
<85 85 1
Contact resistance varies from 5 to 10.
100 85 0.63
Tempco ≈ +4000 ppm/°C 110 85 0.48
Need to derate the current at higher temperatures: 125 85 0.32
IDC(Tj) = Dt·IDC(Tr) 150 85 0.18
Thin Film Resistors

A high-quality resistor fabricated from a thin nickel-chromium alloy or a silicon-
chromium mixture.
Uppermost metal layer:
Inter- Thin Film Resistor Top
mediate Metal
Oxide L Second
Layers
level
from
top metal
060612-01
Performance:
Sheet resistivity is approximately 5-10 ohms/square
Temperature coefficients of less than 100 ppm/°C
Absolute tolerance of better than ±0.1% using laser trimming
Selectivity of the metal etch must be sufficient to ensure the integrity of the thin-
film resistor beneath the areas where metal is etched away.
Resistor Layout Techniques

Metal Metal
LOCOS FOX FOX FOX FOX FOX

Technology
Substrate Substrate
Active area (diffusion) Active area (diffusion) Well diffusion
Metal Metal
DSM Tungsten Tungsten Plug

Technology Plug Intermediate Oxide Intermediate Oxide
Substrate Substrate
Active area (diffusion) Substrate Well diffusion Active area (diffusion)
Contact Active area or Polysilicon W Active area W

Well diffusion
Contact
Cut
Cut
L
Metal 1
Metal 1
L
Diffusion or polysilicon resistor Well resistor 060219-01
End structure calculations:

Rcont Xc-r + 0.75·Lcon
R 1 = N + Rsh(sil)  
cont  W - 2·  W sil 
(Lcon = width of the contact)
Rcont Xc-r + Xcon +1.75·Lcon
R 2 = N + Rsh(sil)  
cont  W - 2·  W sil 
 1 1 -1
Rtotal =  + + ···

 1R  R 2 
Extending the Length of Resistors

Snaked Resistors:
L3
L1
L2 L4 L4 L4 L4 L4 L2
060220-01
These resistors typically have model problems because of non-uniform current flow at
the corners.
Corner corrections:
0.5
1.45 1.25
Fig. 2.6-16B

Extending the Length of Resistors

Link Resistors:
L1 W
060220-02
For good matching between link resistors, keep the link length, L1, identical.
Resistor Ending Influence:
0.5 0.3 0.1
050416-02
Avoid “dogbone” resistors to minimize model errors.

Process Bias Influence on Resistors

Process bias is where the dimensions of the fabricated geometries are not the same as the
layout data base dimensions.
Process biases introduce systematic errors.
Consider the effect of over-etching-
Assume that etching introduces a process bias of 0.1µm. Two resistors designed to
have a ratio of 2:1 have equal lengths but the widths are different by a factor of two.
3.8mm 4mm
1.8mm 2mm
10mm 041020-01
The actual matching ratio due to the etching bias is,
R2 W1 4-0.2 3.8
R1 = W2 = 2-0.2 = 1.8 = 2.11 → 5.6% error in matching
Use the replication principle to eliminate this error.
Etch Rate Variations – Polysilicon Resistors

The size of the area to be etched determines the etch rate. Smaller areas allow less
access to the etchant while larger areas allow more access to the etchant. This is
illustrated below:
Slower Slower Slower
Etch Rate Etch Rate Etch Rate
Dummy
Dummy
A B C A B C
041025-04
The objective is to make A = B = C. In the left-hand case, B is larger due to the slower
etch rates on both sides of B. In the right-hand case, the dummy strips have caused the
etch rates on both sides of A, B and C to be identical leading to better matching.
It may be advisable to connect the dummy strips to ground or some other low impedance
node to avoid static electrical charge buildup.

Diffusion Interaction – Diffused Resistors

Problem:
Consider three adjacent p+ diffusions into a n epitaxial region,
Areas of diffusion interaction Contours of
constant doping
A B C
p+ p+ p+
n-epi
140917-03
If A, B, and C are resistors that are to be matched, we see that the effective concentration
of B is larger than A or C because of diffusion interaction. This would cause the B
resistor to be smaller even though the geometry is identical.
Solution: Place identical dummy resistors to the left of A and right of C. Connect the
dummy resistors to a low impedance to prevent the formation of floating diffusions that
might increase the sensitivity to latchup.

Thermoelectric Effects
The thermoelectric effect, also called the Seebeck effect, is a potential difference that is
developed between two dissimilar materials that are at different temperatures. The
potential developed is given as,
V = S·T
where,
S = Seebeck coefficient ( 0.4mV/°C)
T = temperature difference between the two metals
Thus, a temperature difference between the contacts to a resistor and the resistor of 1°C
can generate a voltage of 0.4mV causing problems in certain circuits (bandgap).
+ + + + + + + +
Cold
Two possible resistor
layouts with regard to
Resistor Segment
Resistor Segment
Resistor Segment
Resistor Segment
Resistor Segment
Resistor Segment
Resistor Segment
Resistor Segment
the thermoelectric
effect:
Hot
- - - - - - - -
Thermoelectric potentials add Thermoelectric potentials cancel 041026-07

High Sheet Resistivity Resistor Layout

High sheet resistivity resistors must use p+ or n+ in order to make contacts to metal.
Thus, there is plenty of opportunity for the thermoelectric effect to cause problems if
care is not taken. Below are three high sheet resistor layouts with differing
thermoelectric performance.
n+ resistor Vertical misalignment
head Cold causes resistor errors
n diffused
resistor
Resistor layout that

n+ resistor minimizes thermoelectric
head Hot
effect and misalignment
041027-01
Sensitive to Sensitive to
thermoelectric misalignment.
effects.

MOS Passive RC Component Typical Performance Summary
Component Type Range of Absolute Relative Temperature Voltage

Values Accuracy Accuracy Coefficient Coefficient
MOSFET gate Cap. 6-7 fF/µm2 10% 0.1% 20ppm/°C ±20ppm/V
Poly-Poly Capacitor 0.3-0.4 fF/µm2 20% 0.1% 25ppm/°C ±50ppm/V
Metal-Metal Capacitor 0.1-1fF/µm2 10% 0.6% -40ppm/°C ±1ppm/V
Diffused Resistor 10-100 /sq. 35% 2% 1500ppm/°C 200ppm/V
Ion Implanted Resistor 0.5-2 k/sq. 15% 2% 400ppm/°C 800ppm/V
Poly Resistor 30-200 /sq. 30% 2% 1500ppm/°C 100ppm/V
n-well Resistor 1-10 k/sq. 40% 5% 8000ppm/°C 10kppm/V
Top Metal Resistor 30 m/sq. 15% 2% 4000ppm/°C -
Lower Metal Resistor 70 m/sq. 28% 3% 4000ppm/°C -

INDUCTORS
Characterization of Inductors
1.) Value of the inductor 2r
Spiral inductor†:
L ≈ µ0n2r = 4x10-7n2r ≈ 1.2x10-6n2r
n=3
L
2.) Quality factor, Q = R
060216-02
1
3.) Self-resonant frequency: fself =
LC
4.) Parasitic and inter-winding capacitances
†H.M Greenhouse, “Design of Planar Rectangular Microelectronic Inductors,” IEEE Trans. Parts, Hybrids, and Packaging, vol. 10, no. 2, June
1974, pp. 101-109.
IC Inductors
What is the range of values for on-chip inductors?
Consider an inductor used to resonate with 5pF at 1000MHz.

1 1
L= 2 2 = = 5nH
4 fo C (2·109)2·5x10-12
Note: Off-chip connections (bond-wires) will result in inductance as well.

Candidates for inductors in CMOS technology are:

1.) Bond wires
2.) Spiral inductors
3.) Multi-level spiral
4.) Solenoid
Bond wire Inductors:
• Function of the pad distance d and the bond angle 

• Typical value is 1nH/mm which gives 2nH to 5nH in typical packages
• Series loss is 0.2 /mm for 1 mil diameter aluminum wire
• Q  60 at 2 GHz

Planar Spiral Inductors in CMOS Technology

I
W
I ID I
I
Nturns = 2.5
Typically: 3 < Nturns < 5 and S = Smin for the given current
Select the OD, Nturns, and W so that ID allows sufficient magnetic flux to flow
through the center.
Loss Mechanisms:
• Skin effect
• Capacitive substrate losses
• Eddy currents in the silicon
Planar Spiral Inductors on a Lossy Substrate

Top Metal
Top Metal
W
S Next Level
Metal
Vias Oxide
Next Level Oxide
Metal
D
Silicon Substrate
N turns
030828-01
D
• Spiral inductor is implemented using metal layers in CMOS technology

• Topmost metal is preferred because of its lower resistivity
• More than one metal layer can be connected together to reduce resistance or area
• Accurate analysis of a spiral inductor requires complex electromagnetic simulation
• Optimize the values of W, S, and N to get the desired L, a high Q, and a high self-
resonant frequency
• Typical values are L = 1-8nH and Q = 3-6 at 2GHz
Inductor Modeling
Cp 37.5µ0N2a2 ox
Model: L  11D-14a Cox = W·L· t
ox
L Rs L
Rs  (low freq. resistive loss)
Cox Cox W(1-e-t/)
2 2 WLCsub
R1  (eddy current substrate loss)
2
C1 R1 C1 R1 ox
Cp = 2
NW L· t (overlap and coupling)
ox
030828-02
2
where C1  WLC (substrate capacitance)
sub
µ0 = 4x10-7 H/m (vacuum permeability)
 = conductivity of the metal
a = distance from the center of the inductor to the middle of the windings
L = total length of the spiral
t = thickness of the metal
 = skin depth given by  = 2/Wµ0
Gsub(Csub) is a process-dependent parameter
Reduction of Capacitance to Ground

Comments concerning implementation:
1.) Put a metal ground shield between the inductor and the silicon to reduce the
capacitance.
• Should be patterned so flux goes through but electric field is grounded
• Metal strips should be orthogonal to the spiral to avoid induced loop current
• The resistance of the shield should be low to terminate the electric field
2.) Avoid contact resistance wherever possible to
keep the series resistance low.
3.) Use the metal with the lowest resistance and
farthest away from the substrate.
4.) Parallel metal strips if other metal levels are
available to reduce the resistance.
Example →
Fig. 2.5-12

Inductor Improvements
Symmetrical Layout:
• Good for differential circuits
• Higher Q
• Can achieve a center tap 131001-02
17 µm metal
Q Improvement:
• Substrate replaced with trenched silicon islands†
†
M. Raieszadeh, Integrated Inductors on Trenched Silicon Islands, MS Thesis, School of Electrical and Computer Engineering, Georgia Institute of Technology, April 2005
Multi-Level Spiral Inductors

Use of more than one level of metal to make the inductor.
• Can get more inductance per area
• Can increase the interwire capacitance so the different levels are often offset to get
minimum overlap.
• Multi-level spiral inductors suffer from contact resistance (must have many
parallel contacts to reduce the contact resistance).
• Metal especially designed for inductors is top level approximately 4µm thick.
Q = 5-6, fSR = 30-40GHz. Q = 10-11, fSR = 15-30GHz1. Good for high L in small area.
1The skin effect and substrate loss appear to be the limiting factor at higher frequencies of self-resonance.
Inductors - Continued
Self-resonance as a function of inductance. Outer dimension of inductors.

Transformers
Transformer structures are easily obtained using stacked inductors as shown below for a
1:2 transformer.
Method of reducing the
inter-winding capacitances.
Measured 1:2 transformer voltage gains:

4 turns
8 turns 3 turns

Transformers – Continued
A 1:4 transformer:
Structure- Measured voltage gain-
Secondary
(CL = 0, 50fF, 100fF, 500fF and 1pF.

CL is the capacitive loading on the
secondary.)

Summary of Inductors
Scaling? To reduce the size of the inductor would require increasing the flux density
which is determined by the material the flux flows through. Since this material will not
change much with scaling, the inductor size will remain constant.
Increase in the number of metal layers will offer more flexibility for inductor and
transformer implementation.
Performance:
• Inductors
Limited to nanohenrys
Very low Q (3-5)
• Transformers
Reasonably easy to build and work well using stacked inductors
ASITIC† – A CAD tool that aids the RF circuit designer to optimize and model spiral
inductors, transformers, capacitors, and substrate coupling. ASITIC calculations include
the electrically induced losses and coupling as well as the magnetically induced eddy
current losses. Skin effect and proximity effects, or eddy currents in the metallization,
are also included.
†http://rfic.eecs.berkeley.edu/~niknejad/asitic.html
SUMMARY
• Types of resistors include diffused, well, polysilicon and metal
• Resistors are characterized by:
- Value
- Linearity
- Power
- Parasitics
• Technology effects on resistors includes:
- Process bias
- Diffusion interaction
- Thermoelectric effects
- Piezoresistive effects
• Inductors are made by horizontal metal spirals, typically in top metal
• Inductors are characterized by:
- Value
- Losses
- Self-resonant frequency
- Parasitics
• RF transformers are reasonably easy to build and work well using stacked inductors
Lecture 08 – Latchup and ESD (4/25/16) Page 08-1
LECTURE 08 – LATCHUP AND ESD

Outline
• MOSFET parasitic BJTs
• Latchup
• ESD
• Summary
Pages 53 - 60 and new material

MOSFET PARASITIC BJTS

Parasitic BJTs of a MOSFET
Furthermore, the resistance from the bases of the NPN transistors and collectors of the
PNP transistor greatly influences both latchup and ESD. Thus, both latchup and ESD are
influenced by layout.

LATCHUP
What is Latchup?
• Latchup is the creation of a low impedance path
between the power supply rails.
• Latchup is caused by the triggering of parasitic
bipolar structures within an integrated circuit
when applying a current or voltage stimulus on
an input, output, or I/O pin or by an over-voltage
on the power supply pin.
• Temporary versus true latchup:
A temporary or transient latchup occurs only while the pulse stimulus is connected to
the integrated circuit and returns to normal levels once the stimulus is removed.
A true latchup remains after the stimulus has been removed and requires a power
supply shut down to remove the low impedance path between the power supply rails.

Latchup Testing
The test for latchup defines how the designer must think about latchup.
• For latchup prevention, you must consider where a current limited (≥100mA), 10ms
pulse is going to go when applied to a pad when the voltage compliance of the pad is
constrained to 50% above maximum power supply and to 2V below ground. (Higher
temperatures, 85C°and 125°C, are more demanding, since VBE is lower.)
• VDD is increased by 150% (must be careful for low voltage ICs)
100m
A
1ms
100mA ms VDD
1
1.5VDD
150% OVERVOLTAGE 130620-01

CURRENT INJECTION
• Latchup is sensitive to layout and is most often solved at the physical layout level.

How Does Latchup Occur?

Latchup is the regenerative process that can occur in a pnpn structure (SCR-silicon
controlled rectifier) formed by a parasitic npn and a parasitic pnp transistor.
iPNPN 1/Slope =
Anode Anode V
DD Limiting To avoid latchup
iPNPN Resistance vPNPN < VS
p
n
vPNPN Triggering by
p Hold Current, IH increasing V
DD
n
Hold vPNPN
Cathode Cathode Avalanche Sustaining
Voltage, VH voltage, VS
Breakdown Body diode 050414-01
(CMOS)
Important concepts:
• To avoid latchup, vPNPN ≤ VS
• Once the pnpn structure has latched up, the large current required by the above i-v
characteristics must be provided externally to sustain latchup
• To remove latchup, the current must be reduced below the holding current

Latchup Triggering
Latchup of the SCR can be triggered by two different mechanisms.
1.) Allowing vPNPN to exceed the sustaining voltage, VS.
2.) Injection of current by a triggering device (gate triggered)
Anode Pad VDD
pnp Gate
Gate Current
Injector Injector
npn Gate
Gate Current
SCR SCR
050414-03 Cathode Pad
Note: The gates mentioned above are SCR junction gates, not MOSFET gates.
From the above considerations, latchup requires the following components:
1.) A four-layer structure (SCR) connected between VDD and ground.
2.) An injector.
3.) A stimulus.
Necessary Conditions for Latchup

1.) The loop gain of the relevant BJT configuration must exceed unity.
+fb ii
VDD bn bp io
loop
050414-04
Loop gain:
io
ii ≈ pn
2.) A bias condition must exist such that both bipolars are turned on long enough for
current through the “SCR” to exceed its switching current.
3.) The bias supply and associated circuits must be capable of supplying the current at
least equal to the switching current and at least equal to the holding current to maintain
the latched state.

Latchup Trigger Modes

Current mode (Positive Injection Example):
Pad VDD
When a current is applied to a pad, it can flow
through an injector and trigger latchup of an SCR formed
from parasitic bipolar transistors.
SCR gate current injection parasitic can occur in p- Injector
well or n-well technology. Gate
Current
050414-05
SCR
Voltage mode:
When the power supply is increased VDD
above the nominal value, the SCR formed
from parasitic bipolar transistors can be
triggered. VAnode
SCR VDD < VAnode <Vabs,max

050414-06

How does Latchup Occur in an IC?

Consider an output driver in CMOS technology:
vIN vOUT
VDD
VDD
vIN
vOUT
p+ p p- n- n n+ Oxide Poly 1 Poly 2 Nitride Salicide Metal 050416-02
Assume that the output is connected to a pad.

Parasitic Bipolar Transistors for the n-well CMOS Inverter
vOUT
vIN
VDD
Rw3
LT2
Rs1 LT1 Rw2
Rs2 Rw4 VT2 VT1 Rw1
Rs3 Rs4
Parasitic components:
Lateral BJTs LT1 and LT2
Vertical BJTs VT1 and VT2
Bulk substrate resistances Rs1, Rs2, Rs3, and Rs4
Bulk well resistances Rw1, Rw2, Rw3, and Rw4

Current Source Injection

Apply a voltage compliant current source to the output pad (vOUT > VDD).
Voltage Compliant
vIN vOUT
Current Source VDD
LT2
Rs LT1 VT2 VT1 Rw
Loop gain:
iout  Rw   Rs 
 
= P1 N1R +r 
iin Rw+rP1  s N1
 Rw  Rs 
= P1N1
P1Vt N1Vt
Rw+ Rs+ 
 IP1  IP2 
Current Sink Injection

Apply a voltage compliant current sink to the output pad (vOUT < 0).
Voltage Compliant
vIN vOUT Current Sink VDD
Rw3
LT2
Rs LT1 VT2 VT1 Rw
Loop gain:
iout  Rw   Rs 
 
= P1 N1R +r 
iin  Rw +r P1   s N1
 Rw  Rs 
= P1N1
P1Vt N1Vt
Rw+ Rs+ 
 IP1  IP2 
Latchup from a Transmission Gate

The classical push-pull output stage is only one of the many configurations that can lead
to latchup. Here is another configuration:
Internal Core
Transmission Pad
Circuitry
Gate Clk VDD
Internal
Core Pad
VDD
Circuits
VDD
Clk
Injectors Receiver
Driver
Transmission Gate Clock Driver
050416-09 p+ p p- n- n n+ Oxide Poly 1 Poly 2 Nitride Salicide Metal
The two bold solid bipolar transistors in the transmission gate act as injectors to the npn-
pnp parasitic bipolars of the clock driver and cause these transistors to latchup. The
injector sites are the diffusions connected to the pad.

The Influence of Shallow Trench Isolation on Latchup

As seen below, the STI causes the parasitic betas to be smaller and slightly reduces the
sensitivity to latchup.
VDD OUTPUT GRD
Top
Metal
GRD Metal Vias Metal Via Second
Inter- Level
mediate Tungsten Sidewall Tungsten Plugs Metal
Oxide Plugs Spacers Polycide
First
Layers Level
Tungsten Salicide Salicide Salicide Tungsten
Salicide Plugs Plug Metal
p+ n+ p+ p+ n+ n+ p+
n-well p-well
Substrate

Preventing Latch-Up
1.) Keep the source/drain of the MOS device not in the well as far away from the well as
possible. This will lower the value of the BJT betas.
2.) Reduce the values of RN- and RP-. This requires more current before latch-up can
occur.
3.) Surround the transistors with guard rings. Guard rings reduce transistor betas and
divert collector current from the base of SCR transistors.
p-channel transistor n-channel transistor

n+ guard bars p+ guard bars
VDD VSS
FOX
FOX FOX FOX FOX FOX FOX FOX
p-well
n- substrate
140805-01

What are Guard Rings?

Guard rings are used to collect carriers flowing in the silicon. They can be designed to
collect either majority or minority carriers.
Guard rings in n-material: Guard rings in p-material:

n+ guard ring p+ guard ring p+ guard ring n+ guard ring
Collects Collects Collects majority Collects
majority VDD minority carriers minority VDD
carriers carriers carriers
Decreased bulk
Decreased bulk
resistance
resistance
p+ p p- n- n n+
n-
051201-01
p+ p p- n n+ 051201-02
Also, the increased doping level of the n+ (p+)guard ring in n (p) material decreases the
resistance in the area of the guard ring.

Example of Reducing the Sensitivity to Latchup by using Guard Rings

Start with placing guard rings around the NMOS and PMOS transistors (both I/O and
logic) to collect most of the parasitic NPN and PNP currents locally and prevent turn-on
of adjacent devices.
vIN
p+ guard vOUT VDD n+ guard VDD

ring ring
Rw
Rs
Note increased separation

• The guard rings also help to reduce the effective well and substrate resistance.
• The guard rings reduce the lateral beta
Key: The guard rings should act like collectors

Example of Reducing the Sensitivity to Latchup by using Butted Contacts

Finally, use butted source contacts to further reduce the well resistance and reduce the
substrate resistance.
vIN
p+ guard vOUT VDD n+ guard VDD

ring ring
Rs Rw

Guidelines for Guard Rings

• Guard rings should be low resistance paths.
• Guard rings should utilize continuous diffusion areas.
• More than one transistor of the same type can be placed inside the same well inside the
same guard ring as long as the design rules for spacing are followed.
• Only 2 guard rings are required between adjacent PMOS and NMOS transistors
• The well taps and/or the guard ring should be laid out as close to the MOSFET source
as possible.
• I/O output NMOSFET should use butted composite for source to bulk connections
when the source is electrically connected to the p-well tap. If separate well tap and
source connections are required due to substrate noise injection problems, minimize the
source-well tap spacing. This will minimize latch up and early snapback of the output
MOSFETs with the drain diffusion tied directly (in metal) to the bond pad.

ESD IN CMOS TECHNOLOGY

What is Electrostatic Discharge?
Triboelectric charging happens when 2 materials come in contact and then are separated.
An ESD event occurs when the stored charge is discharged.

ESD and Integrated Circuits

• ICs consist of components that are very sensitive to excess current and voltage above
the nominal power supply.
• Any path to the outside world is susceptible to ESD
• ESD damage can occur at any point in the IC assembly and packaging, the packaged
part handling or the system assembly process.
• Note that power is normally not on during an ESD event
050727-01

ESD Models and Standards

• Standard tests give an indication of the ICs robustness to withstand ESD stress.
• Increased robustness:
- Reduces field failures due to ESD
t=0 RLim
- Demanded by customers
• Simple ESD model: + i(t)
VSE IC
- VSE = Charging Voltage - C
- Key parameters of the model:
o Maximum current flow Current
o Time constant or how fast the ESD I
max
event discharges
Time constant (t)
o Risetime of the pulse ≈ RLimC
Risetime
0 t
0 070210-01

ESD Models
• Human body model (HBM): Representative of an ESD
event between a human and an electronic component.
050423-02
• Machine model (MM): Simulates the ESD event when a

charged “machine” discharges through a component.
040929-03
• Charge device model (CDM): Simulates the ESD event

when the component is charged and then discharges through
a pin. The substrate of the chip becomes charged and
discharges through a pin.
110214-01
14
Discharge Current, IESD (A)
11 CDM
2 HBM
-1
MM
-4
0 20 40 60 80 100 120
Time, t (ns)

ESD Influence on Components

An ESD event typically creates very high values of current (1-10A) for very short periods
of time (150 ns) with very rapid rise times (1ns).
Therefore, components experience extremely high values of current with very little power
dissipation or thermal effects.
Resistors – become nonlinear at high currents and will breakdown
Capacitors – become shorts and can breakdown from overvoltage (pad to substrate)
Diodes – current no longer flows uniformly (the connections to the diodes represent the
ohmic resistance limit)
Transistors – ESD event is only a two terminal event, the third terminal is influenced by
parasitics and many of the transistor parameters are poorly controlled.
• MOSFETs – the parasitic bipolar experiences snapback under an ESD event
• BJTs – will experience snapback under ESD event

Objective of ESD Protection

• There must be a safe low impedance path between every combination of pins to sink the
ESD current (i.e. 1.5A for 2kV HBM)
• The ESD device should clamp the voltage below the breakdown voltage of the internal
circuitry
• The metal busses must be designed to survive 1.5A (fast transient) without building up
excessive voltage drop
• ESD current must be steered away from sensitive VDD
circuits Limiting
Resistor ESD
Sensitive Power
Circuits Rail
Clamp
VSS 041008-01
• ESD protection will require area on the chip (busses
and timing components)

ESD Protection Architecture

VDD Rail based protection
Local Local
Clamp Clamp ESD
Input Internal Output Power
Pad Circuits Pad Rail
Local Local Clamp
Clamp Clamp
040929-06
Local clamp based protection VSS
Local clamps – Conducts ESD current without loading the internal (core) circuits
ESD power rail clamps – Conducts a large amount of current with a small voltage drop
ESD Events:
Pad-to-rail (uses local clamps only)
Pad-to-pad (uses either local or local and ESD power rail clamps)

Example of an ESD Breakdown Clamp

A normal MOSFET that uses the parasitic lateral BJT to achieve a snapback clamp.
Normally, the MOSFET has the gate shorted to the source so that drain current is zero.
S G D B iDS
- +
vDS Device destruction
iDS
Negative TC
n+ n+ p+ Second Breakdown
iC
Shallow Shallow
Positive TC Snapback Region
Trench Trench
First Breakdown
Isolation Rsub iSub Isolation
Avalanche
p-substrate B Linear Region Region
Saturation Region
DS v
Operation: 041217-04
Vt1 Vt2
• Impact ionization at drain edge generates a substrate current
• Substrate current causes the transistor to turn on creating current from the emitter and
“snapping back” from a BVCES to BVCER characteristic
Issues:
• If the drain voltage becomes too large, the gate oxide may breakdown
• The current should be distributed evenly among multiple fingers
• The SCR discussed previously makes an excellent breakdown clamp
Example of a Non-Breakdown Clamp

NMOS Clamp:
Speed-up
VDD Capacitor
R
Trigger NMOS
Circuit Clamp
C Inverter
Driver
VSS 041001-03
Operation:
• Normally, the input to the driver is high, the output low and the NMOS clamp off
• For a positive ESD event, the voltage increases across R causing the inverter to turn on
the NMOS clamp providing a low impedance path between the rails
• Cannot be used for pads that go above power supply or are active when powered up
• For power supply turn-on, the circuit should not trigger (C holds the clamp off during
turn-on)
Also, forward biased diodes serve as non-breakdown clamps.
IV Characteristics of Good ESD Protection

Goal: Sink the ESD current and clamp the voltage.
Current
Current
ITarget ITarget
ESD Clamp ESD Clamp
Protected Protected
Device Device
Voltage Voltage
Protected ESD
Case 1 - Okay Case 2 - Protected Device Fails
Device Clamp
Current
Current
ITarget ITarget
ESD Clamp ESD Clamp
Protected
Protected Device
Device
Voltage Voltage
Case 3 - Okay Case 4 - Protected Device Fails
070221-02

Comparison Between the NMOS Clamp and the Snapback Clamp

Increasing the width of either the active or snapback NMOS clamp will reduce the clamp
voltage.
Max. operating voltage

Target
ESD
Current
Increasing
Current
NMOS W
Increasing
Snapback W
NMOS VT Holding Trigger Voltage

150617-01 Voltage Voltage
Note that the NMOS clamp does not normally exceed the absolute maximum voltage.
NMOS clamps should be used with EPROMs to avoid reprogramming during an ESD
event.

ESD Practice
General Guidelines:
• Understand the current flow requirements for an ESD event
• Make sure the current flows where desired and is uniformly distributed
• Series resistance is used to limit the current in the protected devices
• Minimize the resistance in protecting devices
• Use distributed (smaller) active clamps to minimize the effect of bus resistance
• Understand the influence of packaging on ESD
• Use guard rings to prevent latchup
Check list:
• Check the ESD path between every pair of pads
• Check for ESD protection between the pad and internal circuitry
• Check for low bus resistance
- Current: Minimum metal for ESD  40 x Electromigration limit
- Voltage: 1.5A in a metal bus of 0.03/square of 1000µm long and 30µm wide
gives a voltage drop of 1.5V
• Check for sufficient contacts and vias in the ESD path (uniform current distribution)

SUMMARY
• Latchup is a low impedance path between VDD and ground causing excessive current.
• The conditions for latchup are:
- A four-layer, pnpn structure connected between power supply rails
- An injector (any diffusion connected to a pad)
- A stimulus
• Latchup is prevented by:
- Keeping the NMOS and PMOS transistors separated
- Reducing the well resistance with appropriate well ties
- Surrounding the transistors with guard rings
• ESD is caused by triboelectric charging which discharges through the IC
• The current produced by an ESD event must be controlled – uniform current flow,
minimum voltage drop, and must not flow through sensitive circuitry
• An ESD event turns on very quickly (<1ns), has a high peak current (1A), and lasts for
approximately 100 ns.
• ESD clamps consist of breakdown clamps (snapback) and non-breakdown clamps.
• A 16-lecture, on-line course on the Analog Design viewpoint of ESD can be found at
http://www.udemy.com/esd-an-analog-design-viewpoint
Lecture 09 – Large Signal MOSFET Model (5/14/18) Page 09-1
LECTURE 09 – LARGE SIGNAL MOSFET MODEL

Outline
• Introduction to modeling
• Operation of the MOS transistor
• Simple large signal model (SAH model)
• Subthreshold model
• Short channel, strong inversion model
• Summary
Pages 68-76 and 96-98

INTRODUCTION TO MODELING
Models Suitable for Understanding Analog Design
The model required for analog design with CMOS technology is one that leads to
understanding and insight as distinguished from accuracy.
Technology
Understanding
and Usage
Updating Model Thinking Model Updating Technology

Simple,
±10% to ±50% accuracy
Comparison of Design Decisions- Extraction of Simple

simulation with "What can I change to Model Parameters
expectations accomplish ....?" from Computer Models
Expectations
"Ballpark"
Computer Simulation
Refined and
optimized
design Fig.3.0-02
This lecture is devoted to the simple model suitable for design not using simulation.

Categorization of Electrical Models
Time Dependence
Time Independent Time Dependent
Linear Small-signal, midband Small-signal frequency

Rin, Av, Rout response-poles and zeros
Linearity (.AC)
(.TF)
Nonlinear DC operating point Large-signal transient

iD = f(vD,vG,vS,vB) response - Slew rate
(.OP) (.TRAN)
Based on the simulation capabilities of SPICE.

OPERATION OF THE MOS TRANSISTOR

Formation of the Channel for an Enhancement MOS Transistor
Subthreshold (VG<VT)
VB = 0 VS = 0 VG < VT VD = 0
Polysilicon
p+ n+ n+
p- substrate Depletion Region
Threshold (VG=VT)
VB = 0 VS = 0 VG =VT VD = 0
Polysilicon
p+ n+ n+
p- substrate Inverted Region
Strong Threshold (VG>VT)

VB = 0 VS = 0 VG >VT VD = 0
Polysilicon
p+ n+ n+
Fig.3.1-02

Transconductance Characteristics of an Enhancement NMOS when VDS = 0.1V

Output Characteristics of an Enhancement NMOS Transistor for VGS = 2VT

VDS=0:
VB = 0 VS = 0 vG =2VT VD = 0V iD
iD
Polysilicon VGS = 2VT
p+ n+ n+

0 vDS
VDS=0.5VT:
0 0.5VT VT
VB = 0 VS = 0 VG = 2VT VD = 0.5VT iD
iD
Polysilicon VGS = 2VT
p+ n+ n+
p- substrate Channel current

0 vDS
0 0.5VT VT
VDS=VT:
VB = 0 VS = 0 VG = 2VT VD =VT iD
iD VGS = 2VT
Polysilicon
p+ n+ n+
A depletion region
p- substrate
forms between the drain and channel 0 vDS
0 0.5VT VT Fig.3.1-04

Output Characteristics of an Enhancement NMOS when vDS = 2VT

VGS=VT:
VB = 0 VS = 0 vG =VT VD = 2VT iD
iD
Polysilicon
p+ n+ n+
p- substrate VGS =VT

0 vDS
0 VT 2VT 3VT
VGS=2VT:
VB = 0 VS = 0 VG = 2VT VD = 2VT iD
iD
Polysilicon
VGS =2VT
p+ n+ n+
p- substrate
0 vDS
0 VT 2VT 3VT
VGS=3VT:
VB = 0 VS = 0 VG = 3VT VD = 2VT iD
VGS =3VT
iD
Polysilicon
p+ n+ n+
Further increase in
p- substrate
VG will cause the FET to become active 0 vDS
0 VT 2VT 3VT
Fig.3.1-05

Output Characteristics of an Enhancement NMOS Transistor

2000
VGS = 3.0
1500
VGS = 2.5
iD(mA) 1000
VGS = 2.0
500
VGS = 1.5
VGS = 1.0
0
0 1 2 3 4 5
vDS (Volts)
SPICE Input File: Fig. 3.1-6
Output Characteristics for NMOS M5 6 5 0 0 MOS1 w=5u l=1.0u
M1 6 1 0 0 MOS1 w=5u l=1.0u VGS5 5 0 3.0
VGS1 1 0 1.0 VDS 6 0 5
M2 6 2 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VGS2 2 0 1.5 +gamma=0.4 lambda=.04 phi=.7)
M3 6 3 0 0 MOS1 w=5u l=1.0u .dc vds 0 5 .2
VGS3 3 0 2.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 6 4 0 0 MOS1 w=5u l=1.0u ID(M5)
VGS4 4 0 2.5 .end

Transconductance Characteristics of an Enhancement NMOS Transistor

6000
VDS = 5V
5000
VDS = 4V
VDS = 3V
4000
iD(mA)
3000
VDS = 2V
2000
VDS = 1V
1000
0
0 1 2 3 4 5
vGS (Volts) Fig. 3.1-7
SPICE Input File:
Transconductance Characteristics for NMOS M5 5 6 0 0 MOS1 w=5u l=1.0u
M1 1 6 0 0 MOS1 w=5u l=1.0u VDS5 5 0 5.0
VDS1 1 0 1.0 VGS 6 0 5
M2 2 6 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VDS2 2 0 2.0 +gamma=0.4 lambda=.04 phi=.7)
M3 3 6 0 0 MOS1 w=5u l=1.0u .dc vgs 0 5 .2
VDS3 3 0 3.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 4 6 0 0 MOS1 w=5u l=1.0u ID(M5)
VDS4 4 0 4.0 .probe
.end

SIMPLE LARGE SIGNAL MODEL (SAH MODEL)

Large Signal Model Derivation +
vGS +
1.) Let the charge per unit area in the channel -
iD - vDS
inversion layer be
n+ n+
QI(y) = -Cox[vGS-v(y)-VT] (coul./cm2) v(y)
Source dy Drain
p- y
2.) Define sheet conductivity of the inversion 0 y y+dy L
layer per square as Fig.110-03
cm2coulombs amps 1
S = µoQI(y)  v·s  cm2  = volt =
  
   /sq.
3.) Ohm's Law for current in a sheet is
iD dv -iD -iDdy
JS = W = -SEy = -S dy → dv = dy = µ Q (y)W → iD dy = -WµoQI(y)dv
SW o I
4.) Integrating along the channel for 0 to L gives

L vDS vDS
 iDdy = - WµoQI(y)dv = WµoCox[vGS-v(y)-VT] dv

0 0 0
5.) Evaluating the limits gives
WµoCox  v2(y)vDS WµoCox  vDS2
2  0 →
iD = (vGS-VT)v(y) - iD = (vGS-VT)vDS -
L  L  2 
Saturation Voltage - VDS(sat) iD

vDS = vGS-VT
Interpretation of the large signal model:
Active Region Saturation Region
Increasing
values of vGS
vDS
Fig. 110-04
The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of
the inverted parabolas. vDS
diD µoCoxW
dvDS = [(vGS-VT) - vDS] = 0
L Cutoff Saturation Active
T
-V
vDS(sat) = vGS - VT S
vG
=
S
Useful definitions: vD
0 vGS
µoCoxW K’W 0 VT Fig. 3.2-4
= L =
L
Note that newest editions of Analysis and Design of Analog ICs, P.R. Gray et.al,
switches the definition for the active and saturation regions.
The Simple Large Signal MOSFET Model

Regions of Operation of the MOS Transistor:
1.) Cutoff Region:
vGS - VT < 0
iD = 0
(Ignores subthreshold currents)
2.) Active Region Output Characteristics of the MOSFET:
0 < vDS < vGS - VT iD/ID0
vDS = vGS-VT
µoCoxW vGS-VT
1.0 = 1.0
iD = 2(v - V ) - v  v Active VGS0-VT
2L  GS T DS  DS Region Saturation Region
vGS-VT
0.75 = 0.867
VGS0-VT
Channel modulation effects
3.) Saturation Region vGS-VT
= 0.707
0.5 VGS0-VT
0 < vGS - VT < vDS vGS-VT
= 0.5
VGS0-VT
µoCoxW 0.25 vGS-VT
iD = v - V 2 Cutoff Region VGS0-VT
=0
2L  GS T
vDS
0
0 0.5 1.0 1.5 2.0 2.5 VGS0-VT
Fig. 110-05

Performance Limitations of the Simple Sah

25µA
It turns out, that if we compare
the Sah model to a more precise K’ = 44.8µA/V 2,
k = 0,
model (SPICE level 2) that the 20µA
VDS(sat) = 1.0V K’ = 44.8µA/V 2,
Sah model has issues with the k = 0.5,
“knee” area as shown. VDS(sat) = 1.0V
15µA
iD
SPICE Level 2 Model
10µA
K’ = 29.6µA/V 2,
5µA
k = 0,
VDS(sat) = 1.0V
0µA
0 0.2 0.4 0.6 0.8 1.0
vDS (volts) 140825-01
VGS = 2.0V, W/L = 100µm/100µm
This discrepancy is due to the fact that we assumed that the threshold, VT, was constant
over the channel.
If we let VT (y) = VT + kv(y) then the Sah model is exactly the same as the SPICE model.

Modification of the Previous Model to Include the Effects of vDS on VT

From the previous derivation:
L vDS vDS
  
i dy = - WµoQI(y)dv = WµoCox[vGS - v(y) -VT]dv
 D  
0 0 0
Assume that the threshold voltage varies across the channel in the following way:
VT(y) = VT + kv(y)
where VT is the value of VT the at the source end of the channel and k is a constant.
Integrating the above gives,
v
WµoCox  v(y)2 DS WµoCox  vDS2
iD = L (vGS-VT)v(y) - (1+k) 2  → iD = L (vGS-VT)vDS - (1+k) 2 
  0  
To find vDS(sat), set the diD/dvDS equal to zero and solve for vDS = vDS(sat),
vGS - VT
vDS(sat) =
1+k
Therefore, in the saturation region, the drain current is
WµoCox
iD = 2(1+k)L (vGS - VT)2
For k = 0.5 and K’ = 44.8µA/V2, excellent correlation is achieved with SPICE 2 as seen
on the previous slide.

Influence of vDS on the Output Characteristics

Channel modulation effect: VG > V T VD > VDS(sat)
As the value of vDS increases, the
B S
effective L decreases causing the
Depletion
current to increase. Polysilicon Region
p+ n+ n+
Illustration:
Leff
Note that Leff = L - Xd p- substrate Xd

Fig110-06
Therefore the model in saturation
becomes,
K’W diD K’W dLeff iD dXd
iD = 2L (vGS-VT) → dv = -
2
2
2
(vGS - VT) dv = L dv  iD
eff DS 2Leff DS eff DS
Therefore, a good approximation to the influence of vDS on iD is
diD K’W
iD  iD( = 0) + vDS = iD( = 0)(1 + vDS) = (vGS-VT)2(1+vDS)
dvDS 2L

Channel Length Modulation Parameter, 

Assume the MOS is transistor is saturated-
µCoxW
 iD = 2L (vGS - VT)2(1 + vDS)
Define iD(0) = iD when vDS = 0V.
µCoxW
 iD(0) = 2L (vGS- VT)2
Now,
iD = iD(0)[1 + vDS] = iD(0) + iD(0) vDS
Matching with y = mx + b gives the value of 

Influence of Channel Length on 

Note that the value of  varies with channel length, L. The data below is from a 0.25µm
CMOS technology.
Channel Length Modulation (V-1)

0.6
0.5
0.4
PMOS
0.3
0.2
NMOS
0.1
0
0 0.5 1 1.5 2 2.5
Channel Length (microns) Fig.130-6
Most analog designers stay away from minimum channel length to get better gains and
matching at the sacrifice of speed.

Lecture 09 – Large Signal MOSFET Model (5/14/18) VBS0 = 0V PageV09-18
GS
Influence of the Bulk Voltage on the Large Signal MOSFET Model Polysilic
The components of the threshold voltage VSB0 = 0: p+ n+

are: p- substrate
VT = Gate-bulk work function (MS) VBS1 > 0V VGS
+ voltage to change the surface
potential (-2F)
Polysilic
p+ n+
+ voltage to offset the channel-bulk VSB1 > 0:
VD > 0
depletion charge (-Qb/Cox) p- substrate
+ voltage to compensate the VSB2 >VSB1: VGS
undesired interface charge

(-Qss/Cox)
VSB2 >VSB1: n+
We know that
Qb =  2|F| - vBS
Therefore, as the bulk becomes more
reverse biased with respect to the
source, the threshold voltage must p+
060613-02
increase to offset the increased channel- p- substrate
bulk depletion charge.
Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued
Bulk-Source (vBS) influence on the transconductance characteristics-
iD
Decreasing values
of bulk-source voltage
VBS = 0
ID
vDS > vGS-VT
VGS
vGS
VT0 VT1 VT2 VT3
060612-02
In general, the simple model incorporates the bulk effect into VT by the previously
developed relationship:
VT(vBS) = VT0 +  2|f| - vBS -  2|f|

Summary of the Simple Large Signal MOSFET Model D

N-channel reference convention: +
iD
G B
Non-saturation- v
+ + DS
WµoCox  vDS2 vGS vBS
iD =  
(v - VT)vDS - 2 (1 + vDS)
L  GS  - -
S Fig. 110-10
Saturation-
WµoCox vDS(sat)2 WµoCox
iD = (vGS-VT)vDS(sat)- (1+vDS)= (vGS-VT)2(1+vDS)
L  2  2L
where:
µo = zero field mobility (cm2/volt·sec)
Cox = gate oxide capacitance per unit area (F/cm2)
 = channel-length modulation parameter (volts-1) Terms in red are
VT = VT0 +  2|f| - vBS - 2|f| model parameters
VT0 = zero bias threshold voltage
 = bulk threshold parameter (volts0.5)
2|f| = strong inversion surface potential (volts)
For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert
the current.
Silicon Constants
Constant Constant Description Value Units

Symbol
VG Silicon bandgap (27C) 1.205 V
k Boltzmann’s constant 1.381x10-23 J/K
ni Intrinsic carrier concentration (27C) 1.45x1010 cm-3
o Permittivity of free space 8.854x10-14 F/cm
si Permittivity of silicon 11.7 o F/cm
ox Permittivity of SiO2 3.9 o F/cm

MOSFET Parameters
Model Parameters for a Typical CMOS Bulk Process (0.25µm CMOS n-well):
Parameter Typical Parameter Value Units

Parameter Description
Symbol N-Channel P-Channel
VT0 Threshold Voltage 0.5± 0.15 -0.5 ± 0.15 V
(VBS = 0)
K' Transconductance Para- 120.0 ± 10% 25.0 ± 10% µA/V2
meter (in saturation)
 Bulk threshold 0.4 0.6 (V)1/2
parameter
 Channel length 0.32 (L=Lmin) 0.56 (L=Lmin) (V)-1
modulation parameter 0.06 (L ≥2Lmin) 0.08 (L ≥2Lmin)
2|F| Surface potential at 0.7 0.8 V
strong inversion

SUBTHRESHOLD MODEL
Large-Signal Model for Weak Inversion
The electrons in the substrate at the source side can be expressed as,
s 
np(0) = npoexpV 
 t
The electrons in the substrate at the drain side can be expressed as,
s-vDS
np(L) = npoexp V 
 t 
Therefore, the drain current due to diffusion is,
np(L)- np(0) W s    vDS
iD = qADn   = qXDnnpoexp  1 - exp- 
 L  L Vt   Vt  
where X is the thickness of the region in which iD flows.
In weak inversion, the changes in the surface potential, s are controlled by changes in
the gate-source voltage, vGS, through a voltage divider consisting of Cox and Cjs, the
depletion region capacitance. Poly
ds Cox 1 vGS vGS-VT Oxide Cox vGS
 dv = C + C = n → s = n + k1 = n + k2 Channel
GS ox js Dep. Cjs fs
where VT
k2 = k1 + n Substrate
060405-04
Large-Signal Model for Weak Inversion – Continued

Substituting the above relationships back into the expression for iD gives,
W k2 vGS-VT  vDS
iD = L qXDnnpo expV exp nV 1 - exp- V 
 t  t   t 
Define It as
k2
It = qXDnnpo expV 
 t
to get,
W vGS-VT  vDS
iD = L It exp nV 1 - exp- V 
 t   t 
where n  1.5 – 3 iD
VGS=VT
If vDS > 0, then 1mA
W vGS-VT vDS
iD = It exp 1 + 
L  nV t  V A
VGS<VT
The boundary between nonsaturated and
saturated is found as,
Vov = VDS(sat) = VON = VGS -VT = 2nVt 0 vDS
0 1V
Fig. 140-03

SHORT CHANNEL, STRONG INVERSION MODEL

What is Velocity Saturation?
Electron Drift Velocity (m/s)

The most important short-channel 105
effect in MOSFETs is the velocity
saturation of carriers in the channel. 5x104
A plot of electron drift velocity
2x104
versus electric field is shown below.
104
5x103
An expression for the electron drift 105 106 107
velocity as a function of the electric Electric Field (V/m) Fig130-1
field is,
µnE
vd  1 + E/E
c
where
vd = electron drift velocity (m/s)
µn = low-field mobility ( 0.07m2/V·s)
Ec = critical electrical field at which velocity saturation occurs

Short-Channel Model Derivation

As before,
iD WQI(y)µnE  E
JD = JS = W = QI(y)vd(y) → iD = WQI(y)vd(y) = 1 + E/E → iD 1+ E  = WQI(y)µnE
c  c
Replacing E by dv/dy gives,
 1 dv dv
iD 1 + E dy= WQI(y)µndy
 c 
Integrating along the channel gives,
L
vDS
  1 dv
iD1 + E dydy = WQI(y)µndv
  c 
0
0
The result of this integration is,
µnCox W µnCox W
iD = 2
[2(vGS-VT)vDS-vDS ] =  2
 L [2(vGS-VT)vDS-vDS ]
 1 DSv  L 21 +  vDS

21 + E L 
 c 
where  = 1/(EcL) with dimensions of V-1.

Saturation Voltage
Differentiating iD with respect to vDS and setting equal to zero gives,
1 
  (VGS-VT) 
V’DS(sat) =  1 + 2(VGS-VT -1  (VGS-VT)1 -
 + ···
  
 2 
if
 (VGS-VT)
<1
2
Therefore,
  (VGS-VT) 

V’DS(sat)  VDS(sat) 1 - + ··· 
 2 
Note that the transistor will enter the saturation region for vDS < vGS - VT in the
presence of velocity saturation.

Large Signal Model for the Saturation Region

To develop the large signal model, we will assume that
 (VGS-VT)
<1
2
so that we can substitute the less complex expression of
V’DS(sat)  (VGS-VT)
into the active region version of the model to get,
K’ W 2]
iD =  [2(v -V )(v -V )- (v -V )
21 +  (vGS - VT) L
 GS T GS T GS T
K’ W
= [ v - V ]2
2[1 + (vGS-VT)] L GS T
However, we continue to use the following to define when the MOSFET is in the
saturation region,
  (VGS-VT) 

vDS ≥ (VGS-VT) 1 - + ··· 
 2 

The Influence of Velocity Saturation on the Transconductance Characteristics

The following plot was made for K’ = 110µA/V2 and W/L = 1:
Note as the velocity saturation effect becomes stronger, that the drain current-gate
voltage relationship becomes linear.

Circuit Model for Velocity Saturation

A simple circuit model to include the influence of velocity saturation is is shown:
We know that
K’W
iD = 2L (vGS’ -VT)2 and vGS = vGS’ + iD RSX
or
vGS’ = vGS - iDRXS
Substituting vGS’ into the current relationship gives,
K’W
iD = 2L (vGS - iDRSX -VT)2
Solving for iD results in,
K’ W 2
iD =   (v GS - V T)
W L
21 + K’ L RSX(vGS-VT)
 
Comparing with the previous result, we see that
W L 
 = K’ L RSX → RSX = K’W = E K’W
c
Therefore for K’ = 110µA/V2, W = 1µm and Ec = 1.5x106V/m, we get RSX = 6.06k.

SUMMARY
• The modeling of this lecture is devoted to understanding how the circuit works
• The two primary current-voltage characteristics of the MOSFET are the
transconductance characteristic and the output characteristic
• The simple Sah large signal model is good enough for most applications and
technology
• The Sah model can be improved in the region of the knee and for the weak dependence
of drain current on drain-source voltage in the saturation region
• Most designers do not work at minimum channel length because of the channel length
modulation effect and because worse matching occurs for small areas
• The threshold voltage is increased as the bulk-source is reverse biased
• The subthreshold model accounts for very small currents that flow in the channel when
the gate-source voltage is smaller than the threshold voltage
• The subthreshold current is exponentially related to the gate-source voltage
• Velocity saturation occurs at minimum channel length and can be modeled by
including a source degeneration resistor with the simple large signal model

Lecture 10 – MOS Capacitor Model and Large Signal Model Dependence (3/10/14) Page 10-1
LECTURE 10 – MOS CAPACITOR MODEL AND LARGE

SIGNAL MODEL DEPENDENCE
Outline
• MOSFET capacitor model
• Dependence of the large signal model on process
• Dependence of the large signal model on voltage
• Dependence of the large signal model on temperature
• MOSFET reliability
• Summary
Pages 77-86 and new material

MOSFET CAPACITOR MODEL

Submicron Technology
Physical perspective:
SiO2
Gate
Source Drain
C1 C2 C3
FOX FOX
C4
CBS CBD
Bulk
Fig120-06
MOSFET capacitors consist of:

• Depletion capacitances
• Charge storage or parallel plate capacitances
Deep Submicron Technology

Physical perspective:
MOSFET capacitors consist of:

• Depletion capacitances
• Charge storage or parallel plate capacitances

MOSFET Depletion Capacitors Polysilicon gate

Model:
1.) vBS  FC·PB H G
CJ·AS CJSW·PS D C
CBS = MJ +  MJSW,
 vBS vBS Source Drain
 
1 - 1 -
 PB   PB  F
E
and A B
2.) vBS> FC·PB SiO2
Bulk
CJ·AS  VBS Fig. 120-07
CBS = Drain bottom = ABCD
1+MJ 1 - (1+MJ)FC + MJ PB 
1- FC Drain sidewall = ABFE + BCGF + DCGH + ADHE
 
 VBS
CJSW·PS 
+ 1+MJSW  1 - (1+MJSW)FC + MJSW PB 
  
 1 - FC
where
AS = area of the source
PS = perimeter of the source
CJSW = zero bias, bulk source sidewall capacitance
MJSW = bulk-source sidewall grading coefficient
For the bulk-drain depletion capacitance replace "S" by "D" in the above.
SM Charge Storage (Parallel Plate) MOSFET Capacitances - C1, C2, C3 and C4
Mask L Oxide encroachment

Overlap capacitances:
Actual C1 = C3 = LD·Weff·Cox = CGSO or
Actual
LD
L (Leff) Mask
W W (Weff) CGDO (LD  0.015 µm for LDD structures)
Gate
Drain-gate overlap
Channel capacitances:
Source-gate overlap
capacitance CGS (C1) capacitance CGD (C3) C2 = gate-to-channel = CoxWeff·(L-2LD)
Gate
FOX FOX = CoxWeff·Leff
Source Drain
Gate-Channel Channel-Bulk
C4 = voltage dependent channel-
Bulk bulk/substrate capacitance
Capacitance (C2) Capacitance (C4)
Fig. 120-09

SM Charge Storage (Parallel Plate) MOSFET Capacitances - C5

View looking down the channel from source to drain
Overlap Overlap
Gate
FOX C5 Source/Drain C5 FOX
Bulk
Fig120-10
C5 = CGBO
Capacitance values based on an oxide thickness of 140 Å or Cox=24.7  10-4 F/m2:
Type P-Channel N-Channel Units
CGSO 220 10-12 220  10-12 F/m
CGDO 220  10-12 220  10-12 F/m
CGBO 700  10-12 700  10-12 F/m
CJ 560  10-6 770  10-6 F/m2
CJSW 350  10-12 380  10-12 F/m
MJ 0.5 0.5
MJSW 0.35 0.38

DSM Charge Storage MOSFET Capacitances - C1, C2, C3, C4 and C5
C1 and C3 are overlap capacitors due to lateral diffusion of the source and drain
C2 is the gate to channel capacitance
C4 is the depletion capacitance between the channel and the bulk
C5 is the fringing capacitance between the gate and the bulk around the edges of the
channel

MOSFET Capacitors for the Cutoff Region

Side view:
As the gate-source voltage varies from 0 to VT, the channel-bulk capacitor varies from a
very large capacitor (because of a very small depletion region) to a capacitor much
smaller than C2.
Capacitors in Cutoff:
CGS C1 = Cox·LD·W = CGSO·W
CGD C3 = Cox·LD·W = CGDO·W
CGB C2 varies from Cox·L·W to 2C5
CBD CBD = (CJ·AD)/[1 – (vBD/PB)]MJ + (CJSW·PD)/[1 – (vBD/PB)]MJSW
CBS CBS = (CJ·AS)/[1 – (vBS/PB)]MJ + (CJSW·PS)/[1 – (vBS/PB)]MJSW
MOSFET Capacitors for the Saturation Region

Side view:
Source-gate overlap Drain-gate overlap
Source-gate overlap Drain-gate overlap capacitance CGS (C1) capacitance CGD (C3)
capacitance CGS (C1) capacitance CGD (C3)
Gate
FOX FOX Shallow
Source Drain Gate-Channel Trench
Shallow Capacitance (C2)
Gate-Channel Trench Isolation
Capacitance (C2) Bulk Isolation
070330-06
In the saturation region, C4, becomes small and is not shown above.
Capacitors in Saturation:
CGS C1 = Cox·LD·W + (2/3)Cox·L·W = [CGSO + (2/3)Cox·L]W
CGD C3 = Cox·LD·W = CGDO·W
CGB 2C5 = 2·CGBO·W

MOSFET Capacitors for the Active Region

Side view:
Source-gate overlap Drain-gate overlap
Source-gate overlap Drain-gate overlap capacitance CGS (C1) capacitance CGD (C3)
capacitance CGS (C1) capacitance CGD (C3)
Gate
FOX FOX Shallow
Source Drain Gate-Channel Trench
Shallow Capacitance (C2)
Gate-Channel Trench Isolation
Bulk
Capacitance (C2) Isolation
070330-07
In the saturation region, C4, becomes small and is not shown above.
Capacitors in Active:
CGS C1 = Cox·LD·W + (1/2)Cox·L·W = [CGSO + (1/2)Cox·L]W
CGD C3 = Cox·LD·W + (1/2)Cox·L·W = [CGDO + (1/2)Cox·L]W
CGB 2C5 = 2·CGBO·W

Illustration of CGD, CGS and CGB

Comments on the variation of CBG in the cutoff region:
1
CBG = 1 1 + 2C5
C2 + C4
1.) For vGS  0, CGB  C2 + 2C5 Capacitance
Cox
Cj
Cox
(C4 is large because of the thin Cj Cox
C2 + 2C5 Cj
inversion layer in weak inversion CGS
C1+ 0.67C 2
CGS, CGD
where VGS is slightly less than C1+ 0.5C2
vDS = constant
VT)) CGS, CGD CGD vBS = 0
C1, C3 C4 Small
CGB
2.) For 0 < vGS ≤ VT, CGB  2C5 2C5
0 vGS
Non-
(C4 is small because of the thicker Off Saturation
Saturation
inversion layer in strong inversion) VT vDS +VT 150706-01

DEPENDENCE OF THE LARGE SIGNAL MODEL ON PROCESS

How Does Technology Vary?
1.) Thickness variations in layers (dielectrics and metal)
tox(min) tox(max)
060225-01
2.) Doping variations

n+ p+ p+
n-well Diffusion Differences

060225-02
3.) Process biases – differences between the drawn and actual dimensions due to process
(etching, lateral diffusion, etc.)
Drawn Dimension
Actual Dimension
060225-03

Large Signal Model Dependence on Process Variations

1.) Threshold voltage
VT = VT0 +   |-2F + vSB| - |-2F|
where
Qb0 QSS 2qsiNA
VT0 = MS - 2F - C - C and =
ox ox Cox
If VBS = 0, then VT is dependent on doping and oxide thickness because
kT NSUB 1
F = q ln n  and Cox  t
 i  ox
(Recall that the threshold is also determined by the threshold implant during processing)
2.) Transconductance parameter
1
K’ = µoCox  t
ox
For short channel devices, the mobility is degraded as given by
µo 2x10-9m/V
µeff = and ≈
1 + (VGS - VT) tox

Process Variation “Corners”

For strong inversion operation, the primary influence is the oxide thickness, tox. We see
that K’ will tend to increase with decreasing oxide thickness whereas VT tends to
decrease. PMOS
If the “speed” of a transistor is increased Speed
Large Kʼ
by increasing K’ and decreasing VT, then Fast Small VT
the variation of technology can be PMOS Acceptable
expressed on a two-dimensional graph Technology
Slow Parameters
resulting in a rectangular area of
PMOS Small Kʼ
“acceptable” process limitation. Large V T
Slow Fast NMOS Speed
060118-10
NMOS NMOS
Three corner versus five corner models

DEPENDENCE OF THE LARGE SIGNAL MODEL ON VOLTAGE

What is Voltage Variation?
Voltage variation is the influence of power supply voltage on the component.
(There is also power supply influence on the circuit called power supply rejection ratio,
PSRR. We will deal with this in a later lecture.)
Power supply variation comes from:
1.) Influence of depletion region widths on components.
2.) Nonlinearity (e.g., velocity saturation)
3.) Breakdown voltage
Note: Because the large-signal model for the MOSFET includes all the influences of
voltage on the transistor, we will focus on passive components except for breakdown.

Models for Voltage Dependence of a Component

1.) ith-order Voltage Coefficients
In general a variable y = f(v) which is a function of voltage, v, can be expressed as a
Taylor series,
y(v = V0)  y(V0) + a1(v- V0) + a2(v- V0)2+ a3(v- V0)3 + ···
where the coefficients, ai, are defined as,
df(v) | 1 d2f(v) |
a1 = ,a = , ….
dv v=V0 2 2 dv2 v=V0
The coefficients, ai, are called the first-order, second-order, …. voltage coefficients.
2.) Fractional Voltage Coefficient or Voltage Coefficient
Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a term
called fractional voltage coefficient, VCF, which is defined as,
1 df(v) |
VCF(v=V0) = parts per million/V (ppm/V)
f(v=V0) dv v=V0
or more simply,
1 df(v)
VCF = f(v) dv parts per million/V (ppm/V)
Influence of Voltage on a Diffused Resistor – Depletion Region

Influence of the depletion region on the p+ resistor:
Thickness of
p+ p+ Resistor Thickness of
p+ Resistor
FOX FOX p+ p+
Depletion region
STI STI
n- well
n-well
p- substrate
060305-01 Older LOCOS Technology
As the voltage at the terminals of the resistor become smaller than the n-well potential,
the depletion region will widen causing the thickness of the resistor to decrease.
L
R=  VR
tW
where VR is the reverse bias voltage from the resistor to the well.
This effect is worse for well resistors because the doping concentration of the resistor is
smaller.
Voltage coefficient for diffused resistors ≈ 200-800 ppm/V
Voltage coefficient for well resistors ≈ 8000 ppm/V
Voltage Coefficient of Polysilicon Resistors

Why should polysilicon resistors be sensitive to voltage?
There is a small depletion region between the polysilicon and its surrounding material
that has a very small dependence on the voltage between the polysilicon and the
surrounding material.

Voltage Nonlinearity and Breakdown Voltage

Conductivity modulation:
As the current in a resistor increases, the conductivity becomes modulated and the
resistance increases. i
i= v
Example of a n-well resistor: R
0.1A
Conductivity
modulation
v
060311-01
As the reverse bias voltage across a pn junction becomes large, at some point, called the
breakdown voltage, the current will rapidly increase. Both transistors, diodes and
depletion capacitors experience this breakdown.
iR
Model for current multiplication factor:
1
iR = M·IR where M =
 vR  n
1 - BV
  Breakdown
voltage
vR
060311-02 BV
DEPENDENCE OF THE LARGE SIGNAL MODEL ON TEMPERATURE

Temperature Dependence of the MOSFET
Transconductance parameter:
K’(T) = K’(T0) (T/T0)-1.5 (Exponent becomes +1.5 below 77°K)
Threshold Voltage:
VT(T) = VT(T0) + (T-T0) + ···
Typically NMOS = -2mV/°C to –3mV/°C from 200°K to 400°K (PMOS has a + sign)
Example
Find the value of ID for a NMOS transistor at 27°C and 100°C if VGS = 2V and W/L =
5µm/1µm if K’(T0) = 110µA/V2 and VT(T0) = 0.7V and T0 = 27°C and NMOS = -2mV/°C.
Solution
At room temperature, the value of drain current is,
110µA/V2·5µm 2 = 465µA
ID(27°C) = (2-0.7)
2·1µm
At T = 100°C (373°K), K’(100°C)=K’(27°C) (373/300)-1.5=110µA/V2·0.72=79.3µA/V2
and VT(100°C) = 0.7 – (.002)(73°C) = 0.554V
79.3µA/V2·5µm
 ID(100°C) = (2-0.554) 2 = 415µA (Repeat with VGS = 2.0855V)
2·1µm
Zero Temperature Coefficient (ZTC) Point for MOSFETs

For a given value of gate-source voltage, the drain current of the MOSFET will be
independent of temperature. Consider the following circuit:
Assume that the transistor is saturated and that:
 T -1.5 ID
 = oT  and VT(T) = VT(To) + (T-To)
 o
oCoxW  T -1.5 VGS
 ID(T) = T  [VGS – VT0 - (T-To)]2
2L  o Fig. 4.5-12
dID -3oCoxW T -2.5 oCoxW T -1.5
dT = 4LTo To [VGS-VT0-(T-To)] - L To [VGS-VT0-(T-To)] = 0
2
-4T 
 VGS – VT0 - (T-To) = 3  VGS(ZTC) = VT0 - To - 3
Let K’ = 20µA/V2, W/L = 0.375,  = -0.0016V/°C and VT0 = 0.46V.

At T=27°C(300°K), VGS(ZTC)=0.46-(-0.0016)(300°K)-(0.333)(-0.0016)(300°K)=1.10V
At T = 27°C (300°K), ID = (20µA/V2)(1.5/4)(1.10-0.46)2 = 3.07µA

Experimental Verification of the ZTC Point

The plot below is the simulation results for an n-channel MOSFET with W = 1.5µm and
L = 4µm.
A similar result holds for the p-channel MOSFET.

ZTC Point for UDSM Technology

50 nm CMOS:
1.0
0.9 25°C
0.7 NMOS
25°C 0.8 50°C
Normalized Drain Current

Normalized Drain Current
L=50nm
0.6 50°C 0.7 NMOS 100°C
100°C L=500nm 140°C
0.5 140°C 0.6
0.4 0.5
0.3 Zero Temperature 0.4

Coefficient Zero Temperature
0.3
0.2 Coefficient
0.2
0.1
0.1
0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Gate Source Voltage 071108-01 Gate Source Voltage 110409-02
Note that the ZTC point can be close to VDD.

PMOS will have similar characteristics.

Bulk-Drain (Bulk-Source) Leakage Currents

Cross-section of a NMOS in a p-well:
VG > VT VD > VDS(sat)
VGS>VT:
B S
Depletion
Polysilicon Region
p+ n+ n+
p-well
n- substrate
Fig.3.6-5
VGS<VT: VG <VT VD > VDS(sat)
B S
Depletion
Polysilicon Region
p+ n+ n+
p-well
n- substrate
Fig.3.6-6
Temperature Modeling of the PN Junction

PN Junctions (Reverse-biased only):
Dppno Dnnpo qAD ni −VGo
2
−iD  Is = qA  +  = KT exp  
3
 Lp Ln  L N  Vt 
Differentiating with respect to temperature gives,
dIs 3KT 3 −VGo qKT 3VGo −VGo 3Is Is VGo
= exp  + exp  = +
dT T  Vt  KT 2  Vt  T T Vt
dIs 3 1 VGo
TCF = = +
IsdT T T Vt
Example
Assume that the temperature is 300° (room temperature) and calculate the reverse
diode current change and the TCF for a 5° increase.
Solution
The TCF can be calculated from the above expression as TCF = 0.01 + 0.155 = 0.165.
Since the TCF is change per degree, the reverse current will increase by a factor of 1.165
for every degree  (or C) change in temperature. Multiplying by 1.165 five times gives
an increase of approximately 2. Thus, the reverse saturation current approximately
doubles for every 5C temperature increase. (Experimental is closer to 8°C.)

Experimental Verification of the PN Junction Temperature Dependence
10-5
200°C Data
-6
10 Symbol Min. L
6 mm
250°C 5 mm
10-7
Leakage Current (A)
4 mm
10-8 IR 2 mm
50mm
Lmin 100°C
-9
10 1V
Theory
10-10 matched
at 150°C Generation-
Diffusion Recombination
10-11
Leakage Leakage
Dominant Dominant
10-12
1.8 2 2.2 2.4 2.6 2.8
1000/T (°K -1) 100324-03
Theory:
VG(T)
Is(T)  T exp kT  3
 

Temperature Modeling of the PN Junction – Continued

PN Junctions (Forward biased – vD constant):
vD
iD  Is exp  V 
 t
Differentiating this expression with respect to temperature and assuming that the diode
voltage is a constant (vD = VD) gives
diD iD dIs 1 VD
dT = Is dT - T Vt iD
The fractional temperature coefficient for iD is
1 diD 1 dIs VD 3 VGo - VD
= - = + 
iD dT Is dT TVt T  TVt 
If VD is assumed to be 0.6 volts, then the fractional temperature coefficient is equal to
0.01+(0.155-0.077) = 0.0879. The forward diode current will approx. double for a 10°C.
PN Junctions (Forward biased – iD constant):
VD = Vt ln(ID/Is)
Differentiating with respect to temperature gives
dvD vD  1 dIs vD 3Vt VGo VGo-vD 3Vt
= T -Vt I dT  = T - T - T = - T  - T ≈ -2.3 mV/°C if vD = VD = 0.6V
dT s   

Resistor Dependence on Temperature

Diffused Resistors:
The temperature dependence of resistors depends mostly on the doping level of diffused
and implanted resistors. As the doping level or sheet resistance increases from 100 /
to 400 /, the temperature coefficient varies from about +1000 ppm/°C to +4000
ppm/°C. Diffused and implanted resistors have good thermal conduction to the substrate
or well.
Polysilicon Resistors:
Typically has a sheet resistance of 20 / to 80 / and has poor thermal conduction
because it is electrically isolated by oxide layers.
Metal:
Metal is often used for resistors and has a positive temperature coefficient.
Temperature Coefficients of Resistors:
n-well = 4000 ppm/°C Diffusion = +1500 ppm/°C
Polysilicon = 500-2000 ppm/°C Ion implanted = +400 ppm/°C
Metal = +3800 ppm/°C (aluminum)

MOSFET RELIABILITY
Hot Carrier Injection
Hot carriers depend on channel length. Longer channel lengths minimize hot carrier
effects. The worst-case hot carrier degradation occurs in NMOS devices when the gate
voltage is between VT and 0.5VDS and VDS is large.
Substrate current- Gate current-
Target specifications:
1.) No more than 100mV change in VT within a year of stress.
2.) No more than a 10% change in IDsat or Rdson within a year of stress.
Substrate current is a measure of hot carrier injection.

Typical NMOS Reliability Data

100.0 100.0
10.5 years 3.2 years

10 mV Degradation 10% Degradation
IDSat Degradation in %
VT Degradation in mV
10.0 10.0
Extra-
1.0 Extra- 1.0 polated
polated Data
Data
10 years
10 years
0.1 0.1
0.01 0.01
101 102 103 104 105 106 107 108 109 101 102 103 104 105 106 107 108 109
Time (Seconds) Time (Seconds) 140826-01
Note the extrapolation of short time data out to a year or more.
Also:
• NBTI (negative bias temperature instability) – PMOS with large gate-source voltage
• GOI (gate oxide integrity) – reliability of dielectrics

Antenna Effect
• The antenna effect is the situation during processing the charged plasmas that are used
put charge on the metal and if this metal is connected to the gate of a MOSFET and the
metal area is large enough, the oxide can breakdown.
• Oxide thicknesses less than 100Å are more susceptible to the antenna effect (plasma
induced discharge).
• A reverse biased diode connected from the metal to the semiconductor can be used to
leak this charge during processing (at high temperatures) and protect the gate oxides.
• Design rules exists to avoid having metal with large areas connected to gates (metal
jumpers).
SUMMARY
• The large signal capacitance model includes depletion and parallel plate capacitors
• The depletion capacitors CBD and CBS vary with their reverse bias voltage
• The capacitors CGD, CGS, and CGB have different values for the regions of cutoff,
active and saturated
• The large signal model varies with process primarily through µo and tox
• Voltage dependence of resistors and capacitors is primarily due to the influence of
depletion regions
• The temperature dependent large signal model of the MOSFET yields a gate-source
voltage where the derivative of drain current with respect to temperature is zero
• Other MOSFET temperature dependence comes from the leakage currents across
reverse biased pn junctions
• MOSFET reliability concerns degradation in performance over a specified lifetime

Lecture 11 – Linear Circuit Models (6/10/14) Page 11-1
LECTURE 11 – LINEAR CIRCUIT MODELS

Outline
• Frequency independent small signal transistor models
• Frequency dependent small signal transistor model
• Noise models
• Passive component models
• Interconnects
• Substrate interference
• Summary
Pages 86-90, 96-98 and new material

FREQUENCY INDEPENDENT SMALL SIGNAL TRANSISTOR MODELS

What is a Small Signal Model?
The small signal model is a linear approximation of a nonlinear model.
Mathematically:
 Large Signal to Small Signal
iD = 2 (vGS - VT)2       id = gmvgs
Graphically:
iD
The large signal curve at point Q has been
iD = b(vGS-VT)2
approximated with a small signal model going
id through the point Q and having a slope of gm.
id = gmvgs
ID Q
vgs
vGS
VT VGS 060311-03

Why Small Signal Models?

The small signal model is a linear approximation to the large signal behavior.
1.) The transistor is biased at given DC operating point (Point Q above)
2.) Voltage changes are made about the operating point.
3.) Current changes result from the voltage changes.
If the designer is interested in only the current changes and not the DC value, then the
small signal model is a fast and simple way to find the current changes given the voltage
changes.
id
Large Signal
Model
id = gmvgs
DiD DiDʼ Q
vgs
DVGS 060311-04

How Good is the Small Signal Model?

It depends on how large are the changes and how nonlinear is the large signal model.
• The parameters of the small signal model will depend on the values of the large signal
model.
• The model is a tradeoff in complexity versus accuracy (we will choose simplicity and
give up accuracy).
• What does a simulator do? Exactly the same thing when it makes an ac analysis (i.e.
frequency response)
• Regardless of the approximate nature of the small signal model, it is the primary model
used to predict the signal performance of an analog circuit.
Be alert for situations where the small signal model will be in error (i.e. slide 25-27).

Small-Signal Model for the Saturation Region

The small-signal model is a linearization of the large signal model about a quiescent or
operating point.
Consider the large-signal MOSFET in the saturation region (vDS  vGS – VT) :
WµoCox
iD = (vGS - VT) 2 (1 + vDS)
2L
The small-signal model is the linear dependence of id on vgs, vbs, and vds. Written as,
id  gmvgs + gmbsvbs + gds vds
where
diD |
gm  dv = (VGS-VT) = 2ID
GS Q
diD |  ID
gds  dv =   ID
DS Q 1 +  V DS
and
dD |  diD dvGS |  diD  dVT  | gm
gmbs  dv Q = dv  dv  = -   = = gm
BS  GS BS Q  dV T BSQ 2 2|F| - VBS
dv

Small-Signal Model – Continued

Complete schematic D D
id
G B
model: + + +D
G B G B vgs vbs rds vds
gmvgs gmbsvbs
- - -
S S
where S S Fig. 120-01
diD | diD | iD

gm  dv = (VGS-VT) = 2ID gds  dv =  iD
GS Q DS Q 1 +  v DS
and
D |  iD  vGS |  iD vT  | gm
gmbs = =   = -   = = gm
vBS Q  vGS vBS Q  vT vBSQ 2 2|F| - VBS
Simplified schematic model:
A very useful assumption:

gm  10gmbs  100gds

Small-Signal Model for other Regions

Active region:
iD | K’WVDS K’W iD | K’W VDS
gm = = (1+VDS)   L  VDS gmbs =
 
=
vGS Q L   vBS Q 2L 2F - VBS
iD | K’W ID K’W
gds = = ( V - V - V )(1+ V ) + ≈ L (VGS - VT - VDS)
vDS Q L GS T DS DS
1+VDS
Note:
While the small-signal model analysis is independent of the amplitude of the signal,
the small-signal parameters are not.
Weak inversion region:
If vDS > 0, then
iD = It L exp nV 1 + V 
 t  A
Small-signal model:
diD | W It vGS-VT vDS ID qID ID Cox
gm = dv = It exp nV 1 + V  = nV = nkT = V C +C
GS Q L nV t  t  A t t ox js
diD | ID
gds = dv 
DS Q VA
FREQUENCY DEPENDENT SMALL SIGNAL MODEL

Small-Signal Frequency Dependent Model
The depletion capacitors are found by evaluating the large signal capacitors at the DC
operating point.
The charge storage capacitors are constant for a specific region of operation.

Gain-bandwidth of the MOSFET (fT)

The short-circuit current gain is measure of the frequency capability of the MOSFET.
iout
Small signal model: Cgd iout
+ C
iin gs
VDD vgs rds
iin - gmvgs Cbd
Small signal analysis gives, 060311-05
iin
iout = gmvgs – sCgdvgs and vgs = s(C + C )
gs gd
Therefore,
iout gm-sCgd gm
= ≈
iin s(Cgs + Cgd) s(Cgs + Cgd)
Assume VSB = 0 and the MOSFET is in saturation,
1 gm 1 gm
fT = 2 C + C ≈ 2 C
gs gd gs
Recalling that
2 W 3 µo
Cgs  3 CoxWL and gm = µoCox L (VGS-VT) → fT = 4 2 (VGS-VT)
L
For velocity saturation, fT  1/L.

NOISE MODELS
Derivation of the MOSFET Thermal Noise Model
In the active region, the channel resistance of the MOSFET is given from the simple large
signal model as,
1 1 1 1
Rchannel = = ≈ =
∂iD | K’W K’W gm(sat)
(V GS - V T - V DS ) (V GS - V T)
∂vDSQ L L
The current thermal noise spectral density of a MOSFET in the active region would be
4kT
in2(active) = R = 4kTgm(sat) (A2/Hz)
channel
In the saturation region, approximate the channel resistance as 2/3 the value in the active
region resulting in 2/3 the noise. Therefore in saturation we have the current thermal
noise spectral density as,
2 2 8kTgm(sat)
2
in (sat) = 3 in (active) = (A 2/Hz)
3
Translating this drain current noise to the gate voltage noise by dividing by gm2 gives
8kT
en2 = 3g (V2/Hz)
m

The Influence of the Back Gate on Thermal Noise

The influence of the back gate on the thermal noise can be developed by replacing gm of
the previous expressions with gm + gmbs
Substituting R with Rchannel(sat) gives the voltage and current noise spectral densities as,
8kT 8kT
en2 = (V 2 /Hz) = (V 2/Hz)
3(gm + gmbs) 3gm(1 + )
or
8kT(gm + gmbs) 8kTgm(1 + )
in2 = (A 2 /Hz) = (A 2/Hz)
3 3
where
gmbs
= g
m

1/f Noise Model

Another significant noise contribution to MOSFETs is a noise that is typically inversely
proportional to frequency called the 1/f noise.
This 1/f noise spectral density is given as,
KF IDAF KF
2 
in = fSC L2  or en = 2fSC WL K’
2
 ox  ox
where
KF = Flicker noise coefficient
S = Slope factor of the 1/f noise
Although we do not have a good explanation for the reason why, the value of the 1/f
noise for a PMOS is typically less than that for an NMOS for the same current and W/L.
f = 10Hz
MOS Device Noise at Low Frequencies

D D
D
eN2
G B G in2 G * B
Noise Noise
S B Free
Free S
MOSFET MOSFET S
where
 8kTgm(1+) KF IDAF
in2 =  + S  (amperes2/Hz)
 3 f CoxL 
2
gmbs
= g
m
k = Boltzmann’s constant
KF = Flicker noise coefficient
S = Slope factor of the 1/f noise
AF = Current coefficient

Reflecting the MOSFET Noise to the Gate

Dividing in2 by gm2 gives the voltage noise spectral density as
in2  8kT KF 
en = g 2 = 
2 + 2fC WL K’ (volts2/Hz)
m  3gm(1+) ox 
KF
It will be convenient to use B = 2C K’ to simplify the notation.
ox
Frequency response of MOSFET noise:

Noise Spectral
Density
1/f noise
Thermal noise
fCorner log10 f
060311-06
The 1/f corner frequency is:

8kT KF 3gmB
=  fcorner ≈ if gmbs = 0
3gm(1+) 2fCoxWL K’ 8kTWL

PASSIVE COMPONENT MODELS

Resistor Models v v
i + R (v) i + R (v)
- -
Cp Cp1 Cp2
Distributed Model Lumped Model

060315-01
i
1.) Large signal i= v
R
Conductivity
modulation
v
2.) Small signal 060311-01
v = Ri
3.) Noise
en2 = 4kTR or in2 = 4kTG

Capacitor Models
Rp
One of the parasitic capacitors is i C(v)
the top plate and the other is -
+
associated with the bottom plate. v
Cp Cp
C 060315-03
Linear
1.) Large signal
Nonlinear
v
060315-04
2.) Small signal
q = Cv  i = C(dv/dt)
3.) Do capacitors have noise? See next page.

Switched Capacitor Circuits - kT/C Noise

Capacitors and switches generate an inherent thermal noise given by kT/C. This noise is
verified as follows.
An equivalent circuit for a switched capacitor: R on
vin C vout vin C vout
060315-05
The noise voltage spectral density of switched capacitor above is given as

2kTRon
eR2on = 4kTRon Volts2/Hz = Volt2/Rad./sec.

The rms noise voltage is found by integrating this spectral density from 0 to  to give
∞
2kTRon  12d 2kTRon1 kT
vR2on =  2 2=  = Volts(rms)2
 1 +   2  C
0
where 1 = 1/(RonC). Note that the switch has an effective noise bandwidth of
1
fsw = 4R C Hz
on
which is found by dividing the second relationship by the first.
INTERCONNECTS
Types of “Wires”
1.) Metal
Many layers are available in today’s technologies:
- Lower level metals have more resistance (70 m/sq.)
- Upper level metal has the less resistance because it is thicker (50 m/sq.)
2.) Polysilicon
Better resistor than conductor (unpolysicided) (135/sq.)
Silicided polysilicon has a lower resistance (5/sq.)
3.) Diffusion
Reasonable for connections if silicided (5/sq.)
Unsilicided (55/sq.)
4.) Vias
Vias are vertical metal (tungsten plugs or aluminum)
- Connect metal layer to metal layer (3.5/via)
- Connect metal to silicon or polysilicon contact resistance (5/contact)
Ohmic Contact Resistance

The metal to silicon contact generates resistance because of the presence of a potential
barrier between the metal and the silicon.
Contact and Via Resistance:

Contact
Contact System Resistance Metal 3
(/µm2) Aluminum
Al-Cu-Si to 160/sq. base 750 Vias
Metal 2
Al-Cu-Si to 5/sq. emitter 40 Tungsten
Plugs
Al-Cu/Ti-W/PtSi to 1250 Metal 1
160/sq. base
Al-Cu/Al-Cu (Via) 5
Al-Cu/Ti-W/Al-Cu (Via) 5
Transistors
050319-02

Capacitance of Wires
Self, fringing and coupling capacitances:
Wide Spacing Minimum Spacing
CCoupling CCoupling
CFringe CFringe
Ground plane CSelf
050319-03
Capacitance Typical Value Units

Metal to diffusion, Self capacitance 33 aF/µm2
Metal to diffusion, Fringe capacitance, minimum spacing 7 aF/µm
Metal to diffusion, Fringe capacitance, wide spacing 40 aF/µm
Metal to metal, Coupling capacitance, minimum spacing 85 aF/µm
Metal to substrate, Self capacitance 28 aF/µm2
Metal to substrate, Fringe capacitance, minimum spacing 4 aF/µm
Metal to substrate, Fringe capacitance, wide spacing 39 aF/µm

Electromigration
Electromigration occurs if the current density is too large and the pressure of carrier
collisions on the metal atoms causes a slow displacement of the metal.
Black’s law:
1 (Ea/kTj)
MTF = e
AJ 2 Metal
Where 050304-04
A = rate constant (cm4/A2/hr)

J = current density (A/cm2)
Ea = activation energy in electron volts (0.5eV for Al and 0.7eV for Cu doped Al)
k = Boltzmann’s constant (8.6x10-5 eV/K)
Electromigration leads to a maximum current density, Jmax. Jmax for copper doped
aluminum is 5x105 A/cm2 at 85°C.
If t = 10,000 Angstroms and Jmax = 5x105 A/cm2, then a 10µm wide lead can conduct no
more than 50mA at 85°C.

Where is AC Ground on the Chip?

AC grounds on the chip are any area tied to a fixed potential. This includes the substrate
and the wells. All parasitic capacitances are in reference to these points.
VDD GRD
Top
Metal
GRD Metal Vias Metal Via Second
Inter- Level
mediate Tungsten Sidewall Tungsten Plugs Metal
Oxide Plugs Spacers Polycide
First
Layers Level
Tungsten Salicide Salicide Salicide Tungsten
Salicide Plugs Plug Metal
p+ n+ p+ p+ n+ n+ p+
Isolation AC Ground Isolation DC and AC Ground Isolation
n-well p-well
DC Ground
Substrate

Grounds that are Not Grounds

Because of the resistance of “wires”, current flowing through a wire can cause a voltage
drop.
Bad:
An example of good and bad Circuit Circuit Circuit
practice: A B C
R R R
IA IA+IB IA+IB+IC
Better:
Circuit Circuit Circuit
A B C IC
R
2R IB
3R IA
Best:
Circuit Circuit Circuit
A B C
R IA R IB R IC
050305-04

Kelvin Connections
Avoid unnecessary ohmic drops.
A B A B
X Y
Ohmic Connection Kelvin Connection 041223-12
In the left-hand connection, an IR drop is experienced between X and Y causing the

potentials at A and B to be slightly different.
For example, let the current be 100µA and the metal be 30m/sq. Suppose that the
distance between X and Y is 100 squares. Therefore, the IR drop is
100µA x 30m/sq. x 100sq. = 0.3mV

SUBSTRATE NOISE INTERFERENCE

Methods of Substrate Injection
• Hot carrier
• Leakage
Also: The substrate BJT
and the inductor create
currents in the substrate.
• Minority Carrier
• Displacement Current (large devices)

How is Noise Injected into Components?

MOSFETs:
Injection occurs by the bulk effect on the
threshold and across the depletion capacitance.
BJTs:
Injection primarily across the depletion
capacitance.
Passives:

ISOLATION TECHNIQUES
Isolation Techniques
Isolation techniques include both layout and circuit approaches to isolating quiet from
noisy circuits.

Isolation Techniques – Guard Rings

• Collect the majority/minority carriers in the substrate
• Connect the guard rings to external potentials through conductors with
- Minimum resistance
di
- Minimum inductance v=L
dt

Isolation Techniques - Layout

Separation:
Physical separation – works well for non-epi, less for epi
Trenches:
Good if filled with a dielectric, not good if filled with a
conductor.
Layout:
Common centroid geometry does
not help.
Keep contact and via resistance to a
minimum.
Wells help to isolate (deep n-well)

CIRCUIT TECHNIQUES
Isolation Techniques - Noise Insensitive Circuit Design

• Design for high power supply rejection ratio (PSRR)
• Correlated sampling techniques – eliminate low frequency noise
• Use “quiet” digital logic (power supply current remains constant)
• Use differential signal processing techniques.
Example of a 4th order Sigma Delta modulator using differential circuits:

Noise Isolation Techniques - Reduction of Package Parasitics

• Keep the lead
inductance to a
minimum (multiple
bond wires)
• Package selection†
Leadless lead frame: Micro surface mount device:
Still has Minimum

bond wires inductance
package
†
Electrical Performance of Packages, National Semiconductor Application Note 1205, August 2001.
SUMMARY
• Small signal models are a linear representation of the transistor electrical behavior
• Including the transistor capacitors in the small signal model gives frequency
dependence
• Noise models include thermal and 1/f noise voltage or current spectral density models
• Passive component models include the nonlinearity, small signal and noise models
• Interconnects include metal, polysilicon, diffusion and vias
• Electromigration occurs if the current density is too large causing a displacement of
metal
• Substrate interference is due to interaction between various parts of an integrated circuit
via the substrate
• Method to reduce substrate interference include:
- Physical separation
- Guard rings
- Reduced inductance in the power supply and ground leads
- Appropriate contacts to the regions of constant potential
- Reduce the source of interfering noise
- Use differential signal processing techniques
Lecture 12 – Component Matching (6/10/14) Page 12-1
LECTURE 12 – COMPONENT MATCHING

Outline
• Introduction
• Electrical matching
• Physical matching
• Summary
Pages 640-652 and new material

INTRODUCTION
What is Accuracy and Matching?
The accuracy of a quantity specifies the difference between the actual value of the
quantity and the ideal or true value of the quantity.
The mismatch between two quantities is the difference between the actual ratio of the
quantities and the desired ratio of the two quantities.
Example:
x1 = actual value of one quantity
x2 = actual value of a second quantity
X1 = desired value of the first quantity
X2 = desired value of the second quantity
The accuracy of a quantity can be expressed as,
x - X X
Accuracy = X = X
x 2 X2
The mismatch, , can be expressed as, x1 - X1 X1x2
= X = X x -1
2 2 1
X1
Relationship between Accuracy and Matching

Let:
X1 = |x1 - X1| → x 1 = X 1 ± X 1
and
X2 = |x2 – X2| → x 2 = X 2 ± X 2
Therefore, the mismatch can be expressed as,
X 2
1± X
X1(X2 ± X2) 2  X 2   X 1 
= –1= – 1  1 ± X  1 +- X  – 1
X2(X1 ± X1) X 1  2  1 
1± X
1
X 2
 X1 X 2  X 1
  1 ± X + X – 1 = ± X +- X
-
2 1 2 1
Thus, the mismatch is approximately equal to the difference in the accuracies of x1 and
x2 assuming the deviations (X) are small with respect to X.

Characterization of the Mismatch

Mean of the mismatch for N samples-
1 N
m = N i
i=1
Standard deviation of the mismatch for N samples-
N
1
s =  =
N-1 (i - m)2
i=1
Example:
10
Number of Samples
9
8
7
6
5
4
3
2
1
0 X
0 1 2 3 4 5 6 7 8 9 1011121314
041005-01
253
m = 40 = 6.325 s = 2.115
Motivation for Matching of Components

The accuracy of analog signal processing is determined by the accuracy of gains and
time constants. These accuracies are dependent upon:
Gain  Ratios of components or areas
Time constants  Products of components or areas
Ratio Accuracy?
1± X1
X1± X1 X1  X1  X1  X1 X2 X1  X1 X2
Actual Ratio = = X   ≈ X 1± X 1-+ X  ≈ X 1± X -+ X 
X2± X2 X 2 2 1  2 2 2
2
1±  1
 X2 
If X1 and X2 match (X1/X1 ≈ X2/X2), then the actual ratio becomes the ideal ratio.
Product Accuracy?
 X1 X2  X1 X2
Product accuracy = (X1±X1)(X2±X2) = X1X21± 1±  ≈ X1X21± ± 
 X 1  X 2  X 1 X 2
Unfortunately, the product cannot be accurately maintained in integrated circuits.

Switched Capacitor Circuits

Switched capacitor circuits offer a solution to the product accuracy problem.
A switched capacitor replacement of a resistor: f1
f2
T
Tc R1= c
f1 f2 C1
+ + + +
v1 C1 v2 v1 v2
- - - -
060316-06
The product of a resistor, R1, and a capacitor, C2, now become,
 Tc   1  C2
R1C2 = C  C2 = f C C2 = f C
 1  c 1 c 1
The accuracy of the time constant (product) now becomes,
C2  C2 C1 fc
1± -+ -+ 
fcC1 C2 C1 fc 
Assuming the clock frequency is accurate and larger than the signal bandwidth, then time
constants in analog signal processing can be accurately matched by ratios of elements.

Types of Mismatches
1.) Those controlled or influenced by electrical design
- Transistor operation
- Circuit techniques
- Correction/calibration techniques
2.) Those controlled or influenced by physical design
- Random statistical fluctuations (microscopic fluctuations and irregularities)
- Process bias (geometric variations)
- Pattern shift (misalignment)
- Diffusion interactions
- Stress gradients and package shifts
- Temperature gradients and thermoelectrics
- Electrostatic interactions

ELECTRICAL MATCHING
Matching Principle
Assume that two transistors are matched (large signal model parameters are equal).
Then if all terminal voltages of one transistor are equal to the terminal voltages of the
other transistor, then the terminal currents will be matched.
iC1 iC2 iD1 iD2
iB1 iB2
Q1 Q2 M1 M2
iE1 iE2
041005-02
Note that the terminals may be physically connected together or at the same potential but
not physically connected together.

Examples of the Matching Principle

iD1 iD2 iD1 iD2
M3 M4 iD1 iD2
M3 M4
+ M1 VB M2 + M1 M2
Vio Vio
VB M1 M2 - -
M5 M5
041005-03
Cascode current mirror:
The key transistors are M1 and M2. The gates and sources are physically connected
and the drains are equal due to M3 and M4 gate-source drops. As a result, iD1 will be
very close to iD2.
Differential amplifier:
When iD1 and iD2 are equal, the fact that the drains of M1 and M2 are equal should
give the smallest value of the input offset voltage, Vio.
Note: Since the drain voltages of M3 and M4 in both circuits are not necessarily equal,
the gate-source voltages of M3 and M4 are not exactly equal which cause the drain
voltages of M1 and M2 to not be exactly equal.
Gate-Source Matching
Not as precise as the previous principle but useful for biasing applications.
A. If the gate-source voltages of two or more FETs are equal and the FETs are matched
and operating in the saturation region, then the currents are
related by the W/L ratios of the individual FETs. The gate- iD1 M1 M2
iD2
source voltages may be directly or indirectly connected. W1 W2
L1 + + L2
K’W1 2K’iD1
iD1 = 2L (vGS1-VT1)2 → (vGS1-VT1)2 = (W /L ) vGS1 vGS2
1 1 1 - -
Fig. 290-02
K’W2 2K’iD2
iD2 = 2L (vGS2-VT2)2 → (vGS2-VT2)2 = (W /L )
2 2 2 iD1
W2 W1 W1/L1 W1
If vGS1 = vGS2, then   iD1 =   iD2 or iD1 = W /L  iD2 + L1
 L2   L1   2 2 vGS1
-
B. If the drain currents of two or more transistors are equal and the trans- iD2
M2
W2
istors are matched and operating in the saturation region, then the gate- + L2
source voltages are related by the W/L ratios (ignoring bulk effects). vGS2
-
If iD1=iD2, then Fig. 290-03
W2/L2 W2 W1
vGS1 = VT1+ W1/L1 (vGS2-VT2) or vGS1 = vGS2 if L2 = L1
Process Independent Biasing - MOSFET

The sensitivity of the bias points of all transistors depend on both the variation of the
technological parameters and the accuracy of the biasing circuits.
Gate-source voltage decomposition:
The gate-source voltage of the MOSFET can be divided into two parts:
1.) The part necessary to form or enhance the channel, VT
2.) The part necessary to cause current to
flow, VGS – VT = VON , called the
overdrive.
This overdrive can be expressed,

2ID
VON = VDS(sat) = K’(W/L)
The dependence of the bias point on the technology, VT, can be reduced by making VON
= VDS(sat) >> VT.
This implies that small values of W/L are preferable. Unfortunately, this causes the
transconductance to become small if the current remains the same.
Doubly Correlated Sampling

Illustration of the use of chopper stabilization to remove the undesired signal, vu, from
the desired signal, vin. In this case, the undesired signal is the gate leakage current.
Vu(f) Clock
+1
Vin(f) t
-1
f
vu T =1
fc
f vA vB vC vout
vin A1 A2
VA(f)
f
0 fc 2fc 3fc
VB(f)
f
0 fc 2fc 3fc
VC(f)
f
0 fc 2fc 3fc Fig. 7.5-8

An Op Amp Using Doubly Correlated Sampling to Remove DC Offsets

Problem: M1 and M2 are thin gate oxide which have dc current at gate.
VDD
clkb clkb
M3 M4 R2
clk clkb
Cc vout
Inn clk clkb clk Inp
clk
Inp clk clk Inn
M1 M2
VDD VDD
M5
R1
clkb clkb 140828-01-01
• Chopping with 50% duty cycle

• All switches use thick oxide devices to reduce gate leakage
• Gain ≈ gm1(rds2||rds4)gm5R2
Will examine further in low noise op amps.
Self-Calibration Techniques
The objective of self-calibration is to increase the matching between two or more
components (generally passive).
The requirements for self-calibration:
1.) A time interval in which to perform the calibration
2.) A means of adjusting the value of one or more of the components.
Fixed Comparison Adjustable

Component of values Component
041007-05
Self-calibration can typically improve the matching by a factor of 2-3 bits (4-8).

Example of Capacitor Self-Calibration

Consider the charge amplifier below that should have a gain
of unity.
Assume the amplifier has a DC input offset voltage of Vio. The following shows how to
calibrate one (or both) of the capacitors.
In the calibration phase, vx, is:

 C2   C1   C2-C1 
vx = (VREF-Vio) C +C - (VREF-Vio) C +C = (VREF-Vio) C +C 
   
 1 2  1 2  1 2
The correction circuitry varies C1 or C2 until vx = 0 as observed by vOUT.
Variable Components
The correction circuitry should be controlled by logic circuits so that the correction can
be placed into memory to maintain the calibration of the circuit during application.
Implementation for C1 and C2 of the previous example:
C1 C1 C1 C1 C2 C2 C2 C2
C1 1- 1 2K 2K+1 2K+2 2N C2 1- 1 2K 2K+1 2K+2 2N
2K 2K
S1 S2 S3 SN S1 S2 S3 SN
Capacitor C 1 Capacitor C 2
041007-08
K is selected to achieve the desired tolerance or variation

N is selected to achieve the desired resolution (N > K)
Additional circuitry:
Every self-calibration system will need additional logic circuits to sense when the value
of vx changes from positive to negative (or vice versa) and to store the switch settings in
memory to maintain the calibration.

Basics of Dynamic Element Matching†

Dynamic element matching chooses different, approximately equal-valued elements to
represent a more precise value of a component as a function of time.
Goal of dynamic element matching:
Convert the error due to element mismatch from a dc offset into an ac signal of
equivalent power which can be removed by the appropriate means (doubly-correlated
sampling, highpass filtering of a sigma-delta modulator, etc.)
i
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9
i me t1
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 T
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
VRef
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
Tim S0 S1 S2 S3 S4 S5 S6 S7 S8 S9
e t2
All resistor are approximately equal
valued to within some tolerance
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
041010-01
†L. R. Carley, “A Noise-Shaping Coder Topology for 15+ Bit Converters, IEEE J. of Solid-State Circuits, vol. 24, no. 2, April 1989, pp. 267-273.
How Dynamic Element Matching Works

Assume that we have three approximately equal elements with the following currents:
Element 1 = 0.99mA Element 2 = 1.03mA Element 3 = 0.98mA
Ideal Current (mA)

3
2
Ideal current output level → 1
0 t
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Elements ® 1 1 1 1 1 1 1,2 1,2 1,2 1,2 1,2 1,2 1,2,3
+2
Error (%)
Normal
Error when dynamic +1
element matching is not → 0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
t
used -1
Elements ® 1 3 2 3 1 2 1,2 2,3 1,3 1,2 1,3 2,3 1,2,3
+3
Matching Error (%)
+2
Dynamic Element
Error when dynamic +1
element matching is used → 0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
t
-1
-2
060405-06
-3

Issues of Dynamic Element Matching

• The selection of the elements must be truly random for the maximum benefit to occur.
• If the number of elements is large this can be an overwhelming task to implement. An
approximation to random selection is the butterfly-type randomizer below:
S1 S5 S9
0 0
Three-stage, eight-line
S1 S6 S10
butterfly randomizer. 1 1
Each pair of switches S2 S5 S11
2 2
marked with the same S2 S6 S12
label is controlled to 3 3
either exchange the S3 S7 S9
4 4
two signal lines or S3 S8 S10
5 5
pass them directly S7
S4 S11
to the next stage. 6 6
S5 S8 S12
041010-03 7 7
• When using the dynamic element technique, one needs to be careful that the averaging
activity of the dynamic element matching process does not interfere with other
averaging processes that might be occurring simultaneously (i.e.  modulators).
• Other references:
1.) B.H. Leung and s. Sutarja, “Multibit - A/D Converter Incorporating A Novel Class of Dynamic Element Matching
Techniques,” IEEE Trans. on Circuits and Systems-II, vol. 39, no. 1, Jan. 1992, pp. 35-51.
2.) R. Baird and T. Fiez, “Linearity Enhancement of Multibit - A/D and D/A Converters Using Data Weighted
Averaging,” IEEE Trans. on Circuits and Systems-II, vol. 42, no. 12, Dec. 1995, pp. 753-762.
PHYSICAL MATCHING
Review of Physical Matching
We have examined these topics in previous lectures. To summarize, the sources of
physical mismatch are:

Rules for Resistor Matching†

1.) Construct matched resistors from the same material.
2.) Make matched resistors the same width.
3.) Make matched resistors sufficiently wide.
4.) Where practical, use identical geometries for resistors (replication principle)
5.) Orient resistors in the same direction.
6.) Place matched resistors in close physical proximity.
7.) Interdigitate arrayed resistors.
8.) Place dummy resistors on either end of a resistor array.
9.) Avoid short resistor segments.
10.) Connect matched resistors in order to cancel thermoelectrics.
11.) If possible place matched resistors in a low stress area (minimize pieozoresistance).
12.) Place matched resistors well away from power devices.
13.) Place precisely matched resistors on the axes of symmetry of the die.
†Alan Hastings, Art of Analog Layout, 2nd ed, 2006, Pearson Prentice Hall, New Jersey
Rules for Resistor Matching – Continued

14.) Consider the influence of tank modulation for HSR resistors (the voltage modulation
of the reverse-biased depletion region changes the sheet resistivity).
15.) Sectioned resistors are superior to serpentine resistors.
16.) Use poly resistors in preference to diffused resistors.
17.) Do not allow the buried layer shadow to intersect matched diffused resistors.
18.) Use electrostatic shielding where necessary.
19.) Do not route unconnected metal over matched resistors.
20.) Avoid excessive power dissipation in matched resistors.

Rules for Capacitor Matching†

1.) Use identical geometries for matched capacitors (replication principle).
2.) Use square or octogonal geometries for precisely matched capacitors.
3.) Make matched capacitors as large as possible.
4.) Place matched capacitors adjacent to one another.
5.) Place matched capacitors over field oxide.
6.) Connect the upper electrode of a matched capacitor to the higher-impedance node.
7.) Place dummy capacitors around the outer edge of the array.
8.) Electrostatically shield matched capacitors.
9.) Cross-couple arrayed matched capacitors.
10.) Account for the influence of the leads connecting to matched capacitors.
11.) Do not run leads over matched capacitors unless they are electrostatically shielded.
12.) Use thick-oxide dielectrics in preference to thin-oxide or composite dielectrics.
13.) If possible, place matched capacitors in areas of low stress gradients.
14.) Place matched capacitors well away from power devices.
15.) Place precisely matched capacitors on the axes of symmetry for the die.
Mismatched Transistors
Assume two transistors have vDS1 = vDS2, K1’  K2’ and VT1  VT2. Therefore we have
iO K2’(vGS - VT2)2
iI = K1’(vGS - VT1)2
How do you analyze the mismatch? Use plus and minus worst case approach. Define
K’ = K’2-K’1 and K’ = 0.5(K2’+K1’)  K1’= K’-0.5K’ and K2’= K’+0.5K’
VT = VT2-VT1 and VT = 0.5(VT1+VT2)  VT1 =VT -0.5VT and VT2=VT+0.5VT
Substituting these terms into the above equation gives,
 K’ V T  2
1 +  
iO (K’+0.5K’)(vGS - VT - 0.5VT )2  2K’ 1 - 2(vGS-VT)
iI = (K’-0.5K’)(vGS - VT + 0.5VT)2 =  K’ V T  2
1 -  
 2K’ 1 + 2(vGS-VT)
Assuming that the terms added to or subtracted from “1” are smaller than unity gives
iO  K’ K’ VT 2 VT  2 K’ 2VT
iI ≈ 1 + 2K’ 1 + 2K’ 1 - 2(vGS-VT) 1 - 2(vGS-VT)  1 + K’ - (vGS-VT)
     
If K’/K’ = ±5% and VT/(vGS-VT) = ±10%, then iO/iI  1 ± 0.05 ±(-0.20) = 1±(0.25)
Pelgrom’s Law
Spatial Averaging: Local and random Threshold mismatch for 0.18µm NMOS
variations decrease as the device size

increases, since the parameters “average
out” over a greater area.
Pelgrom’s Law:
Ap2
2(P) = + S 2D 2
WL p x
where,
P = mismatch in a parameter, P
WL = width times the length of the device (effective Pelgrom area)
Ap = proportionality constant between the standard deviation of P and the area of
the device
Dx = distance between the matched devices
Sp = proportionality constant between the standard deviation of P and Dx
As Dx becomes large, the standard deviation tends to infinity which is not realistic.
Geometric Effects
How does the size and shape of the transistor effect its matching?
Gate Area:
CVth CKp CW/W
Vth = Kp = K’ W/W =
WeffLeff WeffLeff WeffLeff
where CVth, CKp and CW/W are constants determined by measurement.
Values from a 0.35µm CMOS technology:
10.6mV·µm 8.25mV·µm
Vth,NMOS = Vth,PMOS =
WeffLeff WeffLeff
and
W 0.0056·µm W 0.0011·µm
  W NMOS =   W PMOS =
  WeffLeff   WeffLeff
The above results suggest that PMOS devices would be better matched than NMOS
devices in this technology.

Rules for Transistor Matching†

1.) Use identical finger geometries.
2.) Use large active areas.
3.) For voltage matching, keep VGS-VT, small ( i.e. 0.1V).
4.) For current matching, keep VGS-VT, large (i.e. 0.5V).
5.) Orient the transistors in the same direction.
6.) Place the transistors in close proximity to each other.
7.) Keep the layout of the matched transistors as compact as possible.
8.) Where practical use common centroid geometry layouts.
9.) Place dummy segments on the ends of arrayed transistors.
10.) Avoid using very short or narrow transistors.
11.) Place transistors in areas of low stress gradients.
12.) Do not place contacts on top of active gate area.
13.) Keep junctions of deep diffusions as far away from the active gate area as possible.
14.) Do not route metal across the active gate region.
15.) Place precisely matched transistors on the axes of symmetry of the die.
16.) Do not allow the buried layer shadow to intersect the active gate area.
17.) Connect gate fingers using metal connections.
SUMMARY
• IC technology offers poor absolute values but good relative values or matching
• In analog circuits, gains are determined by ratios (good matching) and time constants
are determined by products (poor matching)
• Electrical matching is determined in the electrical design phase
- Matching due to equal terminal voltages
- Matching due to process independent biasing
- Doubly correlated sampling
- Self-calibration techniques
- Dynamic element matching
• Physical matching is determined in the physical design phase
Lecture13 – Computer Models and Extraction of Simple Large Signal Model (6/14/14) Page 13-1
LECTURE 13 – COMPUTER MODELS AND EXTRACTION OF

THE SIMPLE LARGE SIGNAL MODEL
Outline
• Computer Models
• Extraction of a large signal model for hand calculations
• Extraction of the simple model for short channel MOSFETs
• Summary
Pages 90-96 and 662-685

COMPUTER MODELS
FET Model Generations
• First Generation – Physically based analytical model including all geometry
dependence.
• Second Generation – Model equations became subject to mathematical conditioning for
circuit simulation. Use of empirical relationships and parameter extraction.
• Third Generation – A return to simpler model structure with reduced number of
parameters which are physically based rather than empirical. Uses better methods of
mathematical conditioning for simulation including more specialized smoothing
functions.
Performance Comparison of Models (from Cheng and Hu, MOSFET Modeling & BSIM3
Users Guide)
Model Minimum Minimum Model iD Accuracy in iD Accuracy in Small signal Scalability
L (µm) Tox (nm) Continuity Strong Inversion Subthreshold parameter
MOS1 5 50 Poor Poor Not Modeled Poor Poor
MOS2 2 25 Poor Poor Poor Poor Fair
MOS3 1 20 Poor Fair Poor Poor Poor
BSIM1 0.8 15 Fair Good Fair Poor Fair
BSIM2 0.35 7.5 Fair Good Good Fair Fair
BSIM3v2 0.25 5 Fair Good Good Good Good
BSIM3v3 0.15 4 Good Good Good Good Good
First Generation Models

Level 1 (MOS1)
• Basic square law model based on the gradual channel approximation and the square law
for saturated drain current.
• Good for hand analysis.
• Needs improvement for deep-submicron technology (must incorporate the square law to
linear shift)
Level 2 (MOS2)
• First attempt to include small geometry effects
• Inclusion of the channel-bulk depletion charge results in the familiar 3/2 power terms
• Introduced a simple subthreshold model which was not continuous with the strong
inversion model.
• Model became quite complicated and probably is best known as a “developing ground”
for better modeling techniques.
Level 3 (MOS3)
• Used to overcome the limitations of Level 2. Made use of a semi-empirical approach.
• Added DIBL and the reduction of mobility by the lateral field.
• Similar to Level 2 but considerably more efficient.
• Used binning but was poorly implemented.
Second Generation Models

BSIM (Berkeley Short-Channel IGFET Model)
• Emphasis is on mathematical conditioning for circuit simulation
• Short channel models are mostly empirical and shifts the modeling to the parameter
extraction capability
• Introduced a more detailed subthreshold current model with good continuity
• Poor modeling of channel conductance
HSPICE Level 28
• Based on BSIM but has been extensively modified.
• More suitable for analog circuit design
• Uses model binning
• Model parameter set is almost entirely empirical
• User is locked into HSPICE
• Model is proprietary
BSIM2
• Closely based on BSIM
• Employs several expressions developed from two dimensional analysis
• Makes extensive modifications to the BSIM model for mobility and the drain current
• Uses a new subthreshold model
• Output conductance model makes the model very suitable for analog circuit design
Third Generation Models

BSIM2 – Continued
• The drain current model is more accurate and provides better convergence
• Becomes more complex with a large number of parameters
• No provisions for variations in the operating temperature
BSIM3
• This model has achieved stability and is being widely used in industry for deep
submicron technology.
• Initial focus of simplicity was not realized.
MOS Model 9
• Developed at Philips Laboratory
• Has extensive heritage of industrial use
• Model equations are clean and simple – should be efficient
Other Candidates
• EKV (Enz-Krummenacher-Vittoz) – fresh approach well suited to the needs of analog
circuit design

BSIM2 Model
Generic composite expression for the model parameters:
LX WX
X = Xo + +
Leff Weff
where
Xo = parameter for a given W and L
LX (WX) = first-order dependence of X on L (W)
Modeling features of BSIM2:
Mobility
• Mobility reduction by the vertical and the lateral field
Drain Current
• Velocity saturation
• Linear region drain current
• Saturation region drain current
• Subthreshold current
µoCoxWeff kT evGS-Vt-Voff  
iDS = · ·1 - eqVDS/kT
   
Leff  q  n
where
NB
Voff = VOF + VOFB ·vBS + VOFD ·vDS and n = NO + + ND ·vDS
PHI - vBS
BSIM2 Output Conductance Model

Rout Saturation
(DIBL) Substrate
Linear current
Region induced
(Triode) body
Drain effect
Channel current (SCBE)
length
modulation
(CLM)
0 vDS
0 vDS(sat) 5V
050829-01
• Drain-Induced Barrier Lowering (DIBL) – Lowering of the potential barrier at the

source-bulk junction allowing carriers to traverse the channel at a lower gate bias than
would otherwise be expected.
• Substrate Current-Induced Body Effect (SCBE) – The high field near the drain
accelerates carriers to high energies resulting in impact ionization which generates a
hole-electron pair (hot carrier generation). The opposite carriers are swept into the
substrate and have the effect of slightly forward-biasing the source-substrate junction.
This reduces the threshold voltage and increases the drain current.
Charge Model
• Eliminates the partitioning choice (50%/50% is used)
• BSIM charge model better documented with more options
BSIM3 Model
The background for the BSIM3 model and the equations are given in detail in the text
MOSFET Modeling & BSIM3 User’s Guide, by Y. Cheng and C. Hu, Kluwer Academic
Publishers, 1999.
The short channel effects included in the BSIM3 model are:
• Normal and reverse short-channel and narrow-width effects on the threshold.
• Channel length modulation (CLM).
• Drain induced barrier lowering (DIBL).
• Velocity saturation.
• Mobility degradation due to the vertical electric field.
• Impact ionization.
• Band-to-band tunneling.
• Velocity overshoot.
• Self-heating.
1.) Channel quantization.
2.) Polysilicon depletion.

BSIM3v3 Model Equations for Hand Calculations

In strong inversion, approximate hand equations are:
Weff 1  AbulkvDS
iDS = µeffCox L vGS -Vth - vDS , vDS < VDS(sat)
eff v DS  2 
1+ E L
sat eff
 vDS - VDS(sat)
iDS = WeffvsatCox[vGS – Vth – AbulkVDS(sat)]1+ , vDS > VDS(sat)
 V A 
where
EsatLeff(vGS-Vth)
VDS(sat) = A E L + (v -V )
bulk sat eff GS th
Leff = Ldrawn – 2L

Weff = Wdrawn – 2W
Esat = Electric field where the drift velocity (v) saturates
vsat = saturation velocity of carriers in the channel
µeff 2vsat
µ = 1+(E /E )  µeff = E
y sat sat
Note: Assume Abulk  1 and extract Vth and VA.

MOSIS Parametric Test Results

http://www.mosis.org/
RUN: T02D VENDOR: TSMC
TECHNOLOGY: SCN025 FEATURE SIZE: 0.25 microns
INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of
MOSIS test structures on each wafer of this fabrication lot. SPICE parameters obtained from similar
measurements on a selected wafer are also attached.
COMMENTS: TSMC 0251P5M.
TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS
MINIMUM 0.36/0.24
Vth 0.54 -0.50 volts
SHORT 20.0/0.24
Idss 557 -256 uA/um
Vpt 7.6 -7.2 volts
WIDE 20.0/0.24
Ids0 6.6 -1.5 pA/um
LARGE 50.0/50.0
Vjbkd 5.8 -7.0 volts
Ijlk -25.0 -1.1 pA
Gamma 0.44 0.61 V0.5
K’ (Uo*Cox/2) 112.0 -23.0 uA/V2
0.25µm BSIM3v3.1 NMOS Parameters

.MODEL CMOSN NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.7E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.4273342
+K1 = 0.3922983 K2 = 0.0185825 K3 = 1E-3
+K3B = 2.0947677 W0 = 2.171779E-7 NLX = 1.919758E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 7.137212E-3 DVT1 = 6.066487E-3 DVT2 = -0.3025397
+U0 = 403.1776038 UA = -3.60743E-12 UB = 1.323051E-18
+UC = 2.575123E-11 VSAT = 1.616298E5 A0 = 1.4626549
+AGS = 0.3136349 B0 = 3.080869E-8 B1 = -1E-7
+KETA = 5.462411E-3 A1 = 4.653219E-4 A2 = 0.6191129
+RDSW = 345.624986 PRWG = 0.3183394 PRWB = -0.1441065
+WR =1 WINT = 8.107812E-9 LINT = 3.375523E-9
+XL = 3E-8 XW = 0 DWG = 6.420502E-10
+DWB = 1.042094E-8 VOFF = -0.1083577 NFACTOR = 1.1884386
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 4.914545E-3 ETAB = 4.215338E-4
+DSUB = 0.0313287 PCLM = 1.2088426 PDIBLC1 = 0.7240447
+PDIBLC2 = 5.120303E-3 PDIBLCB = -0.0443076 DROUT = 0.7752992
+PSCBE1 = 4.451333E8 PSCBE2 = 5E-10 PVAG = 0.2068286
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL =0
+WLN = 1 WW = -1.22182E-16 WWN = 1.2127
+WWL = 0 LL = 0 LLN = 1
+LW = 0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 6.33E-10
+CGSO = 6.33E-10 CGBO = 1E-11 CJ = 1.766171E-3
+PB = 0.9577677 MJ = 0.4579102 CJSW = 3.931544E-10
+PBSW = 0.99 MJSW = 0.2722644 CF = 0
+PVTH0 = -2.126483E-3 PRDSW = -24.2435379 PK2 = -4.788094E-4
+WKETA = 1.430792E-3 LKETA = -6.548592E-3 )
0.25µm BSIM3v3.1 PMOS Parameters

MODEL CMOSP PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.7E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.6193382
+K1 = 0.5275326 K2 = 0.0281819 K3 = 0
+K3B = 11.249555 W0 = 1E-6 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 3.1920483 DVT1 = 0.4901788 DVT2 = -0.0295257
+U0 = 185.1288894 UA = 3.40616E-9 UB = 3.640498E-20
+UC = -6.35238E-11 VSAT = 1.975064E5 A0 = 0.4156696
+AGS = 0.0702036 B0 = 3.111154E-6 B1 = 5E-6
+KETA = 0.0253118 A1 = 2.421043E-4 A2 = 0.6754231
+RDSW = 866.896668 PRWG = 0.0362726 PRWB = -0.293946
+WR =1 WINT = 6.519911E-9 LINT = 2.210804E-8
+XL = 3E-8 XW = 0 DWG = -2.423118E-8
+DWB = 3.052612E-8 VOFF = -0.1161062 NFACTOR = 1.2546896
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.7241245 ETAB = -0.3675267
+DSUB = 1.1734643 PCLM = 1.0837457 PDIBLC1 = 9.608442E-4
+PDIBLC2 = 0.0176785 PDIBLCB = -9.605935E-4 DROUT = 0.0735541
+PSCBE1 = 1.579442E10 PSCBE2 = 6.707105E-9 PVAG = 0.0409261
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL =0
+WLN = 1 WW = 0 WWN = 1
+WWL = 0 LL = 0 LLN = 1
+LW = 0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 5.11E-10
+CGSO = 5.11E-10 CGBO = 1E-11 CJ = 1.882953E-3
+PB = 0.99 MJ = 0.4690946 CJSW = 3.018356E-10
+PBSW = 0.8137064 MJSW = 0.3299497 CF =0
+PVTH0 = 5.268963E-3 PRDSW = -2.2622317 PK2 = 3.952008E-3
+WKETA = -7.69819E-3 LKETA = -0.0119828 )
EXTRACTION OF A LARGE SIGNAL MODEL FOR HAND CALCULATIONS

Objective
Extract a simple model that is useful for design from the computer models such as
BSIM3.
Extraction for Short Channel Models
Procedure for extracting short channel models:
1.) Extract the square-law model parameters for a transistor with length at least 10
times Lmin.
2.) Using the values of K’, VT , , and  extract the model parameters for the following
model:
K’ W
iD = [ vGS – VT]2(1+vDS)
2[1 + (vGS-VT)] L
Adjust the values of K’, VT , and  as needed.

Illustration of the Extraction Procedure

EXTRACTION OF THE SIMPLE, SQUARE-LAW MODEL

Characterization of the Simple Square-Law Model
Equations for the MOSFET in strong inversion:
 Weff 
iD = K’2L (vGS - VT) 2(1 + vDS) (1)
 eff
 2 
Weff  v DS
iD = K’   (vGS - VT)vDS - (1 + vDS)
2 
(2)
 Leff  
where
VT = VT0 +  [ 2F + vSB − 2|F| ] (3)

Extraction of Model Parameters:

First assume that vDS is chosen such that the vDS term in Eq. (1) is much less than one
and vSB is zero, so that VT = VT0.
Therefore, Eq. (1) simplifies to
 Weff 
iD = K’  (vGS - VT0) 2 (4)
2Leff
This equation can be manipulated algebraically to obtain the following
1/2 K' Weff1/2 K' Weff1/2

iD = 2L  vGS -  2L  VT0 (5)
 eff   eff 
which has the form
y = mx + b (6)
This equation is easily recognized as the equation for a straight line with m as the slope
and b as the y-intercept. Comparing Eq. (5) to Eq. (6) gives
1/2
y = iD (7)
x = vGS (8)
K' Weff1/2 K' Weff1/2
m =  2L  and b = - 2L  VT0
 eff   eff 

Illustration of K’ and VT Extraction

1/2
(iD) Mobility degradation
region
vDS >VDSAT
Weak inversion
region
K’Weff 1/2
m = 2L
eff
0 vGS
0 VT0 (iD =0) 140909-08
K’Weff 1/2
b=- V T0 = -mVT0
2Leff
Comments:
• Stay away from the extreme regions of mobility degradation and weak inversion
• Use channel lengths greater than Lmin

Example 13-1 – Extraction of K’ and VT Using Linear Regression

Given the following transistor data shown in Table 1 and linear regression formulas
based on the form,
y = mx + b (11)
and
xi yi - ( xi yi)/n
m= 2 (12)
xi - (xi)2/n
1/2
determine VT0 and K’W/2L. The data in Table 1 also give ID as a function of VGS.
Table 1 Data for Example 13-1
VGS (V) ID (A) ID (A)1/2 VSB (V)

1.000 0.700 0.837 0.000
1.200 2.00 1.414 0.000
1.500 8.00 2.828 0.000
1.700 13.95 3.735 0.000
1.900 22.1 4.701 0.000

Example 13-1 – Continued

Solution
The data must be checked for linearity before linear regression is applied. Checking
slopes between data points is a simple numerical technique for determining linearity.
Using the formula that
y ID2 - ID1
Slope = m = =
x VGS2 - VGS1
Gives
1.414 - 0.837 2.828 - 1.414
m1 = = 2.885 m2 = = 4.713
0.2 0.3
3.735 - 2.828 4.701 - 3.735
m3 = = 4.535 m 4 = = 4.830
0.2 0.2
These results indicate that the first (lowest value of VGS) data point is either bad, or at a
point where the transistor is in weak inversion. This data point will not be included in
subsequent analysis. Performing the linear regression yields the following results.
K'Weff
VT0 = 0.898 V and = 21.92 µA/V2
2Leff

Extraction of the Bulk-Threshold Parameter 

Using the same techniques as before, the following equation
VT = VT0 +  [ 2F + vSB − 2F ]
is written in the linear form where
y = VT
x = 2F + vSB − 2F ()
m=
b = VT0
The term 2F is unknown but is normally in the range of 0.6 to 0.7 volts.
Procedure:
1.) Pick a value for 2F
2.) Extract a value for .
2si q NSUB
3.) Calculate NSUB using the relationship,  = Cox
kT NSUB
4.) Calculate F using the relationship, F = − q ln  n 
 i 
5.) Iterative procedures can be used to achieve the desired accuracy of  and 2F.
Generally, an approximate value for 2F gives adequate results.
Illustration of the Procedure for Extracting 

A plot of iD versus vGS for different values of vSB used to determine  is shown below.
1/2
(iD)
vGS
VT0 VT1 VT2 VT3
FigAppB-02
By plotting VT versus x of Eq. (13) one can measure the slope of the best fit line from
which the parameter  can be extracted. In order to do this, VT must be determined at
various values of vSB using the technique previously described.

Illustration of the Procedure for Extracting  - Continued

Each VT determined above must be plotted against the vSB term. The result is shown
below. The slope m, measured from the best fit line, is the parameter .

Example 13-2 – Extraction of the Bulk Threshold Parameter

Using the results from Ex. 13-1 and the following transistor data, determine the value of 
using linear regression techniques. Assume that 2F is 0.6 volts.
Table 2 Data for Example 13-2.
VSB (V) VGS (V) ID (A)
1.000 1.400 1.431
1.000 1.600 4.55
1.000 1.800 9.44
1.000 2.000 15.95
2.000 1.700 3.15
2.000 1.900 7.43
2.000 2.10 13.41
2.000 2.30 21.2
Solution
Table 2 shows data for VSB = 1 volt and VSB = 2 volts. A quick check of the data in this
table reveals that ID versus VGS is linear and thus may be used in the linear regression
analysis. Using the same procedure as in Ex. 1, the following thresholds are determined:
VT0 = 0.898 volts (from Ex. 1), VT = 1.143 volts (@VSB = 1 V), and VT = 1.322 V (@VSB =
2V). Table 3 gives the value of VT as a function of  2F + VSB − 2F for the three
values of VSB.
Example 13-2 - Continued

Table 3 Data for Example 13-2.
VSB (V) VT (V) [ 2F| + VSB - 2|F| ] (V1/2)

0.000 0.898 0.000
1.000 1.143 0.490
2.000 1.322 0.838
With these data, linear regression must be performed on the data of VT versus [(2F +
VSB)0.5 − (2F )0.5]. The regression parameters of Eq. (12) are
xiyi = 1.668
xiyi = 4.466
2
xi = 0.9423
(xi)2 = 1.764
These values give m = 0.506 = .

Extraction of the Channel Length Modulation Parameter, 

The channel length modulation parameter  should be determined for all device lengths
that might be used. For the sake of simplicity, Eq. (1) is rewritten as
iD = i'D=' vDS + i'D
which is in the familiar linear form where
y = iD (Eq. (1))
x = vDS
m = i'D
b = i'D (Eq. (1) with  = 0)
By plotting iD versus vDS, measuring the slope

of the data in the saturation region, and
dividing that value by the y-intercept,  can be
determined. The procedure is illustrated in the
figure shown.

EXTRACTION OF THE SIMPLE MODEL FOR SHORT CHANNEL MOSFETS

Extraction for Short Channel MOSFETS
The model proposed is the following one which is the square-law model modified by
the velocity saturation influence.
K’ W
iD = [ vGS - VT]2(1+vDS)
2[1 + (vGS-VT)] L
Using the values of K’, VT , , and  extracted previously, use an appropriate extraction
procedure to find the value of  adjusting the values of K’, VT , and  as needed.
Comments:
• We will assume that the bulk will be connected to the source or the standard
relationship between VT and VBS can be used.
• The saturation voltage is still given by
VDS( sat) = VGS - VT

Example of a Genetic Algorithm†

1.) To use this algorithm or any other, use the simulator and an appropriate short-channel
model (BSIM3) to generate a set of data for the transconductance (iD vs. vGS) and
output characteristics (iD vs. vDS) of the transistor with the desired W and L values.
2.) The best fit to the data is found using a genetic algorithm. The constraints on the
parameters are obtained from experience with prior transistor parameters and are:
10E-6 < < 610E-6, 1 <  < 5, 0 < VT < 1, and 0 <  < 0.5
3,) The details of the genetic algorithm are:
Gene structure is A = [  VT, fitness]. A mutation was done by varying all four
parameters. A weighted sum of the least square errors of the data curves was used as
the error function. The fitness of a gene was chosen as 1/error.
4.) The results for an extraction run of 8000 iterations for an NMOS transistor is shown
below.
(A/V2)  VT(V) (V-1)
294.1x10-6 1.4564 0.4190 0.1437
5.) The results for a NMOS and PMOS transistor are shown on the following pages.
† Anurag Kaplish, “Parameter Optimization of Deep Submicron MOSFETS Using a Genetic Algorithm,” May 4, 2000, Special Project Report,
School of ECE, Georgia Tech.
Extraction Results for an NMOS Transistor with W = 0.32µm and L = 0.18µm

Transconductance:

Extraction Results for an NMOS Transistor with W = 0.32µm and L = 0.18µm

Output:

Extraction Results for an PMOS Transistor with W = 0.32µm and L = 0.18µm

Transconductance:

Extraction Results for an PMOS Transistor with W = 0.32µm and L = 0.18µm

Output:

SUMMARY
• Models have greatly improved over time resulting in efficient computer simulation
• Output conductance model is greatly improved
• Narrow channel transistors have difficulty with modeling
• Can have discontinuities at bin boundaries
• The BSIM model is a complex model, widely used and difficult to understand in detail
• The simple large signal model can be extracted from any computer model
• Extract the model at the desired channel length for the design
• Short channel technology can be modeled by finding the  by any optimization routine

Lecture 14 – The MOS Switch and Diode (6/14/14) Page 14-1
LECTURE 14 – THE MOS SWITCH AND MOS DIODE

Outline
• MOSFET as a switch
• Influence of the switch resistance
• Influence of the switch capacitors
- Channel injection
- Clock feedthrough
• Using switches at reduced values of VDD
• MOS Diode
• Summary
Pages 115-128

Switch Model
• An ideal switch is a short-circuit when ON IAB
and an open-circuit when OFF. VC = A B RAB = 0W
(VC= high)
controlling terminal for the switch (VC high +
VAB
 switch ON, VC low  switch OFF) VC
RAB = ¥W
-
(VC= low)
060526-03
• Actual switch:
IOFF
ron = resistance of the switch when ON
rOFF
roff = resistance of the switch when OFF VOS
rON
VOS = offset voltage when the switch is ON A B
CAB
Ioff = offset current when the switch is OFF
CAC CBC
IA and IB are leakage currents to ground IA C IB
CA and CB are capacitances to ground CA

VC
CB
CAC and CBC = parasitic capacitors

060526-04
between the control terminal and switch
terminals

MOS Transistor as a Switch Bulk

A B A B
(S/D) (D/S)
060526-05 C (G)
On Characteristics of a MOS Switch
Assume operation in active region (vDS < vGS - VT) and vDS small.
µCoxW  vDS µCoxW
iD = L (vGS - VT) - 2 vDS  L (vGS - VT)vDS
 
vDS 1
Thus, RON ≈ i = µC W
D ox
L (vGS - VT)
OFF Characteristics of a MOS Switch
If vGS < VT, then iD = IOFF = 0 when vDS  0V.
If vDS > 0, then
1 1
ROFF ≈ = ≈∞
iD IOFF
MOS Switch Voltage Ranges

If a MOS switch is used to connect two circuits that can have analog signal that
vary from 0 to 1V, what must be the value of the bulk and gate voltages for the switch
to work properly? Bulk
(0 to 1V) (0 to 1V)
Circuit (S/D) (D/S) Circuit

1 2
Gate
Fig.4.1-3
• To insure that the bulk-source and bulk-drain pn junctions are reverse biased, the bulk
voltage must be less than the minimum analog signal for a NMOS switch.
• To insure that the switch is on, the gate voltage must be greater than the maximum
analog signal plus the threshold for a NMOS switch.
Therefore:
VBulk  0V
VGate(on) > 1V + VT
VGate(off)  0V
Unfortunately, the large value of reverse bias bulk voltage causes the threshold voltage
to increase.
Current-Voltage Characteristics of a NMOS Switch

The following simulated output characteristics correspond to triode operation of the
MOSFET.
100mA
VGS=3.0V
VGS=3.5V VGS=2.5V
VGS=4.0V
50mA VGS=4.5V
VGS=5.0V VGS=2.0V
iD 0mA VGS=1.5V
VGS=1.0V
-50mA
-100mA
-1V -0.5V 0V 0.5V 1V
vDS Fig. 4.1-4
SPICE Input File: VGS 2 0 DC 0.0

VBS 3 0 DC -5.0
MOS Switch On Characteristics .DC VDS -1 1 0.1 VGS 1 5 0.5
M1 1 2 0 3 MNMOS W=1U L=1U .PRINT DC ID(M1)
.MODEL MNMOS NMOS VTO=0.7, KP=110U, .PROBE
+LAMBDA=0.04, GAMMA=0.4 PHI=0.7 .END
VDS 1 0 DC 0.0

MOS Switch ON Resistance as a Function of Gate-Source Voltage
SPICE Input File: +LAMBDA=0.04, GAMMA=0.4, PHI=0.7

VDS 1 0 DC 0.001V
MOS Switch On Resistance as a f(W/L) VGS 2 0 DC 0.0
M1 1 2 0 0 MNMOS W=1U L=1U .DC VGS 1 5 0.1
M2 1 2 0 0 MNMOS W=5U L=1U .PRINT DC ID(M1) ID(M2) ID(M3) ID(M4)
M3 1 2 0 0 MNMOS W=10U L=1U .PROBE
M4 1 2 0 0 MNMOS W=50U L=1U .END
.MODEL MNMOS NMOS VTO=0.7, KP=110U,

Influence of the ON Resistance on MOS Switches

Finite ON Resistance:
Example
Initially assume the capacitor is uncharged. If VGate(ON) is 5V and is high for 0.1µs,
find the W/L of the MOSFET switch that will charge a capacitance of 10pF in five
time constants.
Solution
The time constant must be 100ns/5 = 20ns. Therefore RON must be less than
20ns/10pF = 2k. The ON resistance of the MOSFET (for small vDS) is
1 W 1 1
RON = K ’(W/L)(V -V )  L = R ·K ’(V -V ) =
N GS T ON N GS T 2k·110µA/V2·4.3
=1.06
Comments:
• It is relatively easy to charge on-chip capacitors with minimum size switches.

• Switch resistance is really not constant during switching and the problem is more
complex than above.

Including the Influence of the Varying On Resistance

Gate-source Constant
K’W 
gON(t) = L (vGS(t)-VT) -0.5vDS(t)
1 gON(0) + gON(∞)
gON(aver.) = r ≈
ON(aver.) 2
K’W K’WVDS(0) K’W
= 2L (VGS-VT) - + 2L (VGS-VT)
4L
K’W K’WVDS(0)
= (VGS-VT) -
L 4L
Gate-source Varying
K’W K’WVDS(0) K’W

gON = 2L [VGS(0)-VT] - + 2L [VGS(∞)-VT]
4L
Example 14-1 - Switch ON Resistance

Assume that at t = 0, the gate of the switch shown is
taken to 5V. Design the W/L value of the switch to
discharge the C1 capacitor to within 1% of its initial charge
in 10ns. Use the MOSFET parameters of Table 3.1-2.
Solution
Note that the source of the NMOS is on the right and is always at ground potential
so there is no bulk effect as long as the voltage across C1 is positive. The voltage
across C1 can be expressed as
 -t 
vC1(t) = 5exp 
RONC1
At 10ns, vC1 is 5/100 or 0.05V. Therefore,
 -10-8   -103  ln(100)
0.05=5exp -11 = 5exp   exp(G ON 103 )=100  G ON = 3 =0.0046S
RON10  R
 ON 10
K’W K’WVDS(0)  110x10-6·5W W
 0.0046 = L (VGS-VT) - = 110x10 ·4.3-
-6  = 356x10-6
4L  4 L L
W 0.0046
Thus, L = = 13.71  14
356x10-6
Influence of the OFF State on MOS Switches

The OFF state influence is primarily in any current that flows from the terminals of the
switch to ground.
An example might be:
Typically, no problems occur unless capacitance voltages are held for a long time. For
example,
vout(t) = vCH e-t/(RBulkCH)
If RBulk  109 and CH = 10pF, the time constant is 109·10-11 = 0.01seconds

Influence of Parasitic Capacitances

The parasitic capacitors have two influences:
• Parasitics to ground at the switch terminals (CBD and CBS) add to the value of the
desired capacitors.
This problem is solved by the use of stray-insensitive switched capacitor circuits
• Parasitics from gate to source and drain cause charge injection and clock feedthrough
onto or off the desired capacitors.
This problem can be minimized but not eliminated.
Model for studying gate capacitance:

Channel Charge Injection

Consider the simple switch configuration shown: ON
Clk
OFF OFF
When the switch is ON, a charge is stored in the vin CL

channel which is equal to,
060613-03
Qch = -WLCox(VH-vin-VT)
where VH is the value of the clock waveform when the switch is on (VH ≈ VDD)
When the switch turns OFF, this charge is injected ON
into the source and drain terminals as shown. Clk
vin
Assuming the charge splits evenly, then the change of OFF DV
voltage across the capacitor, CL, is
vin e- e-
CL
Qch -WLCox(VH-vin-VT)
V = 2C = 2CL 060613-04
L
The charge injection does not influence vin because it is a voltage source.

Clock Feedthrough
In addition to the charge injection, the overlap capacitors of the MOSFET couple the
turning off part of the clock to the load capacitor. This is called clock feedthrough.
The model for this case is given as:
The gate decrease from B to C is modeled as a negative step of magnitude VS +VT - VL.
The output voltage on the capacitor after opening the switch is,
 CL   COL   COL  COL
vCL = C +C VS-C +C VT -(VS+VT -VL)C +C  ≈ VS-(VS+2VT -VL) C 
 OL L  OL L  OL L  L
if COL < CL.
Therefore the error voltage is,
COL COL
Verror ≈ -(VS + 2VT – VL) C  = -(vin + 2VT – VL)  C 
 L  L
Modeling the Influence of Charge Injection and Clock Feedthrough

The influence of charge injection and clock feedthrough on a switch is a complex
analysis which is better suited for computer analysis. Here we will attempt to develop
an understanding sufficient to show ways of reducing these effects.
To begin the model development, there are two cases of charge injection depending
upon the transition rate when the switch turns off.
1.) Slow transition time – the charge in the channel can react instantaneously to changes
in the turning-off, gate-source voltage.
2.) Fast transition time – the charge in the channel cannot react fast enough to respond
to the changes in the turning-off, gate-source voltage.

Slow Transition Time

Consider the following switch circuit:
A A
Switch ON
B vin+VT B vin+VT
Switch OFF
C C
Charge
injection
vin CL vin CL
Fig. 4.1-13
1.) During the on-to-off transition time from A to B, the charge injection is absorbed by
the low impedance source, vin.
2.) The switch turns off when the gate voltage is vin+VT (point B).
3.) From B to C the switch is off but the gate voltage is changing. As a result charge
injection occurs to CL.

Fast Transition Time

For the fast transition time, the rate of transition is faster than the channel time constant
so that some of the charge during the region from point A to point B is injected onto CL
even though the transistor switch has not yet turned off.
A A
Switch ON
B vin+VT B vin+VT
Switch OFF
C C
Charge Charge
injection injection
vin CL vin CL
Fig. 4.1-14

A Quantized Model of Charge Injection/Clock Feedthrough†

Approximate the gate transition as a staircase and discretized in voltage as follows:
Voltage Voltage
Discretized Gate Voltage

Discretized Gate Voltage
vGATE vGATE
Charge
vin+VT vin+VT injection
vin vin due to fast
vCL vCL transition
t t
Slow Transition Fast Transition Fig 4.1-15
The time constant of the channel, Rchannel·Cchannel, determines whether or not the
capacitance, CL, fully charges during each voltage step.
†B.J. Sheu and C. Hu, “Switched-Induced Error Voltage on A Switched Capacitor,” IEEE J. Solid-State Circuits, Vol. SC-19, No. 4, pp. 519-
525, August 1984.
Analytical Expressions to Approximate Charge Injection/Clock Feedthrough

Assume the gate voltage is making a transition from high, VH, to low, VL.
 vGate = vG(t) = VH – Ut where U = magnitude of the slope of vG(t)
K’W
Define VHT = VH - VS - VT and  = L .
The error in voltage across CL, Verror, is given below in two terms. The first term
corresponds to the feedthrough that occurs while the switch is still on and the second
term corresponds to feedthrough when the switch is off.
2
VHT
1.) Slow transition occurs when 2C >> U.
L
W·CGD0 + Cchannel
2 UCL W·CGD0
Verror = -  - (VS+2VT -VL)
 CL  2 CL
2
VHT
2.) Fast transition occurs when 2C << U.
L

W·CGD0 + Cchannel  3 
 2    VHT  W·CGD0
Verror = -  VHT - 6U·C  - C (VS+2VT -VL)
 CL  L L

Example 14-2 - Calculation of Charge Feedthrough Error

vG
Calculate the effect of charge feedthrough on the previous
5V
circuit where VS = 1V, CL = 1pfF, W/L = 0.8µm/0.8µm, and
Case 2
VG is given below for the two cases. Use model parameters Case 1
from Tables 3.1-2 and 3.2-1. Neglect L and W effects. 0V t
0.2ns 50ns
Solution 120512-01
Case 1:
The value of U is equal to 5V/0.2nS or 25x109. Next we must test to see if the
slow or fast transition time is appropriate. First calculate the value of VT as
VT = VT0 +  2|F| -VBS -  2|F| = 0.7 + 0.4 0.7+1 - 0.4 0.7 = 0.887V
Therefore,
2
VHT 110x10-6·3.1132
VHT =VH-VS-VT = 5-1-0.887=3.113V  2C = = 5.32x10 8< 25x109
L 2·1pF
which corresponds to the fast transition case. Using the previous expression gives,
Verror =
176x10-18+0.5(1.58x10-15) 3.32x10-3 176x10-18
- 3.113- - (1+1.774-0) = -3.39mV
 1x10 -12  30x10  1x10
-3 -12


Case 2:
In this case U is equal to 5V/50ns or 1x108 which means that the slow transition
case is valid (1x108 < 5.32x108).
Using the previous expression gives,
176x10-18+0.5(1.58x10-15) 314x10-6 176x10-18
Verror = -  - (1+1.774-0)
 1x10 -12  220x10  1x10-12
-6
= -1.64mV
Comment:
These results are not expected to give precise answers regarding the amount of
charge feedthrough one should expect in an actual circuit. Rather, they are a guide to
understand the effects of various circuit elements and terminal conditions in order to
minimize unwanted behavior by design techniques.

Solutions to Charge Injection

1.) Use minimum size switches to reduce the overlap capacitances and/or increaseCL.
2.) Use a dummy compensating transistor.
• Requires complementary clocks

• Complete cancellation is difficult and may in fact may make the feedthrough
worse
3.) Use complementary switches (transmission gates)
4.) Use differential implementation of switched capacitor circuits (probably the best
solution)

Input-Dependent Charge Injection

Examination of the error voltage reveals that,
Error voltage = Component independent of input + Component dependent on input
This only occurs for switches that are floating and is due to the fact that the input
influences the voltage at which the transistor switches (vin  VS  VD). Leads to
spurious responses and other undesired results.
Solution:
Use delayed clocks to remove
the input dependence by
removing the path for injection
from the floating switches.
Assume that Cs is charged to Vin
(both 1 and 1d are high):
1.) 1 opens, no input-
dependent feedthrough because switch terminals (S3) are at ground potential.
2.) 1d opens, no feedthrough occurs because there is no current path (except through
small parasitic capacitors).

CMOS Switches (Transmission Gate)

Clock
Clock
A B A B
VDD
Clock
Clock Fig. 4.1-21
Advantages:
• Feedthrough somewhat diminished
• Larger dynamic range
• Lower ON resistance
Disadvantages:
• Requires a complementary clock
• Requires more area

Example 14-3 - Charge Injection for a CMOS Switch

Calculate the effect of charge feedthrough on the 5V
circuit shown below. Assume that U = 5V/50ns = vin-|VTP|
108V/s, vin = 2.5V and ignore the bulk effect. Use 0.8mm M2 0V
0.8mm
the model parameters from Tables 3.1-2 and 3.2-1. CL = +
vin 0.8mm M1 1pF vCL
Solution 0.8mm 5V
-
First we must identify the transition behavior. For
vin+VTN
the NMOS transistor we have 0V Fig. 4.1-18
2
NVHTN 110x10-6·(5-2.5-0.7)2
= = 1.78x10 8
2CL 2·10-12
For the PMOS transistor, noting that
VHTP = VS - |VTP| - VL = 2.5-0.7-0 = 1.8
2
PVHTP 50x10-6·(1.8)2
we have 2C = -12 = 8.10x107 . Thus, the NMOS transistor is in the
L 2·10
slow transition and the PMOS transistor is in the fast transition regimes.


Error due to NMOS (slow transition):

176x10-18+0.5(1.58x10-15)
 ·108·10-12 176x10-18
Verror(NMOS) = -   - (2.5+1.4-0)
10-12
  2·110x10-6 10-12
= -1.840mV
Error due to PMOS (fast transition):
176x10-18+0.5(1.58x10-15) 50x10-6(1.8)3 176x10-18

Verror(PMOS)= 1.8- + (5+1.4-2.5)
 10-12  6·108·10-12  10-12
= 1.956mV
Net error voltage due to charge injection is 116µV. This will vary with VS.

Dynamic Range of the CMOS Switch

The switch dynamic range is the
range of voltages at the switch
terminals (VAVB=VA,B) over
which the ON resistance is small.
VDD
M1
A B
VDD
VA,B 1mA
M2
Fig. 4.1-22
Spice File:
Simulation CMOS transmission switch resistance VDD 3 0
M1 1 3 2 0 MNMOS L=1U W=10U VAB 1 0
M2 1 0 2 3 MPMOS L=1U W=10U IA 2 0 DC 1U
.MODEL MNMOS NMOS VTO=0.7, KP=110U, .DC VAB 0 3 0.02 VDD 1 3 0.5
+LAMBDA=0.04, GAMMA=0.4, PHI=0.7 .PRINT DC V(1,2)
.MODEL MPMOS PMOS VTO=-0.7, KP=50U, .END
+ LAMBDA=0.05, GAMMA=0.5, PHI=0.8
Result:
Low ON resistance over a wide voltage range is difficult as the power supply decreases.
Charge Pumps for Switches with Low Power Supply Voltages

As power supply voltages decrease below 2V, it becomes difficult to keep the
switch on at a low value of on-resistance over the range of the power supply. The result
is that rON becomes a function of the signal amplitude and produces harmonics.
Consequently, charge pumps are used to provide a gate voltage above power supply.
Principle of a charge pump:
To another
≈2VDD VDD charge pump
to avoid latchup
VDD M1 vOUT ≈2VDD
+ +
C1 V VDD C2
_ DD _
vIN + CL Single
VDD NMOS
vIN VDD 0
Switch
0 _
t 0 120624-04
C2
vOUT = 2VDD C + C + C
2 L NMOSswitch

Simulation of the Charge Pump Circuit†

Circuit:
VDD
CLK_out M1 M2 CLK_out
M5 M3
C1 C1
M6 M4
CLK_in
VSS Fig. 4.1-23
Simulation:
3.0
Output
2.0
Input
Volts
1.0
0.0
-1.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
Time (ms) Fig. 4.1-24
†T.B. Cho and R.R. Gray, “A 10b, 20 Msample/s, 35mW Pipeline A/D Converter,” IEEE J. of Solid-State Circuits, Vol. 30, No. 3m March 1995,
pp. 166-172.
Bootstrapped Switches with High Reliability†

In the previous charge pump switch driver, the amount of gate-source drive
depends upon the input signal and can easily cause reliability problems because it
becomes too large for low values of input
VDD
signal.
The solution to this problem is a →
bootstrapped switch as shown.
Actual bootstrap switch: OFF ON Fig. 4.1-25
 low: M7 and M10 make vg=0 and C3 charges to VDD,  high: C3 connected to vGS11.
M7 reduces the vDS and vGS of M10 when  = 0. M13 ensures that vGS8 ≤ VDD.
The parasitics at the source of M11 require this node to be driven from a low impedance.
†A.M. Abo and P.R. Gray, “A 1.5V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, IEEE J. of Solid-State Circuits, Vol. 34,
No. 5, May 1999, pp. 599-605.
MOSFET DIODE
MOS Diode
When the MOSFET has the gate connected to the drain, it acts like a diode with
characteristics similar to a pn-junction diode.
i
+ +
i
vSG = v
vGS = v
i
- -
v
VT Fig. 4-2-1
Note that when the gate is connected to the drain of an enhancement MOSFET, the
MOSFET is always in the saturation region.
vDS  vGS - VT  vD - vS  vG - vS - VT  vD - vG  -VT  vDG  -VT
Since VT is always greater than zero for an enhancement device, then vDG = 0 satisfies
the conditions for saturation.
• Works for NMOS or PMOS
• Note that the drain could be VT less than the gate and still be in saturation

How Does the MOS Diode Compare with a pn Diode?

The comparison is basically the difference between an exponential and a square-law
function. However, if the designer is willing to spend W/L, the comparison becomes
more interesting as shown below.
If the threshold voltage is less than 0.4V, the MOS diode can provide more current for
the same voltage than a pn junction diode even for modest W/L ratios. However, at the
same value of current, the pn junction always has a larger transconductance.

SUMMARY
• Symmetrical switching characteristics
• High OFF resistance
• Moderate ON resistance (OK for most applications)
• Clock feedthrough is proportional to size of switch (W) and inversely proportional
to switching capacitors.
• Output offset due to clock feedthrough has 2 components:
Input dependent
Input independent
• Complementary switches help increase dynamic range.
• Fully differential operation should minimize the clock feedthrough.
• As power supply reduces, floating switches become more difficult to fully turn on.
• Switches contribute a kT/C noise which can get folded back into the baseband.
• The gate-drain connected MOSFET can make a good diode realization

Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-1
LECTURE 15 – RESISTOR IMPLEMENTATIONS AND

CURRENT SINKS AND SOURCES
Outline
• Resistor implementations
• Simple current sinks and sources
• Improved performance current sinks and sources
• Summary
Pages 128-138

RESISTOR IMPLEMENTATION USING MOSFETS

Real Resistors versus MOSFET Resistors
• Smaller in area than actual resistors
• Can pass a large current through a large resistance without a large voltage drop
iD
MOSFET (rds = 100kW)
100µA
100kW Resistor
10µA vDS
1V 10V 060526-10
vds 1
AC resistance = =
id gds
where

gds  2 (VGS-VT)2 = ID

MOS Diode as a Resistor

AC and DC resistance:
VDS VT 2
DC resistance = I = I +
D D  ID
Small-Signal Load (AC resistance):

D=G D=G
id
G
+ +D
vgs gmvgs rds vds
- -
S S
S S 120522-01
vds 1 1
AC resistance = i = g + g  g
d m ds m
where
gm = (VGS-VT) = 2ID
Use of the MOSFET to Implement a Floating Resistor

In many applications, it is useful to implement a VBias
resistance using a MOSFET. First, consider the RAB
A B A B
simple, single MOSFET implementation.
L Fig. 4.2-9
RAB = K’W(V - V )
GS T
100mA
VGS=10V
VGS=9V
60mA
VGS=8V
VGS=7V
20mA
VGS=2V
-20mA
VGS=3V
VGS=4V
-60mA
VGS=5V
VGS=6V
-100mA
-1V -0.6V -0.2V 0.2V 0.6V 1V Fig. 4.2-95
Cancellation of Second-Order Voltage Dependence – Parallel MOSFETs

Circuit:
M1
iAB VC VC iAB
A B A RAB B
M2
+ - + -
vAB
vAB 060526-12
Assume both devices are non-saturated

 vAB2

iD1 = ß1 (vAB + VC - VT)vAB - 2 
 
 vAB2

iD2 = ß2 (VC - VT)vAB - 2 
 
 vAB2 vAB2

iAB = iD1 + iD2 = ß v  AB2 + (VC - VT)vAB - 2 + (VC - VT)vAB - 2 
 
1
iAB = 2ß(VC - VT)vAB  RAB = 2ß(V - V )
C T

Parallel MOSFET Performance

Voltage-Current Characteristic:
SPICE Input File:

NMOS parallel transistor realization VDS 10 0
M1 2 1 0 5 MNMOS W=15U L=3U VSS 5 0 DC -5
M2 2 4 0 5 MNMOS W=15U L=3U .DC VDS -2.0 2.0 .2 VC 3 7 1
.MODEL MNMOS NMOS VTO=0.75, KP=25U, +LAMBDA=0.01, .PRINT DC I(VSENSE)
GAMMA=0.8 PHI=0.6 .PROBE
VC 1 2 .END
E1 4 0 1 2 1.0
VSENSE 10 2 DC 0

SIMPLE CURRENT SINKS AND SOURCES

Ideal Current Sinks and Sources
What is an ideal current sink or source?
i
Io
i +
Io v
- v
060527-01
• Current is fixed at a value of Io

• Voltage can be any value from +∞ to -∞
• Be careful when using a current sink or source to replace a MOSFET sink/source in
simulation

Characterization of MOSFET Sinks and Sources

A sink/source is characterized by two quantities:
• rout - a measure of the “flatness” of the current sink/source (its independence of
voltage)
• VMIN - the min. across the sink or source for which the current is no longer constant
NMOS Current Sink:
VDD VDD iDS= i
VMIN
VGG
Io
i Slope = 1/rout
i +
+ v
Io v -
VGG
- vDS = v
0
0 VGG-VT0 VDD
0601527-02
1 1+VDS 1
rout = di /dv =  ≈ and VMIN = VDS(sat) = VGS - VT0 = VGG - VT0
D DS D  ID
Note: The NMOS current sink can only have positive values of v.

PMOS Current Source

VDD VDD iSD= i
VMIN
+ VGG
Io v VGG +
- v Io
- Slope = 1/rout
i i
0 vSD = v
0 VGG-|VT0| VDD
0601527-03

Gate-Source Voltage Components

It is important to note that the gate-source voltage consists of two parts as illustrated
below:
iD
10W/L W/L 0.1W/L
ID
Enhance Provide
Channel Current
0 vGS
0 VT VGS Fig. 280-03
VGS = VT0 + VON = Part to enhance the channel + Part to cause current flow
where
VON = VDS(sat) = VGS - VT0
2ID
 VMIN = VON = VDS(sat) = for the simple current sink.
K’(W/L)
Note that VMIN can be reduced by using large values of W/L.

Simulation of a Simple MOS Current Sink

120
100
Slope = 1/Rout
80
iOUT (mA) iOUT
10mm
60 1mm +
VGS1 = vOUT
40 -
1.126V
20
Vmin
0
0 1 2 3 4 5
vOUT (Volts)
Comments:
VMIN is too large - desire VMIN to approach zero, at least approach VCE(sat)
Slope too high - desire the characteristic to be flat implying very large output
resistance
(KN’ = 110µA/V2, VT = 0.7Vand  = 0.04V-1)  rds = 250k
How is VGG Implemented?

The only voltage source assumed available is VDD.
Therefore, VGG, can be implemented in many ways with the example below being one
way.
VDD VDD
Current
VDD
R
R
IBias i i
IBias + +
+ v v
VBias=VGG - VGG -
-
VBias=VGG VDD Volts 140903-01
Better and more stable implementations of VGG will be shown later.

IMPROVED PERFORMANCE CURRENT SINKS

Improving the Performance of the Simple NMOS Current Sink
The simple NMOS current sink shown previously had two problems.
1.) The value of VMIN may be too large.
2.) The output resistance (250k) was too small.
How can the designer solve these problems?
1.) The first problem can be solved by increasing the W/L value of the NMOS
transistor.
2ID
VMIN = VON = VDS(sat) = K’(W/L)
In the simulation shown previously,
2·100µA
VMIN = = 0.426V
110µA/V2·10
We could decrease this to 0.1V with a W/L = 182.
2.) How can the small output resistance be increased? Answer is feedback.

Blackman’s Formula for Finding the Resistance at a Port with Feedback†

Blackman’s formula to find the resistance at a port X, is
based on the following circuit:
The resistance seen looking into port X is given as,

1 + RR(port shorted)
Rx = Rx(k=0) 1 + RR(port opened)
 
The return ratio, RR, is found by changing the dependent

source to an independent source as shown:
Therefore, the return ratio is defined as,
vc ic
RR = - v ' = - i '
c c
The key is to find a feedback circuit that when we calculate the RR, it is non-zero when
port X is shorted and zero when port X is opened. In this case, the resistance at port X
is
Rx = Rx(k=0)[1 + RR(port shorted)]
†
R.B. Blackman, “Effect of Feedback on Impedance,” Bell Sys. Tech.J., Vol. 23, pp. 269-277, October 1943.
How to find the Proper Type of Feedback

For the port X, the circuit variables associated with the input port should be able to be
expressed as,
Input Variable to Port X = Signal variable to the circuit – Feedback variable
where the variables can be voltage or current.
1.) Series feedback (variables are voltage):
RR(Vx = 0) ≠ 0
RR(Ix = 0) = 0 (Vin is disconnected
from Vfb)
2.) Shunt feedback (variables are current):
RR(Vx = 0) = 0(Iin is disconnected
from Ifb)
RR(Ix = 0) ≠ 0
We see that for series feedback RR(port opened) will be zero and for shunt feedback
that RR(port shorted) will be zero.
Therefore, to boost the resistance at port X select series feedback!

Increasing the Output Resistance of the Simple Current Sink

Choosing series feedback, we select the following circuit to boost
the output resistance of the simple current sink:
Assume that we can neglect the bulk effect and find the input
resistance by 1.) small-signal analysis and 2.) return ratio method.
1.) Small-signal Analysis:
vx = (ix + gmvs)rds + ixR
vx = (ix + gmixR)rds + ixR = ix(rds + R + gmrdsR)
vx
 Rx = = rds + R + gmrdsR ≈ gmrdsR
ix
2.) Return Ratio:
Rx(k=0) = Rx(gm=0) = rds + R
vc  rdsR 
RR(vx = 0) = -v ' = gm  r +R
c  ds 
RR(ix = 0) = 0
  rdsR 
 Rx = (rds + R)1 + gm r +R = rds + R + gmrdsR ≈ gmrdsR
  ds 
Cascode Current Sink iout

iOUT
+
Replacing R with the simple M2 + gm2vgs2 gmbs2vbs2 rds2
current sink leads to a practical
M1 vOUT vout
implementation shown as: VGG2 +
VGG1 gm1vgs1 rds1 vs2
- - -
vgs1 =vg2 = vb2 = 0
Small signal output resistance: Fig. 280-11
Noting that vgs1 = vg2 = vb2 = 0 and writing a loop equation we get,
vout = (iout - gm2vgs2 - gmbs2vbs2)rds2 + rds1iout
However,
vgs2 = 0 - vs2 = -ioutrds1 and vbs2 = 0 - vs2 = -ioutrds1
Therefore,
vout = iout[rds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2]
or
vout
rout = i = rds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2  gm2rds1rds2
out
A general principle is beginning to emerge:

The output resistance of a cascode circuit  R x (Common source voltage gain of the
cascoding transistor)

Design of VGG1 and VGG2
M2 +
+ VDS2 ≥VDS2(sat)
VGS2 - vOUT(min) = VDS1(sat)+VDS2(sat)
- +
VGG2
VDS1= VDS1(sat)
VGG1 -
060527-06
1.) VGG1 is selected to provide the desired current. M1 is assumed to be in saturation.

2.) VGG2 is selected to keep VDS1 as small as possible and still be in saturation.
VGG2 = VDS1(sat) + VGS2 = VDS1(sat) + VT + VDS2(sat)
If W1/L1 = W2/L2, then VGG2 = 2VDS(sat) + VT = 2VON + VT
Thus, for the previous NMOS current sink, VGG2 would be equal to,
VGG2 = 2(0.426) + 0.7 = 1.552V

Simulation of the Cascode CMOS Current Sink

Example 120
Slope = 1/Rout
Use the model parameters 100
KN’=110µA/V2, VT = 0.7 and N =
80 All W/Ls are iOUT
0.04V-1 to calculate (a) the small-
iOUT (mA)
10mm/1mm +
signal output resistance for the simple 60 VGG2 =
current sink if IOUT = 100µA and (b) 1.552V vOUT
the small-signal output resistance for 40
the cascode current sink with IOUT = VGG1 =
-
20 1.126V
100µA. Assume that all W/L values Vmin
are 1. 0
0 1 2 3 4 5
vOUT (Volts) Fig. 280-12
Solution
(a) Using  = 0.04 V-1 and IOUT = 100µA gives rds1 = 250k = rds2. (b) Ignoring the
bulk effect, we find that gm1 = gm2 = 469µS which gives rout =
(250k)(469µS)(250k) = 29.32M.

High-Swing Cascode Current Sink

This current sink achieves the smallest possible VMIN.
Since VDD VDD
2ID
VON = iOUT iOUT
K’(W/L) M2 + VMIN
M4 +
1/1 VON
then if L/W of M4 is 1/4 + +
VT+VON -
quadrupled, VON is VT+2VON M3 - vOUT
M1 +
doubled to get 1/1 + VON
-
VT+VON 1/1 -
VMIN = 2VON. - -
0 2VON vOUT
Example 060527-07
Use the cascode current sink configuration above to design a current sink of 100µA and
a VMIN = 1V. Assume the device parameters of Table 3.1-2.
Solution
With VMIN = 1V, choose VON = 0.5V. Assuming M1 and M2 are identical gives
W 2·IOUT 2·100x10-6 W1 W2 W3 W4
= = = 7.27  L = L = L = 7.27 and L = 1.82
L K’·VON2 110x10-6x0.25 1 2 3 4
Unfortunately, the drain voltages of M1 and M3 are not matched.
Improved High-Swing Cascode Current Sink

Because the drain-source voltages of the VDD VDD
matching transistors, M1 and M3 are not
equal, iOUT ≠ IREF. R1 R2
iOUT
+ +
M4 M5 M2 +
VT 1/1 VON
To circumvent this problem the cascode 1/4 + 1/1 +
- VT+VON -
current sink shown is utilized: + M3 - + vOUT
VT+2VON M1
VON + VON
Note that the drain-source voltage of M1 and 1/1 VT+VON 1/1
- - - - --
M3 are identical causing iOUT to be a
060527-08
replication of IREF.
Design Procedure
1.) Since VMIN = 2VON = 2VDS(sat), let VON = 0.5VMIN.
2IREF W1 W2 W3 W5 2IREF 8IREF
2.) VON = 
K’(W/L) L1 = L2 = L3 = L5 = K’VON2 = K’VMIN2
W4 2IREF 2IREF IREF
3.) = = =
L4 K’(VGS4-VT)2 K’(2VON)2 2K’VON2

Signal Flow in Transistors

The last example brings up an interesting and important point. This point is
illustrated by the following question, “How does IREF flow into the M3-M5
combination of transistors since there is no path to the gate of M5?”
Consider how signals flow in transistors:
Output Only Output Only
D C
- + - +
+ +
Input Input
Only G Only B
+ +
+ + + + VDD
S E
Fig. 4.3-12B
IREF
Answer to the above question:
As VDD increases (i.e. the circuit begins to operate),
M5
IREF cannot flow into the drain of M5, so it flows through
the path indicated by the arrow to the gate of M3. It M3 VT +2VON
charges the stray capacitance and causes the gate-source +
voltage of M3 to increase to the exact value necessary to VGS3
-
cause IREF to flow through the M3-M5 combination. Fig. 4.3-12A
Example 15-1 - Design of a Minimum VMIN Current Sink

Assume IREF = 100µA and design a cascode current sink with a VMIN = 0.3V using the
following parameters: VTO=0.7, KP=110U, LAMBDA=0.04, GAMMA=0.4, PHI=0.7
Solution
From the previous equations, we get
W1 W2 W3 W5 8IREF 8·100
L1 = L2 = L3 = L5 = K’VMIN 2 = 110·(0.3V)2 = 80.8 and
W4 IREF 100
L4 2K’VON 2 2·110·0.152 = 20.2
= =
120
Simulation Results: 100

Low Vmin Cascade Current Sink - Method No. 2
M1 5 1 0 0 MNMOS W=81U L=1U
M2 2 3 5 5 MNMOS W=81U L=1U
80
M3 4 1 0 0 MNMOS W=81U L=1U iOUT(mA)
M4 3 3 0 0 MNMOS W=20U L=1U 60
M5 1 3 4 4 MNMOS W=81U L=1U
.MODEL MNMOS NMOS VTO=0.7 KP=110U
+LAMBDA=0.04 GAMMA=0.4 PHI=0.7 40
VDD 6 0 DC 5V
IIN1 6 1 DC 100U
IIN2 6 3 DC 100U 20
VOUT 2 0 DC 5.0 VMIN
.OP
.DC VOUT 5 0 0.05 0
.PRINT DC ID(M2) 0 1 2 3 4 5
.END vOUT(V) Fig. 290-06

Self-Biased Cascode Current Sink†

The VT + 2VON bias voltage is developed through a series VDD
resistor.
IREF
VT+2VON
Design procedure: +
Same as the previous except VON R
VON VMIN - VT+VON iOUT
R =I = 2I + M3 M4
REF REF
VT
For the previous example, -
0.3V + M1 M2 +
R = 2·100µA = 1.5k VON VON
- -
Fig. 290-07
If the reference current is small, R can become large.
†T.L. Brooks and A.L. Westwick, “A Low-Power Differential CMOS Bandgap Reference,” Proc. of IEEE Inter. Solid-State Circuits Conf., Feb.
1994, pp. 248-249.
Minimum Voltage Cascode Sinks

The following configuration gives increased output resistance with a fixed minimum
7
voltage drop of VDsat: Rout(4) = g + 8rds
m
3 +
Rout(3) = g + 4rds VDS(min)=VDSat
m
-
1 +
Rout(2) = g + 2rds +
m VDS(min)=VDSat VDS=0V
- -
+
+ +
VDS(min)=VDSat VDS=0V VDS=0V
- - -
+ + +
VDS=0V VDS=0V VDS=0V
- - -
150527-03
2n-1-1
It can be shown that Rout(n) is g + 2n-1rds if the gates are grounded. Therefore, the
m
output resistance is increasing by a factor of 2n-1 for each cascade device and the
minimum voltage across the sink remains constant at VDSat.
The upper transistor is in saturation while all the other transistors have VDS = 0 which
implies that gm = 0 and rds = 1/gm(sat).
This really only works well if the transistors are isolated and the bulk can be connected
to the source.
The area required for the sink will increase significantly because of the isolation.
Minimum Voltage Cascode Current Mirrors

The previous technique can be used to create current mirrors with low minimum input
and output voltages as shown. iIN iOUT
3
iIN Rout(3) = g + 4rds
iOUT + m
1 +
Rout(2) = g + 2rds VDS=VGS VDS(min)=VDSat
+ m
+ - -
VDS=VGS VDS(min)=VDSat +
VDS=0V
+
- - VDS=0V
+ -
+ - -
+
VDS=0V + VDS=0V +
V - VDS=0V + VDS=0V
- GS -
- VGS
-
-
150527-04
n
The input resistance to the current mirrors can be written as Rin ≈
. This is illustrated
gm
by the following small signal model (remember when VDS = 0 that gm = 0 and rds =
1/gm(sat). Rin Rin
Rin Rin
gm3vgs3 +
M3 + vgs3 rds3 1/gm3 vgs3 rds3
VGS 1/gm3
- -
M2 +
VDS=0V rds2 = 1/gm(sat) rds2 = 1/gm(sat)
- rds2 = 1/gm(sat)
M1 +
+ VDS=0V rds1 = 1/gm(sat) rds1 = 1/gm(sat)
VGS - - rds1 = 1/gm(sat)
150527-05

MOS Regulated Cascode Sink†
Comments:
• Achieves very high output resistance by increasing the loop gain (return-ratio) due to
the M4-M5 inverting amplifier.
 gm4  gm3rds2gm4rds4
LG = gm3rds2g +g  
 ds4 ds5 2
rds3gm3rds2gm4rds4
If rds4rds5, then rout 
2
• M3 maintains “constant” current even though it is no longer in the saturation region.
†E. Sackinger and W. Guggenbuhl, “A Versatile Building Block: The CMOS Differential Difference Amplifier,” IEEE J. of Solid-State Circuits,
vol. SC-22, no. 2, pp. 287-294, April 1987.
Regulated Cascode Current Sink - Continued

Small signal model:
D2=
Solving for the output resistance: S3= iout
G3=D4=D5
iout = gm3vgs3 + gds3(vout-vgs4) + vgs3 - G4 gm3vgs3
+ D3 +
rds5 rds4 rds2 v vout
But gm4vgs4
gs4 r
ds3
- -
vgs4 = ioutrds2 S2 = G2= S4 Fig. 290-09
and
vgs3 = vg3 - vs3 = -gm4(rds4||rds5)vgs4 - vgs4 = -rds2[1 + gm4(rds4||rds5)]iout
 iout = -gm3rds2[1 + gm4(rds4||rds5)]iout + gds3vout - gds3rds2iout
vout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||rds5)]iout
vout
 rout = = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||rds5)]
iout
 rds3gm3rds2gm4(rds4||rds5)
If IREF = 100µA, all W/Ls are 10µm/1µm we get rds = 0.25M and gm = 469µS which
gives
rout  (0.25M)(469µS)(0.25M)(469µS)(0.125M) = 1.72G
Can 1G Output Resistance Really be Achieved?

No, because of substrate currents. VG > V T
B S VD > VDS(sat)
Substrate currents are caused by impact Polysilicon
Depletion
ionization due to high electric fields cause Region
an impact which generates a hole-electron p+ n+ A
Free n+
electron
pair. The electrons flow out the drain and Fixed
Atom
the holes flow into the substrate causing a p- substrate Free
substrate current flow. hole
Fig130-7
Max. output resistance ≈ 500M-1G
Substrate current: D
iDB = K1(vDS - vDS(sat))iDe-[K2/(vDS-vDS(sat))]
where
iDB
K1 and K2 are process-dependent parameters G
-1
(typical values: K1 = 5V and K2 = 30V) B
Small-signal model:
S Fig130-8
iDB IDB
gdb = = K2 V - V (sat) ≈ 1nS
vDB DS DS
This conductance will prevent the realization of very high-output resistances.

Minimizing the VMIN of the Regulated Cascode Current Sink

VMIN:
Without the use of the VO1 battery shown, VMIN is pretty bad. It is,
VMIN = VGS4 + VDS3(sat) = VT + 2VON
Minimizing VMIN:
If VO1 = VT , then VMIN = 2VON. This is accomplished by the following circuit:
VDD VDD VDD
iOUT
IREF If VGS4A - VGS4B = VDS2(sat) = VON, then VMIN = 2VON
ID4A IB
+IB M3 + +
VDS2 2ID4 2IB 2IB+2IREF
KN’(W4A/L4A) - KN’(W4B/L4B) =
M4A M4B -
KN’(W2/L2)
+ + vOUT
VGS4AVGS4B IB
- - IREF+IB
ID4 IB IB+IREF
or
M1 M2 +
VDS2 W4A/L4A - W4B/L4B = W2/L2
- -
Fig. 290-10
A number of solutions exist. For example, let IB = IREF. This gives ID4A = 5.824IREF
assuming all W/L ratios are identical.

Example 15-2 - Design of a Minimum VMIN Regulated Cascode Current Sink

Design a regulated cascode current sink for 100µA and minimum voltage of VMIN =
0.3V.
Solution
Let the W/L ratios of M1 through M5 be equal and let IB = 10µA. Therefore,
2·100µA 2·110µA
VMIN = 0.3V = VON3 + VON2 = +
110µA/V2(W/L) 110µA/V2(W/L)
2·100µA  
=  1 + 1.1  +5V +5V
110µA/V2(W/L) +5V
110mA 186mA 10mA iOUT
Therefore,
2·100µA M3 +
0.3V = (2.049) 85/1
110µA/V2(W/L)
M4A M4B
W 2·100µA·2.049 2
= = 84.8  85. 85/1 85/1
vOUT
L 110µA/V20.32 10mA
With IB = 10µA, then ID4A = M1 M2 110mA


 10 + 1102 = 186µA 85/1 85/1
-
Fig. 290-11

Comparison of the MOS Cascode and Regulated Cascode Current Sink

Close examination in the knee area reveals interesting differences.
Simulation results:
110
105
BJT Cascode
100 MOS Cascode
Regulated
iOUT (mA)
95 MOS
Cascode
90
85
80
0 0.1 0.2 0.3 0.4 0.5
vOUT (V) Fig. 290-12
Comments:
• The regulated cascode current is smaller than the cascode current because the drain-
source voltages of M1 and M2 are not equal.
• The regulated cascode current sink has a smaller VMIN due to the fact that M3 can
have a drain-source voltage smaller than VDS(sat)
SUMMARY
Summary of Both BJT and MOS Current Sinks/Sources
Current Sink/Source rOUT VMIN
Simple MOS Current Sink 1
rds = VDS(sat) =
D
VON
Simple BJT Current Sink VA VCE(sat)
ro =
C  0.2V
Cascode MOS  gm2rds2rds1 2VON
Cascode BJT  Fro 2VCE(sat)
Regulated Cascode Current Sink  rds3gm3rds2gm4(rds4||rds5)  VT +VON
Minimum VMIN Regulated  rds3gm3rds2gm4(rds4||rds5) VON
Cascode Current Sink
Resistor Implementations
• MOSFET resistors may use less area than actual resistors
• Linearity is the primary issue for MOSFET resistor realizations

Lecture 16 – Current Mirrors and Simple References (6/14/14) Page 16-1
LECTURE 16 – CURRENT MIRRORS AND SIMPLE

REFERENCES
Outline
• MOSFET current mirrors
• Improved current mirrors
• Voltage references with power supply independence
• Current references with power supply independence
• Temperature behavior of voltage and current references
Pages 138-156

MOSFET CURRENT MIRRORS

What is a Current Mirror?
A current mirror replicates the input current of a current sink or current source as an
output current. The output current may be identical to the input current or can be a scaled
version of it.
VDD VDD VDD VDD
IIN IOUT = KIIN

iIN iOUT = KiIN
iin Kiout
iIN iOUT
Current Current
Mirror Mirror
060528-01
The above current mirrors are referenced with respect to ground. Current mirrors can
also be referenced with respect to VDD and can source input and output currents.

Characterization of Current Mirrors

A current mirror is basically nothing more than a current amplifier. The ideal
characteristics of a current amplifier are:
• Output current linearly related to the input current, iout = Aiiin
• Input resistance is zero
• Output resistance is infinity
Also, the characteristic VMIN applies not only to the output but also the input.
• VMIN(in) is the range of vin over which the input resistance is not small
• VMIN(out) is the range of vout over which the output resistance is not large
Graphically:
Therefore, Rout, Rin, VMIN(out), VMIN(in), and Ai will characterize the current mirror.
Simple MOS Current Mirror

Circuit:
iI iO
+ M1 M2 +
vDS1 + vDS2
Assume that vDS2 > vGS - VT2, then - vGS
- -
-
iO L1W2VGS-VT221 + vDS2 K2’ Fig. 300-02
     
iI = W1L2VGS-VT1 1 + vDS1 K1’
If the transistors are matched, then K1’ = K2’ and VT1 = VT2 to give,
iO L1W21 + vDS2
  
iI = W1L21 + vDS1
If vDS1 = vDS2, then
iO L1W2
 
iI = W1L2
Therefore the sources of error are:
1.) vDS1 vDS2
2.) M1 and M2 are not matched.
Influence of the Channel Modulation Parameter, 

If the transistors are matched and the W/L ratios are equal, then
iO 1 + vDS2
iI = 1 + vDS1
if the channel modulation parameter is the same for both transistors (L1 = L2).
Ratio error (%) versus drain voltage difference:
Note that one could use this effect to

measure .
Measure VDS1, VDS2, iI and iO and

solve the above equation for the
channel modulation parameter, .
iO
-1
iI
= iO
vDS2 - i vDS1
I

Illustration of the Offset Voltage Error Influence

Assume that VT1 = 0.7V and K’W/L = 110µA/V2.
Key: Make the part of VGS causing the current to flow, VON, more significant than VT.

Example 16-1 – Aspect Ratio Errors in Current Mirrors

A layout is shown for a one-to-four current amplifier. Assume that the lengths are
identical (L1 = L2) and find the ratio error if W1 = 5  0.1 m. The actual widths of the two
transistors are
W1 = 5  0.1 m and W2 = 20  0.1 m
iI iO
Solution M2
i i O I
M1
We note that M1 M2
+ +
the tolerance VDS1 VDS2
+
is not multi- GND
-
VGS
-
plied by the -
nominal gain Fig. 300-5
factor of 4.
The ratio of W2 to W1 and consequently the gain of the current amplifier is
iO W2 20 ± 0.1 1 ± (0.1/20) 
 0.1 ±0.1 
 0.1 ±0.4
iI = W1 = 5 ± 0.1 = 4 1 ± (0.1/5)  ≈ 41 ± 20 1 - 5  ≈ 41 ± 20 - 20  = 4 - (±0.03)
where we have assumed that the variations would both have the same sign (correlated). It
is seen that this ratio error is 0.75% of the desired current ratio or gain.

Example 16-2 – Reduction of the Aspect Ratio Errors in Current Mirrors

Use the layout technique illustrated below and calculate the ratio error of a current
amplifier having the specifications of the previous example.
Solutions
The actual widths of M1 and M2 are
W1 = 5  0.1 m and W2 = 4(5  0.1) m
The ratio of W2 to W1 and consequently the current gain is given below and is for all
practical purposes independent of layout error.
iO 4(5 ± 0.1)
= =4
iI 5 ± 0.1
iI iO
M2a M2b M1 M2c M2d iI iO
M1 M2
GND
GND
Fig. 300-6

Summary of the Simple MOS Current Mirror/Amplifier

• Minimum input voltage is VMIN(in) = VT+VON
Okay, but could be reduced to VON.
VDD
Principle: M5 M6 M7
Ib Ib
Ib
M3 M4
iI iO
iI VT iO VT
+ M1 M2
VON +
+ M1
VON + M2 - VT+VON Ib
- VT+VON -
-
Fig. 300-7
Will deal with later in low voltage op amps.

• Minimum output voltage is VMIN(out) = VON
1
• Output resistance is Rout = I
D
1
• Input resistance is Rin  g
m
• Current gain accuracy is poor because vDS1  vDS2
IMPROVED CURRENT MIRRORS

Large Output Swing Cascode Current Mirror
VDD VDD VDD
IIN IOUT
R
• Rout  gm2rds2rds1 iin iout
D5=G3
M4 M5 M2 +
1/1 rds5
vin rds5 + rds3 + rds3gm5rds5 1 1/4 1/1 gm5vgs5
• Rin = i = g r (1+g r ) ≈ g iin vin
in m3 ds3 m5 ds5 m3 M3 M1
D3=S5 +
1/1 1/1 gm3vgs3
rds3 vs5
An easier way to find Rin: = gm3vin
- S3=G5 -
060528-02
1.) Apply a small voltage change, vin, at the input.
VDD
2.) Note that this voltage is equal to vgs3.
IIN
3.) This small voltage change causes a current change iin
in the drain of M3 of gm3vgs3 or gm3vin. + M5

1/1
gm3vin
4.) The current iin is equal to gm3vin.
vin M3
5.) Therefore, dividing vin by iin gives Rin = 1/gm3. 1/1
+
vin
• VMIN(out) = 2VON - -
120522-03
• VMIN(in) = VT + VON
• Current gain is excellent because vDS1 = vDS3.
Self-Biased Cascode Current Mirror

VDD VDD
I1 I2
iin iout
+ iin R g v
• Rin = ? R
+ +
m3 gs3
M3 M4
vin = iinR + rds3(iin-gm3vgs3) vin rds3
+
vin v2
+ rds1(iin-gm1vgs1) M1 M2 gm1vgs1 v1 rds1
-
But, - - -
vgs1 = vin-iinR
Self-biased, cascode current mirror Small-signal model to calculate Rin.
and Fig. 310-03
vgs3 = vin-rds1(iin-gm1vgs1) = vin-rds1iin+gm1rds1(vin-iinR)

 vin = iinR+rds3iin-gm3rds3[vin-rds1iin+gm1rds1(vin-iinR)]+rds1[iin-gm1(vin+iinR)]
vin[1+gm3rds3+gm1rds1gm3rds3+gm1rds1]
= iin[R+rds1+rds3+gm3rds3rds1+ gm1rds1gm3rds3R]
R + rds1 + rds3 + gm3rds3rds1 + gm1rds1gm3rds3R 1
Rin = ≈
1 + gm3rds3 + gm1rds1gm3rds3 + gm1rds1 gm1 + R
• Rout  gm4rds4rds2
• VMIN(in) = VT + 2VON •VMIN(out) = 2VON • Current gain matching is excellent
MOS Regulated Cascode Current Mirror
VDD VDD VDD

IBias
II IO
ii io
M3
M1
M4 M2
FIG. 310-11
• Rout  gm2rds3
• Rin  1
gm4
• VMIN(out) = VT+2VON (Can be reduced to 2VON)
• VMIN(in) = VT+VON (Can be reduced to VON)
• Current gain matching - good as long as vDS4 = vDS2
Summary of MOS Current Mirrors
Current Accuracy Output Input Minimum Minimum

Mirror Resistance Resistance Output Input
Voltage Voltage
Simple Poor rds 1 VON VT+VON
gm
Wide Output Excellent gmrds2 1 2VON VT+VON
Swing gm
Cascode
Self-biased Excellent gmrds2 1 2VON VT+2VON
Cascode R+g
m
Regulated Good- gm2rds3 1 VT+2VON VT+VON
Cascode Excellent gm (Can be (Can be
2VON) ≈VON)

VOLTAGE REFERENCES WITH POWER SUPPLY INDEPENDENCE

Power Supply Independence
How do you characterize power supply independence?
Use the concept of:
VREF VREF/VREF VDD  VREF
SV = =  
DD VDD/VDD VREF  VDD 
Application of sensitivity to determining power supply dependence:
VREF  VREF VDD
 
VREF = S VDD  VDD
Thus, the fractional change in the reference voltage is equal to the sensitivity times the
fractional change in the power supply voltage.
For example, if the sensitivity is 1, then a 10% change in VDD will cause a 10% change
in VREF.
VREF
Ideally, we want S to be zero for power supply independence.
VDD

MOSFET-Resistance Voltage References

Simple MOS-R Voltage Reference
VDD Current
2(VDD-VREF)
VREF = VGS = VT + VDD MOSFET
R R R
or Load Line
2(VDD-VT) + VDD-D
1 1 VREF-
VREF = VT - R + + VREF VDD+D
R (R)2 VREF+
- Voltage
VREF VDD
VREF   VDD 
140907-01
1
S V =  1 + 2(V -V )RV 
DD  DD T  REF
VREF
Assume VDD=5V, W/L =100 and R=100k, thus VREF  0.7875V and SV = 0.0653
DD
Higher Voltage Simple MOS-R Voltage Reference
VDD
This circuit allows VREF to be larger. If the current in R1 (and R2)
R
is small compared to the current flowing through the transistor, then vout
+
R1 + R2 R1
VREF   R  VGS VREF
 2  R2
-
140907-02

Bipolar-Resistance Voltage References VCC

VCC
R
R vout
+
+ R1
VREF VREF
- R2
-
Fig. 370-04
kT I
VREF = VEB = q ln I  If the current in R1 (and R2)
 s
VCC − VEB VCC is small compared to the
and I = R

R current flowing through the
kT VCC transistor, then
give VREF  q ln  RI 
 s R1 + R2
VREF 1 1 VREF    VEB
 R 1 
SVCC = ln[V /(RI )] = ln(I/I )
CC s s
If VCC = 5V, R = 4.3k and Is = 1fA,
then VREF = 0.719V.
VREF Can use diodes in place of the BJTs.
Also, S = 0.0362
VCC
CURRENT REFERENCES WITH POWER SUPPLY INDEPENDENCE

Power Supply Independence
Again, we want
IREF/IREF VDD  IREF
IREF
SV = V /V = I  V 
DD DD DD REF  DD 
to approach zero.
IREF
Therefore, as SV approaches zero, the change in IREF as a function of a change in
DD
VDD approaches zero.

Gate-Source Referenced Current Reference

The circuit below uses both positive and negative feedback to accomplish a current
reference that is reasonably independent of power supply.
Circuit: VDD i
K'NW (V 2
I1 = GS1 - VT)
RB M3 M5 2L
M4 Desired
I5
M7 I1 I2 operating
V
IQ
point I2 = GS1
M2 R
I6
M6 Undesired
M8 M1 operating
+ point
VGS1 R
Startup - 0V VQ v
Fig. 370-06
Principle:
2I1
If M3 = M4, then I1  I2. However, the M1-R loop gives VGS1=VT1 +
KN’(W1/L1)
VGS1 VT1  1  2I1
Solving these two equations gives I2 = = + 
R R R KN’(W1/L1)
VT1 1 1 2VT1 1
The output current, Iout=I1=I2 can be solved as Iout= R + + +
1R2 R 1R (1R)2

Simulation Results for the Gate-Source Referenced Current Reference

The current ID2 appears to be okay, why is 120mA
ID1
ID1 increasing? 100mA
Apparently, the channel modulation on the ID2
80mA
current mirror M3-M4 is large.
60mA
At VDD = 5V, VSD3 = 2.83V and VSD4 =
1.09V which gives ID3 = 1.067ID4  107µA 40mA
20mA
Need to cascode the upper current mirror.
SPICE Input File: 0
0 1 2 3 4 5
VDD Fig. 370-07
Simple, Bootstrap Current Reference
VDD 1 0 DC 5.0 RB 1 6 100KILOHM
VSS 9 0 DC 0.0 .OP
M1 5 7 9 9 N W=20U L=1U .DC VDD 0 5 0.1
M2 3 5 7 9 N W=20U L=1U .MODEL N NMOS VTO=0.7 KP=110U
M3 5 3 1 1 P W=25U L=1U GAMMA=0.4 +PHI=0.7 LAMBDA=0.04
M4 3 3 1 1 P W=25U L=1U .MODEL P PMOS VTO=-0.7 KP=50U
M5 9 3 1 1 P W=25U L=1U GAMMA=0.57 +PHI=0.8 LAMBDA=0.05
R 7 9 10KILOHM .PRINT DC ID(M1) ID(M2) ID(M5)
M8 6 6 9 9 N W=1U L=1U .PROBE
M7 6 6 5 9 N W=20U L=1U .END

Cascoded Gate-Source Referenced Current Reference

VDD
120mA
M3 M4
M5 ID2
M3C MC4
100mA
MC5
RB 80mA
I1 RON I2 I5 ID1
M7 60mA
M2
40mA
M8 M1 20mA
+
VGS1 R
Startup - 0
0V 0 1 2 3 4 5
VDD
SPICE Input File: Fig. 370-08
Cascode, Bootstrap Current Reference M8 6 6 9 9 N W=1U L=1U

VDD 1 0 DC 5.0 M7 6 6 5 9 N W=20U L=1U
VSS 9 0 DC 0.0 RB 1 6 100KILOHM
M1 5 7 9 9 N W=20U L=1U .OP
M2 4 5 7 9 N W=20U L=1U .DC VDD 0 5 0.1
M3 2 3 1 1 P W=25U L=1U .MODEL N NMOS VTO=0.7 KP=110U
M4 8 3 1 1 P W=25U L=1U GAMMA=0.4 PHI=0.7 LAMBDA=0.04
M3C 5 4 2 1 P W=25U L=1U .MODEL P PMOS VTO=-0.7 KP=50U
MC4 3 4 8 1 P W=25U L=1U GAMMA=0.57 PHI=0.8 LAMBDA=0.05
RON 3 4 4KILOHM .PRINT DC ID(M1) ID(M2) ID(M5)
M5 9 3 1 1 P W=25U L=1U .PROBE
R 7 9 10KILOHM .END

Base-Emitter Referenced Circuit

VDD
M3 M4 M5
i2 i2=Vtln(i1/Is)/R
M6 I
1 Desired i2=i1
I2 I5 operating
point
M1 M2
+
VEB1
Undesired
+ operating
M7 Q1 - point
R VR
Startup
i1
- -
070621-01
VEB1
Iout = I2 =
R
BJT can be a MOSFET in weak inversion.

Low Voltage Gate-Source Referenced MOS Current Reference

The previous gate-source referenced circuits required at least 2 volts across the power
supply before operating.
A low-voltage gate-source referenced circuit:
VDD
M3 M4 VT+VON
VON VT
I1
VT I2
VON
M1 M2
VT+VON
R VR
VSS Fig. 4.5-8A
Without the batteries, VT, the minimum power supply is VT+2VON+VR.

With the batteries, VT, the minimum power supply is 2VON+VR  0.5V

Summary of Power-Supply Independent References

• Reasonably good, simple voltage and current references are possible
• Best power supply sensitivity is approximately 0.01
(10% change in power supply causes a 0.1% change in reference)
Type of Reference VREF IREF

S or S
VPP VPP
MOSFET-R <1
BJT-R <<1
Gate-source Referenced <<1
Base-emitter Referenced <<1

TEMPERATURE BEHAVIOR OF VOLTAGE AND CURRENT REFERENCES

Characterization of Temperature Dependence
The objective is to minimize the fractional temperature coefficient defined as,
1  VREF 1 VREF
TCF = V   = S parts per million per °C or ppm/°C
REF  T  T T
Temperature dependence of PN junctions:
v
i ≈ IsexpV  
 t
 1  Is (ln Is) 3 VGO VGO
-VGO    =
Is  T  T
= T + TVt  TVt
Is = KT exp V  
3
 t  
dvBE VBE - VGO
dT  = -2mV/°C at room temperature
T
Temperature dependence of MOSFET in strong inversion:
dvGS dVT 2L d  iD  
 
dT = dT + WCox dT µo  dvGS mV
 dT  -  -2.3 °C
µo = KT-1.5 
VT(T) = VT(To) - (T-To) 
Resistors: (1/R)(dR/dT) ppm/°C
Bipolar-Resistance Voltage References

R
From previous work we know that, +
VREF
kT VDD - VREF VDD
VREF = q ln  -
 RI s  140614-02
However, not only is VREF a function of T, but R and Is are also functions of T.
dVREF k VDD-VREF kT  RIs  -1 dVREF VDD-VREF  dR dIs 
 dT = q ln   
+ q V -V   -    + I dT
 RI s   DD REF s RI dT  RI s  RdT s 
VREF Vt dVREF  dR dIs  VREF-VGO Vt dVREF 3Vt Vt dR
= T - V -V - Vt RdT + I dT = - V -V - T - R dT
DD REF dT  s  T DD REF dT
VREF-VGO dR 3Vt
dVREF - Vt RdT - T V -V
T dR 3Vt
 
REF GO
dT = - Vt RdT - T
Vt T
1 + V -V
DD REF
1 dVREF VREF-VGO Vt dR 3Vt

TCF = = - -
VREF dT VREF·T VREF RdT VREF·T
If VREF = 0.6V, Vt = 0.026V, and the R is polysilicon, then at 27°K the TCF is
0.6-1.205 0.026·0.0015 3·0.026 -6-65x10-6-433x10-6 =-3859ppm/°C

TCF = 0.6·300 - - = 33110
CMOS Analog Circuit Design
0.6 0.6·300 © P.E. Allen - 2016
MOSFET Resistor Voltage Reference

From previous results we know that VDD
2(VDD-VREF)
VREF = VGS = VT + R
R
1 2(VDD-VT) 1 +
or VREF = VT - + +
R R (R)2 VREF
-
Note that VREF, VT, , and R are all functions of temperature.
Fig. 380-02
It can be shown that the TCF of this reference is
VDD − VREF 1.5 1 dR
dVREF − + 2R 
 T
− R dT 

=
dT 1
1+
2R (VDD − VREF)
VDD − VREF 1.5 1 dR
− +  − R dT
2R  T 
 TCF = 1
VREF(1 + )
2R (VDD − VREF)
Example 16-3 - Calculation of MOSFET-Resistor Voltage Reference TCF

Calculate the temperature coefficient of the MOSFET-Resistor voltage reference where
W/L=2, VDD=5V, R=100k using the parameters of Table 3.1-2. The resistor, R, is
polysilicon and has a temperature coefficient of 1500 ppm/C.
Solution
dR
First, calculate VREF . Note that R = 220x10-6x105 = 22 and RdT = 1500ppm/°C
1 2(5 − 0.7)  1 2

 VREF = 0.7 − 22 + + 22 = 1.281V
22  
5 − 1.281  1.5 

dVREF −2.3x10-3 +    − 1500x10 -6

222 300 
Now, = = -1.189x10-3V/°C
dT 1
1+  
222 (5 - 1.281)
The fractional temperature coefficient is given by
 1 
TCF = −1.189x10 1.281 = −928 ppm/°C
-3
 

Gate-Source and Base-Emitter Referenced Current Source/Sinks

Gate-source referenced source:
VT1 1 1 2VT1 1
The output current was given as, Iout = R + + +
1R2 R 1R (1R)2
Although we could grind out the derivative of Iout with respect to T, the temperature
performance of this circuit is not that good to spend the time to do so. Therefore, let us
assume that VGS1  VT1 which gives
VT1 dIout 1 dVT1 1 dR
Iout  R  dT = R dT - 2 dT
R
In the resistor is polysilicon, then
1 dIout 1 dVT1 1 dR - 1 dR -2.3x10-3 -3 = -4786ppm/°C
TCF = I = - = - = -1.5x10
out dT VT1 dT R dT VT1 R dT 0.7
Base-emitter referenced source:
VBE1
The output current was given as, Iout = I2 = R
1 dVBE1 1 dR
The TCF = V - R dT
BE1 dT
1
If VBE1 = 0.6V and R is poly, then the TCF = 0.6 (-2x10-3) - 1.5x10-3 = -4833ppm/°C.
Low VDD Current Reference

Consider the following circuit with all transistors having a
W/L = 10. This is a bootstrapped reference which creates a
Vbias independent of VDD. The two key equations are:
I3 = I4  I 1 = I2
and
VGS1 = VGS2 + I2R
Solving for I2 gives:
VGS1-VGS2 1  2I1 2I2 2I1  1
I2 = =R - = 1 - 
R  ß 1 ß 2 R ß 1 2
1 1 1
 I2 =  I2 = I1 = = = 18.18µA
R 2ß1 2ß1R2 2·110x10-6·10·25x106
Now, Vbias can be written as
2I2 1 1
Vbias=VGS1= +VTN = +VTN = -6 3 + 0.7 = 0.1818+0.7=0.8818V
ß1 ß1 R 110x10 ·10·5x10
Any transistor with VGS = Vbias will have a current flow that is given by 1/2ßR2.
2ß 1 1
Therefore, gm = 2Iß = 2 =  gm = R
2ßR R
Summary of Reference Performance

VREF
Type of Reference SV TCF Comments
DD
MOSFET-R <1 >1000ppm/°C
BJT-R <<1 >1000ppm/°C
Gate-Source Good if currents >1000ppm/°C Requires start-
Referenced are matched up circuit
Base-emitter Good if currents >1000ppm/°C Requires start-
Referenced are matched up circuit
• A MOSFET can have zero temperature dependence of iD for a certain vGS
• If one is careful, very good independence of power supply can be achieved
• None of the above references have really good temperature independence
Consider the following example:
A 10 bit ADC has a reference voltage of 1V. The LSB is approximately 0.001V.
Therefore, the voltage reference must be stable to within 0.1%. If a 100°C change in
temperature is experienced, then the TCF must be 0.001%/C or multiplying by 104
requires a TCF = 10ppm/°C.

Lecture 17 – Temperature Stable References (5/15/18) Page 17-1
LECTURE 17 – TEMPERATURE STABLE REFERENCES

Outline
• Principles of temperature stable references
• Examples of temperature stable references
• Design of bias voltages for a chip
• Summary
Pages 156-172

PRINCIPLES OF TEMPERATURE STABLE REFERENCES

Temperature Stable References
• The previous reference circuits failed to provide small values of temperature
coefficient although sufficient power supply independence was achieved.
• This section introduces a temperature stable reference that cancels a positive
temperature coefficient with a negative temperature coefficient. The technique is
sometimes called the bandgap reference although it has nothing to do with the bandgap
voltage.
Principle
VREF(T) = VPTAT(T) + K·VCTAT(T)
where
VPTAT(T) is a voltage that is proportional to
absolute temperature (PTAT)
VCTAT(T) is a voltage that is complimentary
to absolute temperature (CTAT)
and
K is a temperature independent constant that makes VREF(T) independent of
temperature
PTAT Voltage
The principle illustrated on the last slide requires perfectly linear positive and negative
temperature coefficients to work properly. We will now show a technique of generating
PTAT voltages that are linear with respect to temperature.
Implementation of a PTAT voltage:
 I1   I2 
VPTAT = VD = VD1 – VD2 = Vt ln I  - Vt ln I 
 s1  s2
 I1 Is2   Is2   A2  kT  A2 
= Vt ln I  = Vt ln     
 2 Is1  Is1 = Vt ln A1 = q ln A1
if I1 = I2.
Therefore, if A2 = 10A1, VD at room temperature becomes,

k A2 1.381x10-23J/°K 
VD = q ln A T =
    ln(10) T = (+ 0.086mV/°C)T
  1  1.6x10 -19 Coul 
A2
 VPTAT = Vt ln 
A1

Psuedo-PTAT Currents
In developing temperature independent voltages, it is useful to show
how to generate PTAT currents. A straight-forward method is to
superimpose VPTAT across a resistor as shown:
Because R is always dependent on temperature, this current is called a pseudo-PTAT
current and is designated by IPTAT’.
When a pseudo-PTAT current flows through a second
resistor with the same temperature characteristics as the
first, it creates a new VPTAT voltage.
The new VPTAT voltage, VPTAT2 is equal to,
R2
VPTAT2 = R VPTAT1
1
Differentiating with respect to temperature gives
dVPTAT2 R2  dR2 dR1  dVPTAT1
=  - +
dT R1  R2dT R1dT dT
Therefore, if the temperature coefficient of R1 and R2 are equal, then the temperature
dependence of VPTAT2 is the same as VPTAT1.

Pseudo-PTAT Currents - Continued

Pseudo-PTAT currents can be generated through the circuits below which use only
MOSFETs and pn junctions or MOSFETs, an op amp, and pn junctions.
VDD VDD VDD VDD VDD VDD
M1 M2
M3 M5 M3
I1 M4 I2 I1 I2
IPTAT’ IPTAT’
- +
M1 + + M2
VGS1 VGS2
- -
R IPTAT’ R IPTAT’
D1 D1
A1 D2 A1 D2
A2 A2
Psuedo-PTAT current generator using Psuedo-PTAT current generator using

only MOSFETs and pn junctions. MOSFETs, an op amp and pn junctions.
100326-04
In these circuits, I1 = I2 and the voltage across D1 is made equal to the voltage across the
series combination of R and D2 to create the pseudo-PTAT current,
VD1 - VD2 kT  A2 
IPTAT’ = = Rq ln A 
R  1
where VGS1 = VGS2 for the MOSFET only version.
CTAT Voltage
This becomes more challenging because a true CTAT voltage does not exist. The best
approach is to examine the pn junction (can be a diode or BJT).
The diode voltage can be written as
æ iD ö
vD = Vt ln ç ÷ = Vt ln(iD ) -Vt ln(I s )
è Is ø
where g
æ -VBG ö
I s = AT exp ç ÷ and iD = BT a
è Vt ø
and where A and B are temperature independent constants,  is the temperature
coefficient for Is ( ≈ 3),  is the temperature coefficient for iD ( =1 for PTAT), and VBG
is the bandgap voltage of silicon (1.205V at 27°C).
The diode voltage as a function of temperature is,
é g æ VBG öù
÷ú = VBG -Vt (g - a )ln(T ) -Vt ln(A / B)
a
vD (T ) = VCTAT = Vt ln(BT ) -Vt ln êAT exp ç -
ë è Vt øû
Note that the term Vt(-)ln(T) is not linear with temperature and cannot completely
cancel the perfectly linear PTAT voltage.

Pseudo CTAT Currents

The circuits below show three ways of creating a pseudo CTAT current using negative
feedback:†
VDD VDD VDD
IPTAT’
M3 M4 M1
M4 M5 M2
M5 M6
IPTAT’ IPTAT’ I2
ICTAT’ ICTAT’ ICTAT’ ICTAT’
ICTAT’ - +
M2 M3
M1 M2
Q1 + + R ICTAT’
VBE R VD R D2
A2
- -
Generation of a pseudo CTAT current Generation of a pseudo CTAT current Generation of a pseudo CTAT current using
using a bipolar transistor. using a diode. MOSFETs, an op amp and pn junctions.
120326-01
The negative feedback loop shown causes the current designated as ICTAT’ to be,
VBE VD
ICTAT’ = R = R
†
I.M. Gunawan, G.C.M. Jeijer, J. Fonderie, and J.H. Huijsing, “A Curvature-Corrected Low-Voltage Bandgap Reference, IEEE J. Solid-state Circuits, vol. SC-28, No. 6, June
1993, pp. 677-670.
Temperature Independent Voltage References

Basic structures:
Series form:
R2
VREF = IPTAT’R2 + VD = R VPTAT + VCTAT
 1
Parallel form:
R3 R3 R3R2 
VREF = (IPTAT’ + ICTAT’)R3 = R VPTAT + R VCTAT = R R VPTAT + VCTAT
 1  2  2 1 
To achieve temperature independence, VREF must be differentiated with respect to
temperature and set equal to zero. The resistor ratios and other parameters can be used
to achieve temperature independence.

Series Temperature Stable Voltage Source

Series Configuration: VDD
From the circuit on the right, we get IPTAT’ =
VPTAT
VREF = I PTAT ' R2 +VD = (R2 / R1 )VPTAT +VCTAT = KVPTAT +VCTAT R1
+
Substituting for VPAT and VCTAT gives, R2
VREF = KVt ln(A2 / A1 )+VBG -Vt (g - a )ln(T)-Vt ln(A / B) VD = +

VREF
VCTAT
- -
Differentiating with respect to T and setting T = T0 gives, 131010-01
dVREF V V V V
(T = T0 ) = K ln(A2 / A1 ) t 0 - t 0 ln(A/B) - t 0 (g - a )ln(T0 ) - (g - a ) t 0
dT T0 T0 T0 T0
Equating the derivative to zero gives,
Kln(A2 / A1 )- ln(A/B) = (g - a )[1+ ln(T0 )]
Substituting back gives,
é æ T0 öù
VREF = (g - a )Vt [1+ ln(T0 )]+VBG -Vt (g - a )ln(T ) = VBG + (g - a )Vt ê1+ ln ç ÷ú
ë è T øû
At T = T0, assuming  = 3.2 and  = 1, the reference voltage is
VREF = VBG + Vt(-) = 1.205V + 0.057V = 1.262V (T0 = 27°C)
Because VREF ≈ VBG, this voltage reference is called the “bandgap reference”.


Eliminating the constants ln(A/B):
Express the pn junction voltage at a reference temperature, To, and T
vD (T) = VCTAT = VBG -Vt (g - a )ln(T) -Vt ln(A / B)
and
vD (To ) = VBG -Vto (g - a )ln(To )-Vto ln(A / B)
Eliminating the ln(A/B) term gives,
T æT ö
vD (T ) = VBG - [VBG - vD (To )] - (g - a )Vt ln ç ÷
To è To ø
Approximating the ln(T/To) term with a Taylor’s series expansion gives,
æ T ö æ T - To ö 1 æ T - To ö2 1 æ T - To ö3
ln ç ÷ » ç ÷+ ç ÷ + ç ÷ +
è To ø è T ø è
2 T ø è
3 T ø
Substituting this into the above gives
æ T - To ö (g - a )Vt æ T - To ö (g - a )Vt æ T - To ö
2 3
T
vD (T ) = VBG - [VBG - vD (To )] - (g - a )Vt ç ÷- ç ÷ - ç ÷ +
To è To ø 2 è To ø 3 è To ø


Tuning VREF (solving for K):
From the previous slide, let VCTAT be approximated as,
T æ T - To ö
vD (T ) = VCTAT » VBG - [VBG - vD (To )] - (g - a )Vt ç ÷
To è To ø
VREF can be written as,
æ A2 ö T æ T - To ö
VREF = K ×VPTAT +VCTAT » KVt ln ç ÷ +VBG - [VBG - vD (To )] - (g - a )Vt ç ÷
è A1 ø To è To ø
Differentiating VREF with respect to temperature and setting T = To gives,
dVREF KVto æ A2 ö VBG - v D (To ) (g - a )Vto
(T = To ) = ln ç ÷ - - =0
dT To è A1 ø To To
Solving for K gives,
VBG - v D (To ) - (g - a )Vto VBG - v D (To ) - (g - a )Vto
K= Þ R2 =
æA ö IPTAT
Vto ln çç 2 ÷÷
è A1 ø

Example 17-1 – Temp. Independent Constant for Series and Parallel References
(a.) Design the ratio of R2/R1 for the series configuration if VCTAT = 0.6V and A2/A1 = 10
for room temperature (Vt = 0.026V). Assume  = 3.2 and  = 1. Find the value of VREF.
R2 VGO - VCTAT + (-)Vt0 1.205 - 0.6 + 2.2(0.026)
R1 = = = 11.05
VPTAT 0.026(2.3026)
VREF = 1.205 + 2.2(0.026) = 1.262V
If R1 = 1k, then R2 = 11.05k
(b.) For the parallel configuration find the values of R2/R1 and R3/R2 if VREF = 0.5V.
From (a.) we know that R2/R1 = 11.05. We also know that,
R3 R3 R3R2 
VREF = R VPTAT + R VCTAT = R R VPTAT + VCTAT 
 1  2  2 1 
= (R3/R2)[11.05ln(10)(0.026) + 0.6] = (R3/R2)1.262 = 0.5
 (R3/R2) = 0.3963
If R1 = 1k, then R2 = 11.05k and R3 = 4.378k

Simple Brokaw Bandgap† VCC

Circuit:
The voltage across R2 is, Q3 Q4
Q5
VR2 = VPTAT =Vt ln(N) IC2 IC1
Q2 R3 Q1
VBG +
creating the PTAT current flowing through Q2. R4
The bandgap voltage, VBG, is, xN
R2
x1
VREF
2R1Vt ln(N ) R5
VBG = +VBE1 R1
R2 140115-03
-
The resistor divider R4-R5 “gains up” this voltage to
æ R4 + R5 öé 2R1Vt ln(N) ù
VREF =ç ÷ê +VBE1 ú
è R5 øë R2 û
The resistor R3 eliminates the impact of the base currents of Q1 and Q2
2(R4 + R5 )R1 R2 R4 R5
VREF
'
= VREF + R4 (I B1 + I B2 ) - I B2 R3 ® R3 =
R2 R5 R1 (R4 + R5 )
†
A.P. Brokaw, “A Simple Three-Terminal IC Bandgap Reference,” IEEE J. Solid-State Circuits, Vol. SC-6, No. 1, 1971, pp. 2-7.
A Series Temperature Independent Voltage

Reference
An early realization of the series form is shown below†:
Assuming VOS = 0, then VR1 is
 J2   J1 
VR1 = VEB2 - VEB1 = Vt lnJ  - Vt lnJ 
 s2  s1
I2AE1 R2AE1
= Vt lnI A  = Vt lnR A 
 1 E2  3 E2
The op amp forces the relationship I1R2 = I2R3
R2 R2 R2AE1 R2 R2AE1
VREF =VEB2+I2R3=VEB2+VR1R  = VEB2+R VtlnR A  = VCTAT+ R lnR A Vt
 1  1  3 E2  1  3 E2
Differentiating the above with respect to temperature and setting the result to zero, gives
R2 R2AE1 VGO - VCTAT + (-)Vt0
  ln =
R R A
 1  3 E2 Vt
If VOS ≠ 0, then VREF becomes,
 R2 R2 R2AE1 VOS 
VREF = VEB2 - 1 + R VOS + R Vt lnR A 1 - I R 
 1 1  3 E2 1 2
†
K.E. Kujik, “A Precision Reference Voltage Source,” IEEE Journal of Solid-State Circuits, Vol. SC-8, No. 3 (June 1973) pp. 222-226.
Example 17-2 – Design of the Previous Temperature Independent Reference

Assume that AE1 = 10 AE2, VEB2 = 0.7 V, R2 = R3, and Vt = 0.026 V at room temperature
for temperature independent reference on the previous slide. Find R2/R1 to give a zero
temperature coefficient at room temperature. If VOS = 10 mV, find the change in VREF.
Note that I1R2 = VREF − VEB2 − VOS.
Evaluating the temperature independent constant gives
R2 R2 AE1 VGO - VCTAT + (-)Vt0 1.205 - 0.7 + (2.2)(0.026)
  ln  = = = 21.62
R R A
 1  3 E2  V PTAT 0.026
Therefore, R2/R1 = 9.39. In order to use the equation for VREF with VOS ≠ 0, we must
know the approximate value of VREF and iterate if necessary because I1 is a function of
VREF. Assuming VREF to be 1.262, we obtain from
 R2 R2 R2AE1 VOS 
VREF = VEB2 - 1 + R VOS + R Vt lnR A 1 - V 
 1 1  1 E2 REF - V EB2 - V OS
a new value VREF = 1.153 V. The second iteration makes little difference on the result
because VREF is in the argument of the logarithm

Series Temperature Independent Voltage References

The references shown do not use an op amp and avoid the issues of loop stability and
PSRR.
VBE2 - VBE1 Vt   I2   I1  
  VD1 = I2R1 + VD2
I1 = IPTAT’ = = ln   - ln  
R2 R2  Is2 Is1
Vt Is1 Vt AE1 Vt
= R lnI  = R lnA  I3 = I2 = IPTAT’ = R ln(n)
2  s2 2  E2 1
 R1 AE1 Let R1 = R and R2 = kR,
Since I1= I2, VREF = VBE2 + I1R1 = VBE2 + R lnA Vt

 2  E2 VREF = VD3 + I3(kR) = VD3 + kVt ln(n)
R1
= VCTAT + R  VPTAT = VCTAT + kVPTAT
 2

Parallel Temperature Independent Voltage Reference

A parallel form of the temperature independent voltage reference is shown below:
R3 R3
VREF = R VPTAT + R VCTAT
 1  2
Comments:
• The BJT of the ICTAT’ generator can be replaced with an MOSFET-diode equivalent
• Any value of VREF can be achieved
• Part (b.) of Example 17-1 showed how to design the resistors of this implementation

How Can a Bandgap “Current” Reference be Obtained?

Use a MOSFET under ZTC operation and design the parallel form of the bandgap
voltage reference to give a value of VZTC.
VDD VDD
IPTAT IREF
IVBE
+
R3 VREF =VGS(ZTC)
-
060529-09
Comments:
• Ability of the ZTC point not to drift with temperature restricts the temperature range
• The reference voltage must be equal to the ZTC voltage
• The voltage VREF will suffer the bandgap curvature problem which can be translated
into IREF.

Bandgap Curvature Problem

kT T0
Unfortunately, the q ln T  term of the pn
 
junction contributed a nonlinearity to the
CTAT realization. This is illustrated by the
dashed lines in the plot shown.
The result is shown below where the reference
voltage is not constant with temperature.
Comments:
• True temperature independence is only achieved over a small range of temperatures
• References that do not correct this problem have a temperature dependence of 10
ppm°/C to 50 ppm/°C over 0°C to 70°C.
Some Curvature Correction Techniques

• Squared PTAT Correction:
VBE
Temperature coefficient ≈ 1-20 ppm/°C VPTAT
• VBE loop
Voltage
M. Gunaway, et. al., “A Curvature- VPTAT2
Corrected Low-Voltage Bandgap
Reference,” IEEE Journal of Solid- VRef = VBE + VPTAT + VPTAT2
State Circuits, vol. 28, no. 6, pp. 667- Temperature
670,
Fig. 400-01
June 1993.
• Nonlinear cancellation
G.M. Meijer et. al., “A New Curvature-Corrected Bandgap Reference,” IEEE
Journal of Solid-State Circuits, vol. 17, no. 6, pp. 1139-1143, December 1982.

VBE Loop Curvature Correction Technique

Circuit: VDD
Operation:
VBE1-VBE2 Vt Ic1A2
3-Output Current Mirror (IVBE+INL) INL = = R lnA I 
VDD VDD VDD R 3 3  1 c2
IVBE+INL
IPTAT IPTAT Vt  2IPTAT 
IVBE = R lnI +I 
R3 INL VREF 3  NL Constant 
IPTAT
IConstant where
Qn1 Qn2 Iconstant = INL + IPTAT + IVBE
x1 R1
R2 x2
Vt VBE
Fig. 400-02 ≈ INL + R + R
x 2
(Iconstant a quasi-temperature independent current subject to the TCF of the resistors)
where
Vt = kT/q
Ic1 and Ic2 are the collector currents of Qn1 and Qn2, respectively
Rx = a resistor used to define IPTAT
 VBE Vt  2IPTAT  
 VREF = R + R ln I + I
   + IPTAT  R1
 2 3  NL constant 
Temperature coefficient  3 ppm/°C with a total quiescent current of 95µA.
Series Temperature Independent Voltage Reference with Curvature Correction

Objective: Eliminate nonlinear term from VCTAT.
Result: 0.5 ppm/°C from -25°C to 85°C.
Operation:
VREF = VPTAT + 3VCTAT – 2VConstant
Note that, IPTAT  Ic  T 1 =1
and IConstant  Ic  T 0   = 0,
Previously we found,
T T
VCTAT(T) ≈ VGO - T VGO-VCTAT(T0) -( -)Vt lnT 
0  0
so that
T T
VCTAT(IPTAT) =VGO-T VGO-VBE(T0)-(-1)Vt lnT 
0  0
T  T
and VCTAT(IConstant) =VGO - T VGO -VCTAT(T0) -Vt lnT 

0  0
Combining the above relationships gives,
VREF(T) = VPTAT + VGO - (T/T0)[VGO - VCTAT(T0)] - [ - 3] Vt ln(T/T0)
If   3, then VREF(T) ≈ VPTAT + VGO1 - (T/T0) + VCTAT(T0)(T/T0)
A Parallel Version of the Nonlinear Curvature Correction Technique

Disadvantages of the series temperature independent voltage reference includes stacking
of transistors and integer resolution in the cancellation of the nonlinear term.
Concept:
VDD VDD
IPTAT’ ICTAT(1)’ IPTAT’ ICTAT(1)’ IREF

ICTAT(0)’
+ + +
VREF VCTAT(0) R
IREF ICTAT(0)’ IREF ICTAT(0)’ VREF VCTAT(0)
R R
- - -
120326-02
VREF = K1·IPTAT’+ K2·ICTAT’(=1) - K3·ICTAT’(=0)

Block Diagram:

Design Relationships for the Parallel Nonlinear Curvature Correction Reference

From the previous block diagram, if R4A = R4B = R4, then
R4 R4 R4
VREF = R VPTAT + R VCTAT1 - R VCTAT0
1 2 3
Previously we saw that,
T T
VCTAT1 = VCTAT(IPTAT) =VGO-T VGO-VBE(T0)-(-1)Vt lnT 
0  0
and
T  T
VCTAT0 = VCTAT(IConstant) =VGO - T VGO -VCTAT(T0) -Vt lnT 

0  0
To cancel the nonlinear temperature term requires that,
R4  T  R4 T R3 
R2 (-1)Vt lnT0 = R3  Vt lnT0 or R2 = −
T
Define VCTAT = VGO-T VGO-VBE(T0) = VBE(T0) if T = T0.
0
Therefore,
R4 1 R4
VREF = R VPTAT + R VCTAT
1  2
Design Relationships – Continued

Differentiating VREF with respect to temperature at T = T0 and setting equal to 0 gives,
dVCTAT
R2 dT
R1 = - T  VPTAT
The design procedure for the parallel, curvature corrected reference is:
1.) Pick R1. Can be used to set the magnitude of current flow based on IPTAT.
R2 dVCTAT/dT
2.) Choose R2 to satisfy R = - T
1  VPTAT
R3 
3.) Pick R3 to satisfy R =
2 −
4.) Finally, select R4A = R4B = R4 to achieve the desired magnitude of VREF
R4 1 R4 R4R2 VCTAT
VREF = R VPTAT + R VCTAT = R R VPTAT + 
1  2 2 1  
R4-T d  T T  VCTAT R4 VGO
= R  dTVGO - T VGO + T VCTAT +  =
2   0 0    R2 
Example 17-3 – Design of a Zero Temperature Coefficient Voltage Reference

Assume that VCTAT = 0.7 V, R1 = 10k,  = 3.2, A2 = 10A1, Vt = 0.026 V and
dVCTAT/dT = -3mV/°C at room temperature for the parallel temperature independent
voltage reference. Find R2, R3 and R4 to give a zero temperature coefficient at room
temperature and a reference voltage of 0.72V.
Solution
Following the previous design procedure, we get,
(-0.003)
1.) R2 = (-300)3.2(0.0259)ln10 10k = 47.16 k
 47.16k(3.2)
2.) R3 = R2 = = 68.60 k
-1 2.2
R4 VGO VREF 0.72
3.) VREF = 0.72V = R ⇒ R4 = V  R2 = 1.205 (47.16 k)) = 90.17 k
2  GO

Results and Practical Considerations

Worst case tempco:
Practical considerations: VDD
• Stability of feedback loops 10GF
10GH
• Influence of the op amp VOS vout
vin
R4 R4 R4 IIN - +

VREF(error) ≈ VOS + + 
R1 R2 R3
R1
• Tuning + - VOS IX DQ1 DQ2

x1 x10
IX PTAT Block
111208-09
RX R4 VREF
DQX
x1

Other Characteristics of Bandgap Voltage References

Noise
Voltage references for high-resolution ADCs are particularly sensitive to noise.
Noise sources: Op amp, resistors, switches, etc.
PSRR
Maximize the PSRR of the op amp.
Offset Voltages
Becomes a problem when op amps are used.
VBE2 = VBE1 + VR1 + VOS
i A 
VBE = VBE2 - VBE1 = VR1 + VOS = Vt lni A 
C2 E1
 C1 E2
Since iC2R3 = iC1R2 - VOS
iC2 R2 VOS R2  VOS 
then = - = 1+
iC1 R3 iC1R3 R3  iC1R2
R A  VOS 
 2 E1
Therefore, VR1 = -VOS + Vt ln 1 +
R3AE2 iC1R2
V  R 
VREF = VBE2 - VOS + iC1R2 = VBE2 - VOS +  R R2 = VBE2 - VOS + R 
 R1 2
 1  1
 R2 R2 R A  VOS 
  2 E1
 VREF = VBE2 - VOS1+ R  + R Vt ln R A 1 - i R 
CMOS Analog Circuit Design  1 1  3 E2 C1 2 © P.E. Allen - 2016
DESIGN OF BIAS VOLTAGES FOR A CHIP

Distributing Bias Voltages over a Distance
The major problem is the IR drops in busses. For example,
100µA
ID1 ID2
VBias 100µA
M1 M2
100µA
050716-01 1mm
If the bus metal is 50m/sq. and is 5µm wide, the resistance of the bus in one direction
is (50m/sq.)x(1000µm/5µm) = 10 The difference in drain currents for an overdrive
of 0.1V is,
VGS1 = 1mV + VGS2 + 1mV = VGS2 + 2mV
ID1 (VGS1-VTN)2 (VGS2-VTN+2mV)2 0.1+0.0022
ID2 = (VGS2-VTN)2 = =  0.1  = 1.04
(VGS2-VTN)2  

Use Current to Avoid IR Drops in Long Metal Lines

Example:

Practical Aspects of Temperature-Independent and Supply-Independent Biasing

A temperature-independent and supply-independent current source and its distribution:
The currents are used to distribute the bias voltages to remote sections of the chip.

Practical Aspects of Bias Distribution Circuits - Continued

Distribution of the current avoids change in bias voltage due to IR drop in bias lines.
Slave bias circuit: VDD
VPBias1
From Master Bias
Ib Ib VPBias2
VNBias2
VNBias1
Fig. 400-08
From here on out in these notes,

VPBias1 = VPB1 = VDD-|VTP|-VSD(sat) VPBias2 = VPB2 = VDD-|VTP|-2VSD(sat)
and
VNBias1 = VNB1 = VTN + VDS(sat) VNBias2 = VNB2 = VTN + 2VDS(sat)
SUMMARY OF TEMPERATURE STABLE REFERENCES

• The classical form of the temperature stable reference has a value of voltage close to
the bandgap voltage and is called the “bandgap voltage reference”.
• Bandgap voltage references can achieve temperature dependence less than 50 ppm/°C
• Correction of second-order effects in the bandgap voltage reference can achieve very
stable (1 ppm/°C) voltage references.
• Watch out for second-order effects such as noise when using the bandgap voltage
reference in sensitive applications.
• Distribution of bias voltages over a long distance should be done by current rather than
voltage.

Lecture 18 – Inverting Amplifiers (8/14/17) Page 18-1
LECTURE 18 – INVERTING AMPLIFIERS

Outline
• Introduction
• Active Load Inverting Amplifier
• Current Source Load Inverting Amplifier
• Push-Pull Inverting Amplifier
• Noise Analysis of Inverting Amplifiers
• Summary
Pages 186-198

INTRODUCTION
Types of Amplifiers
Type of Amplifier Output Ideal Input Ideal Output

Gain = Input Resistance Resistance
Voltage Output Voltage Infinite Zero
Av = Input Voltage
Current Output Current Zero Infinite

Ai = Input Current
Transconductance Output Current Infinite Infinite

Gm = Input Voltage
Transresistance Output Voltage Zero Zero

Rm = Input Current
Most CMOS amplifiers fit naturally into the transconductance amplifier category as they
have large input resistance and fairly large output resistance.
If the load resistance is high, the CMOS transconductance amplifier is essentially a
voltage amplifier.

Characterization of an Amplifier
1.) Large signal static characterization:
• Plot of output versus input (transfer curve)
• Large signal gain
• Output and input swing limits
2.) Small signal static characterization:
• AC gain
• AC input resistance
• AC output resistance
3.) Small signal dynamic characterization:
• Bandwidth
• Noise
• Power supply rejection
4.) Large signal dynamic characterization:
• Slew rate
• Nonlinearity

Inverting and Noninverting Amplifiers

The types of amplifiers are based on the various configurations of the actual transistors.
If we assume that one terminal of the transistor is grounded, then three possibilities
result:
VDD VDD VDD
Load Load vin

+
- vout + vout vout
+
+ +
vin vin Load
Common Common Common

060608-01 Source Gate Drain
Note that there are two categories of amplifiers:

1.) Noninverting - Those whose input and output are in phase (common gate and
common drain)
2.) Inverting - Those whose input and output are out of phase (common source)

ACTIVE LOAD INVERTING AMPLIFIER

Voltage Transfer Characteristic of the Active Load Inverter
vIN=5.0V vIN=4.5V
vIN=4.0V
0.5 5V
K JI vIN=3.5V
vIN=2.5V
0.4 H vIN=3.0V W2 1mm
=
G L2 1mm
ID
F M2
ID (mA)
0.3
M1 +
E vIN=2.0V vOUT
0.2
M2 + W1 = 2mm
vIN L1 1mm
0.1 vIN=1.5V - -
D
C A,B vIN=1.0V
0.0
0 1 2 3 4 5
vOUT 5
A B M2 cutoff
4 M2 saturated
C
d
3 rate
u
vOUT
D at ve
1 s acti
2 M 1
E M
F
1 G H I J K
Fig. 320-02 0
0 1 2v
IN
3 4 5
The boundary between active and saturation operation for M1 is
vDS1  vGS1 - VTN → vOUT  vIN - 0.7V

Large-Signal Voltage Swing Limits of the Active Load Inverter

Maximum output voltage, vOUT(max):
vOUT(max)  VDD - |VTP|
(ignores subthreshold current influence on the MOSFET)
Minimum output voltage, vOUT(min):
Assume that M1 is nonsaturated and that VT1 = |VT2| = VT.
vDS1 ≤ vGS1 - VTN → vOUT ≤ vIN - 0.7V
The current through M1 is
 
vDS1   (vOUT)2

iD = 1 (vGS1 − VT)vDS1 −  = 1 (VDD − VT)(vOUT ) − 
 2   2 
and the current through M2 is
2 2 2
iD = 2 (vSG2 − VT)2 = 2 (VDD − vOUT − VT)2 = 2 (vOUT + VT − VDD)2
Equating these currents gives the minimum vOUT as,
VDD − VT
vOUT(min) = VDD − VT −
1 + (2/1)

Small-Signal Midband Performance of the Active Load Inverter

The development of the small-signal model for the active load inverter is shown below:
VDD
S2=B2
M2 gm2vgs2
ID vOUT G1 rds2 Rout
D1=D2=G2
+ + + +
vIN vin gm1vgs1 vout vin vout
M1 rds1 gm1vin rds1 gm2vout rds2
- - - -
S1=B1 Fig. 320-03
Sum the currents at the output node to get,
gm1vin + gds1vout + gm2vout + gds2vout = 0
Solving for the voltage gain, vout/vin, gives
vout −gm1 gm1 K'NW1L2
= − =− 
vin gds1 + gds2 + gm2 gm2  P 1 2
K' L W
The small-signal output resistance can also be found from the above by letting vin = 0 to
get,
1 1
Rout = g + g + g  g
ds1 ds2 m2 m2

Frequency Response of the Active Load Inverter

Incorporation of the parasitic Cgs2 VDD
capacitors into the small-signal
M2
model: Cbd2 CM
If we assume the input voltage has a Vout + +

Cgd1 Cbd1 Vin gmVin Vout
small source resistance, then we can Rout Cout
CL - -
write the following: Vin M1
sCM(Vout-Vin) + gmVin Cgs1

Fig. 320-04
+ GoutVout + sCoutVout = 0
 Vout(Gout + sCM + sCout) = - (gm – sCM)Vin
 sCM
1- g   s
−gmRout 1 - 
Vout
=
-(gm – sCM)
= -gmRout
 m  =
 z1
Vin Gout+ sCM + sCout 1+ sRout(CM + Cout) 1-
s
p1
−1 gm1
where gm = gm1, p1 = R and z1 = C
(C
out out +CM) M
1
and Rout = [gds1+gds2+gm2]  gm2 , CM = Cgd1 , and
-1 Cout = Cbd1+Cbd2+Cgs2+CL

Complex Frequency (s) Analysis of Circuits – (Optional)

The frequency response of linear circuits can be analyzed using the complex frequency
variable s which avoids having to solve the circuit in the time domain and then transform
into the frequency domain.
Passive components in the s domain are:
1
ZR(s) = R ZL(s) = sL and ZC(s) = sC
s-domain analysis uses the complex impedance of elements as if they were “resistors”.
Example: C1 s-domain A
1/sC1
+ + conversion + +
1
V1 gmV1 R2 C2 V2 V1(s) R2 V (s)
sC2 2
- - - gmV1(s) -
060204-06
Sum currents flowing away from node A to get,

sC1(V2 – V1) + gmV1 + G2V2 + sC2V2 = 0
Solving for the voltage gain transfer function gives,
V2(s) -sC1 + gm  sC1/gm - 1 
T(s) = = = -gmR2  
V1(s) s(C1+ C2) + G2  s(C1 + C )R
2 2 + 1 

Complex Frequency Plane – (Optional)

The complex frequency variable, s, is really a complex number and can be expressed as
s =  + j where  = Re[s] and  = Im[s].
Complex frequency plane:
It is useful to plot the roots of the transfer function on the complex frequency plane.
For the previous T(s), the roots are:
The numerator root (zero) is s = z1 = +(gm/C1)
The denominator root (pole) is s = p1= -[1/R2(C1+ C2)]
What is the Frequency Response of an Amplifier? – (Optional)

Frequency response results when we replace the complex frequency variable s with j in
the transfer function of an amplifier. (This amounts to evaluating T(s) on the imaginary
axis of the complex frequency plane.)
The frequency response is characterized by the magnitude and phase of T(j).
Example:
a0 + a1s s = j a0 + a1j a0 + ja1
Assume T(s) = T(j) = =
b0 + b1s  b0 + b1j b0 + j b1
Since T(j) is a complex number, we can express the magnitude and phase as,
a02 + (a1)2 a1 b1
|T(j)| = Arg[T(j)] = +tan a - tan  b 
-1   -1
b02 + ( b1)2  0  0 
For the previous example, the magnitude and phase would be,
1 + (C1/gm)2 Note: Because the zero is on
|T(j)| = gmR2
1 + [ R2(C1+C2)]2 the positive real axis, the
phase due to the zero is
Arg[T(j)] = -tan-1(C1/gm) - tan-1[ R2(C1+C2)] -tan-1( ) rather than +tan-1( ).
More about that later.
Linear Graphical Illustration of Magnitude and Phase – (Optional)

The important concepts of frequency response are communicated through the graphical
portrayal of the magnitude and phase.
Consider our example,
V2(s)  sC1/gm - 1   s/z1 - 1 
T(s) = = -gmR2   = -T(0) 
V1(s)  s(C1 + C )R
2 2 + 1  s/p -
1 1
where T(0) = gmR2, z1 = +(gm/C1) and p1= -[1/R2(C1+ C2)].
Replacing s with j gives [remember tan-1(-x) = - tan-1(x)],
1 + (z1)2
|T(j)| = T(0) and Arg[T(j)] = ±180°-tan-1(z1) - tan-1[/p1]
1 + ( /p1) 2
Graphically, we get the following if we assume |p1| = 0.1|z1|,

Logarithmic Graphical Illustration of Frequency Response – (Optional)

If the frequency range is large, it is more useful to use a logarithmic scale for the
frequency. In addition, if one expresses the magnitude as 20 log10(|T(j)|, the plots can
be closely approximated with straight lines which enables quick analysis by hand. Such
plots are called Bode plots.
To construct a Bode asymptotic magnitude plot for a low pass transfer function in the
form of products of roots:
1.) Start at a low frequency and plot 20 log10(|T(0)| until you reach the smallest root.
2.) At the frequency equal to magnitude of the smallest root, change to a line with a
slope of +20dB/decade if the root is a zero or -20dB/decade if the root is a pole.
3.) Continue increasing in frequency until you have plotted the influence of all roots.
Influence of the Complex Frequency Plane on Frequency Response – (Optional)

The root locations in the complex frequency plane have a direct influence on the
frequency response as illustrated below. Consider the transfer function:
 s/z1 - 1  |p1|  s-z1   s-z1 
T(s) = -T(0) s/p - 1  = - z T(0) s-p  = - 0.1T(0) s-p  where z1 = 10|p1|
 1  1  1  1
jw |T(jw)|/T(0)
Region of
j10 1.0 maximum
0.8 influence Region of
j8 by p1 maximum
j10-p1 j10-z1 0.6 influence
0.4 by z1
j8-p1 j8-z1
j6
0.2
j6-z1
j6-p1 0.0 w
j4 0 1 2 3 4 5 6 7 8 9 10
j4-z1
j4-p1 j2-z1
j2 j0-z1
j2-p1
j0-p1
j0
s
p1=-1 z1=10 070413-03
Note: The roots maximally influence the magnitude when  is such that the angle
between the vector and the horizontal axis is 45°. This occurs at j1 for p1 and j10 for z1.

Bandwidth of a Low-Pass Amplifier – (Optional)

One of the most important aspects of frequency analysis is to find the frequency at which
the amplitude decreases by -3dB or 1/ 2. This can easily be found from the magnitude
of the frequency response.
|A(jw)|
A(0)
A 0.707A(0)
+ +
V1(jw) V2(jw) Bandwidth
- -
0 w
0 wA=0.707 060205-03
Amplifier with a Dominant Root:

Since the amplifier is low-pass, the poles will be smaller in magnitude than the
zeros. If one of the poles is approximately 4-5 times smaller than the next smallest pole,
the bandwidth of the amplifier is given as
Bandwidth ≈ |Smallest pole|
Amplifier with no Dominant Root:
If there are several poles with roughly the same magnitude, then one should use the
graphical method above to find the bandwidth.
Frequency Response of the Active Inverter - Continued
So, back to the frequency response of the active load inverter, we find that if |p1| < z1,
then the -3dB frequency is approximately equal to the magnitude of the pole which is
[Rout(Cout+CM)]-1.
dB
20log10(gmRout)
z1
0dB log10w
|p1| » w-3dB
0512-06-02.EPS
Observation:
In general, the poles in a MOSFET circuit can be found by summing the capacitance
connected to a node and multiplying this capacitance times the equivalent resistance
from this node to ground and inverting the product.

Example 18-1 - Performance of an Active Load Inverter

Calculate the output-voltage swing limits for VDD = 5 volts, the small-signal gain, the
output resistance, and the -3 dB frequency of active load inverter if (W1/L1) is 2 µm/1 µm
and W2/L2 = 1 µm/1 µm, Cgd1 = 100fF, Cbd1 = 200fF, Cbd2 = 100fF, Cgs2 = 200fF, CL =
1 pF, and ID1 = ID2 = 100µA, using the parameters in Table 3.1-2.
Solution
From the above results we find that:
vOUT(max) = 4.3 volts
vOUT(min) = 0.418 volts
Small-signal voltage gain = -1.92V/V
Rout = 9.17 k including gds1 and gds2 and 10 k ignoring gds1 and gds2
z1 = 2.10x109 rads/sec
p1 = -68.127x106 rads/sec.
Thus, the -3 dB frequency is 10.84 MHz.

CURRENT SOURCE INVERTER

Voltage Transfer Characteristic of the Current Source Inverter
Regions of operation for the transistors:
M1: vDS1  vGS1 -VTn vIN=5.0V vIN=4.5V
0.5
vIN=4.0V
5V
vIN=3.5V
vIN=2.5V
or 0.4 vIN=3.0V W2 2mm
=
L2 1mm
ID
vOUT  vIN - 0.7V
2.5V M2
0.3
ID (mA)
M1 +
KJIH F E vIN=2.0V vOUT
0.2
M2: vSD2  vSG2 - |VTp| 0.1
G M2
D
+
vIN
W1 = 2mm
L1 1mm
vIN=1.5V - -
C
or 0.0
0 1 2 3 4
A,B
5
vIN=1.0V
vOUT 5 A B C
VDD-vOUT VDD -VGG2 - |VTp| D
4
or M2 active
3 M2 saturated
t u rat
ed
a ve
vOUT
1 s ti
vOUT  3.2V 2 M 1 ac
M
E
Swing limits: 1 F
G H I J K
0
vOUT (max)  VDD 0 1 2v
IN
3 4 5 Fig. 5.1-5
  
 2
VDD - VGG - |VT2|2 
vOUT(min) = (VDD - VT1)1 - 1-     
 1  V DD - V T1  

Small-Signal Midband Performance of the Current Source Load Inverter

Small-Signal Model:
VDD
S2=B2
M2 rds2
VGG2 ID vOUT G1 Rout
D1=D2
+ + + +
vIN vin gm1vgs1 vout vin vout
M1 rds1 gm1vin rds1 rds2
- - - -
S1=B1=G2 Fig. 5.1-5B
Midband Performance:
vout −gm1 2K'NW1  −1  1 1 1
= =   !!! and Rout = 
vin gds1 + gds2  L1ID  1 + 2 D gds1 + gds2 ID(1 + 2)
vout
vin Strong Inversion
Weak
Invers-
ion
log(IBias)
» 1µA
060614-01

Frequency Response of the Current Source Load Inverter

Incorporation of the parasitic capacitors VDD
Cgs2
into the small-signal model (x is
connected to VGG2): x M2
CM
Cbd2
If we assume the input voltage has Cgd2 Vout + +
Cgd1 Cbd1 Vin gmVin Vout
a small source resistance, then we Rout Cout
CL - -
can write the following: Vin M1
 s Fig. 5.1-4
−gmRout 1 - 
Vout(s)  z1
Vin(s) = s
1-p
1
−1 gm
where gm = gm1, p1 =  and z1 =
Rout(Cout+CM) CM
1
and Rout = g and Cout = Cgd2 + Cbd1 + Cbd2 + CL CM = Cgd1
ds1 + gds2
Therefore, if |p1|<|z1|, then the −3 dB frequency response can be expressed as
gds1 + gds2
-3dB  1 =
Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL
Example 18-2 - Performance of a Current-Sink Inverter + VDD

VSG1
A current-sink inverter is shown. Assume that W1 = 2 m, L1 = 1 -
vIN M1
m, W2 = 1 m, L2 = 1m, VDD = 5 volts, VNB1 = 3 volts, and the vOUT
ID
parameters of Table 3.1-2 describe M1 and M2. Use the capacitor values VNB1
of Example 18-1 (Cgd1 = Cgd2). Calculate the output-swing limits and M2
the small-signal performance. 070413-04
Solution
To attain the output signal-swing limitations, treat the current sink inverter as a current
source CMOS inverter with PMOS (NMOS) parameters for the NMOS (PMOS) and use
NMOS equations. Using a prime notation to designate the results of the current source
CMOS inverter that exchanges the PMOS and NMOS model parameters,
 110·1 3-0.7  
vOUT(max)’ = 5V and vOUT(min)’ = (5-0.7)1 - 1 -  50·2 5-0-0.72  = 0.74V
    
In terms of the current sink CMOS inverter, these limits are subtracted from 5V to get
vOUT(max) = 4.26V and v OUT (min) = 0V.
To find the small signal performance, first calculate the dc current. The dc current, ID, is
KN’W1 110·1
ID = 2L (VGG1-VTN)2 = 2·1 (3-0.7)2 = 291µA
1
vout/vin = −9.2V/V, Rout = 38.1 k and f-3dB = 2.78 MHz.
PUSH-PULL INVERTING AMPLIFIER

Voltage Transfer Characteristic of the Push-Pull Inverting Amplifier
v =4.5V
vIN=5.0V IN vIN=4.0V vIN=3.5V
1.0 5V
vIN=0.5V
vIN=1.0V W2 2mm
0.8 =
vIN=1.5V L2 1mm
vIN=2.0V vIN=3.0V
ID
0.6 M2
ID (mA)
vIN=2.5V + M1 +
vIN=2.5V vOUT
0.4
F vIN W1 = 1mm
G vIN=3.0V E vIN=2.0V L1 1mm
0.2 - -
H vIN=3.5V vIN=4.5V D vIN=1.5V
I
0.0 vIN=1.0V
0 J,K 1 2 3 4 CA,B 5
vOUT A B C D
E
4 d
u rat e Note
at v e the rail-
3 1 s acti
M 1 to-rail
vOUT
e M
c tiv ted output
2 2 a ra
M satu F voltage
2 swing
1 M
G
H I J K
0
0 1 2v 3 4 5 Fig. 5.1-8
IN
Regions of operation for M1 and M2:

M1: vDS1  vGS1 - VT1 → vOUT  vIN - 0.7V
M2: vSD2  vSG2-|VT2| → VDD -vOUT  VDD -vIN-|VT2| → vOUT  vIN + 0.7V
Small-Signal Performance of the Push-Pull Amplifier

5V
CM
+ +
M2
vin gm1vin rds1 gm2vin rds2 vout
+ M1 + Cout
- -
vin vout
Fig. 5.1-9
- -
Small-signal analysis gives the following results:

vout −(gm1 + gm2)  K'N(W1/L1) + K'P(W2/L2)
= = − (2/ID)  
vin gds1 + gds2   1 +  2 
1
Rout = g
ds1 + gds2
gm1+gm2 gm1+gm2 −(gds1 + gds2)
z= C = C +C and p1 = C
M gd1 gd2 gd1 + Cgd2 + Cbd1 + Cbd2 + CL
If z1 > |p1|, then

gds1 + gds2
-3dB =
Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL

Example 18-3 - Performance of a Push-Pull Inverter

The performance of a push-pull CMOS inverter is to be examined. Assume that W1 =
1 m, L1 = 1 m, W2 = 2 m, L2 = 1m, VDD = 5 volts, and use the parameters of Table 3.1-
2 to model M1 and M2. Use the capacitor values of Example 18-1 (Cgd1 = Cgd2). Calculate
the output-swing limits and the small-signal performance assuming that ID1 = ID2 =
300µA.
Solution
The output swing is seen to be from 0V to 5V. In order to find the small signal
performance, we will make the important assumption that both transistors are operating in
the saturation region. Therefore:
vout -257µS - 245µS
vin = 12µS + 15µS = -18.6V/V
Rout = 37 k
f-3dB = 2.86 MHz
and
z1 = 399 MHz

NOISE ANALYSIS OF INVERTING AMPLIFIERS

Noise Analysis of Inverting Amplifiers
Noise model:
VDD Noise VDD Noise
en22 Free Free
MOSFETs MOSFETs
* M2 M2
eout2 eout2
en12 eeq2
vin M1 vin M1
* *
Fig. 5.1-10
Approach:
1.) Assume a mean-square input-voltage-noise spectral density en2 in series with the gate
of each MOSFET.
(This step assumes that the MOSFET is the common source configuration.)
2.) Calculate the output-voltage-noise spectral density, eout2 (Assume all sources are
additive).
3.) Refer the output-voltage-noise spectral density back to the input to get equivalent input
noise eeq2.
4.) Substitute the type of noise source, 1/f or thermal.
Noise Analysis of the Active Load Inverter

1.) See model to the right. VDD Noise VDD Noise
gm12 en22 Free Free
2.) eout2 = en12 g  + en22 * M2
MOSFETs
M2
MOSFETs
 m2
eout2 eout2
 gm22en22 en12 eeq2
3.) eeq2 = en12 1 +      vin vin
 gm1 en1  * M1 * M1
Up to now, the type of noise is not defined. Fig. 5.1-10
1/f Noise
KF B
Substituting en2= 2fC WLK’ = fWL , into the above gives,
ox
 B1   K'2B2 L1  B1 1/2  K'2B2 L11/2
eeq(1/f) = fW L  1 + K' B  L   → eeq(1/f) = fW L  1 + K' B  L  
2
 1 1   1 1  2   1 1   1 1  2 
To minimize 1/f noise, 1.) Make L2>>L1, 2.) Increase W1 and 3.) choose M1 as a PMOS.
Thermal Noise
2 8kT
Substituting en = into the above gives,
3gm
 8kT   W2L1K'21/21/2
eeq(th) = 3[2K' (W/L) I ]1/2 1+ L W K'  

 1 1 1    2 1 1  
To minimize thermal noise, maximize the gain of the inverter.

Noise Analysis for Weak Inversion

How does the analysis change for weak inversion operation?
ID qID
Small signal transconductance is gm = nV = nkT
t
Noise sources in weak inversion:
2
KF B
1) 1/f noise given as en = 2fC WLK’ = fWL
ox
 gm2en2  B1   ID2/n2Vt  B2/f W2L2 
eeq(1/f)2 = en12 1 + g  e   = fW L  1 + I /n V  B /f W L 
  m1  n1   1 1   D1 1 t  1 1 1 
 B1   n12B2W1L1
= fW L  1 +  2 
 1 1   n2 B1W2L2 
8kT
2.) Thermal noise given as en2= 3g
m
 gm2gm1  8kT   gm2  8kT   n1
eeq(th)2 = en12 1 +     =   1 + g  = 3g  1 + n 
 g g 3g
 m1  m2  m1   m1  m1   2
Therefore, weak inversion operation does not lend itself to easy minimization of the 1/f
or thermal noise.

Noise Analysis of the Current Source Load Inverting Amplifier

Model:
VDD Noise VDD Noise
en22 Free Free
MOSFETs MOSFETs
* M2 M2
VGG2
eout2 eout2
en12 eeq2
vin M1 vin M1
* *
Fig. 5.1-12.
The output-voltage-noise spectral density of this inverter can be written as,

eout2 = (gm1rout)2en12 + (gm2rout)2en22
or
(gm2rout)2  gm22 en22
eeq2 = en12 + e 2 = en12 1 +   
(gm1rout)2 n2  gm1 en12
This result is identical with the active load inverter.
Thus the noise performance of the two circuits are equivalent although the small-signal
voltage gain is significantly different.

Noise Analysis of the Push-Pull Amplifier VDD Noise

Model: en22 Free
MOSFETs
* M2
vin en12 eout2
* M1
Fig. 5.1-13.
The equivalent input-voltage-noise spectral density of the push-pull inverter can be

found as
 gm1en1  2  gm2en2  2
eeq =   + 
gm1 + gm2 gm1 + gm2
If the two transconductances are balanced (gm1 = gm2), then the noise contribution of
each device is divided by two.
The total noise contribution can only be reduced by reducing the noise contribution of
each device.
(Basically, both M1 and M2 act like the “load” transistor and “input” transistor, so there
is no defined input transistor that can cause the noise of the load transistor to be
insignificant.)
SUMMARY
Table of Performance
AC Voltage AC Output Equivalent,
Inverter Bandwidth (CGB=0) input-referred,mean-
Gain Resistance
square noise voltage
p-channel -gm1 1 gm2
gm22
active load gm2 gm2 CBD1+CGS1+CGS2+CBD2 en12 + en22 
inverter gm1
Current -gm1 1 gds1+gds2
gm2
source load gds1+gds2 gds1+gds2 CBD1+CGD1+CDG2+CBD2 en12 + en22g 2
inverter  m1
Push-Pull -(gm1+gm2) 1 gds1+gds2  gm1en1 2  gm1en1 2
inverter gds1+gds2 gds1+gds2 CBD1+CGD1+CGS2+CBD2   + 
 m1 m2 gm1+ gm2
g + g

Lecture 19 – Differential Amplifier (6/24/14) Page 19-1
LECTURE 19 – DIFFERENTIAL AMPLIFIER

Outline
• Characterization of a differential amplifier
• Differential amplifier with a current mirror load
• Differential amplifier with MOS diode loads
• An intuitive method of small signal analysis
• Large signal performance of differential amplifiers
• Differential amplifiers with current source loads
• Design of differential amplifiers
• Summary
Pages 198-217

CHARACTERIZATION OF A DIFFERENTIAL AMPLIFIER

What is a Differential Amplifier?
A differential amplifier is an amplifier that amplifies the difference between two
voltages and rejects the average or common mode value of the two voltages.
Differential and common mode voltages:
v1 and v2 are called single-ended voltages. They are voltages referenced to ac
ground.
The differential-mode input voltage, vID, is the voltage difference between v1 and v2.
The common-mode input voltage, vIC, is the average value of v1 and v2 .
v1+v2
 vID = v1 - v2 and vIC =  v1 = vIC + 0.5vID and v2 = vIC - 0.5vID
2
v1 + v2
vOUT = AVDvID ± AVCvIC = AVD(v1 - v2) ± AVC  2 
 
where
AVD = differential-mode voltage gain
AVC = common-mode voltage gain

Differential Amplifier Definitions

• Common mode rejection rato (CMRR)
AVD
CMRR = A 
 VC 
CMRR is a measure of how well the differential amplifier rejects the common-mode
input voltage in favor of the differential-input voltage.
• Input common-mode range (ICMR)
The input common-mode range is the range of common-mode voltages over which
the differential amplifier continues to sense and amplify the difference signal with
the same gain.
Typically, the ICMR is defined by the common-mode voltage range over which all
MOSFETs remain in the saturation region.
• Output offset voltage (VOS(out))
The output offset voltage is the voltage which appears at the output of the differential
amplifier when the input terminals are connected together.
• Input offset voltage (VOS(in) = VOS)
The input offset voltage is equal to the output offset voltage divided by the
differential voltage gain.
VOS(out)
VOS = A © P.E. Allen - 2016
VD
Transconductance Characteristic of the Differential Amplifier

Consider the following n-channel differential VDD
amplifier (called a source-coupled pair). Where
iD1 iD2 M2 v
should bulk be connected? Consider a p-well, vG1 M1 G2
CMOS technology: v
+
v vGS2
+
D1 G1 S1 S2 G2 D2 VDD IBias ID GS1
- -
M4 M3 ISS
n+ n+ p+ n+ n+ n+
VBulk
p-well
n-substrate Fig. 5.2-2
Fig. 5.2-3
1.) Bulks connected to the sources: No modulation of VT but large common mode
parasitic capacitance.
2.) Bulks connected to ground: Smaller common mode parasitic capacitors, but
modulation of VT.
What are the implications of a large common mode capacitance?
+
R - R
vIN
vIN 0V
Little -
+ Large charging
charging of of capacitance
capacitance 070416-02
Transconductance Characteristic of the Differential Amplifier - Continued

Defining equations:
iD1 iD2
2iD1 2iD2 M1
vID = vGS1 − vGS2 =  −  and ISS = iD1 + iD2 vID
+
vGS1
M2
vGS2
+
- -
Solution: 141009-01
ISS
ISS ISS vID 2vID1/2 ISS ISS vID 2vID1/2
2 4 2 4
iD1 = 2 + 2  I − 2  and iD2 = 2 − 2  I − 2 
SS 4ISS
  SS 4ISS  
which are valid for vID  2(ISS/)1/2. iD/ISS
Illustration of the result: 1.0
0.8
iD1
0.6
0.4 iD2
0.2
vID
-2.0 -1.414 0.0 1.414 2.0 (ISS/ß)0.5 Fig. 5.2-4
Differentiating iD1 (or iD2) with respect to vID and setting VID =0V gives
diD1 ISS K'1ISSW1
gm = (V = 0) = = (half the gm of an inverting amplifier)
dvID ID 4 4L1

DIFFERENTIAL AMPLIFIER WITH A CURRENT MIRROR LOAD

Voltage Transfer Characteristic of the Differential Amplifier
In order to obtain the voltage transfer characteristic, a load for the differential amplifier
must be defined. We will select a current mirror load as illustrated below.
VDD
2mm 2mm
1mm 1mm
M3 M4
iD3 iD4 iOUT
2mm
1mm iD1 2mm iD2 +
1mm
VDD
M1 M2 2
+ vGS2 +
vGS1 vOUT
- -
vG1 2mm
1mm ISS vG2
Note that output signal to ground is M5
- - -
equivalent to the differential output VBias
signal due to the current mirror. Fig. 5.2-5
The short-circuit, transconductance is given as

diOUT K'1ISSW1
gm = (VID = 0) = ISS =
dvID L1

Voltage Transfer Function of the Differential Amplifer with a Current Mirror Load
Regions of operation of the transistors:

M2 is saturated when,
vDS2  vGS2-VTN → vOUT-VS1  VIC-0.5vID-VS1-VTN → vOUT  VIC-VTN
where we have assumed that the region of transition for M2 is close to vID = 0V.
M4 is saturated when,
vSD4  vSG4 - |VTP| → VDD-vOUT  VSG4-|VTP| → vOUT  VDD-VSG4+|VTP|
The regions of operations shown on the voltage transfer function assume ISS = 100µA.
2·50
50·2 +|VTP| = 1 + |VTP|  vOUT  5 - 1 - 0.7 + 0.7 = 4V
Note: VSG4 =
Input Common Mode Range (ICMR) VDD

2mm 2mm
ICMR is found by setting vID = 0 and varying vIC 1mm 1mm
M3 M4
until one of the transistors leaves the saturation. iD3 iD4 iOUT
Highest Common Mode Voltage 2mm
1mm iD1 2mm iD2 +
1mm
VDD
Path from G1 through M1 and M3 to VDD: +
M1 M2 2
vGS1 vGS2 + vOUT
VIC(max) =VG1(max) =VG2(max) - -
vG1 2mm
1mm ISS vG2
=VDD -VSG3 -VDS1(sat) +VGS1 M5
- - -
or VBias
VIC(max) = VDD - VSG3 + VTN1 Fig. 330-02
Path from G2 through M2 and M4 to VDD:

VIC(max)’ =VDD -VSD4(sat) -VDS2(sat) +VGS2
=VDD -VSD4(sat) + VTN2
 VIC(max) = VDD - VSG3 + VTN1
Lowest Common Mode Voltage (Assume a VSS for generality)
VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
where we have assumed that VGS1 = VGS2 during changes in the input common mode
voltage.
Small-Signal Analysis of the Differential-Mode of the Diff. Amp

A requirement for differential-mode operation is that the differential amplifier is
balanced†.
VDD
C3
M3 M4 D1=G3=D3=G4
iD3 iD4 iout G1 G2 rds1 S1=S2 rds2 D2=D4
+ vid -
+ + i3 +
iD1 iD2 +
vg1 vg2 rds5 i3 vout
rds4 C2
C1 1
M1 M2 gm3 rds3 gm1vgs1 gm2vgs2
- - -
vid vout S3 S4
M5 iout'
ISS G1 G2 D1=G3=D3=G4 D2=D4
- + vid -
VBias + + i3 +
vgs1 vgs2 C3
vout
gm1vgs1 1
C1 gm2vgs2 i3 rds2 rds4 C2
- - rds1 rds3 gm3 -
S1=S2=S3=S4
Differential Transconductance: Fig. 330-03
Assume that the output of the differential amplifier is an ac short.

gm1gm3rp1
iout’ = v − gm2vgs2  gm1vgs1 − gm2vgs2 = gmdvid
1 + gm3rp1 gs1
where gm1 = gm2 = gmd, rp1 = rds1rds3 and i'out designates the output current into a short
circuit.
†It can be shown that the current mirror causes this requirement to be invalid because the drain loads are not matched. However, we will continue to
use the assumption regardless.
Small-Signal Analysis of the Differential-Mode of the Diff. Amplifier - Continued

Output Resistance: Differential Voltage Gain:
1 vout gmd
rout = g + g = rds2||rds4 Av = v = g + g
ds2 ds4 id ds2 ds4
If we assume that all transistors are in saturation and replace the small signal parameters
of gm and rds in terms of their large-signal model equivalents, we achieve
vout (K'1ISSW1/L1)1/2 2 K'1W11/2 1
Av = = =   
vid (2 + 4)(ISS/2) 2 + 4  ISSL1  ISS
Note that the small-signal gain is inversely
vout
proportional to the square root of the bias current! vin Strong Inversion
Example: Weak
Invers-
If W1/L1 = 2µm/1µm and ISS = 50µA (10µA), then ion
log(IBias)
» 1µA
Av(n-channel) = 46.6V/V (104.23V/V) 060614-01
Av(p-channel) = 31.4V/V (70.27V/V)

1 1
rout = g + g = 25µA·0.09V-1 = 0.444M (2.22M)
ds2 ds4

Common Mode Analysis for the Current Mirror Load Differential Amplifier
The current mirror load differential amplifier is not a good example for common mode
analysis because the current mirror rejects the common mode signal.
Total common  Common mode  Common mode

 mode Output  =  output due to  -  output due to 
 due to vic  M1-M3-M4 path  M2 path 
Therefore:
• The common mode output voltage should ideally be zero.
• Any voltage that exists at the output is due to mismatches in the gain between the two
different paths.

DIFFERENTIAL AMPLIFIER WITH MOS DIODE LOADS

Small-Signal Analysis of the Common-Mode of the Differential Amplifier
The common-mode gain of the differential amplifier with a current mirror load is ideally
zero.
To illustrate the common-mode gain, we need a different type of load so we will consider
the following:
VDD VDD VDD
M3 M4 M3 M4 M3 M4
vo1 vo2 vo1 vo2 vo1 vo2
v1 v2
M1 M2 M1 M2 M1 M2
ISS 1
M5x 2 ISS
vid vid ISS 2 2
2 2 vic vic
M5
VBias VBias
Differential-mode circuit General circuit Common-mode circuit

110214-02
Differential-Mode Analysis:
vo1 gm1 vo2 gm2
vid ≈ -2gm3 and v ≈ + 2g
id m4
Note that these voltage gains are half of the active load inverter voltage gain.
Small-Signal Analysis of the Common-Mode of the Differential Amplifier – Cont’d

Common-Mode Analysis:
+ vgs1 - gm1vgs1
Assume that rds1 is large and can be ignored + +
rds1 rds3
(greatly simplifies the analysis). vic 2rds5 1 vo1
gm3
 vgs1 = vg1-vs1 = vic - 2gm1rds5vgs1 - -
Fig. 330-06
Solving for vgs1 gives
vic
vgs1 = 1 + 2g r
m1 ds5
The single-ended output voltage, vo1, as a function of vic can be written as
vo1 gm1[rds3||(1/gm3)] (gm1/gm3) gds5
vic = - 1 + 2gm1rds5  - 1 + 2gm1rds5  - 2gm3
Common-Mode Rejection Ratio (CMRR):
|vo1/vid| gm1/2gm3
CMRR = |v /v | = g /2g = gm1rds5
o1 ic ds5 m3
How could you easily increase the CMRR of this differential amplifier?

Frequency Response of the Differential Amplifier

Back to the current mirror load differential amplifier:
VDD
Cgs3+Cgs4
G1 G2 D1=G3=D3=G4 D2=D4
Cbd3 M3 M4 + vid -
Cbd4 + + i3 +
vgs1 vgs2 C3
v vout
Cgd4 rds4 C2
Cgd1 gm1 gs1 1 i3
Cgd2 + gm3 C1 gm2vgs2 rds2
Cbd1 - - -
vout S1=S2=S3=S4
Cbd2 CL
vid -
M1 M2
+ vid -
M5 + + i3 +
vgs1 vgs2 vout
VBias gm1vgs1 1 i3 rds2 rds4 C2
- - gm3 gm2vgs2 -
070416-03
Ignore the zeros that occur due to Cgd1, Cgd2 and Cgd4.
C1 = Cgd1+Cbd1+Cbd3+Cgs3+Cgs4, C2 = Cbd2 +Cbd4+Cgd2+CL and C3 = Cgd4
The poles are p1 = - gm3/C1 and p2 = -(gds2+gds4)/C2. Since |p1| >> |p2|, then we can write
gm1  2  gds2 + gds4
Vout(s)  g + g  [Vgs1(s) - Vgs2(s)] where 2 ≈
ds2 ds4 s + 2 C2
The approximate frequency response of the differential amplifier reduces to
Vout(s)  gm1   2 
  
Vid(s)  gds2 + gds4 s + 2
SMALL SIGNAL PERFORMANCE OF THE DIFFERENTIAL AMPLIFIER

Simplification of Small Signal Analysis
Small signal analysis is used so often in analog circuit design that it becomes desirable to
find faster ways of performing this important analysis.
Intuitive Analysis (or Schematic Analysis)
Technique:
1.) Identify the transistor(s) that convert the input voltage to current (these transistors are
called transconductance transistors).
2.) Trace the currents to where they flow into an equivalent resistance to ground.
3.) Multiply this resistance by the current to get the voltage at this node to ground.
4.) Repeat this process until the output is reached.
Simple Example: VDD VDD
R1 M2
vo1 gm2vo1 vout
gm1vin
vin M1 R2
Fig. 5.2-10C
vo1 = -(gm1vin) R1 → vout = -(gm2vo1)R2 → vout = (gm1R1gm2R2)vin

Intuitive Analysis of the Current-Mirror Load Differential Amplifier
1.) i1 = 0.5gm1vid and i2 = -0.5gm2vid VDD
2.) i3 = i1 = 0.5gm1vid M3 M4
3.) i4 = i3 = 0.5gm1vid gm1vid gm1vid rout
2 2
4.) The short-circuit output current is +
M1 gm1vid gm2vid M2
i4 - i2 = 0.5gm1vid + 0.5gm2vid = gm1vid + 2 2 -
vid vid
vout
4.) The resistance at the output node, rout, is 2 - + 2
1 + -
rds2||rds4 or g M5 vid
-
ds2 + gds4 VBias
140624-02
5.)  vout = (0.5gm1vid+0.5gm2vid )rout
gm1vin gm2vin vout gm1
= g +g = 
ds2 ds4 gds2+gds4 vin = gds2+gds4

Some Concepts to Help Extend the Intuitive Method of Small-Signal Analysis

1.) Approximate the output resistance of any cascode circuit as
Rout  (gm2rds2)rds1
where M1 is a transistor cascoded by M2.
2.) If there is a resistance, R, in series with the source of the transconductance transistor,
let the effective transconductance be
gm
gm(eff) = 1+g R
m
Proof:
gm2(eff)vin gm2(eff)vin
gm2vgs2 iout
M2 M2 + vgs2 -
vin rds1
vin M1 vin
rds1
VBias Small-signal model
Fig. 5.2-11A
vin
 vgs2 = vg2 - vs2 = vin - (gm2rds1)vgs2  vgs2 = 1+g r
m2 ds1

gm2vin
Thus, iout = 1+g r = gm2(eff) vin
m2 ds1

Noise Analysis of the Differential Amplifier

VDD VDD
M5
M5 M5
VBias VBias
en12 en22 eeq2
* M1 M2 * * M1 M2
ito2 vOUT
en32 en42
M3 * * M4 Vout M3 M4
Fig. 5.2-11C
Solve for the total output-noise current to get,
ito 2 = gm12en12 + gm22en22 + gm32en32 + gm42en42
This output-noise current can be expressed in terms of an equivalent input noise voltage,
eeq2, given as ito2 = gm12eeq2
Equating the above two expressions for the total output-noise current gives,
gm3 2
eeq = en1 + en2 + g  en32 + en42 
2 2 2
 m1
1/f Noise (en12=en22 and en32=en42): Thermal Noise (en12=en22 and en32=en42):
2BP  K’N BN L12 16kT  W3L1K'3
eeq (1/f) = fW L 1+  K’ B  L  
2 2
eeq (th) = 1+ 
1 1  P P   3  3[2K'1 (W/L) I
1 1 ] 1/2  L3 1 1
W K'
CMOS Input Offset Voltage - Strong Inversion

Circuit:
VDD
RD1 RD2
ID1 ID2
V1 VOUT
+ +
VGS1 VGS2
-
V2 -
140423-04
ISS
Input Offset Voltage:

2ID1 L1  2ID2 L2 
VIO = VGS1 – VGS2 = VT1 – VT2 +  · -  · 
 K' W1  K' W2
But ID1R D1 = ID2R D2, therefore
2L1  ID2RD2 ID2 2IDL1  RD2 1
VIO = VT + W1 

K1RD1 - K2  = VT +

W1 

K1RD1 -

K2
where ID1 ≈ ID2 = ID and VT = VT1-VT2.
Assuming matched geometries, W1/L1 = W2/L2 = W/L,
2IDL  RD2 1
VIO = VT +  - 
W  K1RD1 K2
CMOS Input Offset Voltage - Strong Inversion

Define the following,
RD1 = R + 0.5R, RD2 = R - 0.5R, K1 = K + 0.5K, and K2 = K - 0.5K
where R = 0.5(RD1 + RD2), R = RD1 - RD2, K = 0.5(K1 + K2), and K = K1 - K2.
Substituting these relationships into the expression for VIO gives,
2IDL  R - 0.5R 1 
VIO = VT +  
W  (K + 0.5K)(R + 0.5R) - K - 0.5K
Factoring out R and K gives,
2IDL  1 - 0.5R/R 1 
VIO = VT +  
KW  (1 + 0.5K/K)(1 + 0.5R/R) - 1 - 0.5K/K
Approximating 1/(1 ± ) as 1∓  results in,
2IDL  
VIO ≈ VT +  (1 - 0.5R/R)(1 - 0.5K/K)(1 - 0.5R/R) - 1 + 0.5  K/K 
KW
Finally, multiplying terms and ignoring higher order terms and letting x ≈ 0.5x gives,
1 R K 2IDL 1 R K
VIO ≈ VT - 2  R + K  = VT - 2  R + K  (VGS - VT)
  KW  

CMOS Input Offset Voltage Temperature Drift – Strong Inversion

Assumptions:
Drain current is constant, R/R and K/K have very little temperature dependence.
Therefore only VT and K will considered in the expression below
1 R K 2IDL
VIO ≈ VT -  + 
2 R K  KW
Assuming VT(T) = VT(To) - (T- To) and K(T) = kT-1.5, then we get,
V T d
dT = dT [VT1 – (T- To) - VT2 + (T- To)] =  –  =   
and
d 2IDL 2IDL  3 T-2.5  3 2IDL
dT KW = KW -2 T-1.5 = -2T KW
Therefore,
dVIO 3 R K 2IDL 3 R K 1 2 1
=  +  =  +  (VGS - VT) =
dT 4T  R K  KW 4T  R K  400 100 10 = 5µV/°C
Comments:
When the overdrive is large, the input offset voltage temperature drift will be larger
Typical values of dVIO/dT are 1-10µV/°C
CMOS Input Offset Voltage Temperature Drift – Weak Inversion
Repeating the previous analysis with the following model for the transistors
W æV - V ö
iD = IT 1 exp çç GS T ÷
÷
L è nVt ø
gives,
æi L ö æi L ö æi LI W ö
VIO = VGS1 - VGS2 = VT 1 + nVt ln çç D1 1 ÷ - V + nV ln ç
÷ T 2 t
D2 2
çI W ÷
÷ = DV + nV ln ç D1 1 T 2 2 ÷
T t çi L I W ÷
I W
è T1 1 ø è T2 2 ø è D2 2 T 1 1 ø
But iD1RD1 = iD2R D2 and W1/L1 = W2/L2 = W/L which gives,
æR I ö
VIO = DVT + ln çç D2 T 2 ÷÷
Define the following, è RD1IT 1 ø
RD1 = R + 0.5R, RD2 = R - 0.5R, IT1 = IT + 0.5IT, and IT2 = IT - 0.5IT
where R = 0.5(RD1 + RD2), R = RD1 - RD2, IT = 0.5(IT1 + IT2), and IT = IT1 – IT2.
Substituting these relationships into the expression for VIO gives,
æ (R - 0.5DR)(I - 0.5DI ) ö æ (1 - 0.5DR R)(1 - 0.5DI I ) ö
VIO = DVT + nVt ln çç T T ÷
÷ = DVT + nVt ln çç T T ÷
÷
è (R + 0.5DR)(IT + 0.5DIT ) ø è (1 + 0.5DR R)(1 + 0.5DIT IT ) ø
» DVT + nVt ln éë(1 - 0.5DR R)2(1 - 0.5DIT IT )2 ùû » DVT + nVt ln éë1 - DR R - DIT IT ùû
æ DR DI ö
» DVT - nVt çç + T ÷÷
è R IT ø

LARGE SIGNAL PERFORMANCE OF THE DIFFERENTIAL AMPLIFIER

Linearization of the Transconductance
iout iout
Goal:
ISS ISS
Linearization
vin vin
-ISS -ISS
060608-03
Method (degeneration):
VDD VDD
M3 M4 M3 M4
iout iout
M1 M2 M1 M2
+ RS RS VDD or + VDD
vin 2 2 2 vin RS 2
- -
M5
VNBias1 M5 VNBias1 M6
060118-10

Linearization with Active Devices

VDD VDD
M3 M4 M3 M4
iout iout
M1 VBias M2 M1 M2
+ VDD + VDD
or
vin M6 2 M6 2
vin
- M7
M5x1/2 -
VNBias1 M5x1/2 M5
VNBias1 M6
M6 is in deep triode region 060608-05 M6 and M7 are in the triode region
Note that these transconductors on this slide and the last can all have a varying
transconductance by changing the value of ISS.

Slew Rate of the Differential Amplifier

Slew Rate (SR) = Maximum output-voltage rate (either positive or negative)
dvOUT
It is caused by, iOUT = CL dt . When iOUT is a constant, the rate is a constant.
Consider the following current-mirror load, differential amplifiers:
VDD VDD
M5
M3 M4
iD4 iOUT VBias IDD
iD3
- -
vSG1 vSG2
iD1 iD2 + + +
M1 M2
CL + +
M1 M2 iD1 iD2 iOUT
+
vGS1 vGS2 +
- - iD3 iD4 +
vG1 ISS vG2 vOUT vG1 vG2
M3 M4 CL vOUT
M5
- - - - - -
VBias
Fig. 5.2-11B
Note that slew rate can only occur when the differential input signal is large enough to
cause ISS (IDD) to flow through only one of the differential input transistors.
ISS IDD
SR = C = C  If CL = 5pF and ISS = 10µA, the slew rate is SR = 2V/µs.
L L
(For the BJT differential amplifier slewing occurs at ±100mV whereas for the MOSFET
differential amplifier it can be ±2V or more.)
DIFFERENTIAL AMPLIFIERS WITH CURRENT SOURCE LOADS

Current-Source Load Differential Amplifier
VDD
Gives a truly balanced differential amplifier.
M3 M4
X1
X1 X1
M7 I3 I4
v3 v4
Also, the upper input common-mode range is
IBias v1 I1 I2 v2
extended.
M1 X1 X1 M2
M6 M5 I5
X1 X2
However, a problem occurs if I1 I3 or if I2  I4.
Fig. 5.2-12
Current Current
I1 I3
I3 I1
0 vDS1 0 vDS1
0 VDS1<VDS(sat) VDD 0 VSD3<VSD(sat) VDD
(a.) I1>I3. (b.) I3>I1. Fig. 5.2-13

A Differential-Output, Differential-Input Amplifier

Probably the best way to solve the current mismatch problem is through the use of
common-mode feedback.
Consider the following solution to the previous problem.
VDD
M3 M4
IBias MC3
MC4 v3 I3 I4 v4
Common- IC3 IC4
mode feed- Self-
back circuit resistances
MC1 MC2A of M1-M4
v1 v2
VCM M1 M2
MC2B
MC5 M5
MB
VSS Fig. 5.2-14
Operation:
• Common mode output voltages are sensed at the gates of MC2A and MC2B and
compared to VCM.
• The current in MC3 provides the negative feedback to drive the common mode output
voltage to the desired level.
• With large values of output voltage, this common mode feedback scheme has flaws.
Common-Mode Stabilization of the Diff.-Output, Diff.-Input Amplifier - Continued

The following circuit avoids the large differential output signal swing problems.
VDD
M3 M4
IBias MC3
MC4 v3 I3 I4 v4
Common- IC3 IC4 RCM1
mode feed- Self-
back circuit resistances
RCM2
MC1 MC2 of M1-M4
v1 v2
VCM M1 M2
MC5 M5
MB
VSS Fig. 5.2-145
Note that RCM1 and RCM2 must not load the output of the differential amplifier.
(We will examine more CM feedback schemes in Lecture 28.)

DESIGN OF DIFFERENTIAL AMPLIFIERS

Design of a CMOS Differential Amplifier with a Current Mirror Load
Design Considerations: VDD
Constraints Specifications
Power supply Small-signal gain M3 M4
Technology Frequency response (CL) vout
CL
Temperature ICMR +
Slew rate (CL) vin M1 M2
-
Power dissipation
I5
Relationships
VBias M5
Av = gm1Rout
VSS ALA20
-3dB = 1/RoutCL
VIC(max) = VDD - VSG3 + VTN1
VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
SR = ISS/CL
Pdiss = (VDD+|VSS|)x(All dc currents flowing from VDD or to VSS)

Design of a CMOS Differential Amplifier with a Current Mirror Load - Continued
Schematic-wise, the design procedure is illustrated as

shown:
Procedure:
1.) Pick ISS to satisfy the slew rate knowing CL or
the power dissipation
2.) Check to see if Rout will satisfy the frequency
response, if not change ISS or modify circuit
3.) Design W3/L3 (W4/L4) to satisfy the upper ICMR
4.) Design W1/L1 (W2/L2) to satisfy the gain
5.) Design W5/L5 to satisfy the lower ICMR
6.) Iterate where necessary

Example 19-1 - Design of a MOS Differential Amp. with a Current Mirror Load
Design the currents and W/L values of the current mirror load MOS differential amplifier
to satisfy the following specifications: VDD = -VSS = 2.5V, SR  10V/µs (CL=5pF), f-
3dB  100kHz (CL=5pF), a small signal gain of 100V/V, -1.5VICMR2V and Pdiss
 mW. Use the parameters of KN’=110µA/V2, KP’=50µA/V2, VTN=0.7V, VTP=-0.7V,
N=0.04V-1 and P=0.05V-1.
Solution
1.) To meet the slew rate, ISS  50µA. For maximum Pdiss, ISS  200µA.
2
2.) f-3dB of 100kHz implies that Rout  318k Therefore Rout =  318k
(N+P)ISS
 ISS  70µA Thus, pick ISS = 100µA
3.) VIC(max) = VDD - VSG3 + VTN1 → 2V = 2.5 - VSG3 + 0.7
2·50µA
VSG3 = 1.2V = + 0.7
50µA/V2(W3/L3)
W3 W4 2
 L =L = 2 =8
3 4 (0.5)


gm1 2·110µA/V2(W1/L1) W1 W1 W2
L1 → L1= L2 = 18.4
4.) 100=gm1Rout=g +g = = 23.31
ds2 ds4 (0.04+0.05) 50µA
5.) VIC(min) = VSS +VDS5(sat)+VGS1
2·50µA
-1.5 = -2.5+VDS5(sat)+ + 0.7
110µA/V2(18.4)
W5 2ISS
VDS5(sat) = 0.3 - 0.222 = 0.0777  L = = 150.6
5 KN’VDS5(sat)2
We probably should increase W1/L1 to reduce VGS1. If we choose W1/L1 = 40, then
VDS5(sat) = 0.149V and W5/L5 = 41. (Larger than specified gain should be okay.)

SUMMARY
• Differential amplifiers are compatible with the matching properties of IC technology
• The differential amplifier has two modes of signal operation:
- Differential mode
- Common mode
• Differential amplifiers are excellent input stages for voltage amplifiers
• Differential amplifiers can have different loads including:
- Current mirrors
- MOS diodes
- Current sources/sinks
- Resistors
• The small signal performance of the differential amplifier is similar to the inverting
amplifier in gain, output resistance and bandwidth
• The large signal performance includes slew rate and the linearization of the
transconductance
• The design of CMOS analog circuits uses the relationships of the circuit to design the
dc currents and the W/L ratios of each transistor
Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-1
LECTURE 20 – LOW INPUT RESISTANCE AMPLIFIERS – THE

COMMON GATE, CASCODE AND CURRENT AMPLIFIERS
Outline
• Voltage driven common gate amplifiers
• Voltage driven cascode amplifier
• Non-voltage driven cascode amplifier – the Miller effect
• Further considerations of cascode amplifiers
• Current amplifiers
• Summary
Pages 218-236

VOLTAGE-DRIVEN COMMON GATE AMPLIFIER

Common Gate Amplifier VDD VDD
Circuit: VPBias1
R M3 L
vOUT vOUT
VNBias2 VNBias2
M2
VNBias1
vIN IBias vIN M1
060609-01
Large Signal Characteristics: vOUT

VOUT(max) ≈ VDD – VDS3(sat) VDD
VON3
VOUT(min) ≈ VDS1(sat) + VDS2(sat)
Note VDS1(sat) = VON1
VON2
VON1+VON2
VT2
vIN
VON1 VNBias2
060609-02

Small Signal Performance of the Common Gate Amplifier

Small signal model:
rds2 rds2
Rin Rout Rin Rout
i1
- +
vin rds1 vgs2 gm2vgs2 vout vin rds1 vs2 gm2vs2 vout
rds3 rds3
+ -
060609-03
 rds2  gm2rds2rds3 vout gm2rds2rds3

vout = gm2vs2 r +r rds3 =  r +r  vin  Av = v = + r +r
 ds2 ds3   ds2 ds3  in ds2 ds3
Rin = Rin’||rds1, Rin’ is found as follows
vs2 = (i1 - gm2vs2)rds2 + i1rds3 = i1(rds2 + rds3) - gm2 rds2vs2
vs2 rds2 + rds3 rds2 + rds3
Rin' = i = 1 + g r  Rin = rds1||1 + g r
1 m2 ds2 m2 ds2
Rout ≈ rds2||rds3

Influence of the Load on the Input Resistance of a Common Gate Amplifier

Consider a common gate amplifier with a general load:
VDD VDD VDD VDD
VPBias1
VPBias1 M4
Load M3 VPBias2
vOUT vOUT vOUT M3 v
OUT
VNBias2 VNBias2 M2 VNBias2 M2 VNBias2
M2 M2
Rin1 Rin2 Rin3
VNBias1 VNBias1 VNBias1 VNBias1
vIN M1 vIN M1 vIN M1 vIN M1
070420-01
From the previous page, the input resistance to the common gate configuration is,
rds2 + RLoad
Rin = 1 + g r
m2 ds2
For the various loads shown, Rin becomes:
rds2 1 rds2+rds3 2 rds2+rds4gm3rds3
Rin1 = 1+g r ≈ g Rin2 = 1+ g r ≈ g Rin3 = 1+ g r ≈ rds!!!
m2 ds2 m2 m2 ds2 m2 m2 ds2
The input resistance of the common gate configuration depends on the load at the drain.

VOLTAGE-DRIVEN CASCODE AMPLIFIER

Cascode† Amplifier
VDD
VPBias1
M3
vOUT
VNBias2
M2
M1
vIN
060609-05
Advantages of the cascode amplifier:

• Increases the output resistance and gain (if M3 is cascoded also)
• Eliminates the Miller effect when the input source resistance is large
†“Cascode” = “Cascaded triode” see H. Wallman, A.B. Macnee, and C.P. Gadsden, “A Low-Noise Amplifier, Proc. IRE, vol. 36, pp. 700-708, June
1948.
Large-Signal Characteristics of the Cascode Amplifier

vIN=5.0V vIN=4.5V
5V
0.5 vIN=4.0V M3 W3 2mm
vIN=3.5V =
L3 1mm
0.4 vIN=3.0V ID
2.3V
vIN=2.5V M2 +
0.3
ID (mA)
K G F
W2 = 2mm
JIH E L2 1mm
0.2 vIN=2.0V 3.4V
M3 vOUT
M1
0.1 D W1 = 2mm
vIN=1.5V + L1 1mm
A,B
C vIN
0.0 vIN=1.0V - -
0 1 2 3 4 5
vOUT 5 A B C
D
4
E
M3 active
3 M3 saturated M2 saturated
vOUT
M2 active
2
F
G H
1
M1 sat- M1 I J K
urated active
0
Fig. 5.3-2 0 1 2v
IN
3 4 5
M1 sat. when VGG2-VGS2  VGS1-VT → vIN  0.5(VGG2+VTN) where VGS1=VGS2
M2 sat. when VDS2VGS2-VTN → vOUT-VDS1VGG2-VDS1-VTN → vOUT VGG2-VTN
M3 is saturated when VDD-vOUT  VDD - VGG3 - |VTP| → vOUT  VGG3 + |VTP|
Large-Signal Voltage Swing Limits of the Cascode Amplifier

Maximum output voltage, vOUT(max):
vOUT(max) = VDD
Minimum output voltage, vOUT(min):
Referencing all potentials to the negative power supply (ground in this case), we may
express the current through each of the devices, M1 through M3, as
 vDS12
iD1 = 1 (VDD - VT1)vDS1 -  ≈ 1(VDD - VT1)vDS1
 2 
 (vOUT - vDS1)2
iD2 = 2 (VGG2 - vDS1 - VT2)(vOUT - vDS1) - 
 2 
 2(VGG2 - vDS1 - VT2)(vOUT - vDS1)
and
3
iD3 = 2 (VDD − VGG3 − VT3)2
where we have also assumed that both vDS1 and vOUT are small, and vIN = VDD.
Solving for vOUT by realizing that iD1 = iD2 = iD3 and 1 = 2 we get,
3  1 1 
vOUT(min) = (VDD − VGG3 − VT3)2  + 
22  GG2
V − V T2 V DD − V T1
Small-Signal Midband Performance of the Cascode Amplifier

gm2vgs2= -gm2v1
Small-signal model:
G1 D1=S2 D2=D3
+ + r ds2 +
vin = v1
vgs1 gm1vgs1 rds3 vout
rds1
- - S1=G2=G3 -
Small-signal model of cascode amplifier neglecting the bulk ef fect on M2.
C1 rds2
G1 D1=S2 D2=D3
+ + +
vin 1 v1
gm1vin rds1 gm2 C2 gm2v1 rds3 C3 vout
- - -
Simplified equivalent model of the above circuit. Fig. 5.3-3
Using nodal analysis, we can write,
[gds1 + gds2 + gm2]v1 − gds2vout = −gm1vin
−[gds2 + gm2]v1 + (gds2 + gds3)vout = 0
Solving for vout/vin yields
vout −gm1(gds2 + gm2) −gm1 2K'1W1
vin = gds1gds2 + gds1gds3 + gds2gds3 + gds3gm2  g =−
ds3 L1ID23
The small-signal output resistance is,
rout = [rds1 + rds2 + gm2rds1rds2]rds3  rds3

Frequency Response of the Cascode Amplifier

Small-signal model (RS = 0): C1 rds2
G1 D1=S2 D2=D3
where + + +
vin 1 v1
C1 = Cgd1, gm1vin rds1 gm2 C2 gm2v1 rds3 C3 vout
- - -
C2 = Cbd1+Cbs2+Cgs2, and Fig. 5.3-4A
C3 = Cbd2+Cbd3+Cgd2+Cgd3+CL
The nodal equations now become:
(gm2 + gds1 + gds2 + sC1 + sC2)v1 − gds2vout = −(gm1 − sC1)vin
and −(gds2 + gm2)v1 + (gds2 + gds3 + sC3)vout = 0
Solving for Vout(s)/Vin(s) gives,
Vout(s)  1  −(gm1 − sC1)(gds2 + gm2) 
Vin(s) = 1 + as + bs2 gds1gds2 + gds3(gm2 + gds1 + gds2)
 
C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3)

where a =
gds1gds2 + gds3(gm2 + gds1 + gds2)
C3(C1 + C2)
and b=
gds1gds2 + gds3(gm2 + gds1 + gds2)

A Simplified Method of Finding an Algebraic Expression for the Two Poles

Assume that a general second-order polynomial can be written as:
 s s 1 1 s2
P(s) = 1 + as + bs = 1 − p  1 − p  = 1 − s p + p  + p p
2
 1  2  1 2 1 2
Now if p2 >> p1, then P(s) can be simplified as
s s2
P(s) ≈ 1 − p + p p
1 1 2
Therefore we may write p1 and p2 in terms of a and b as
−1 −a
p1 = a and p2 = b
Applying this to the previous problem gives,
−[gds1gds2 + gds3(gm2 + gds1 + gds2)] −gds3
p1 =  C
C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3) 3
The nondominant root p2 is given as
−[C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3)] −gm2
p2 = 
C3(C1 + C2) C1 + C2
Assuming C1, C2, and C3 are the same order of magnitude, and gm2 is greater than gds3,
then p1 is smaller than p2. Therefore the approximation of p2 >> p1 is valid.
Note that there is a right-half plane zero at z1 = gm1/C1.
Repeating the Previous Example Using Intuitive Approach

Circuit:
VDD Gain:
VPBias1 vout
M3 vout ≈ (-gm1vin) rds3 ⇒ v ≈ -gm1rds3
p1 vout in
VNBias2 rout ≈ rds3 Poles:
gm1vin
M2 p2 1.) Dominant pole (one with the largest resistance to
Rin ground):
+ M1
vIN vin -1
- p1 ≈
120515-01
rds3C3
-1
2.) Next dominant pole is p2 ≈ R (C +C )
in 1 2
1
However, in this case, p1 has already shorted the output to ground so that Rin is ≈ g
m2
2 -gm2
rather than ≈ g . Thus, p2 ≈ C +C .
m2 1 2
Much easier!!!
NON-VOLTAGE DRIVEN CASCODE AMPLIFIER – THE MILLER EFFECT

Miller Effect
Consider the following inverting amplifier:
CM
I1
-Av
+ +
Solve for the input impedance: V1 V2 = -AvV1
- -
V1 060610-03
Zin(s) = I
1
I1 = sCM(V1 – V2) = sCM(V1 + AvV1) = sCM(1 + Av)V1
Therefore,
V1 V1 1 1
Zin(s) = I = sC (1 + A )V = sC (1 + A ) = sC
1 M v 1 M v eq
The Miller effect can take Cgd = 5fF and make it look like a 0.5pF capacitor in parallel
with the input of the inverting amplifier (Av ≈ -100).
If the source resistance is large, this creates a dominant pole at the input.

Simple Inverting Amplifier Driven with a High Source Resistance

Examine the frequency
response of a current-source load
inverter driven from a high
resistance source:
Assuming the input is Iin, the
nodal equations are,
[G1 + s(C1 + C2)]V1 − sC2Vout = Iin and (gm1−sC2)V1+[G3+s(C2+C3)]Vout = 0
where
G1 = Gs (=1/Rs), G3 = gds1 + gds2, C1 = Cgs1, C2 = Cgd1 and C3 = Cbd1+Cbd2 + Cgd2.
Solving for Vout(s)/Vin(s) gives
Vout(s) (sC2−gm1)G1
= or,
Vin(s) G1G3+s[G3(C1+C2)+G1(C2+C3)+gm1C2]+(C1C2+C1C3+C2C3)s2
Vout(s) −gm1 [1−s(C2/gm1)]
Vin(s) =  G3  1+[R1(C1+C2)+R3(C2+C3)+gm1R1R3C2]s+(C1C2+C1C3+C2C3)R1R3s2
 
Assuming that the poles are split allows the use of the previous technique to get,
−1 −1 −gm1C2
p1 =  and p2 
R1(C1+C2)+R3(C2+C3)+gm1R1R3C2 gm1R1R3C2 C1C2+C1C3+C2C3
How Does the Cascode Amplifier Solve the Miller Effect?

Cascode amplifier:
The Miller effect causes Cgs1 to be increased by the value of 1 + (v1/vin) and appear in
parallel with the gate-source of M1 causing a dominant pole to occur.
The cascode amplifier eliminates this problem by keeping the value of v1/vin small by
making the value of Rs2 approximately 2/gm2.

Comparison of the Inverting and Cascode Non-Voltage Driven Amplifiers

The dominant pole of the inverting amplifier with a large source resistance was found to
be
−1 −1
p1(inverter) = ≈ g R R C
R1(C1+C2)+R3(C2+C3)+gm1R1R3C2 m1 1 3 2
Now if a cascode amplifier is used, R3, can be approximated as 2/gm of the cascoding
transistor (assuming the drain sees an rds to ac ground).
−1
 p1(cascode) =
2 2
R1(C1+C2)+ g (C2+C3)+gm1R1g C2
 m  m
−1 −1
= 
2 R1(C1+3C2)
R1(C1+C2)+ g (C2+C3)+2R1C2
 m
Thus we see that p1(cascode) >> p1(inverter).

FURTHER CONSIDERATIONS OF CASCODE AMPLIFIERS

High Gain and High Output Resistance Cascode Amplifier
V
If the load of the cascode M4 DD
VPBias1 D2=D3
amplifier is a cascode +
current source, then both VPBias2 M3
gm2v1 gmbs2v1 rds2 gm3v4 gmbs3v4 rds3
high output resistance vout
M2
and high voltage gain is VNBias2 Rout G1 D1=S2 D4=S3 vout
+ + +
achieved. vin M1
vin v1 rds1 v4 rds4
gm1vin
- - - -
G2=G3=G4=S1=S4 060609-07
The output resistance is,
-1.5
ID
rout  [gm2rds1rds2][gm3rds3rds4] =
12 34
+
2K'2(W/L)2 2K'3(W/L)3
Knowing rout, the gain is simply
-1
2K'1(W/L)1ID
Av = −gm1rout  −gm1{[gm2rds1rds2][gm3rds3rds4]} 
12 34
+
2K'2(W/L)2 2K'3(W/L)3
Example 20-1 - Comparison of the Cascode Amplifier Performance

Calculate the small-signal voltage gain, output resistance, the dominant pole, and the
nondominant pole for the low-gain, cascode amplifier and the high-gain, cascode
amplifier. Assume that ID = 200 microamperes, that all W/L ratios are 2m/1µm, and
that the parameters of Table 3.1-2 are valid. The capacitors are assumed to be: Cgd = 3.5
fF, Cgs = 30 fF, Cbsn = Cbdn = 24 fF, Cbsp = Cbdp = 12 fF, and CL = 1 pF.
Solution
The low-gain, cascode amplifier has the following small-signal performance (no upper
cascode, just lower cascode):
Av = −37.1V/V Rout = 125k
p1  -gds3/C3 → 1.22 MHz p2  -gm2/(C1+C2) → 605 MHz.
The high-gain, cascode amplifier has the following small-signal performance (with upper
and lower cascode):
Av = −414V/V Rout = 1.40 M
p1  -1/RoutC3 → 108 kHz p2  -gm2/(C1+C2) → 579 MHz
(Note at this frequency, the drain of M2 is shorted to ground by the load capacitance, CL)

CURRENT AMPLIFIERS
What is a Current Amplifier?
• An amplifier that has a defined output-input current relationship
• Low input resistance
• High output resistance
Application of current amplifiers:
RS >> Rin and Rout >> RL
Advantages of current amplifiers:

• Currents are not restricted by the power supply voltages so that wider dynamic
ranges are possible with lower power supply voltages.
• -3dB bandwidth of a current amplifier using negative feedback is independent of the
closed loop gain.

Frequency Response of a Current Amplifier with Current Feedback

Consider the following current amplifier with resistive
negative feedback applied.
Assuming that the small-signal resistance looking into

the current amplifier is much less than R1 or R2,
vin 
io = Ai(i1-i2) = Ai R - io
 1 
Solving for io gives
 Ai  vin R2  Ai 
io =   → vout = R2io =   vin
1+A i 1
R R 11+A i
Ao
If Ai(s) = , then
s
+1
A
vout R2
 1  = R2  Ao  = R2  Ao   1 
=
vin R1  1  R1 s  R1 1+Ao 
+1
s
1+ A (s)  +(1+Ao)
 i  A  A(1+Ao) 
 -3dB = A(1+Ao)
Bandwidth Advantage of a Current Feedback Amplifier

The unity-gainbandwidth is,
R2 A o R2 R2
GB = |Av(0)| -3dB = R (1+A ) · A(1+Ao) = R Ao·A = R GBi
1 o 1 1
where GBi is the unity-gainbandwidth of the current amplifier.
Note that if GBi is constant, then increasing R2/R1 (the voltage gain) increases GB.
Illustration: Magnitude dB R
Voltage Amplifier, R2 > K
R2 Ao 1
dB
R1 1+Ao R
Voltage Amplifier, R2 = K >1
Ao 1
K dB
1+Ao Current Amplifier
Ao dB
(1+Ao)wA
0dB wA log10(w)
GBi GB1 GB2
Note that GB2 > GB1 > GBi 141013-01
The above illustration assumes that the GB of the voltage amplifier realizing the voltage
buffer is greater than the GB achieved from the above method.
Current Amplifier using the Simple Current Mirror
1 1 W2/L2
Rin = g Rout = and Ai = W /L .
m1 Io 1 1
Frequency response:
-(gm1+gds1) -(gm1+gds1) -gm1
p1 = = ≈
C1+C2 Cbd1+Cgs1+Cgs2+Cgd2 Cbd1+Cgs1+Cgs2+Cgd2
Note that the bandwidth can be almost doubled by including the resistor, R.
(R removes Cgs1 from p1)

Example 20-2 - Performance of a Simple Current Mirror as a Current Amplifier

Find the small-signal current gain, Ai, the input resistance, Rin, the output resistance,
Rout, and the -3dB frequency in Hertz for the current amplifier of previous slide if 10I1 =
I2 = 100µA and W2/L2 = 10W1/L1 = 10µm/1µm. Assume that Cbd1 = 10fF, Cgs1 = Cgs2 =
100fF, and Cgd2 = 50fF.
Solution
Ignoring channel modulation and mismatch effects, the small-signal current gain,
W2/L2
Ai = W /L  10A/A.
1 1
The small-signal input resistance, Rin, is approximately 1/gm1 and is
1 1
Rin  = = 21.3k
2KN(1/1)10µA 46.9µS
The small-signal output resistance is equal to
1
Rout = = 250k.
NI2
The -3dB frequency is
46.9µS
-3dB = 260fF = 180.4x106 radians/sec. → f-3dB = 28.7 MHz
Wide-Swing, Cascode Current Mirror Implementation of a Current Amplifier

VDD VDD
IIN IOUT
iin iout
+ M3 +
VNBias2 M4
vIN vOUT
M1 M2
- -
060610-01
1 W2/L2
Rin  g , Rout  rds2gm4rds4, and Ai = W /L
m1 1 1

Example 20-3 - Current Amplifier Implemented by the Wide-Swing, Cascode

Current Mirror
Assume that IIN and IOUT of the wide-swing cascode current mirror are 100µA. Find
the value of Rin, Rout, and Ai if the W/L ratios of all transistors are 182µm/1µm.
Solution
The input resistance requires gm1 which is 2·110·182·100 = 2mS
 Rin  500
From our knowledge of the cascode configuration, the small signal output resistance
should be
Rout  gm4rds4rds2 = (2001µS)(250k)(250k) = 125M
Because VDS1 = VDS2, the small-signal current gain is
W2/L2
Ai = =1
W1/L1
Simulation results using the level 1 model for this example give
Rin= 497, Rout = 164.7M and Ai = 1.000 A/A.
The value of VON for all transistors is
2·100µA
VON = = 0.1V
110µA/V2·182
Low-Input Resistance Current Amplifier

To decrease Rin below 1/gm requires feedback but what kind of feedback?
Consider Blackman’s formulation for input resistance:
1 + RR(port shorted)
Rx = Rx(k=0) 1 + RR(port opened)
 
Therefore, we want a configuration where the return ratio (RR) goes to zero when the port
is shorted. We know that the shunt configuration shown below accomplishes this.
It is easy to see that the return ratio for the input shorted is zero and the return ratio for
the input open is,
RR(port opened) = Agm1rds1 ≠ 0
Therefore based on these ideas, a low-input resistance realization is proposed on the next
slide.
Low-Input Resistance Current Amplifier

VDD VDD
Blackmann’s formula:
iin I1 I2 iout
Choosing gm1 as k, we see that, iin i=0
M3 - gm3vgs3
Rx(k=0) = rds1 + +
M1 M2 vin vgs3 rds3 vgs1
The circuits for calculating I3 VGG3 - gm1vgs1 rds1 + -
the shorted and open Fig. 5.4-5
return-ratios are: Current Amplifier
vc
RR(vx = 0): - = 0 RR(ix = 0): vc = - vgs3(1+ gm3rds3) = - gm1rds1 (1+ gm3rds3)vc’
v c'
vc
 RR(ix = 0) = -v ' = gm1rds1 (1+ gm3rds3)
c
1+0 1
Finally, Rx = Rin = rds1 1 + g r (1+ g r ) ≈ g g r
m1 ds1 m3 ds3 m1 m3 ds3
Small signal analysis gives the same result and is much easier to calculate.
Differential-Input, Current Amplifiers

Definitions for the differential-mode, iID, and common-mode, iIC, input currents of the
differential-input current amplifier.
i1+i2
iO = AIDiID ± AICiIC = AID(i1 - i2) ± AIC 2 
 
Implementations:
VDD
VDD VDD VDD M3 M4
iO
I 2I I
i1 iO
M1 M2
i2 i1 i2
i2 VGG1
i1-i2
M1 M2 M3 M4
M5 M6
VGG2
Fig. 5.4-7

SUMMARY
• Low input resistance amplifiers use the source as the input terminal with the gate
generally on ground
• The input resistance to the common gate amplifier depends on what is connected to the
drain
• The voltage driven common gate/common source amplifier has one dominant pole
• The current driven common gate/common source amplifier has two dominant poles
• The cascode amplifier eliminates the input dominant pole for the current driven
common gate/common source amplifier
• Current amplifiers have a low input resistance, high output resistance, and a defined
output-input current relationship
• Input resistances less than 1/gm require feedback
However, all feedback loops have internal poles that cause the benefits of negative
feedback to vanish at high frequencies.
In addition, feedback loops can have a slow time constant from a pole-zero pair.
• Voltage amplifiers using a current amplifier have high values of gain-bandwidth
• Current amplifiers are useful at low power supplies and for switched current
applications
Lecture 21 – Output Amplifiers (6/24/14) Page 21-1
LECTURE 21 – OUTPUT AMPLIFIERS

Outline
• Introduction
• Class A Amplifiers
• Push-Pull Amplifiers
• Bipolar Junction Transistor Output Amplifiers
• Using Negative Feedback to Reduce the Output Resistance
• Summary
Pages 236-247

INTRODUCTION
General Considerations of Output Amplifiers
VDD
Requirements:
1.) Provide sufficient output power in the form of f1(vIN) i1
iOUT
vIN
voltage or current.
+
2.) Avoid signal distortion. f2(vIN) i2 RL vOUT
Buffer -
3.) Be efficient Class A VSS
4.) Provide protection from abnormal conditions i1
Current
(short circuit, over temperature, etc.)
Types of Output Amplifiers: t
i2=IQ iOUT
1.) Class A amplifiers Class AB
i1
2.) Source followers iOUT
Current
t
3.) Push-pull amplifiers
i2
4.) Substrate BJT amplifiers Class B
i1
5.) Amplifiers using negative iOUT
Current
t
shunt feedback i2
Fig. 5.5-005

Output Current Requirements for an Output Amplifier

Consider the current requirements placed by the load on the output amplifier:
vOUT Imax due to RL
iOUT
Output Imax due to CL
t
Amplifier +
CL RL vOUT
- Imax due to RL 070422-01
Result:
|iOUT| > CL·SR
vOUT(peak)
|iOUT| >
RL
Fortunately, the maximum current for the resistor and capacitor do not occur at the same
time.

Output Resistance Requirements for an Output Amplifier

In order to avoid attenuation of the amplifier voltage signal, the output resistance of the
amplifier must be less than the load resistance.
vOA(t) RL
vOUT(t) = v (t)
RL+Rout OA
Volts
Output
vIN Amplifier R
out
vOA t
+
RL vOUT
-
070422-02
To avoid attenuation of the amplifier voltage signal, Rout << RL.

Separation of the Amplifier Bias from the Load Resistance

Unfortunately, when a low load resistance is connected to the output of an amplifier, the
bias conditions can be changed. V DD Loss of bias
current
VBP1
through RL
vOUT
vIN IQ
RL
070422-03
Solution:
1.) Use a coupling capacitance for singled-ended power supplies.
2.) Redefine the output analog ground as (VDD/2).
3.) Use dc coupling for split power supplies.
VDD VDD VDD
VBP1 VBP1 VBP1

IDC = 0
vOUT vOUT 0V vOUT
vIN IQ vIN IQ vIN IQ
RL RL RL
0.5VDD VSS 070422-04

CLASS A AMPLIFIERS
Current source load inverter
VDD i
A Class A circuit has VDD+|VSS| D
RL
current flow in the MOSFETs M2
during the entire period of a VGG2 IQ iOUT RL dominates
vOUT
sinusoidal signal. IQ as the load line
iD1
Characteristics of Class A
amplifiers: vIN M1CL RL vOUT
IQRL IQRL
VSS VDD
• Unsymmetrical sinking and
VSS Fig. 5.5-1
sourcing
• Linear
• Poor efficiency
vOUT(peak)2 vOUT(peak)2
PRL 2RL 2RL vOUT(peak)2
Efficiency = P = (V -V )I = = V 
Supply DD SS Q  (V -V
DD SS )  -V
 DD SS 
(VDD -VSS) 2R 
 L 
Maximum efficiency occurs when vOUT(peak) = VDD = |VSS| which gives 25%.

Small-Signal Performance of the Class A Amplifier

Although we have considered the small-signal performance of the Class A amplifier as
the current source load inverter, let us include the influence of the load.
The modified small-signal model:
C1
+ +
vin rds1 rds2 RL C2 vout
gm1vin
- -
Fig. 5.5-2
The small-signal voltage gain is:
vout -gm1
vin = gds1+gds2+GL
The small-signal frequency response includes:
A zero at
gm1
z =C
gd1
and a pole at
-(gds1+gds2+GL)
p = C +C +C +C +C
gd1 gd2 bd1 bd2 L
Example 21-1 - Design of a Simple Class-A Output Stage

Assume that KN’=2KP’=100µA/V2, VTN = 0.5V and VTP = -0.5V. Design the W/L ratios
of M1 and M2 so that a voltage swing of 1V and a slew rate of 1 V/s is achieved if
RL = 1 k and CL = 1000 pF. Assume VDD = |VSS| = 2V and VGG2 = 0V. Let L = 1 m
and assume that Cgd1 = 100fF. Find the voltage gain and roots of this output amplifier.
Solution
Let us first consider the effects of RL and CL.
iOUT(peak) = ±1V/1k = ±1000µA and CL·SR = 10-9·106 = 1000µA
Since the current for CL and RL occur at different times, choose a bias current of 1mA.
W1 2(IOUT-+IQ) 4000 3µm
= = ≈
L1 KN’(VDD+|VSS| -VTN)2 100·(3.5)2 1µm
and
W2 2IOUT+ 2000 18µm
= = ≈
L2 KP’(VDD-VGG2-|VTP|)2 50·(1.5)2 1µm
The small-signal performance is Av = -0.775 V/V.
The roots are, zero = gm1/Cgd1  1.23GHz and pole ≈ 1/(RLCL)  -159.15 kHz

Broadband Harmonic Distortion

The linearity of an amplifier can be characterized by its influence on a pure sinusoidal
input signal. Assume the input is,
Vin() = Vp sin(t)
The output of an amplifier with distortion will be
Vout() = a1Vp sin (t) + a2Vp sin (2t) +...+ anVp sin(nt)
Harmonic distortion (HD) for the ith harmonic can be defined as the ratio of the
magnitude of the ith harmonic to the magnitude of the fundamental.
For example, second-harmonic distortion would be given as
a2
HD2 = a
1
Total harmonic distortion (THD) is defined as the square root of the ratio of the sum of
all of the second and higher harmonics to the magnitude of the first or fundamental
2 2 2
[a2 + a3 +...+ an]1/2
Thus, THD can be expressed as THD =
a1
The distortion of the class A amplifier is good for small signals and becomes poor at
maximum output swings because of the nonlinearity of the voltage transfer curve for
large-signal swings.
Class-A Source Follower

The class-A source follower has lower output resistance and less attenuation of the
amplifier voltage signal.
N-Channel Source Follower Voltage transfer curve:
with current sink bias: vOUT
VDD
VDD VDD
VDD-VON1 Triode
VDD-VGS1
vIN M1
IQ
iOUT VGS1
VSS |VSS|+VON2+VGS1
vOUT vIN
VDD-VON1+VGS1
M3 M2 RL
VSS VSS IQRL<|VSS|+VON2

Fig. 040-01
Triode |VSS|+VON2
Maximum output voltage swings: |VSS| Fig. 040-02
vOUT(min)  VSS - VON2 (if RL is large)

or vOUT(min)  -IQRL (if RL is small)
vOUT(max) = VDD - VON1 (if vIN > VDD) or vOUT(max)  VDD - VGS1

Output Voltage Swing of the Follower

The previous results do not include the bulk effect on VT1 of VGS1.
Therefore,
VT1 = VT01 + [ 2|F| -vBS- 2|F|] ≈ VT01+ vSB = VT01+1 vOUT(max)-VSS
 vOUT(max)-VSS ≈ VDD-VSS-VON1-VT1 = VDD-VSS-VON1-VT01-1 vOUT(max)-VSS
Define vOUT(max)-VSS = vOUT’(max)
which gives the quadratic,
vOUT’(max)+1 vOUT’(max)-(VDD-VSS -VON1-VT01)=0
Solving the quadratic gives,
12 1 12+ 4(VDD-VSS-VON1-VT01)
vOUT’(max) 
4
-
2
12+4(VDD-VSS-VON1-VT01) + 4
If VDD = 2.5V, N = 0.4V1/2, VTN1= 0.7V, and VON1 = 0.2V, then vOUT’(max) = 3.661V
and
vOUT(max) = 3.661-2.5 = 1.161V

Maximum Sourcing and Sinking Currents for the Source Follower

Maximum Sourcing Current (into a short circuit): VDD VDD
We assume that the transistors are in saturation and vIN M1
VDD = -VSS = 2.5V , thus IQ
iOUT
VSS
K’1W1 vOUT
IOUT(sourcing) = 2L [VDD − vOUT− VT1]2-IQ
1
M3 M2 RL
where vIN is assumed to be equal to VDD. VSS VSS Fig. 040-01

If W1/L1 =10 and if vOUT = 0V, then
VT1 = 1.08V  IOUT equal to 1.11 mA.
However, as vOUT increases above 0V, the current rapidly decreases.
Maximum Sinking Current:
For the current sink load, the sinking current is limited by the bias current.
IOUT(sinking) = IQ
Efficiency of the Class A, source follower:
Same as the Class A, common source which is 25% maximum efficiency
Small Signal Performance of the Source Follower

v
Small-signal model: + gs1 -
+ C1 +
- gm1vgs1 gmbs1vbs1
-
vgs1
+ -
+ C1 +
- gm1vin gm1vout gmbs1vout -
Fig. 040-04
Vout gm1 gm1 gm1RL
Vin = gds1 + gds2 + gm1 + gmbs1+GL  gm1 + gmbs1+GL  1 +gm1RL
If VDD = -VSS = 2.5V, Vout = 0V, W1/L1 = 10m/1 m, W2/L2 = 1m/1 m,
and ID = 500 A, then:
For the current sink load follower (RL = ):
Vout Vout
= 0.869V/V, if the bulk effect were ignored, then = 0.963V/V
Vin Vin
For a finite load, RL = 1000
Vout
Vin = 0.512V/V
Small Signal Performance of the Source Follower - Continued

The output resistance is:
1
Rout = g + g
m1 mbs1 + gds1 + gds2
For the current sink load follower:
Rout = 830
The frequency response of the source follower:
Vout(s) (gm1 + sC1)
Vin(s) = gds1 + gds2 + gm1 + gmbs1 + GL + s(C1 + C2)
where
C1 = capacitances connected between the input and output  CGS1
C2 = Cbs1 +Cbd2 +Cgd2(or Cgs2) + CL
gm1 gm1+GL
z=- C and p  - C +C
1 1 2
The presence of a LHP zero leads to the possibility that in most cases the pole and zero
will provide some degree of cancellation leading to a broadband response.
PUSH-PULL AMPLIFIERS
Push-Pull Source Follower VDD VDD
VDD
Can both sink and source M1
M6
VGG
current and provide a slightly M5 M1 VSS
VBias VSS
lower output resistance. VSS iOUT
vIN iOUT vOUT
VBias vOUT
RL VDD M4 M2 VDD RL
M2 VDD
Efficiency: vIN M3
Depends on how the transistors VSS
VSS VSS Fig. 060-01
are biased.
• Class B - one transistor has current flow for only 180° of the sinusoid (half period)
vOUT(peak)2
PRL 2RL  vOUT(peak)
 Efficiency = P = 1 2v
=2 V
VDD   OUT (peak)  DD -VSS
(VDD -VSS)2  
   R L 
Maximum efficiency occurs when vOUT(peak) =VDD and is 78.5%
• Class AB - each transistor has current flow for more than 180° of the sinusoid.
Maximum efficiency is between 25% and 78.5%
Illustration of Class B and Class AB Push-Pull, Source Follower

Output current and voltage characteristics of the push-pull, source follower (RL = 1k):
2V 1mA 2V 1mA
vG1 vG1 iD1
iD1
1V 1V
0V 0mA 0V 0mA
vout vG2 vout vG2
-1V -1V
iD2 iD2
-2V -1mA -2V -1mA
-2 -1 0 1 2 -2 -1 0 1 2
Vin(V) Vin(V)
Class B, push-pull, source follower Class AB, push-pull, source follower Fig. 060-02
Comments:
• Note that vOUT cannot reach the extreme values of VDD and VSS
• IOUT+(max) and IOUT-(max) is always less than VDD/RL or VSS/RL
• For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB
• Note that there is significant distortion at vIN =0V for the Class B push-pull follower

Small-Signal Performance of the Push-Pull Follower

Model: v
+ gs1 -
+ C1 +
- gm1vgs1 gmbs1vbs1 gm2vgs2 gmbs2vbs2 -
vgs1
+ -
+ C1 +
vin 1 RL C2 vout
g
- gm1vin gm1vout gmbs1vout rds1 gm2vin gm2vout m2gmbs2vout rds2 -
Fig. 060-03
vout gm1 + gm2
vin = gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL
1
Rout = g +g +g +g (does not include RL)
ds1 ds2 m1 mbs1+gm2+gmbs2
If VDD = -VSS = 2.5V, Vout = 0V, ID1 = ID2 = 500µA, and W/L = 20µm/2µm, Av = 0.787
(RL=) and Rout = 448.
A zero and pole are located at
-(gm1+gm2) -(gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL)
z= and p=
C1 C1+C2
These roots will be at high frequencies because the associated resistances are small.
Push-Pull, Common Source Amplifiers

Similar to the class A but can operate as class B providing higher efficiency.
VDD
M2
VTR2 iOUT
vIN vOUT
VTR1
M1CL RL
VSS Fig. 060-04

Comments:
• The batteries VTR1 and VTR2 are necessary to control the bias current in M1 and M2.
• The efficiency is the same as the push-pull, source follower.

Illustration of Class B and Class AB Push-Pull, Inverting Amplifier

Output current and voltage characteristics of the push-pull, inverting amplifier (RL =
1k):
vG2
2V 2mA 2V vG2 2mA
iD1
vG1 vG1
1V 1mA 1V 1mA
iD1 iD2 iD1
iD1
0V 0mA 0V 0mA
iD2 iD2
-1V -1mA -1V iD2 vOUT -1mA
vOUT
-2V -2mA -2V -2mA
-2V -1V 0V 1V 2V -2V -1V 0V 1V 2V

vIN vIN
Class B, push-pull, inverting amplifier. Class AB, push-pull, inverting amplifier. Fig.060-06
Comments:
• Note that there is significant distortion at vIN =0V for the Class B inverter
• Note that vOUT cannot reach the extreme values of VDD and VSS
• IOUT+(max) and IOUT-(max) is always less than VDD/RL or VSS/RL
• For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB

Practical Implementation of the Push-Pull, Common Source Amplifier – Method 1
VDD
M5 M6
M1 M3 VGG3
iOUT
vIN vOUT
M2 M4 VGG4
CL RL
M7 M8
VSS Fig. 060-05
VGG3 and VGG4 can be used to bias this amplifier in class AB or class B operation.
Note, that the bias current in M6 and M8 is not dependent upon VDD or VSS (assuming
VGG3 and VGG4 are not dependent on VDD and VSS).

Practical Implementation of the Push-Pull, Common Source Amplifier – Method 2

In steady-state, the current through M5 and M6 is 2Ib. If W4/L4 = W9/L9 and W3/L3 =
W8/L8, then the currents in M1 and M2 can be determined by the following relationship:
W1/L1   W2/L2 
I1 = I2 = Ib W /L = Ib W /L 
  VDD
 7 7  10 10
M5
If vin+goes low, M5 pulls the gates of M1 and M7 I=2Ib Ib
M2 high. M4 shuts off causing all of the vin+ M1
current flowing through M5 (2Ib) to flow
M8 M3 M4 M9
through M3 shutting off M1. The gate of M2 is
vin-
high allowing the buffer to strongly sink M2
M6
current. If vin- goes high, M6 pulls the gates of Ib I=2Ib M10
M1 and M2 low. As before, this shuts off M2
and turns on M1 allowing strong sourcing. VSS Fig. 060-055

Additional Methods of Biasing the Push-Pull Common-Source Amplifier
VDD
VDD -VT+VSat
VDD
IBias
VDD -VT+2VSat
vOUT VB2 VB1 vOUT
VT+2VSat vIN
vIN
050423-10
050423-08

BIPOLAR JUNCTION TRANSISTOR OUTPUT AMPLIFIERS

What about the use of BJTs?
VDD VDD VDD
M3
Q1 M2
iB vout vout
iB
Comments: M2 Q1
CL M3 CL
• Can use either substrate
VSS VSS VSS
or lateral BJTs. p-well CMOS n-well CMOS Fig. 5.5-8A
• Small-signal output resistance is 1/gm which can easily be less than 100.
• Unfortunately, only PNP or NPN BJTs are available but not both on a standard CMOS
technology.
• BJTs will cause substrate current unless they surrounded by a deep well
• In order for the BJT to sink (or source) large currents, the base current, iB, must be
large. Providing large currents as the voltage gets to extreme values is difficult for
MOSFET circuits to accomplish.
• If one considers the MOSFET driver, the emitter can only pull to within vBE+VON of
the power supply rails. This value can be 1V or more.
Low Output Resistance using BJTs

The output resistance of a class A BJT stage is:
VDD
r1 + RB 1 RB RB
Rout = =g + Q1
1+F m1 1+F Rout
vIN
VBN1
Note that the second term must be less than 1/gm1 in order to M2
achieve the low output resistance possible. 070423-02
Consequently, the driver for the BJT should be a MOS follower as shown:
VDD VDD
r1 + 1/gm3 1 1 1
Rout = =g + ≈g M3
1+F m1 gm3(1+F) m1 vIN
Q1
Rout
VBN1
M2
M4
070423-03
We will consider the BJT as an output stage in more detail later.

USING NEGATIVE FEEDBACK TO REDUCE THE OUTPUT RESISTANCE

Concept
Use negative shunt feedback – Class A implementation:
VDD VBP1 VDD
VDD VBP1
VBP1 M7
M2
M2
vIN vOUT vIN vOUT
M3 M4
- +
A
M1 M5 M6 M1
070423-01
rds1||rds2 1
Rout = 1+Loop Gain ≈ ≈ 10 if gm = 500µS and gmrds ≈ 100.
2gm2rds
The actual value of Rout will be influenced by the value of RL, particularly if it is small.

Push-Pull Implementation
rds1||rds2
Rout = 1+Loop Gain
Comments:
• Can achieve output resistances as low as 10.
• If the error amplifiers are not balanced, it is difficult to control the quiescent current in
M1 and M2
• Great linearity because of the strong feedback
• Can be efficient if operated in class B or class AB
• We will consider this circuit in more detail in a later lecture.
Boosting the Transconductance of the Source Follower

The following configuration allows the output resistance of the source follower to be
decreased by a factor of K, where K is the current ratio between M4 and M3.
VDD
1:K
M3 M4
vIN
M1
vOUT
VBN1 Rout
M2
070423-04
1
Rout =
gm1K

SUMMARY
• The objectives are to provide output power in form of voltage and/or current.
• In addition, the output amplifier should be linear and be efficient.
• Low output resistance is required to provide power efficiently to a small load resistance.
• High source/sink currents are required to provide sufficient output voltage rate due to
large load capacitances.
• Types of output amplifiers considered:
Class A amplifier
Source follower
Class B and AB amplifier
Use of BJTs
Negative shunt feedback

Lecture 22 – Compensation of Op Amps (6/24/14) Page 22-1
LECTURE 22 – INTRODUCTION TO OP AMPS

LECTURE OUTLINE
Outline
• Op Amps
• Categorization of Op Amps
• Compensation of Op Amps
• Miller Compensation
• Other Forms of Compensation
• Op Amp Slew Rate
• Summary
Pages 261-286

OP AMPS
What is an Op Amp?
The op amp (operational amplifier) is a high gain, dc coupled amplifier designed to
be used with negative feedback to precisely define a closed loop transfer function.
The basic requirements for an op amp:
• Sufficiently large gain (the accuracy of the signal processing determines this)
• Differential inputs
• Frequency characteristics that permit stable operation when negative feedback is
applied
Other requirements:
• High input impedance
• Low output impedance
• High speed/frequency

Why Op Amps?
The op amp is designed to be used with single-loop, negative feedback to accomplish
precision signal processing as illustrated below.
Single-Loop Negative Feedback Network Op Amp Implementation of a Single-Loop
Negative Feedback Network
Feedback Network
Vf(s) Vf(s)
F(s) F(s)
- Vout(s) Vout(s)
Vin(s) + -
S A(s) Vin(s)
+
Av(s)
Op Amp 060625-01
Vout(s)
The voltage gain, V (s) , can be shown to be equal to,
in
Vout(s) Av(s)
Vin(s) = 1+Av(s)F(s)
If the product of Av(s)F(s) is much greater than 1, then the voltage gain becomes,
Vout(s) 1
The precision of the voltage gain is defined by F(s).
Vin(s) ≈ F(s)

OP AMP CHARACTERIZATION
Linear and Static Characterization of the CMOS Op Amp
A model for a nonideal op amp that includes some of the linear, static nonidealities:
where
Rid = differential input resistance
Cid = differential input capacitance
Ricm = common mode input resistance
Ricm = common mode input capacitance
VOS = input-offset voltage
CMRR = common-mode rejection ratio (when v1=v2 an output results)
en2 = voltage-noise spectral density (mean-square volts/Hertz)
Linear and Dynamic Characteristics of the Op Amp

Differential and common-mode frequency response:
V1(s)+V2(s)
Vout(s) = Av(s)[V1(s) - V2(s)] ± Ac(s)  
 2 
Differential-frequency response:
Av0 Av0 p1p2p3···
Av(s) = s = (s -p )(s -p )(s -p )···
  s  s  1 2 3
p - 1p - 1p - 1···
 1  2  3 
where p1, p2, p3,··· are the poles of the differential-frequency response (ignoring zeros).

Other Characteristics of the Op Amp

Power supply rejection ratio (PSRR):
VDD Vo/Vin (Vdd = 0)
PSRR = Av(s) = V /V (V = 0)
VOUT o dd in
Input common mode range (ICMR):
ICMR = the voltage range over which the input common-mode signal can vary
without influence the differential performance
Slew rate (SR):
SR = output voltage rate limit of the op amp
Settling time (Ts):

OP AMP CATEGORIZATION
Classification of CMOS Op Amps
Conversion Hierarchy
Voltage Classic Differential Modified Differential

to Current Amplifier Amplifier
First
Voltage
Stage
Current Differential-to-single ended Source/Sink MOS Diode
to Voltage Load (Current Mirror) Current Loads Load
Current
Voltage Transconductance Transconductance Stage
to Current Grounded Gate Grounded Source
Second
Voltage
Current Class A (Source Class B Stage
to Voltage or Sink Load) (Push-Pull)
Table 110-01

Two-Stage CMOS Op Amp

Classical two-stage CMOS op amp broken into voltage-to-current and current-to-voltage
stages:

Folded Cascode CMOS Op Amp

Folded cascode CMOS op amp broken into stages.

COMPENSATION OF OP AMPS
Compensation
Objective
Objective of compensation is to achieve stable operation when negative feedback is
applied around the op amp.
Types of Compensation
1. Miller - Use of a capacitor feeding back around a high-gain, inverting stage.
• Miller capacitor only
• Miller capacitor with an unity-gain buffer to block the forward path through the
compensation capacitor. Can eliminate the RHP zero.
• Miller with a nulling resistor. Similar to Miller but with an added series resistance
to gain control over the RHP zero.
2. Self compensating - Load capacitor compensates the op amp (later).
3. Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can
be less than unity.
Because compensation plays such a strong role in design, it is considered before design.

Single-Loop, Negative Feedback Systems

Block diagram:
A(s) = differential voltage gain of the op amp
F(s) = feedback transfer function
Definitions:
• Open-loop gain = L(s) = -A(s)F(s)
Vout(s) A(s)
• Closed-loop gain = V (s) = 1+A(s)F(s)
in
Stability Requirements for a Single-Loop, Negative Feedback System:
At the frequency where the phase-shift of the loop is 0°, the magnitude of the loop must
be less than 1. This is expressed as,
A(j0°)F(j0°) = L(j0°)  1
where 0° is defined as
Arg[-A(j0°)F(j0°)] = Arg[L(j0°)] = 0°
Alternately, at the frequency where the loop gain is unity, the phase shift must be greater
than 0°. This expressed as,
Arg[-A(j0dB)F(jw0dB)] = Arg[L(j0dB)]  0°
where 0dBis defined as
A(j0dB)F(j0dB) = L(j0dB) = 1
Illustration of the Stability Requirement using Bode Plots

|A(jw)F(jw)|
-20dB/decade
Note that the loop phase

0dB w
-40dB/decade shift starts at ±180°. We
180° have chosen +180° for
Arg[-A(jw)F(jw)]
this analysis. If we had

135° selected -180°, then the
90°
vertical axis would
be -180°, -225°, -270°,
45° -315°, and finally -360°.
FM
0° w0dB w
Frequency (rads/sec.) 150128-01
A measure of stability is given by the phase when |A(j)F(j)| = 1. This phase is called
phase margin.
Phase margin = M = Arg[-A(j0dB)F(j0dB)] = Arg[L(j0dB)]

Why Do We Want Good Stability?

Consider the step response of second-order system that closely models the closed-loop
gain of the op amp connected in unity gain.
A “good” step response is one that quickly reaches its final value.
Therefore, we see that phase margin should be at least 45° and preferably 60° or larger.
(A rule of thumb for satisfactory stability is that there should be less than three rings.)
Note that good stability is not necessarily the quickest rise time.
Uncompensated Frequency Response of Two-Stage Op Amps

Two-Stage Op Amps: VDD VCC
M3 M4 Q3 Q4
M6 Q6
vout vout
- M1 M2 - Q1 Q2
vin vin
+ +
+ M7 + Q7
VBias M5 VBias Q5
- -
VSS VEE Fig. 120-04
Small-Signal Model:
D1, D3 (C1, C3) D2, D4 (C2, C4) D6, D7 (C6, C7)

+ + +
g v
gm1vin R1 C1 v1 m2 in v2 R3 C3 vout
gm4v1 R2 C2
- gm6v2
2
2 - -
Fig. 120-05
Note that this model neglects the base-collector and gate-drain capacitances for purposes
of simplification.

Uncompensated Frequency Response of Two-Stage Op Amps - Continued

For the MOS two-stage op amp:
1 1
R1  g ||rds3||rds1  g R2 = rds2|| rds4 and R3 = rds6|| rds7
m3 m3
C1 = Cgs3+Cgs4+Cbd1+Cbd3 C2 = Cgs6+Cbd2+Cbd4 and C3 = CL +Cbd6+Cbd7
For the BJT two-stage op amp:
1 1
R1 = g ||r3||r4||ro1||ro3g R2 = r6|| ro2|| ro4  r6 and R3 = ro6|| ro7
m3 m3
C1 = C3+C4+Ccs1+Ccs3 C2 = C6+Ccs2+Ccs4 and C3 = CL+Ccs6+Ccs7
Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives,
+ + + +
gm1vin v2 R3 C3 vout gm1Vin VI RII CII Vout
R2 C2 RI CI
- gm6v2 - - gmIIVI -
Fig. 120-06
The locations for the two poles are given by the following equations
-1 -1
p’1 = R C and p’2 = R C
I I II II
where RI (RII) is the resistance to ground seen from the output of the first (second) stage
and CI (CII) is the capacitance to ground seen from the output of the first (second) stage.

Uncompensated Frequency Response of an Op Amp (F(s) = 1)

Avd(0) dB
-20dB/decade
|A(jw)|
GB
0dB log10(w)
Phase Shift -40dB/decade
-45/decade
180°
Arg[-A(jw)]
135°
-45/decade
90°
45°
0° log10(w)
|p1'| |p2'| w0dB 150128-02
If we assume that F(s) = 1 (this is the worst case for stability considerations), then the
above plot is the same as the loop gain.
Note that the phase margin is much less than 45° (≈ 6°).
Therefore, the op amp must be compensated before using it in a closed-loop
configuration.
MILLER COMPENSATION
Miller Compensation of the Two-Stage Op Amp
VDD VCC
M3 M4
Q3 Q4
CM M6 CM Q6
Cc vout Cc vout
M1 M2 Q1 Q2
- -
vin CI CII vin CI CII
+ +
+ M7 + Q7
VBias M5 VBias Q5
- -
VSS VEE Fig. 120-08
The various capacitors are:

Cc = accomplishes the Miller compensation
CM = capacitance associated with the first-stage mirror (mirror pole)
CI = output capacitance to ground of the first-stage
CII = output capacitance to ground of the second-stage

Compensated Two-Stage, Small-Signal Frequency Response Model Simplified

Use the CMOS op amp to illustrate:
1.) Assume that gm3 >> gds3 + gds1
gm3
2.) Assume that C >> GB
M
Therefore,
Cc
v1 v2
+
-gm1vin vout
1 gm2vin
2
rds1||rds3 CM gm3 2 gm4v1 C1 rds2||rds4 gm6v2 rds6||rds7 CL -
Cc
v2
+ +
vin gm1vin CI CII vout
rds2||rds4 gm6v2 rds6||rds7
- -
Fig. 120-09
Same circuit holds for the BJT op amp with different component relationships.

General Two-Stage Frequency Response Analysis

Cc where
V2
+ + gmI = gm1 = gm2, RI = rds2||rds4, CI = C1
Vin gmIVin Vout and
CI RI gmIIV2 RII CII
- -
Fig.120-10
gmII = gm6, RII = rds6||rds7, CII = C2 = CL
Nodal Equations:
-gmIVin = [GI + s(CI + Cc)]V2 - [sCc]Vout and 0 = [gmII - sCc]V2 + [GII + sCII + sCc]Vout
Solving using Cramer’s rule gives,
Vout(s) gmI(gmII - sCc)
Vin(s) = GIGII+s [GII(CI+CII)+GI(CII+Cc)+gmIICc]+s2[CICII+CcCI+CcCII]
Ao[1 - s (Cc/gmII)]
= 1+s [R (C +C )+R (C +C )+g R R C ]+s2[R R (C C +C C +C C )]
I I II II 2 c mII 1 II c I II I II c I c II
where, Ao = gmIgmIIRIRII
 s s 1 1  s2 s s2
In general, D(s) = 1-p  1-p  = 1-s p + p +p p → D(s) ≈ 1-p + p p , if |p2|>>|p1|
 1  2  1 2 1 2 1 1 2
-1 -1 gmII
 p1 = R (C +C )+R (C +C )+g R R C ≈ g R R C , z= C
I I II II II c mII 1 II c mII 1 II c c
-[RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc] -gmIICc -gmII

p2 = ≈C C +C C +C C ≈ C , CII > Cc > CI
R R (C C +C C +C
I II I II c I c II
C ) I II c I c II II © P.E. Allen - 2016
Summary of Results for Miller Compensation of the Two-Stage Op Amp

There are three roots of importance:
1.) Right-half plane zero:
gmII gm6
z1= C = C
c c
This root is very undesirable- it boosts the magnitude while decreasing the phase.
2.) Dominant left-half plane pole (the Miller pole):
-1 -(gds2+gds4)(gds6+gds7)
p1 ≈ g R R C =
mII I II c gm6Cc
This root accomplishes the desired compensation.
3.) Left-half plane output pole:
-gmII -gm6
p2 ≈ C ≈ C
II L
p2 must be ≥ unity-gainbandwidth or satisfactory phase margin will not be achieved.
Root locus plot of the Miller compensation:

Compensated Open-Loop Frequency Response of the Two-Stage Op Amp
Avd(0) dB Uncompensated
|A(jw)F(jw)| -20dB/decade
F(jw)=1
Compensated
GB
0dB log10(w)
Phase Shift -40dB/decade
Uncompensated
180°
Arg[-A(jw)F(jw)|
-45°/decade
135°
F(jw)=1
90° -45°/decade
Compensated Phase
45°
No phase margin Margin
0° log10(w)
|p1| |p1'| |p2'| |p2|
150128-04
Note that the unity-gainbandwidth, GB, is

1 gmI gm1 gm2
GB = Avd(0)·|p1| = (gmIgmIIRIRII)g R R C = C = C = C
mII I II c c c c
Conceptually, where do these roots come from?

1.) The Miller pole:
1
|p1| ≈ R (g R C )
I m6 II c
2.) The left-half plane output pole:
gm6
|p2| ≈ C
II
3.) Right-half plane zero (One source of zeros is from multiple paths from the input to
output): VDD
 gm6  RII
-RIIsC - 1 Cc
-gm6RII(1/sCc)  RII   c  vout
   
vout = R + 1/sC v’ + R + 1/sC v’’ = R + 1/sC v
 II c   II c II c v''
M6
v'
where v = v’ = v’’. Fig. 120-15

Further Comments on p2
The previous observations on p2 can be proved as follows:
Find the resistance RCc seen by the compensation capacitor, Cc.
Cc VDD
vx
RCc RII
RCc
ix ix
M6 +
RI RI vgs6 RII
- gm6vgs6
060626-02
vx = ixRI + (ix + gm6vgs6)RII = ixRI + (ix + gm6ixRI)RII

Therefore,
vx
RCc = i = RI + (1 + gm6RI)RII ≈ gm6RIRII
x
The frequency at which Cc begins to become a short is,
1 1
< gm6RIRII  > gm6RIRII Cc ≈ |p1|
Cc or
Thus, at the frequency where CII begins to short the output, Cc is acting as a short.
Influence of the Mirror Pole

Up to this point, we have neglected the influence of the pole, p3, associated with the
current mirror of the input stage. A small-signal model for the input stage that includes
C3 is shown below:
i3 +
gm1Vin gm2Vin Vo1
2 1 i3
rds1 rds3 gm3 C3 2 rds2 rds4 -
Fig. 120-16
The transfer function from the input to the output voltage of the first stage, Vo1(s), can be
written as
Vo1(s) -gm1  gm3+gds1+gds3  -gm1 sC3 + 2gm3
Vin(s) = 2(gds2+gds4) gm3+ gds1+gds3+sC3 + 1  2(gds2+gds4)  sC3 + gm3 
   
VDD
We see that there is a pole and a zero given as
gm3 2gm3
p3 = - C and z3 = - C gmvin
3 3 C3 gmvin
2
Normally, the mirror pole will have negligible + 2
vin
influence on the stability of the op amp. -
VBias
140521-01
Summary of the Conditions for Stability of the Two-Stage Op Amp

• Unity-gainbandwith is given as:
 1  gmI
GB = Av(0)·|p1| =(gmIgmIIRIRII)·g R R C  = C =
 mII I II c c
 1  gm1
(gm1gm2R1R2)· =
gm2R1R2Cc Cc
• The requirement for 45° phase margin is:
  
±180° - Arg[Loop Gain] = ±180° - tan-1|p | - tan-1|p | - tan-1 z  = 45°
 1  2  
Let  = GB and assume that z  10GB, therefore we get,
GB
GB  GB
±180° - tan-1|p | - tan-1|p | - tan-1 z  = 45°
 1  2  
GB GB
135°  tan (Av(0)) + tan |p | + tan (0.1) = 90° + tan |p | + 5.7°
-1 -1 -1 -1
 2  2
GB GB
39.3°  tan-1   = 0.818  |p2|  1.22GB
|p2| |p2|
• The requirement for 60° phase margin: |p2|  2.2GB if z  10GB
• If 60° phase margin is required, then the following relationships apply:

gm6 10gm1 gm6 2.2gm1

 
Cc > Cc gm6 > 10gm1 and C > C Cc > 0.22C2
2 c

OTHER FORMS OF COMPENSATION

Feedforward Compensation
Use two parallel paths to achieve a LHP zero for lead compensation purposes.
RHP Zero Cc LHP Zero Cc LHP Zero using Follower
A -A Cc
Vi Vout Vi Vout Vi Vout

+1
Inverting Inverting
High Gain CII RII High Gain CII RII
Amplifier Amplifier
Cc
A
+ +
Vi gmIIVi CII RII Vout
s + gmII/ACc
- -
Vout(s) ACc   Fig.430-09
Vin(s) = Cc + CII s + 1/[RII(Cc + CII)]

 
To use the LHP zero for compensation, a compromise must be observed.

• Placing the zero below GB will lead to boosting of the loop gain that could deteriorate
the phase margin.
• Placing the zero above GB will have less influence on the leading phase caused by the
zero.
Note that a source follower is a good candidate for the use of feedforward compensation.
Self-Compensated Op Amps
Self compensation occurs when the load capacitor is the compensation capacitor (can
never be unstable for resistive feedback)
Voltage gain:
vout
vin = Av(0) = GmRout
Dominant pole: Stability:
-1 Large load capacitors simply reduce
p1 = R GB but the phase is still 90° at GB.
outCL
Unity-gainbandwidth:
Gm
GB = Av(0)·|p1| = C
L
FINDING ROOTS BY INSPECTION

Identification of Poles from a Schematic
1.) Most poles are equal to the reciprocal product of the resistance from a node to ground
and the capacitance connected to that node.
2.) Exceptions (generally due to feedback):
a.) Negative feedback:
C3
C2 C2
-A -A
R1 C1 R1 C1 C3(1+A)
RootID01
b.) Positive feedback (A<1):

C3
C2 C2
+A +A
R1 C1 R1 C1 C3(1-A)
RootID02

Identification of Zeros from a Schematic

1.) Zeros arise from poles in
the feedback path.
1
If F(s) = s ,
+1
p1
s 
A(s) +1
Vout A(s) A(s) p1 
then V = 1+A(s)F(s) = =s
in 1
1+A(s) s p1 +1+ A(s) VDD
p1 +1 Cc
RII
vout
2.) Zeros are also created by two paths from the input to the M6
output and one or more of the paths is frequency dependent. v''
v'
3.) Zeros also come from simple RC networks. 070425-01
C1
+ + Vout s + 1/(R1C1)
Vin R1 R2 Vout =
Vin s + 1/(R1||R2)C1
- -
070425-02
CMOS OP AMP SLEW RATE

Slew Rate of a Two-Stage CMOS Op Amp
Remember that slew rate occurs when currents flowing in a capacitor become limited
and is given as
dvC
Ilim = C dt where vC is the voltage across the capacitor C.
 I5 I6-I5-I7 I5  I5 I7-I5 I5
SR = minC , C  = C because I6>>I5
+ SR = minC , C  = C if I7>>I5.
-
 c L  c  c L  c
Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew
rate of the two-stage op amp should be, I5/Cc.
SUMMARY
• Op amps achieve accuracy by using negative feedback
• Compensation is required to insure that the feedback loop is stable
• The degree of stability is measured by phase margin and is necessary to achieve small
settling times
• A compensated op amp will have one dominant pole and all other poles will be greater
than GB
• A two-stage op amp requires some form of Miller compensation
• A high output resistance op amp is compensated by the load capacitor
• Poles of a CMOS circuit are generally equal to the negative reciprocal of the product of
the resistance to ground from a node times the sum of the capacitances connected to
that node.
• The slew rate of the two-stage op amp is equal to the input differential stage current
sink/source divided by the Miller capacitor

Lecture 23 – Design of Two-Stage Op Amps (3/11/16) Page 23-1
LECTURE 23 – DESIGN OF TWO-STAGE OP AMPS

LECTURE OUTLINE
Outline
• Steps in Designing an Op Amp
• Design Procedure for a Two-Stage Op Amp
• Design Example of a Two-Stage Op Amp
• Right Half Plane Zero
• PSRR of the Two-Stage Op Amp
• Summary
Pages 286-309

STEPS IN DESIGNING A CMOS OP AMP

Design Inputs
Boundary conditions:
1. Process specification (VT, K', Cox, etc.)
2. Supply voltage and range
3. Supply current and range
4. Operating temperature and range
Requirements:
1. Gain 8. Output-voltage swing
2. Gain bandwidth 9. Output resistance
3. Settling time 10. Offset
4. Slew rate 11. Noise
5. Common-mode input range, ICMR 12. Layout area
6. Common-mode rejection ratio, CMRR
7. Power-supply rejection ratio, PSRR

Outputs of Op Amp Electrical Design

The basic outputs are:
1.) The topology
2.) The dc currents
3.) The W and L values of transistors
4.) The values of components
Op amp circuit VDD
or systems M3 M4 Cc
M6
Topology
specifications
vout
-
vin
M1 M2 CL L
+
+ M7
VBias
-
M5 W
VSS
DC Currents
Design of 50µA
CMOS
Op Amps
W/L ratios
Component C R
values
060625-06

Some Practical Thoughts on Op Amp Design

1.) Decide upon a suitable topology.
• Experience is a great help
• The topology should be the one capable of meeting most of the specifications
• Try to avoid “inventing” a new topology but start with an existing topology
2.) Determine the type of compensation needed to meet the specifications.
• Consider the load and stability requirements
• Use some form of Miller compensation or a self-compensated approach
3.) Design dc currents and device sizes for proper dc, ac, and transient performance.
• This begins with hand calculations based upon approximate design equations.
• Compensation components are also sized in this step of the procedure.
• After each device is sized by hand, a circuit simulator is used to fine tune the
design
Two basic steps of design:
1.) “First-cut” - this step is to use hand calculations to propose a design that has
potential of satisfying the specifications. Design robustness is developed in this
step.
2.) Optimization - this step uses the computer to refine and optimize the design.
A DESIGN PROCEDURE FOR THE TWO-STAGE CMOS OP AMP

Unbuffered, Two-Stage CMOS Op Amp
VDD
M6
M3 M4 Cc
vout
- M1 M2 CL
vin
+
+ M7
VBias M5
-
VSS Fig. 6.3-1
Notation:
Wi
Si = L = W/L of the ith transistor
i

DC Balance Conditions for the Two-Stage Op Amp

For best performance, keep all transistors in VDD
VSG4 + VSG6 +
saturation. - -
M6
M4 is the only transistor that cannot be forced into M3 M4 I4 Cc I6
vout
saturation by internal connections or external voltages.
- M1 M2 CL
Therefore, we develop conditions to force M4 to be in vin I7
saturation. +
I5
M7
1.) First assume that VSG4 = VSG6. This will cause +
VBias M5
“proper mirroring” in the M3-M4 mirror. Also, the -
VSS
Fig. 6.3-1A
gate and drain of M4 are at the same potential so that
M4 is “guaranteed” to be in saturation.
S6
2.) If VSG4 = VSG6, then I6 = S I4
 4
S7 S7
3.) However, I7 = S I5 = S  (2I4)
 5  5
S6 2S7
4.) For balance, I6 must equal I7  called the “balance conditions”
S4 = S5
5.) So if the balance conditions are satisfied, then VDG4 = 0 and M4 is saturated.
Summary of the Design Relationships for the Two-Stage Op Amp

I5
Slew rate SR = C (Assuming I7 >>I5 and CL > Cc)
c
gm1 2gm1
First-stage gain Av1 = g + g = I (l + l )
ds2 ds4 5 2 4
gm6 gm6
Second-stage gain Av2 = g + g = I (l + l )
ds6 ds7 6 6 7
gm1
Gain-bandwidth GB = C
c
-gm6
Output pole p2 = C
L
gm6
RHP zero z1 = C
c
60° phase margin requires that gm6 = 2.2gm2(CL/Cc) if all other roots are  10GB.
I5
Positive ICMR Vin(max) = VDD - b3 - VT03(max) + VT1(min))
I5
Negative ICMR Vin(min) = VSS + b1 + VT1(max) + VDS5(sat)
Op Amp Specifications
The following design procedure assumes that specifications for the following parameters
are given.
1. Gain at dc, Av(0)
2. Gain-bandwidth, GB
3. Phase margin (or settling time)
4. Input common-mode range, ICMR
5. Load Capacitance, CL
6. Slew-rate, SR
7. Output voltage swing
8. Power dissipation, Pdiss

Unbuffered Op Amp Design Procedure

This design procedure assumes that the gain at dc (Av), unity gain bandwidth (GB), input
common mode range (Vin(min) and Vin(max)), load capacitance (CL), slew rate (SR),
settling time (Ts), output voltage swing (Vout(max) and Vout(min)), and power dissipation
(Pdiss) are given. Choose the smallest device length which will keep the channel
modulation parameter constant and give good matching for current mirrors.
1. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60° phase
margin we use the following relationship. This assumes that z  10GB.
Cc  0.22CL
2. Determine the minimum value for the “tail current” (I5) from
I5 = SR .Cc
3. Design for S3 from the maximum input voltage specification.
I5
S3 = K' [V − V (max) − V (max) + V (min)]2
3 DD in T03 T1
4. Verify that the pole of M3 due to Cgs3 and Cgs4 (= 0.67W3L3Cox) will not be dominant
by assuming it to be greater than 10 GB
gm3
2Cgs3 > 10GB.
Unbuffered Op Amp Design Procedure - Continued

5. Design for S1 (S2) to achieve the desired GB.
gm12
gm1 = GB . Cc → S2 = K' I
1 5
6. Design for S5 from the minimum input voltage. First calculate VDS5(sat) then find S5.
I5 2I5
VDS5(sat) = Vin(min) - VSS- -V (max) ≥ 100 mV → S5 =
1 T1 K'5[VDS5(sat)]2
7. Find S6 by letting the second pole (p2) be equal to 2.2 times GB and assuming that
VSG4 = VSG6.
gm6 2KP'S6I6 S6I6 S6 gm6
gm6 = 2.2gm2(CL/Cc) and →
gm4 = = S4I4 = S4 S6 = g S4
2KP'S4I4 m4
8. Calculate I6 from
gm62
I6 =
2K'6S6
Check to make sure that S6 satisfies the Vout(max) requirement and adjust as necessary.
9. Design S7 to achieve the desired current ratios between I5 and I6.
S7 = (I6/I5)S5 (Check the minimum output voltage requirements)
Unbuffered Op Amp Design Procedure - Continued

10. Check gain and power dissipation specifications.
2gm2gm6
Av = I ( +  )I ( +  ) Pdiss = (I5 + I6)(VDD + VSS)
5 2 4 6 6 7
11. If the gain specification is not met, then the currents, I5 and I6, can be decreased or
the W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked
to insure that they are satisfied. If the power dissipation is too high, then one can only
reduce the currents I5 and I6. Reduction of currents will probably necessitate increase of
some of the W/L ratios in order to satisfy input and output swings.
12. Simulate the circuit to check to see that all specifications are met.

Unbuffered Op Amp Design Summary
Step Design Equations Comments

1 Let Cc ≥ 0.2CL PM = 60° and RHP Z=10GB
2 Let I5 ≥ SR·CcCCL Assumes SR limited by Cc 0° and RB
W3 W4 I5
3 = = ' Maximum input common mode range
L3 L4 K3 [VDD -Vin (max)- | VT 3 | +VT1 ] 2
W1 W2 gm1
2
4 gm1 = GB ×Cc ® = = GB defines the W/L of M1 and M2

L1 L2 K1'I 5
W5 2I 5
5 = ' Minimum input common mode range
L5 K 5VDS 5 (sat)2
W6 gm6 W4
6 = DC balance conditions
L6 gm 4 L4
gm6
2
7 I6 = PM = 60° and p2 = 2.2GB give gm6 ≈ 10gm1

2K 6' (W6 / L6 )
W7 é I 6 W5 2I 7 ù
8 = max ê , ' 2ú Determines the current in M7
L7 ë I 5 L5 K 7VDS 7 (sat) û
Check gain and power
2gm1gm6
9 dissipation and iterate Av = and Pdiss = (I 5 + I 6 )(VDD + | VSS |)
if necessary I 5 (l2 + l4 )I 6 (l6 + l7 )

DESIGN EXAMPLE OF A TWO-STAGE OP AMP

Example 23-1 - Design of a Two-Stage Op Amp
If KN’=120µA/V2, KP’= 25µA/V2, VTN = |VTP| = 0.5±0.15V, N = 0.06V-1, and P =
0.08V-1, design a two-stage, CMOS op amp that meets the following specifications.
Assume the channel length is to be 0.5µm and the load capacitor is CL = 10pF.
Av > 3000V/V VDD =2.5V GB = 5MHz SR > 10V/µs
60° phase margin 0.5V<Vout range < 2V ICMR = 1.25V to 2V Pdiss  2mW
Solution
1.) The first step is to calculate the minimum value of the compensation capacitor Cc,
Cc  (2.2/10)(10 pF) = 2.2 pF
2.) Choose Cc as 3pF. Using the slew-rate specification and Cc calculate I5.
I5 = (3x10-12)(10x106) = 30 µA
3.) Next calculate (W/L)3 using ICMR requirements (use worst case thresholds ±0.15V).
30x10-6
(W/L)3 = = 30 → (W/L)3 = (W/L)4 = 30
(25x10-6)[2.5 - 2 - .65 + 0.35]2


4.) Now we can check the value of the mirror pole, p3, to make sure that it is in fact
greater than 10GB. Assume the Cox = 6fF/µm2. The mirror pole can be found as
-gm3 - 2K’pS3I3
p3 ≈ 2C = 2(0.667)W L C = -1.25x109(rads/sec)
gs3 3 3 ox
or 199 MHz. Thus, p3, is not of concern in this design because p3 >> 10GB.
5.) The next step in the design is to calculate gm1 to get
gm1 = (5x106)(2)(3x10-12) = 94.25µS
Therefore, (W/L)1 is
gm12 (94.25)2
(W/L)1 = (W/L)2 = 2K’ I = 2·120·15 = 2.47  3.0  (W/L)1 = (W/L)2 = 3
N 1
6.) Next calculate VDS5,
30x10-6
VDS5 = 1.25 - - .65 = 0.31V
120x10-6·3
Using VDS5 calculate (W/L)5 from the saturation relationship.
2(30x10-6)
(W/L)5 = (120x10-6)(0.31)2 = 5.16  6 → (W/L)5 = 6


7.) For 60° phase margin, we know that
gm6  10gm1  942.5µS
Assuming that gm6 = 942.5µS and knowing that gm4 = 150µS, we calculate (W/L)6 as
942.5x10-6
(W/L)6 = 30 = 188.5  190 (W/L)6 = 190
(150x10-6)
8.) Calculate I6 using the small-signal gm expression:
(942.5x10-6)2
I6 = (2)(25x10-6)(188.5) = 94.2µA  95µA
Calculating (W/L)6 based on Vout(max), gives a value of 15. Since 190 exceeds the
specification and gives better phase margin, we choose (W/L)6 = 190 and I6 = 95µA.
With I6 = 95µA the power dissipation is Pdiss = 2.5V·(30µA+95µA) = 0.3125mW
9.) Finally, calculate (W/L)7
95x10-6
(W/L)7 = 6 30x10-6 = 19  20 → (W/L)7 = 20
 
Let us check the Vout(min) specification although the W/L of M7 is so large that this is
probably not necessary. The value of Vout(min) is
Vout(min) = VDS7(sat) = (2·95)/(120·20) = 0.281V
which is less than required. At this point, the first-cut design is complete.

10.) Now check to see that the gain specification has been met
(94.25x10-6)(942.5x10-6)
Av = 15x10-6(.06 + .08)95x10-6(.06 + .08) = 3,180V/V
which barely exceeds the specifications. Since we are at 2xLmin, it won’t do any good to
increase the channel lengths. Decreasing the currents or increasing W6/L6 will help.
The figure below shows the results of the first-cut design. The W/L ratios shown do
not account for the lateral diffusion discussed above. The next phase requires simulation.

RIGHT-HALF PLANE ZERO

Controlling the Right-Half Plane Zero
Why is the RHP zero a problem?
Because it boosts the magnitude but lags the phase - the worst possible combination for
stability.
jw
jw3 Loop
Gain RHP Zero Boost
jw2 0dB log10w

180 > q1 > q2 > q3
180°
q3 Loop
jw1 q2
q1 Phase
s Shift
z1 0° log10w
150129-013 RHP Zero Lag
Solution of the problem:

The compensation comes from the feedback path through Cc, but the RHP zero
comes from the feedforward path through Cc so eliminate the feedforward path!

Elimination of the Feedforward Path through the Miller Capacitor

Feedback Only
1.) Removing the feedforward path.
Cc
Roots: Dominant pole and output pole. +1
Inverting vOUT
High-Gain
Stage
120523-01
2.) Controlling the RHP zero location using a Rz Cc

nulling resistor†.
Roots: Inverting vOUT
High-Gain
a.) Dominant pole (Miller pole) Stage
120523-02
b.) Output pole

-1
c.) Pole due to Rz and first stage output capacitance, p4 ≈ R C
z I
1
d.) Controllable zero, z1 = C (1/g - R )
c mII z
Note that z1 can be placed anywhere on the real axis.
† W.J. Parrish, “An Ion Implanted CMOS Amplifier for High Performance Active Filters”, Ph.D. Dissertation, 1976, Univ. of CA, Santa Barbara.
A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p2
We desire that z1 = p2 in terms of the previous notation.
Therefore,
1 -gmII
Cc(1/gmII - Rz) = CII
The value of Rz can be found as
Cc + CII
Rz =  C  (1/gmII)
 c 
With p2 canceled, the remaining roots are p1 and p4(the pole due to Rz) . For unity-gain
stability, all that is required is that
Av(0) gmI
p4  Av(0)p1 = g R R C = C and (1/RzCI)  (gmI/Cc) = GB
mII II I c c
Substituting Rz into the above inequality and assuming CII >> Cc results in
gmI
Cc  gmII CICII
This procedure gives excellent stability for a fixed value of CII ( CL).
Unfortunately, as CL changes, p2 changes and the zero must be readjusted to cancel p2.
Using the Nulling Resistor in the Miller Compensated Two-Stage Op Amp

VDD
Circuit:
M11 M3 M4 V
B
VA M6
M10 CM Cc vout
M8
VC vin- vin+
M1 M2
CL
IBias
M9 M5
M12 M7
VSS Fig. 160-03

We saw earlier that the roots were:
gm2 gm1 gm6
p1 = - A C = - A C p2 = - C
v c v c L
1 -1
p4 = - z1 =
RzCI RzCc - Cc/gm6
where Av = gm1gm6RIRII.
(Note that p4 is the pole resulting from the nulling resistor compensation technique.)
Design of the Nulling Resistor (M8)
For the zero to be on top of the second pole (p2), the following relationship must hold
1 CL + Cc Cc+CL  1
Rz = g  C  =  C 
m6  c   c  2K’PS6I6
The resistor, Rz, is realized by the transistor M8 which is operating in the active region
because the dc current through it is zero. Therefore, Rz, can be written as
vDS8 1
Rz =  =
iD8 V =0 K’PS8(VSG8-|VTP|)
DS8
The bias circuit is designed so that voltage VA is equal to VB.
W11 I10 W6
 VGS10 − VT = VGS8 − VT  VSG11 = VSG6   =  
 L11   I6   L6 
In the saturation region
2(I10)
VGS10 − VT =
K'P(W10/L10) = VGS8 − VT
1 K’PS10 1 S10
 Rz =
K’PS8 2I10 = S8 2K’PI10
W8  Cc  S10S6I6
Equating the two expressions for Rz gives   =  
 L8  CL + Cc I10

Example 23-2 - RHP Zero Compensation

Use results of Ex. 23-1 and design compensation circuitry so that the RHP zero is
moved from the RHP to the LHP and placed on top of the output pole p2. Use device
data given in Ex. 23-1.
Solution
The task at hand is the design of transistors M8, M9, M10, M11, and bias current
I10. The first step in this design is to establish the bias components. In order to set VA
equal to VB, then VSG11 must equal VSG6. Therefore,
S11 = (I11/I6)S6
Choose I11 = I10 = I9 = 15µA which gives S11 = (15µA/95µA)190 = 30.
VDD
The aspect ratio of M10 is essentially a free parameter,
and will be set equal to 1. There must be sufficient supply M11 M4
VB
VA M6
voltage to support the sum of VSG11, VSG10, and VDS9. The M10 M8
Cc
ratio of I10/I5 determines the (W/L) of M9. This ratio is VC

I9
(W/L)9 = (I10/I5)(W/L)5 = (15/30)(6) = 3 IBias I5
Now (W/L)8 is determined to be M12

M9 M5

3pF  1·190·95µA 100327-03
 VSS
(W/L)8 = 3pF+10pF
 =8
  15µA

It is worthwhile to check that the RHP zero has been moved on top of p2. To do this, first
calculate the value of Rz. VSG8 must first be determined. It is equal to VSG10, which is
2I10 2·15
VSG10 = + |V | =
K’PS10 TP 25·1 + 0.5 = 1.595V
Next determine Rz.
1 106
Rz = = = 4.564k
K’PS8(VSG10-|VTP|) 25·8(1.595-.7)
The location of z1 is calculated as
-1
z1 = -12 = -94.91x106 rads/sec
3x10
(4.564 x 103)(3x10-12) -
950x10-6
The output pole, p2, is
950x10-6
p2 = - = -95x106 rads/sec
10x10-12
Thus, we see that for all practical purposes, the output pole is canceled by the zero
that has been moved from the RHP to the LHP.
The results of this design are summarized below where L = 0.5µm.
W8 = 4µm W9 = 1.5µm W10 = 0.5µm and W11 = 15 µm
An Alternate Form of Nulling Resistor

To cancel p2, VDD
Cc+CL 1
z1 = p2 → Rz = g C = g M11 M10
m6A C m6B M3 M4
Which gives M6
vout
 Cc  - M1 M2 M6B
gm6B = gm6AC +C  vin Cc CL
 c L
+
In the previous example, + M8 M9
M7
VBias M5
gm6A = 950µS, Cc = 3pF -
VSS Fig. 6.3-4A
and CL = 10pF.
Choose I6B = 10µA to get
gm6ACc 2KPW6BI6B  Cc  2KPW6AID6
gm6B = → = 
Cc + CL L6B  Cc+CL L6A
or
W6B  3 2 I6A W6A  3 2 95
= = (190) = 96.12 → W6B = 48µm
L6B 13 I6B L6A 13 10

Increasing the Magnitude of the Output Pole†

The magnitude of the output pole, VDD VDD
M11 M12 M11 M12
p2, can be increased by introducing Cc
M7
Cc
M7
vOUT vOUT
gain in the Miller capacitor feedback
A
path as shown where, M8 VBias
A ≈ gm8(rds8||rds9||rds2||rds4). M6 M6
M10 M9 M10 M9
The roots become, VSS VSS
120523-03
1.) The dominant pole increased slightly because RI (output of first stage) is decreased.
VDD VDD
2.) The output pole is increased by a rds7 rds7
Cc
-Agm6 vout A vout
factor of A to get new p2 ≈ C 1
II M8 GB·Cc » 0 M6
CII
M6 CII
3.) The pole at the source of M8 (-gm8/Cc)
becomes a zero on the negative real axis. 120523-04
Roots: jw
s
-Agm6 -gm8 -1 gm6
C2 Cc gm6rds2Cc Cgd6 120523-05
† B.K. Ahuja, “An Improved Frequency Compensation Technique for CMOS Operational Amplifiers,” IEEE J. of Solid-State Circuits, Vol. SC-18,
No. 6 (Dec. 1983) pp. 629-633.
Issues with the Previous Method†

The previous technique assumed that the gate-source capacitance of M8 could be
neglected. Unfortunately, this assumption ignores a pair of complex poles near the unity
gain frequency. Below is the small signal model with the capacitance that causes this
that includes Cgs8. Cgd6 Cc
+ + +
1 Cgs8
Iin R1 V1 Vs8 R2 C2 Vout
gm8 gm6V1
- gm8Vs8 - -
160311-01
The solution proposed in the reference below is to decrease the impedance at the source
of M8 by using a negative feedback loop. Below is a possible solution that will have
better phase margin. VDD
M11 M12 M16 M7
M13
vOUT
M8 Cc
M6
M10 M9 M14 M15
160311-02
VSS
† Uday Dasgupta, “Issues with ‘Ahuja’ Frequency Compensation Technique,” Proc. of IEEE Inter. Symposium on Radio Frequency Integration
Technology, Jan. 9, 2009, pp. 326-329.
POWER SUPPLY REJECTION RATIO OF THE TWO-STAGE OP AMP

What is PSRR?
Av(Vdd=0)
PSRR = A (V =0)
dd in
How do you calculate PSRR?

You could calculate Av and Add and divide, however
Vout = AddVdd + Av(V1-V2) = AddVdd - AvVout → Vout(1+Av) = AddVdd

Vout Add Add 1
 =  = (Good for frequencies up to GB)
Vdd 1+Av Av PSRR+

Approximate Model for PSRR+
1.) The M7 current sink causes VSG6 to act like a battery.

2.) Therefore, Vdd couples from the source to gate of M6.
3.) The path to the output is through any capacitance from gate to drain of M6.
Conclusion:
The Miller capacitor Cc couples the positive power supply ripple directly to the output.
Must reduce or eliminate Cc.

Approximate Model for PSRR-

M6 VDD
Cc Vout
M3 M4
rds7
vout
M1 M2 CI CII
Vss Zout
M5 rds7
Vss Path through Cgd7
VBias M7
is negligible
VBias connected to VSS VSS
Fig. 180-11
What is Zout?
Vt  gmIVt 
Zout = I  It = gmIIV1 = gmIIG +sC +sC  Cc CII+Cgd7 It
t  I I c
+ rds6||rds7 +
GI+s(CI+Cc) CI RI V1 gmIIV1 Vout Vt
Thus, Zout = g g gmIVin
- -
mI MII
150131-01
rds7
1+ Z
Vout out s(Cc+CI) + GI+gmIgmIIrds7 -GI
 = =  Pole at
Vss 1 s(Cc+CI) + GI Cc+CI
The negative PSRR is much better than the positive PSRR.
SUMMARY
• The output of the design of an op amp is
- Schematic
- DC currents
- W/L ratios
- Component values
• Design procedures provide an organized approach to creating the dc currents, W/L
ratios, and the component values
• The right-half plane zero causes the Miller compensation to deteriorate
• Methods for eliminating the influence of the RHP zero are:
- Nulling resistor
- Increasing the magnitude of the output pole
• The PSRR of the two-stage op amp is poor because of the Miller capacitance, however,
methods exist to eliminate this problem
• The two-stage op amp is a very general and flexible op amp

Lecture 24 Cascode Op Amps (9/7/17) Page 24-1
LECTURE 24 – CASCODE OP AMPS

Outline
• Lecture Organization
• Single Stage Cascode Op Amps
• Two Stage Cascode Op Amps
• Summary
Pages 310-328

Cascode Op Amps
Why cascode op amps?
• Control of the frequency behavior
• Can get more gain by increasing the output resistance of a stage
• In the past section, PSRR of the two-stage op amp was insufficient for many
applications
• A two-stage op amp can become unstable for large load capacitors (if nulling resistor
is not used)
• The cascode op amp leads to wider ICMR and/or smaller power supply requirements
Where Should the Cascode Technique be Used?
• First stage -
Good noise performance
Requires level translation to second stage
Degrades the Miller compensation
• Second stage -
Self compensating
Increases the efficiency of the Miller compensation
Increases PSRR
SINGLE STAGE CASCODE OP AMPS

Simple Single Stage Cascode Op Amp
VDD VDD
M3 M4 Implementation of the M3 M4
floating voltage VBias
which must equal
MB3 MB4
2VON + VT.
VPBias2 VPBias2 MC4
MC3 MC4 vo1 MC3
MB5
MC1 MC2 MC1 + MC2
M1 M2 M1 VBias M2
VBias MB1 MB2
+v - +v
in vin in - vin -
2- + 2 2- + 2
+ M5 + M5
VNBias1 VNBias1
- -
VSS VSS 060627-01
Rout of the first stage is RI  (gmC2rdsC2rds2)||(gmC4rdsC4rds4)

vo1
Voltage gain = v = gm1RI [The gain is increased by approximately 0.5(gMCrdsC)]
in
As a single stage op amp, the compensation capacitor becomes the load capacitor.

Example 24-1 Single-Stage, Cascode Op Amp Performance

Assume all W/L ratios are 10 m/1 m, and that IDS1 = IDS2 = 50 A of single stage op
amp. Find the voltage gain of this op amp and the value of CI if GB = 10 MHz. Use KN’
= 120µA/V2, KP’ = 25µA/V2, VTN = 0.5V, VTP = -0.5V, N = 0.06V-1 and P = 0.08V-1.
Solution
The device transconductances are
gm1 = gm2 = gmI = 346.4 S
gmC1 = gmC2 = 346.4S
gmC3 = gmC4 = 158.1 S.
The output resistance of the NMOS and PMOS devices is 0.333 M and 0.25 M,
respectively.
 RI = 7.86 M
Av(0) = 2,722 V/V.
For a unity-gain bandwidth of 10 MHz, the value of CI is 5.51 pF.
What happens if a 100pF capacitor is attached to this op amp?
GB goes from 10MHz to 0.551MHz.
Enhanced Gain, Single Stage, Cascode Op Amp

VDD VDD
M7 M8 M7 M8
M15
-A M5 M6
VNB1
M5 M6 M16
vOUT VDD VDD vOUT
VPB1
M3 M4
M13 M14
-A -A M3 M4
M11 M12
M1 M2 M1 M2
+ +
vIN vIN
- -
M9
VNB1 M9 VNB1 M10
060627-02
From inspection, we can write the voltage gain as,
vOUT
Av = v = gm1Rout where Rout = (Ards6gm6rds8)|| (Ards2gm4rds4)
IN
If rdsn ≈ rdsp, then A ≈ gmrds/2 and the voltage gain would be equal to 100K to 500,K.
Output is not optimized for maximum signal swing.
TWO-STAGE, CASCODE OP AMPS

Two-Stage Op Amp with a Cascoded First-Stage
VDD Current
W6/L6 W6’/L6’<< W6/L6
M3 M4
MT2
ID6
MB3 MB4
M6
MC3 MC4
MT1 VT6
Cc
R vo1 vout
VSG6 VSG6 = Volts
MB5 = VSD4 VSD4+VSDC4
MC1 + MC2
M1 VBias M2
MB1 MB2
-v vin +
in -
2 + - 2
M5 M7
+
VBias
-
VSS 070427-01
• MT1 and MT2 are required for level shifting

from the first-stage to the second.
• The PSRR+ is not improved by MT1
• Internal loop pole at the gate of M6 may cause
the Miller compensation to fail.
• The voltage gain of this op amp could easily be 100,000V/V
Implementation of Gain in Cc Feedback Loop Using the Previous Amplifier

In Lecture 23, we showed that a common-gate amplifier in the compensation feedback
prevented feed forward and moved the output pole further away from the origin.
Modifying the previous amplifier: VDD
Connecting Cc to the source of M4C
M6
results in two improvements: M4 MT2
M3
1.) MC4 gives gain in the compensation
VPB2 Cc
feedback path pushing the output pole vOUT
M3C M4C
further away from the origin.
MT1
2.) The compensation capacitor, Cc, is - M1 M2
vIN
disconnected from the gate of MT1 +
eliminating the poor PSRR. M5
VNB1 M7
120523-06

Two-Stage Op Amp with a Cascode Second-Stage

VDD
Av = gmIgmIIRIRII
where gmI = gm1 = gm2, gmII = gm6, M6
M3 M4
VBP MC6
1 2 Rz Cc
RI = = vout
gds2 + gds4 (2 + 4)ID5
- M1 M2 VBN MC7 CL
and vin
+
RII = (gmC6rdsC6rds6)(gmC7rdsC7rds7) +
VBias M5
M7
-
VSS Fig. 6.5-3
Comments:
• The second-stage gain has greatly increased improving the Miller compensation
• The overall gain is approximately (gmrds)3 if rdsn >> rdsp or if rdsp >> rdsn
• Output pole, p2, is approximately the same if Cc is constant
• The zero RHP is the same if Cc is constant
• PSRR is poor unless the Miller compensation is removed (then the op amp becomes
self compensated)
A Balanced, Two-Stage Op Amp using a Cascode Output Stage

VDD
gm1gm8 vin gm2gm6 vin
vout =  g + g  RII
M4 M6  m3 2 m4 2 
gm1 gm2
M3 M8 VPB2
M7 =  2 + 2 kvin RII = gm1·k·RII
 
vout vin
- M1 M2
VNB2 M9
vin M12 CL where
+
M5 M10
RII = (gm7rds7rds6)||(gm12rds12rds11)
+ M11
VNB1
and
-
VSS 060627-03
gm8 gm6
k=g =g
m3 m4
This op amp is balanced because the drain-to-ground loads for M1 and M2 are identical.
TABLE 1 - Design Relationships for Balanced, Cascode Output Stage Op Amp.
Iout gm1gm8 1 gm1gm8 gm2gm6
Slew rate = GB = Av =  + R
CL gm3CL 2  gm3 gm4  II
 I5 1/2  I5 1/2
Vin(max) = VDD −  − VTO3(max) +VT1(min) Vin(min) = VSS + VDS5 +   + VT1(min)
3 1

Technological Implications of the Cascode Configuration
A
A B C D
B Thin
oxide Poly I Poly II
n+ n-channel n+
C p substrate/well
D
Fig. 6.5-5
If a double poly CMOS process is available, inter-node parasitics can be minimized.
As an alternative, one should keep the drain/source between the transistors to a minimum
area.
Minimum Poly
A separation
A B C D
B Thin
oxide Poly I Poly I
n+ n-channel n+ n-channel n+
C p substrate/well
D
Fig. 6.5-5A

Input Common Mode Range for Two Types of Differential Amplifier Loads
VDD-VSD3+VTN
VDD VDD
VDD-VSG3+VTN
+ + + +
VSG3 VSD4 V VSD4
Input SD3
Input
- M3 M4 - Common - M3 M4 -
VBP
Common Mode
Mode Range
Range M1 M2 M1 M2
VSS+VDS5+VGS1 VSS+VDS5+VGS1
+ M5 vicm + M5 vicm
VBias VBias
- -
VSS VSS
Differential amplifier with Differential amplifier with
a current mirror load. current source loads. Fig. 6.5-6
In order to improve the ICMR, it is desirable to use current source (sink) loads without
losing half the gain.
The resulting solution is the folded cascode op amp.

The Folded Cascode Op Amp VDD

VPB1
I4 I5
M4 M5
RA VPB2 RB
I1 I2
I6 I7
M6 vOUT
M7
+
M1 M2 VNB2
vIN
- M8 M9 CL
M3
VNB1 I3 M11
M10
Comments: 060628-04
• I4 and I5, should be designed so that I6 and I7 never become zero (i.e. I4=I5=1.5I3)
• This amplifier is nearly balanced (would be exactly if RA was equal to RB)
• Self compensating
• Poor noise performance, the gain occurs at the output so all intermediate transistors
contribute to the noise along with the input transistors. (Some first stage gain can be
achieved if RA and RB are greater than gm1 or gm2.

Small-Signal Analysis of the Folded Cascode Op Amp

Model:
The easiest way to analyze this amplifier is to first find the short-circuit output current
and multiple this current by the output resistance.
gm7vgs7
RB
i7
gm6vgs6 gm9vgs9
RA rds7
- iout
gm2vin
vgs7
- 2 rds2 rds5 i9
gm1vin i10
rds1 rds4 vgs6 rds6 +
i10
rds9
2 1 rds11
+ gm10
140531-01
With the output short-circuited, RA ≈ 1/gm6 and RB ≈ 1/gm7. Therefore the currents i7
and i9 can be written as,
gm2(rds2||rds5)vin gm2vin gm1(rds1||rds4)vin gm1vin
i7 = ≈ and i9 ≈ -i10 = ≈
2[RB + (rds2||rds5)] 2 2[RA + (rds1||rds4)] 2
The output resistance with the short-circuit removed is,
Rout ≈ (gm9rds9rds11)||[ gm7rds7(rds2|| rds5)]
Finally,
gm1vin gm2vin
vout = (i7 + i9)Rout =  + 2  Rout = gm1Rout = gm2Rout
 2 
Intuitive Analysis of the Folded Cascode Op Amp

Assume that a voltage of V is applied. We know that
VDD
RA(M6) ≈ 1/gm6 and RB(M7) ≈ 1/gm7 VPB1
The currents flowing to the short-circuited output are,
M4 M5
gm1V gm2V
2 + 2 gm1DV
2
gm2DV gm1DV
2
VPB2 gm2DV
2
2
Rout
The output resistance is approximately, M6 vout
+ M7
M1 M2 VNB2
Rout ≈ (gm9rds9rds11)||[ gm7rds7(rds2||rds5)] vin = DV M8
gm1DV
2
CL
-
M3 M9
gmrds2 VNB1 gm1DV
≈  3  if rdsn ≈ rdsp 2 gm1DV
  M10 M11 2
100328-01
Therefore, the approximate voltage gain is,

vout gm1 gm2 gm2rds2
   
vin =  2 + 2  Rout ≈ gm Rout =  3 
The GB is,
Av(0) gmRout gm
GB = = =
|p1| |Rout CL| CL

Frequency Response of the Folded Cascode Op Amp

The frequency response of the folded cascode op amp is determined primarily by the
output pole which is given as
-1
pout = R C
out out VDD
where Cout is the capacitance connected from the output to ground. VPB1
All other poles must be greater than GB = gm1/Cout. M4 M5

A
The approximate expressions for each pole is (ignoring Cgd): VPB2
B
1.) Pole at node A: pA  - gm6/(Cgs+ 2Cdb) vout

M6 M7
2.) Pole at node B: pB  - gm7/(Cgs+ 2Cdb) VNB2
M8 CL
3.) Pole at drain of M6: p6 -gm10/(2Cgs+ 2Cdb) M9
4.) Pole at source of M8: p8 ≈ -(gm8rds8gm10)/(Cgs+ Cdb)
M10 M11
5.) Pole at source of M9: p9  -gm9/(Cgs+ Cdb) 150216-01
where the approximate expressions are found by the reciprocal product of the resistance
and parasitic capacitance seen to ground from a given node. One might feel that because
RB is approximately rds that this pole also might be small. However, at frequencies
where this pole has influence, Cout, causes Rout to be much smaller making pB also non-
dominant.
Example 24-3 - Folded Cascode, CMOS Op Amp

Assume that all gmN = gmP = 100µS, rdsN = 2M rdsP = 1M, and CL = 10pF. Find
all of the small-signal performance values for the folded-cascode op amp.
Rout = (gm9rds9rds11)||[gm7rds7(rds5||rds2)] = 400M||[(100)(0.667M)] = 57.143M
vout
vin = gmN Rout = (100)(57.143) = 5,714.3 V/V
1 1
|pout| = R C = 57.143M·10pF = 1,750 rads/sec.  278Hz  GB = 1.21MHz
out out

PSRR of the Folded Cascode Op Amp

Consider the following circuit used to model the PSRR-:
VDD
R
Cgd9 Vout rds9
Vss
Cgd9
M9
Cgd11 Vss
+
Vss
VGSG9 Vss Cout Rout Vout
rds11 -
VGS11 M11
Vss
Fig. 6.5-9A
This model assumes that gate, source and drain of M11 and the gate and source of M9 all
vary with VSS.
We shall examine Vout/Vss rather than PSRR-. (Small Vout/Vss will lead to large PSRR-.)
The transfer function of Vout/Vss can be found as
Vout sCgd9Rout
Vss ≈ sCoutRout+1 for Cgd9 < Cout
The approximate PSRR- is sketched on the next page.

Frequency Response of the PSRR- of the Folded Cascode Op Amp
We see that the PSRR of the cascode op amp is much better than the two-stage op amp
without any modifications to improve the PSRR.

Design Approach for the Folded-Cascode Op Amp

Step Relationship Design Equation/Constraint Comments
1 Slew Rate I3 = SR·CL
2 Bias currents in I4 = I5 = 1.2I3 to 1.5I3 Avoid zero current in
output cascodes cascodes
3 Maximum output 2I5 2I7 VSD5(sat)=VSD7(sat)
voltage, S5= , S7= , (S4=S5 and S6= S7)
KP’VSD52 KP’VSD72 = 0.5[VDD-Vout(max)]
vout(max)
4 Minimum output 2I11 2I9 VDS9(sat)=VDS11(sat)
voltage, S11= , S9= , (S10=S11and S8=S9) = 0.5[Vout(min)-VSS]
KN’VDS112 KN’VDS92
vout(min)
5 gm1 gm12 GB2CL2
GB = S1=S2= =
CL KN’I3 KN’I3
6 Minimum input 2I3
CM S3 =
2
KN’Vin(min)-VSS- (I3/KN’S1) -VT1
7 Maximum input 2I4 2 S4 and S5 must meet or
CM S 4 = S =
5 K ’V -V (max)+V  exceed value in step 3
P  DD in T1
8 Differential vout gm1 gm2
= + R = gmIRout
Voltage Gain vin  2 2  out
9 Power dissipation Pdiss = (VDD-VSS)(I3+I10+I11)

Example 24-4 Design of a Folded-Cascode Op Amp

Design a folded-cascode op amp if the slew rate is 10V/µs, the load capacitor is 10pF,
the maximum and minimum output voltages are 2V and 0.5V for a 2.5V power supply,
the GB is 10MHz, the minimum input common mode voltage is +1V and the maximum
input common mode voltage is 2.5V. The differential voltage gain should be greater
than 3,000V/V and the power dissipation should be less than 5mW. Use KN’=120µA/V2,
KP’= 25µA/V2, VTN = |VTP| = 0.5V, N = 0.06V-1, and P = 0.08V-1. Let L = 0.5 m.
Solution
Following the approach outlined above, I3 = SR·CL = 10x106·10-11 = 100µA.
Select I4 = I5 = 125µA.
Next, we see that the value of 0.5(VDD-Vout(max)) is 0.5V/2 or 0.25V. Thus,
2·125µA 2·125·16
S4 = S5 = = = 160
25µA/V2·(0.25V)2 25
and assuming worst case currents in M6 and M7 gives,
2·125µA 2·125·16
S6 = S7 = = = 160
25µA/V2(0.25V)2 25
The value of 0.5(Vout(min)-|VSS|) is 0.25V which gives the value of S8, S9, S10 and S11 as
2·I8 2·125
S8 = S9 = S10 = S11 = = = 20
KN’VDS82 120·(0.25)2

In step 5, the value of GB gives S1 and S2 as
GB2·CL2 (20x106)2(10-11)2
S1 = S2 = K ’I = = 32.9 ≈ 33
N 3 120x10-6·100x10-6
The minimum input common mode voltage defines S3 as
2I3 200x10-6
S3 = = ≈ 15
 I3   100 2
KN’Vin(min)-VSS- - VT12 120x10-61.0+0- 120·33 -0.5
 KN’S1 
We need to check that the values of S4 and S5 are large enough to satisfy the maximum
input common mode voltage. The maximum input common mode voltage of 2.5
requires
2I4 2·125µA
S4 = S5 ≥ = = 40
KP’[VDD-Vin(max)+VT1]2 25µA/V2[0.5V]2
which is less than 160. In fact, with S4 = S5 = 160, the maximum input common mode
voltage is 2.75V.
The power dissipation is found to be
Pdiss = 2.5V(125µA+125µA) = 0.625mW


The small-signal voltage gain requires the following values to evaluate:
S4, S5: gm = 2·125·25·160 = 1000µS and gds = 125x10-6·0.08 = 10µS
S6, S7: gm = 2·75·25·160 = 774.6µS and gds = 75x10-6·0.08 = 6µS
S8, S9, S10, S11: gm = 2·75·120·20 = 600µS and gds = 75x10-6·0.06 = 4.5µS
S1, S2: gmI = 2·50·120·33 = 629µS and gds = 50x10-6(0.06) = 3µS
Thus,

1  1 

RII  gm9rds9rds11 = (600µS) 4.5µS4.5µS = 29.63M


 
 1  1 
Rout  29.63M||(774.6µS)6µS10µS+3µS = 7.44M
 
  
The small-signal, differential-input, voltage gain is

Avd = gmIRout = (629)(7.44) = 4,680 V/V
The gain is slightly larger than the specified 3,000 V/V.

Comments on Folded Cascode Op Amps

• Good PSRR
• Good ICMR
• Self compensated
• Can cascade an output stage to get extremely high gain with lower output resistance
(use Miller compensation in this case)
• Need first stage gain for good noise performance
• Widely used in telecommunication circuits where large dynamic range is required

Enhanced-Gain, Folded Cascode Op Amps

If more gain is needed, the folded cascode op amp can be enhanced to boost the output
impedance even higher as follows. VDD
M10 M11
VPB1 M3
-A
+
vIN M8 M9
- vOUT
M1 M2
M6 M7
-A -A
Voltage gain = gm1Rout,

VNB1 M4
M5
where
Rout ≈ [Ards7gm7(rds1||rds5)]|| (Ards9gm9rds11) 060718-03
If rdsn >> rdsp or if rdsp >> rdsn, then A ≈ gmrds and the voltage gain would be in the
range of 100,000 to 500,000.
Note that to achieve maximum output swing, it will be necessary to make sure that M5
and M11 are biased with VDS = VDS(sat).
What are the Enhancement Amplifiers?

Requirements:
1.) Need a gain of gmrds.
2.) Must be able to set the dc voltage at its input to get wide-output voltage swing.
Possible Enhancement Amplifiers:
VDD VDD
VPB1 VPB1
vin M4 vin M6 M3
vout
vin
M6
-A VPB2 VNB2 M5
M1 M2
vout -A vin M1 M2
M5 VDD
M9
vout VNB1 -VSD(Sat) vout VNB1
M4 VDS(Sat)
M6 M3
140713-02

Enhanced-Gain, Folded Cascode Op Amp

Detailed realization:

Frequency Response of the Enhanced Gain Cascode Op Amps

Normally, the frequency response of the cascode op amps would have one dominant pole
at the output. The frequency response would be,
 Rout(1/sCout)  gm1Rout gm1Rout
Av(s) = gm1 R +1/sC  = sR C +1 =
 out out out out s
1-p
1
If the amplifier used to boost the output resistance had no frequency dependence then the
frequency response would be as follows. VDD
Gain (db) M10 M11

VPB1
100dB M3
Enhanced Gain Cascode Op Amp -A
+
vIN M8 M9
80dB - vOUT
M1 M2
M6 M7
60dB Normal Cascode
-A -A
Op Amp
40dB
VNB1 M4
M5
0dB log10w
|p1(enh)| |p1| GB 060718-03
060629-02

SUMMARY
• Cascode op amps give additional flexibility to the two-stage op amp
- Increase the gain
- Control the dominant and nondominant poles
• Enhanced gain, cascode amplifiers provide additional gain and are used when high
gains are needed
• Folded cascode amplifier is an attractive alternate to the two-stage op amp
- Wider ICMR
- Self compensating
- Good PSRR

Lecture 25 – Measurement and Simulation of Op amps (6/25/14) Page 25-1
LECTURE 25 – SIMULATION AND MEASUREMENT OF OP

AMPS
Outline
• Introduction
• Open Loop Gain
• CMRR and PSRR
• A general method of measuring Avd, CMRR, and PSRR
• Other op amp measurements
• Simulation of a Two-Stage Op Amp
• Summary
Pages 328-341

INTRODUCTION
Simulation and Measurement Considerations
Objectives:
• The objective of simulation is to verify and optimize the design.
• The objective of measurement is to experimentally confirm the specifications.
Similarity between Simulation and Measurement:
• Same goals
• Same approach or technique
Differences between Simulation and Measurement:
• Simulation can idealize a circuit
- All transistor electrical parameters are ideally matched
- Ideal stimuli
• Measurement must consider all nonidealities
- Physical and electrical parameter mismatches
- Nonideal stimuli
- Parasistics

OPEN LOOP GAIN

Simulating or Measuring the Open-Loop Transfer Function of the Op Amp
Circuit (Darkened op amp identifies the op amp under test):
Simulation: vIN +VOS - VDD

vOUT
This circuit will give the voltage transfer
function curve. This curve should identify:
CL RL VSS
1.) The linear range of operation
2.) The gain in the linear range Fig. 240-01
3.) The output limits
4.) The systematic input offset voltage
5.) DC operating conditions, power dissipation
6.) When biased in the linear range, the small-signal frequency response can be
obtained
7.) From the open-loop frequency response, the phase margin can be obtained (F = 1)
Measurement:
This circuit probably will not work unless the op amp gain is very low.

A More Robust Method of Measuring the Open-Loop Frequency Response

Circuit:
VDD
vIN vOUT
CL RL VSS
C R
Fig. 240-02
Resulting Closed-Loop Frequency Response:
dB Op Amp
Av(0) Open Loop
Frequency
Response
0dB
1 Av(0) log10(w)
RC RC Fig. 240-03
Make the RC product as large as possible.

CMRR AND PSRR

Simulation of the Common-Mode Voltage Gain
VOS VDD
+ -
vout
+
vcm VSS
- CL RL
Fig. 6.6-5
Make sure that the output voltage of the op amp is in the linear region.
Divide (subtract dB) the result into the open-loop gain to get CMRR.

Simulation of CMRR of an Op Amp

A simulation method that avoids dividing the differential gain by the common mode gain
is given on this slide. For this method to work, the op amp should be balanced.
Consider the following:
V1+V2
Vout = Av(V1-V2) ±Acm 2  = -AvVout ± AcmVcm
 
±Acm ±Acm
Vout = V ≈ V
1+Av cm Av cm
Av Vcm
 |CMRR| = =
Acm Vout

Direct Simulation of PSRR

Circuit:
Vout = Av(V1-V2) ±AddVdd = -AvVout ± AddVdd

±Add ±Add
Vout = V ≈ V
1+Av dd Av dd
Av Vdd Av Vss
 PSRR = = + and PSRR = = -
Add Vout Ass Vout
Works well as long as CMRR is much greater than 1.

A GENERAL METHOD OF MEASURING AVD, CMRR, AND PSRR

General Principle of the Measurement
Circuit:
The amplifier under test is shown as the darkened op amp.

Principle:
Apply the stimulus to the output of the op amp under test and see how the input
responds. Note that:
vOS
vOUT = - vSET and vI ≈ 1000
Measurement of Open-Loop Gain

Measurement configuration:
Vout Vout
Avd = V = V
id i
Vos ≈ 1000Vi
1000Vout
Therefore, Avd = V
os
Sweep Vout as a function of frequency, invert the result and multiply by 1000 to get
Avd (j).
Measurement of CMRR
Measurement Configuration:
Note that the whole amplifier is stimulated by
Vicm while the input responds to this change.
The definition of the common-mode rejection
ratio is
 Avd  (vout/vid)
CMRR =  =
Acm (vout/vicm)
However, in the above circuit the value of vout
is the same so that we get
vicm
CMRR = v
id
vos
But vid = vi and vos  1000vi = 1000vid  vid = 1000
vicm 1000 vicm
Substituting in the previous expression gives, CMRR = v =
os vos
1000
Make a frequency sweep of Vicm, invert the result and multiply by 1000 to get CMRR.
Measurement of PSRR
100kW
Measurement Configuration: Vos
The definition of the positive power supply rejection 100kW

Vdd
ratio is 10kW
Avd  (Vout/Vid)
PSRR = A  = (V /V )
+
Vout
VDD
 dd  out dd
+
However, in the above circuit the value of Vout is the 10W Vi
VSS
- CL RL
same so that we get
Vss
Vdd 070429-02
PSRR =+
Vid
Vos
But Vid = Vi and Vos  1000Vi = 1000Vid  Vid =
1000
Vdd 1000 Vdd
Substituting in the previous expression gives, +
PSRR = V = V
os os
1000
Make a frequency sweep of Vdd, invert the result and multiply by 1000 to get PSRR+.
(Same procedure holds for PSRR-.)
OTHER OP AMP MEASUREMENTS

Simulation or Measurement of ICMR
vOUT
IDD 1
VDD
vOUT 1
+ vIN
vIN ICMR
- VSS
C RL
ISS L
Also, monitor
IDD or ISS. Fig.240-11
Initial jump in sweep is due to the turn-on of M5.

Should also plot the current in the input stage (or the power supply current).

Measurement or Simulation of Slew Rate and Settling Time

Volts Peak Overshoot
vin
IDD Settling Error
VDD Tolerance
vout +SR -SR
+
vout
vin 1 1
- VSS t
CL RL
Settling Time
Feedthrough Fig. 240-14
If the slew rate influences the small signal response, then make the input step size small
enough to avoid slew rate (i.e. less than 0.5V for MOS).

Phase Margin and Peak Overshoot Relationship

It can be shown (Appendix D of the 3rd edition of text) that:
Phase Margin (Degrees) = 57.2958cos-1[ 44+1 - 22]
 - 
Overshoot (%) = 100 exp  80 100
 1- 2 
70
20
Phase Margin (Degrees)

60
vout
10
Overshoot (%)
Peak Overshoot 50
5
40 Phase Margin Overshoot
30
t 1.0
150303-01 20
For example, a 5% overshoot
10
corresponds to a phase margin
of approximately 64°. 0 0.1
0 0.2 0.4 0.6 0.8 1
z= 1 070429-03
2Q

SIMULATION OF A TWO-STAGE CMOS OP AMP

Example 25-1 Simulation of a Two-Stage CMOS Op Amp
An op amp designed using the procedure described in Lecture 23 is to be simulated
by SPICE. The device parameters to be used are those of Tables 3.1-2 and 3.2-1 of the
textbook CMOS Analog Circuit Design.
VDD = 2.5V
M3 M4 M6
15mm 15mm 94mm
1mm 1mm 1mm
Cc = 3pF
vout
30mA M1 M2
- 3mm 3mm CL =
1mm 1mm 10pF
vin 95mA
+
30mA
4.5mm 14mm
1mm 4.5mm 1mm
M8 M5 1mm M7
Fig. 240-16
VSS = -2.5V
The specifications of this op amp are as follows where the channel length is to be 1µm
and the load capacitor is CL = 10pF:
Av > 3000V/V VDD = 2.5V VSS = -2.5V
GB = 5MHz SR > 10V/µs 60° phase margin
Vout range = ±2V ICMR = -1 to 2V Pdiss  2mW

Bulk Capacitance Calculation:
If the values of the area and perimeter of the drain and source of each transistor are
known, then the simulator will calculate the values of CBD and CBs. Since there is no
layout yet, we estimate the values of the area and perimeter of the drain and source of
each transistor as:
AS = AD  W[L1 + L2 + L3]
PS = PD  2W + 2[L1 + L2 + L3]
where L1 is the minimum allowable distance between the polysilicon and a contact in the
moat (2µm), L2 is the length of a minimum-size square contact to moat (2µm), and L3 is
the minimum allowable distance between a contact to moat and the edge of the moat
(2µm). (These values will be found from the physical design rules for the technology).
For example consider M1:
AS = AD = (3µm)x(2µm+2µm+2µm) = 18µm2
PS = PD = 2x3µm + 2x6µm = 19µm


Op Amp Subcircuit:
.SUBCKT OPAMP 1 2 6 8 9
M1 4 2 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M3 4 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M5 3 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
M8 7 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
CC 5 6 3.0P
.MODEL NMOS1 NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N
.MODEL PMOS1 PMOS VTO=-0.7 KP=50U GAMMA=0..57 LAMBDA=0.05 PHI=0.8
+MJ=0.5 MJSW=.35 CGBO=700P CGSO=220P CGDO=220P CJ=560U CJSW=350P +LD=0.014U TOX=14N
IBIAS 8 7 30U
.ENDS


PSPICE Input File for the Open-Loop Configuration:
EXAMPLE 25-1 OPEN LOOP CONFIGURATION
.OPTION LIMPTS=1000
VIN+ 1 0 DC 0 AC 1.0
VDD 4 0 DC 2.5
VSS 0 5 DC 2.5
VIN - 2 0 DC 0
CL 3 0 10P
X1 1 2 3 4 5 OPAMP
..
.
(Subcircuit of previous slide)
..
.
.OP
.TF V(3) VIN+
.DC VIN+ -0.005 0.005 100U
.PRINT DC V(3)
.AC DEC 10 1 10MEG
.PRINT AC VDB(3) VP(3)
.PROBE (This entry is unique to PSPICE)
.END


Open-loop transfer characteristic:
2.5
2
VOS
1
vOUT(V)
-1
-2
-2.5
-2 -1.5 -1.0 -0.5 0 0.5 1 1.5 2
vIN(mV) Fig. 240-18


Open-loop transfer frequency response:
80 200
150
60
Phase Shift (Degrees)

100
Magnitude (dB)
40
50
20 0
-50
0
-100
-20
-150 Phase Margin
GB GB
-40 -200
4 5 6 7 8
10 100 1000 10 10 10 10 10 10 100 1000 104 105 106 107 108
Frequency (Hz) Frequency (Hz) Fig. 6.6-16


Input common mode range:
EXAMPLE 25-1 UNITY GAIN CONFIGURATION.
.OPTION LIMPTS=501
VIN+ 1 0 PWL(0 -2 10N -2 20N 2 2U 2 2.01U -2 4U -2 4.01U
+ -.1 6U -.1 6.0 1U .1 8U .1 8.01U -.1 10U -.1)
VDD 4 0 DC 2.5 AC 1.0
VSS 0 5 DC 2.5
CL 3 0 20P 4 40
X1 1 3 3 4 5 OPAMP ID(M5)
..
ID(M5) mA
. 3 30
(Subcircuit of Table 6.6-1)
.. 2 20
. Input CMR
vOUT (V)
.DC VIN+ -2.5 2.5 0.1 1 10
.PRINT DC V(3)
.TRAN 0.05U 10U 0 10N 0 0
.PRINT TRAN V(3) V(1)
.AC DEC 10 1 10MEG -1
.PROBE (This entry is unique to PSPICE) -2
.END -3
-3 -2 -1 0 1 2 3
vIN(V) Fig. 240-21
Note the usefulness of monitoring the
current in the input stage to determine the lower limit of the ICMR.


Positive PSRR:
This PSRR+ is poor because of the Miller capacitor. The degree of PSRR+ deterioration
will be better shown when compared with the PSRR-.


Negative PSRR:


Large-signal and small-signal transient response:
1.5 0.15
1 0.1 vin(t)
0.5 0.05
vout(t)
vout(t)
Volts
Volts
0 0
-0.5 -0.05
vin(t)
-1 -0.1
-1.5 -0.15
2.5 3.0 3.5 4.0 4.5
0 1 2 3 4 5
Time (Microseconds) Time (Microseconds) Fig. 240-24
Why the negative overshoot on the slew rate? VDD

If M7 cannot sink sufficient current then the output stage
M6
slews and only responds to changes at the output via the Cc iCc iCL dvout
vout
feedback path which involves a delay. dt
Note that -dvout/dt  -2V/0.3µs = -6.67V/µs. For a CL

95mA
10pF capacitor this requires 66.7µA and only 95µA-66.7µA
= 28µA is available for Cc. For the positive slew rate, M6 +
VBias
M7
can provide whatever current is required by the capacitors -

VSS Fig. 240-25
and can immediately respond to changes at the output.

Insight into slewing:
When an op amp slews, the input loses control of the output.
In the above example, the current in M6 is zero and any change in the input of the op
amp has no influence on the output current.
Simple op amp models:


Comparison of the Simulation Results with the Specifications of Example 25-1:
Specification Design Simulation

(Power supply = ±2.5V)
Open Loop Gain >5000 10,000
GB (MHz) 5 MHz 5 MHz
Input CMR (Volts) -1V to 2V -1.2 V to 2.4 V,
Slew Rate (V/µsec) >10 (V/µsec) +10, -7(V/µsec)
Pdiss (mW) < 2mW 0.625mW
Vout range (V) 2V +2.3V, -2.2V
PSRR+ (0) (dB) - 87
PSRR- (0) (dB) - 106
Phase margin (degrees) 60° 65°
Output Resistance (k) - 122.5k

Relative Overshoots of Ex. 25-1 VDD = 2.5V
Why is the negative-going overshoot 94/1 0.1V

M6 i6
larger than the positive-going overshoot iCc
iCL
on the small-signal transient response of Cc
vout t
a previous slide? 95mA CL
Consider the following circuit and M7

-0.1V
VBias 0.1ms 0.1ms
waveform:
VSS = -2.5V Fig. 240-26
During the rise time,
iCL = CL(dvout/dt )= 10pF(0.2V/0.1µs) = 20µA and iCc = 3pf(2V/µs) = 6µA
 i6 = 95µA + 20µA + 6µA = 121µA  gm6 = 1066µS (nominal was 942.5µS)
During the fall time, iCL = CL(-dvout/dt) = 10pF(-0.2V/0.1µs) = -20µA
and iCc = -3pf(2V/µs) = -6µA
 i6 = 95µA - 20µA - 6µA = 69µA gm6 = 805µS
The dominant pole is p1  (RIgm6RIICc)-1 but the GB is gmI/Cc = 94.25µS/3pF =
31.42x106 rads/sec and stays constant. Thus we must look elsewhere for the reason.
Recall that p2  gm6/CL which explains the difference.
 p2(95µA) = 94.25x106 rads/sec, p2(121µA) = 106.6 x106 rads/sec, and p2(69µA) =
80.05 x106 rads/sec. Thus, phase margin is less during the fall time than the rise time.
SUMMARY
• Simulation and measurement of op amps has both similarities and differences
• Measurement of open loop gain is very challenging – the key is to keep the quiescent
point output of the op amp well defined
• The method of stimulating the output of the op amp or power supplies and letting the
input respond results in a robust method of measuring open loop gain, CMRR, and
PSRR
• Carefully investigate any deviations or aberrations from expected behavior in the
simulation and experimental results
• Be alert for when the small-signal model calculations are influenced by the large signal
performance

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-1
LECTURE 26 – BUFFERED OP AMPS

Outline
• Introduction
• Open Loop Buffered Op Amps
• Closed Loop Buffered Op Amps
• Use of the BJT in Buffered Op Amps
• Summary
Pages 354-370

INTRODUCTION
Buffered Op Amps
What is a buffered op amp?
Buffered op amps are op amps with the ability to drive a low output resistance and/or
a large output capacitance. This requires:
- An output resistance typically in the range of 10  Ro  1000
- Ability to sink and source sufficient current (CL·SR)
Rout Rout
+ Large Small
vIN vOUT
- vOUT’
Op Amp Buffer 070430-01
Types of buffered op amps:

- Open loop using output amplifiers
- Closed loop using negative shunt feedback to reduce the output resistance of the op
amp

OPEN LOOP BUFFERED OP AMPS

The Class A Source Follower as a Buffer
• Simple VDD
gm vIN M1
• Small signal gain ≈ g + g <1
m mbs + GL vOUT
• Low efficiency VNBias1
1 M2
• Rout = ≈ 500 to 1000
gm + gmbs
060118-10
• Level shift from input to output
• Maximum upper output voltage is limited
• Broadbanded as the pole and zero due to the source follower are close so compensation
is typically not a problem

The Push-Pull Follower as a Buffer

• Voltage loss from 2 cascaded followers VDD VDD
 gm3  gm1  VPBias1 M5
Av ≈ g + g  <1 I5 M1 I1
 m3 g
mbs3 m1 + g mbs1 + G L
VSG3 + V
• Higher efficiency DD V +
- GS1-
0.5 vIN M3 vOUT
• Rout ≈ g + g ≈ 250 to 500
m mbs VDD
M4
• Current in M1 and M2 determined by:
+ VSG2 + VDD
VGS4 + VSG3 = VGS1 + VSG2 VGS4 -
-
VNBias1 I6 I
2I6 2I5 M2 2
M6
Kn'(W4/L4) + Kp'(W3/L3) 060706-02
2I1 2I2
= Kn'(W1/L1) + Kp'(W2/L2)
Use the W/L ratios to define I1 and I2 from I5 and I6
• Maximum positive and negative output voltages are limited

Two-Stage Op Amp with Follower

VDD
M6
M3 M4 Cc M8
vout
- M1 M2
vin
+ CL
M5 I5 M7 I7 M9 I9
VNBias
060706-03
Power dissipation now becomes (I5 + I7 + I9)VDD

Gain becomes,
 gm1   gm6   gm8 
Av = g +g  g +g  g + g 
+g +g
 ds2 ds4  ds6 ds7  m8 mbs8 ds8 ds9

Source-Follower, Push-Pull Output Op Amp

VDD
M6 M9
M17
IBias M5 M10 I17

M22
R1 M8
M11
VSG18 + VSS
+
- VDD V
GS22
M7 M12 M18 - vout
Cc M19
R1 CL
M15 VSS
+
VGS19 VSG21 +
+ M1 M2 - -
R1 VDD
vin
M21
- M13 I20
M4 M3 M16 M20
M14
VSS Buffer Fig. 7.1-1
1
Rout ≈  1000, Av(0)=65dB (IBias=50µA), and GB = 60MHz for CL = 1pF
gm21+gm22
Note the bias currents through M18 and M19 vary with the signal.

Compensation of Op Amps with Output Amplifiers

Compensation of a three-stage amplifier:
This op amp introduces a third pole, p’3
(what about zeros?)
With no compensation,
Vout(s) -Avo
Vin(s) =  s  s  s 
p’ - 1 p’ - 1p’ - 1
 1  2  3 
Illustration of compensation choices:

Crossover-Inverter, Buffer Stage Op Amp

Principle: If the buffer has high output resistance and voltage gain (common source), this
is okay if when loaded by a small RL the gain of this stage is approximately unity.
• This buffer trades gain for the ability to drive a low load resistance
• The load resistance should be fixed in order to avoid changes in the buffer gain
• The push-pull common source output will give good output voltage swing capability

Crossover-Inverter, Buffer Stage Op Amp - Continued

How does the output buffer work?
The two inverters, M1-M3 and M2-M4 are designed to work over different regions of the
buffer input voltage, vin’.
Consider the idealized voltage transfer characteristic of the crossover inverters:
VDD
VDD vout
M6
M7 M3 M4 M6 Active
IBias M1-M3 M2-M4
Inverter M6 Satur- Inverter
C1 C2 vout
M5 Saturated ated
M1 M2 M5 RL M5 Active
vin'
0 vin'
VSS VA VB VDD
VSS 060706-05
Crossover voltage  VC = VB-VA  0

VC is designed to be small and positive for worst case variations in processing.

Large Output Current Buffer

In the case where the load consists of a large capacitor, the ability to sink and source a
large current is much more important than reducing the output resistance. Consequently,
the common-source, push-pull is ideal if the quiescent current can be controlled.
VDD
A possible implementation:
VDD M5
M7 I=2Ib Ib
M1
vin vout vin vout
M8 M3 M4 M9
M2
M6
Ib I=2Ib M10
If W4/L4 = W9/L9 and W3/L3 = VSS
W8/L8, then the quiescent VSS 070430-07
currents in M1 and M2 can be

determined by the following relationship:
W1/L1   W2/L2 
I1 = I2 = Ib W /L  = Ib W /L 
 7 7  10 10
When vin is increased, M6 turns off M2 and turns on M1 to source current. Similarly,
when vin is decreased, M5 turns off M1 and turns on M2 to sink current.
CLOSED LOOP BUFFERED OP AMPS

Principle
Use negative shunt feedback to reduce the output resistance of the buffer.
- Ro ROUT
vIN + vOUT
Av
RL
070430-02
• Output resistance
Ro
ROUT = 1 + A
v
• Watch out for when small RL causes Av to decrease.
• The bandwidth will be limited by the feedback (i.e. at high frequencies, the gain of Av
decreases causing the output resistance to increase.

Two Stage Op Amp with a Gain Boosted, Source Follower Buffer

VDD
1:K
M6 M9 M10
M3 M4 Cc
Rout
M8
- M1 M2 vout
vin
+
I7 M11 I11
VNBiasM5 I5
M7
070430-03
1
Rout ≈ g
m8K
Power dissipation now becomes (I5 + I7 + I11)VDD
Gain becomes,
 gm1   gm6   gm8K 
Av = g +g  g +g  g K+ g 
 ds2 ds4  ds6 ds7  m8 mbs8 K +G L

Gain Boosted, Source-Follower, Push-Pull Output Op Amp

VDD
+ M6 M9 1:K
VT+2VON M17
- M24 M23 M24
M10 I17
M5 M22
M8
M11
VSG18 +
+
IBias - VDD VGS22 Rout
M12 M18 -
M7 vout
Cc M19
M15 VSS
+
VGS19 VSG21 +
+ M1 M2 - -
R1
vin
M21
M23
- M13 I20
M4
M3 M16 M20 M25 M26
M14 1:K
070430-04 VSS Gain Enhanced Buffer
1 1000
Rout ≈ ≈ ≈ 100
K(gm21+gm22) K
Av(0)=65dB (IBias=50µA)
Note the bias currents through M18 and M19 vary with the signal.

Common Source, Push Pull Buffer with Shunt Feedback

To get low output resistance using MOSFETs, negative feedback must be used.
Ideal implementation:
Comments:
• The output resistance will be equal to rds1||rds2 divided by the loop gain
• If the error amplifiers are not perfectly matched, the bias current in M1 and M2 is not
defined

Low Output Resistance Op Amp - Continued

Offset correction circuitry:
The feedback circuitry of the two error amplifiers tries to insure that the voltages in
the loop sum to zero. Without the M9-M12 feedback circuit, there is no way to adjust the
output for any error in the loop. The circuit works as follows:
When VOS is positive, M6 tries to turn off and so does M6A. IM9 reduces thus reducing
IM12. A reduction in IM12 reduces IM8A thus decreasing VGS8A. VGS8A ideally decreases
by an amount equal to VOS. A similar result holds for negative offsets and offsets in EA2.
Low Output Resistance Op Amp - Continued

Error amplifiers:
VDD
+
VBias
M6 M5A -
M3 M4 Cc1
vin
vin MR1 M2A M1A
M1 M2 vout MR2
Cc2
+ M6A M4A M3A
VBias M5
-
A1 amplifier VSS A2 amplifier
070430-05
Basically a two-stage op amp with the output push-pull transistors as the second-stage of
the op amp.

Low Output Resistance Op Amp - Complete Schematic
RC CC
Short circuit protection(max. output 60mA):
MP3-MN3-MN4-MP4-MP5 gm1 gm6
MN3A-MP3A-MP4A-MN4A-MN5A
C1 CL
rds6||rds6A 50k R1 RL
Rout  Loop Gain ≈ 5000 = 10

Simpler Implementation of Negative Feedback to Achieve Low Output Resistance

VDD
M8 M3 M4 M6
200mA 10/1 1/1 1/1 10/1
vout
Output Resistance:
M1 M2 CL Ro
+ Rout =
vin 10/1 10/1 1+LG
-
1/1 where
M5 1
M10 1/1 Ro =
10/1 10/1 gds6+gds7
M9 M7 and
gm2
VSS Fig. 7.1-9 |LG| = 2g (gm6+gm7)Ro
m4
Therefore, the output resistance is:
1
Rout =
  gm2  

(gds6+gds7) 1 +   (gm6+gm7)Ro
 2g
 m4 

Example 26-1 - Low Output Resistance Using Shunt Negative Feedback Buffer
Find the output resistance of above op amp using the model parameters of KN’ =
120µA/V2, KP’ = 25µA/V2, N = 0.06V-1 and P = 0.08V-1.
Solution
The current flowing in the output transistors, M6 and M7, is 1mA which gives Ro of
1 1000
Ro = = 0.14 = 7.143kΩ
(N+P)1mA
To calculate the loop gain, we find that
gm2 = 2KN’·10·100µA = 490µS
gm4 = 2KP’·1·100µA = 70.7µS
and
gm6 = 2KP’·10·1000µA = 707µS
Therefore, the loop gain is
490
|LG| = 2·70.7 (0.707+0.071)7.143 = 19.26
Solving for the output resistance, Rout, gives
7.143k
Rout = 1 + 19.26 = 353 (Assumes that RL is large)

USE OF THE BJT IN BUFFERED OP AMPS

Substrate BJTs
Illustration of an NPN substrate BJT available in a p-well CMOS technology:
Emitter Base Collector
(VDD)
Collector (VDD)
n+ (Emitter) p+ n+
Base
p- well (Base)
n- substrate (Collector)
Fig. 7.1-10
Emitter
Comments:
• gm of the BJT is larger than the FET so that the output resistance w/o feedback is lower
• Collector current will be flowing in the substrate
• Current is required to drive the BJT
• Only an NPN or a PNP bipolar transistor is available

A Lateral Bipolar Transistor

VC B LC E LC
n-well CMOS technology:
n+ p+ p+ p+
• It is desirable to have the lateral
collector current much larger than the STI STI
vertical collector current.
n-well
• Triple well technology allows the Substrate
current of the vertical collector to avoid 060221-01
flowing in the substrate.
Vertical STI Lateral Collector
• Lateral BJT generally has good Collector
matching.
Emitter
Base

A Field-Aided Lateral BJT

Use minimum channel length to VC B LC E LC
enhance beta:
ßF  50 to 100 depending on the n+ p+ p+ pp++
process Keeps carriers from

STI flowing at the surface STI
and reduces 1/f noise
n-well
Substrate
060221-02
Vertical STI Lateral Collector Emitter

Collector
Base

Two-Stage Op Amp with a Class-A BJT Output Buffer Stage

VDD
Purpose of the M8-M9 source
follower: M5 M7
M12 M8
+ Q10
1.) Reduce the output resistance vin
(includes whatever is seen from the - M1 M2
vout
base to ground divided by 1+F)
IBias M9
Cc
M3 M4 CL RL
2.) Reduces the output load at the M6
M13 M11
drains of M6 and M7
VSS Output Buffer Fig. 7.1-11
r10 + (1/gm9) 1 1
Small-signal output resistance : Rout ≈ = +
1+ßF gm10 gm9(1+ßF)
= 51.6+6.7 = 58.3 where I10=500µA, I8=100µA, W9/L9=100 and ßF is 100
2KP’ Ic10
vOUT(max) = VDD - VSD8(sat) - vBE10 = VDD -  
I8(W8/L8) - Vt lnIs10 
Voltage gain:
vout  gm1  gm6  gm9  gm10RL 
    
vin ≈ gds2+gds4gds6+gds7gm9+gmbs9+gds8+g101+gm10RL
Compensation will be more complex because of the additional stages.
Example 26-2 - Designing the Class-A, Buffered Op Amp

Use an n-well, 0.25µm CMOS technology to design an op amp using a class-A, BJT
output stage to give the following specifications. Assume the channel length is to be
0.5µm. The FETs have the model parameters of KN’ = 120µA/V2, KP’ = 25µA/V2, VTN
= |VTP| = 0.5V, N = 0.06V-1 and P = 0.08V-1 along with the BJT parameters of Is =
10-14A and ßF = 50.
VDD = 2.5V VSS = 0V GB = 10MHz Avd(0)  2500V/V Slew rate  10V/µs
RL = 500 Rout  50 CL = 100pF ICMR = +1V to 2V
Solution
VDD
A quick comparison shows that the VPB1 VPB1
I4 I5 M14
specifications of this problem are similar to
M4 M5 I15
the folded cascode op amp that was designed Rout
VPB2 vOUT
in Ex. 24-4. Borrowing that design for this I1 I2 I12
I6 I7
example results in the following op amp. M6 M7 CL
M1 M2 VNB2 M12
+
Therefore, the goal of this example will vIN
- M8 M9
be the design of M12 through Q15 to satisfy M3 M11 V
NB1
Q15
VNB1 I3
the slew rate and output resistance M10 M13
requirements. 070430-06


BJT follower (Q15):
SR = 10V/µs and 100pF capacitor give I15 = 1mA.
 Assuming the gate of M14 is connected to the gate of M5, the W/L ratio of M14
becomes
W14/L14 = (1000µA/125µA)160 = 1280  W14 = 640µm
I15 = 1mA  1/gm15 = 0.0258V/1mA = 25.8
MOS follower:
To source 1mA, the BJT requires 20µA (ß =50) from the MOS follower (M12-M13).
Therefore, select a bias current of 100µA for M13. If the gates of M3 and M13 are
connected together, then
W13/L13 = (100µA/100µA)15 = 15  W13 = 7.5µm
To get Rout = 50, if 1/gm15 is 25.8, then design gm12 as
1 1 1 1
= = 24.2 g m12 (24.2)(1+ß ) 24.2·51 = 810µS
= =
gm15 gm12(1+ßF) F
 gm12 and I12  W/L = 27.3 ≈ 30  W12 = 15µm

To calculate the voltage gain of the MOS follower we need to find gmbs9 (N = 0.4 V).
gm12N 810·0.4
 gmbs12 = = = 158µS
2 2F + VBS12 2 0.5+0.55
where we have assumed that the value of VSB12 is approximately 1.25V – 0.7V = 0.55V.
810µS
 AMOS = = 0.825
810µS+158µS+6µS+8µS
The voltage gain of the BJT follower is
500
ABJT = 25.8+500 = 0.951 V/V
Thus, the gain of the op amp is
Avd(0) = (4,680)(0.825)(0.951) = 3,672 V/V
The power dissipation of this amplifier is,
Pdiss. = 2.5V(125µA+125µA+100µA+1000µA) = 3.375mW
The signal swing across the 500 load resistor will be restricted to ±0.5V due to the
1000µA output current limit.
SUMMARY
• A buffered op amp requires an output resistance between 10  Ro  1000
• Output resistance using MOSFETs only can be reduced by,
- Source follower output (1/gm)
- Negative shunt feedback (frequency is a problem in this approach)
• Use of substrate (or lateral) BJT’s can reduce the output resistance because gm is larger
than the gm of a MOSFET
• Adding a buffer stage to lower the output resistance will most likely complicate the
compensation of the op amp

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-1
LECTURE 27 – HIGH SPEED OP AMPS

Outline
• Extending the GB of conventional op amps
• Cascade Amplifiers
- Voltage amplifiers
- Voltage amplifiers using current feedback
• Summary
Pages 370-386

INCREASING THE GB OF OP AMPS

What is the Influence of GB on the Frequency Response?
The unity-gainbandwidth represents a limit in the trade-off between closed loop voltage
gain and the closed-loop -3dB frequency.
Example of a gain of -10 voltage amplifier:
What defines the GB?

We know that
gm
GB = C
where gm is the transconductance that converts the input voltage to current and C is the
capacitor that causes the dominant pole.
This relationship assumes that all higher-order poles are greater than GB.

What is the Limit of GB? jw

jGB’
The following illustrates what happens
when the next higher pole is not greater Dominant jGB
High Order Pole
than GB: Poles
a
-wA GB
For a two-stage op amp, the poles and zeros are:

-gm1
1.) Dominant pole p1 =
Av(0)Cc 150504-01
-gm6
2.) Output pole p2 = C
L
-gm3
3.) Mirror pole p3 = C +C
gs3 gs4
and z3 = 2p3
-1
4.) Nulling pole p4 =
RzCI
-1
5.) Nulling zero z1 =
RzCc-(Cc/gm6)

Higher-Order Poles
For reasonable phase margin, the smallest higher-order pole should be 2-3 times larger
than GB if all other higher-order poles are larger than 10GB.
Av(0) dB
Larger non- Smallest non- Dominant
dominant poles dominant pole pole
-10GB -GB
10GB
0dB
GB GB log10w
Av(0)
060709-01
If the higher-order poles are not greater than 10GB, then the distance from GB to the
smallest non-dominant pole should be increased for reasonable phase margin.

Increasing the GB of a Two-Stage Op Amp

1.) Use the nulling zero to cancel the closest pole beyond the dominant pole.
2.) The maximum GB would be equal to the magnitude of the second closest pole
beyond the dominant pole.
3.) Adjust the dominant pole so that 2.2GB  (second closest pole beyond the dominant
pole)
Illustration which assumes that p2 is the next closest pole beyond the dominant pole:

Example 27-1 - Increasing the GB of the Op Amp Designed in Ex. 23-1

Use the two-stage op amp designed in Examples 23-1 and 23-2 and apply the above
approach to increase the gainbandwidth VDD = 2.5V
M3 M4 M6
as much as possible. Use the capacitor 15µm 15µm 85µm
0.5µm 0.5µm 0.5µm
values in the table shown along with Cox Cc =3pF
vout
= 6fF/µm2. 30µA M1
1.5µm 1.5µm
M2
Rz = 4.56kW CL =
-
0.5µm 0.5µm 95µA 10pF
Solution vin
+
1.) First find the values of p2, p3, and p4. 30µA
3µm 10µm
0.5µm 3µm 0.5µm
a.) From Ex. 23-2, we see that M8 M5 0.5µm M7
p2 = -95x106 rads/sec. 140709-01
b.) p3 was found in Ex. 23-1 as Type P-Channel N-Channel Units

CGSO 220 10-12 220  10-12 F/m
p3 = -1.25x109 rads/sec. (also CGDO 220  10-12 220  10-12 F/m
there is a zero at -2.5x109 CGBO 700  10-12 700  10-12 F/m
rads/sec.) CJ F/m2
560  10-6 770  10-6
CJSW 350  10-12 380  10-12 F/m
MJ 0.5 0.5
MJSW 0.35 0.38


(c.) To find p4, we must find CI which is the output capacitance of the first stage of the
op amp. CI consists of the following capacitors,
CI = Cbd2 + Cbd4 + Cgs6 + Cgd2 + Cgd4
For Cbd2 the width is 1.5µm  L1+L2+L3=3µm  AS/AD=4.5µm2 and PS/PD=9µm.
For Cbd4 the width is 15µm  L1+L2+L3=3µm  AS/AD=45µm2 and PS/PD=36µm.
From Table 3.2-1:
Cbd2 = (4.5µm2)(770x10-6F/m2) + (9µm)(380x10-12F/m) = 3.47fF+3.42fF ≈ 6.89fF
Cbd4 = (45µm2)(560x10-6F/m2) + (36µm)(350x10-12F/m) = 25.2fF+12.6F ≈ 37.8fF
Cgs6 in saturation is,
Cgs6=CGDO·W6+0.67(CoxW6L6)=(220x10-12)(85x10-6)+(0.67)(6x10-15)(42.5)
= 18.7fF + 255fF = 273.7fF
Cgd2 = 220x10-12x1.5µm = 0.33fF and Cgd4 = 220x10-12x15µm = 3.3fF
Therefore, CI = 6.9fF + 37.8fF + 273.7fF + 0.33fF + 3.3fF = 322fF. Although Cbd2 and
Cbd4 will be reduced with a reverse bias, let us use these values to provide a margin.
Thus let CI be 322fF.
In Ex. 23-2, Rz was 4.564k which gives p4 = - 0.680x109 rads/sec.

Therefore, the roots are:
jw
p2 = -0.095G New GB
z3 = -2.5G p3 = -1.25G p4 = -0.68G
s x 109
-3 -2 -1
070503-01
When p2 is cancelled, the next smaller pole is p4 which will define the new GB. 2.)
Using the nulling zero, z1, to cancel p2, gives p4 as the next smallest pole.
For 60° phase margin GB = |p4|/2.2 if the next smallest pole is more than 10GB.
 GB = 0.680x109/2.2 = 0.309x109 rads/sec. or 49.2MHz.
This value of GB is designed from the relationship that GB = gm1/Cc. Assuming gm1 is
constant, then Cc = gm1/GB = (94.25x10-6)/(0.309x109) = 307fF. It might be useful to
increase gm1 in order to keep Cc above the surrounding parasitic capacitors (Cgd6 =
18.7fF). The success of this method assumes that there are no other roots with a
magnitude smaller than 10GB.
The result of this example is to increase the GB from 5MHz to 49MHz.

Example 27-2 - Increasing the GB of the Folded Cascode

VDD
Use the folded-cascode op amp designed in
VPB1
Example 24-4 and apply the above approach to I4 I5
increase the gainbandwidth as much as possible. M4 M5
Assume that the drain/source areas are equal to
RA VPB2 RB
2µm times the width of the transistor and that all I1 I2
I6 I7
voltage dependent capacitors are at zero voltage. M6 M7
vOUT
+
M1 M2 VNB2
Solution vIN
- M8 M9 CL
The poles of the folded cascode op amp are: M3
VNB1 I3 M11
-1 M10
pA ≈ R C (the pole at the source of M6 )
A A 060628-04
-1
pB ≈ R C (the pole at the source of M7)
B B
-gm10 M6
p6 ≈ C (the pole at the drain of M6)
6 IT = gm8VT rds8 gm10
IT M8
-gm8rds8gm10 VT 1 M10
p8 ≈ (the pole at the source of M8) R8 = = +
C8 IT gm8rds8 gm10 VT
- 150708-01
-gm9
p9 ≈ C (the pole at the source of M9)
9

Let us evaluate each of these poles.
1.) For pA, the resistance RA is approximately equal to gm6 and CA is given as
CA = Cgs6 + Cbd1 + Cgd1 + Cbd4 + Cbs6 + Cgd4
From Ex. 24-4, gm6 = 774.6µS and capacitors giving CA are found as,
Cgs6 = (220x10-12·80x10-6) + (0.67)(80µm·0.5µm·6fF/µm2) = 177.6fF
Cbd1 = (770x10-6)(16.5x10-6·2x10-6) + (380x10-12)(37x10-6) = 39.5fF
Cgd1 = (220x10-12·16.5x10-6) = 3.6fF
Cbd4 = Cbs6 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fF
and
Cgd4 = (220x10-12)(80x10-6) = 17.6fF
Therefore,
CA = 177.6fF + 39.5fF + 3.6fF + 147fF + 17.6fF + 147fF = 0.532pF
Thus,
-774.6x10-6
pA = 0.532x10-12 = -1.456x109 rads/sec.
2.) For the pole, pB, the capacitance connected to this node is
CB = Cgd2 + Cbd2 + Cgs7 + Cgd5 + Cbd5 + Cbs7

The various capacitors above are found as
Cgd2 = (220x10-12·16.5x10-6) = 3.6fF
Cbd2 = (770x10-6)(16.5x10-6·2x10-6) + (380x10-12)(37x10-6) = 39.5fF
Cgs7 = (220x10-12·80x10-6) + (0.67)(80µm·0.5µm·6fF/µm2) = 177.6fF
Cgd5 = (220x10-12)(80x10-6) = 17.6fF
and
Cbd5 = Cbs7 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fF
The value of CB is the same as CA and gm6 is assumed to be the same as gm7 giving pB =
pA = -1.456x109 rads/sec.
3.) For the pole, p6, the capacitance connected to this node is
C6= Cbd6 + Cgd6 + Cgs10 + Cgs11+ Cbd8 + Cgd8
The various capacitors above are found as
Cbd6 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fF
Cgs10 = Cgs11 = (220x10-12·10x10-6) + (0.67)(10µm·0.5µm·6fF/µm2) = 22.2fF
Cbd8 = (770x10-6)(10x10-6·2x10-6) + (380x10-12)(2·12x10-6) = 24.5fF
Cgd8 = (220x10-12)(10x10-6) = 2.2fF and Cgd6 = Cgd5 =17.6fF
Therefore, C6 = 147fF + 17.6fF + 22.2fF + 22.2fF + 2.2fF + 17.6fF = 0.229pF

From Ex. 24-4, gm10 = 600x10-6. Therefore, p6, can be expressed as M6
1
600x10-6 gm10
-p6 = -12 = 2.62x109 rads/sec.
0.229x10 M8
4.) Next, we consider the pole, p8. The capacitance connected to this node is M10
C8= Cbd10 + Cgd10 + Cgs8 + Cbs8 150504-02
These capacitors are given as,

Cbs8 = Cbd10 = (770x10-6)(10x10-6·2x10-6) + (380x10-12)(2·12x10-6) = 24.5fF
Cgs8 = (220x10-12·10x10-6) + (0.67)(10µm·0.5µm·6fF//µm2) = 22.2fF
and
Cgd10 = (220x10-12)(10x10-6) = 2.2fF
The capacitance C8 is equal to
C8 = 24.5fF + 2.2fF + 22.2fF + 24.5fF = 73.4FF
Using the values of Ex. 24-4 of 600µS, the pole p8 is found as,
-p8 = gm8rds8 gm10/C8 = -600µS·600µS·/4.5µS·73.4fF = -1090x109 rads/sec.
5.) The capacitance for the pole at p9 is identical with C8. Therefore, since gm9 is
600µS, the pole p9 is -p9 = 8.17x109 rads/sec.

The poles are summarized below:
pA = -1.456x109 rads/sec pB = -1.456x109 rads/sec p6 = -2.62x109 rads/sec
p8 = -1090x109 rads/sec p9 = -8.17x109 rads/sec
jw
p8 = -1090G pA = pB New GB
p9 = -8.17G p6 = -2.62G = -1.456G = 0.2x109
-8 -7 -6 -5 -4 -3 -2 -1 s x 109
070503-02
The smallest of these poles is pA or pB. Since p6 is not much larger than pA or pB, we
will find the new GB by dividing pA or pB by 4 (which is a guess rather than 2.2) to get
364x106 rads/sec. Thus the new GB will be 364/2 or 58MHz.
Checking our guess gives a phase margin of,
PM = 90° - 2tan-1(0.364/1.456) - tan-1(0.364/2.62) = 54° which is okay
The magnitude of the dominant pole is given as
pdominant = GB/Avd(0) = 364x106/3,678 = 99,000 rads/sec.
The value of load capacitor that will give this pole is
CL = (pdominant·Rout)-1 = (99x103·7.44M)-1 = 1.36pF
Therefore, the new GB = 58MHz compared with the old GB = 10MHz.
Elimination of Higher-Order Poles

Principle - minimize the number of nodes in the amplifier.
The minimum circuitry for a cascode op amp is shown below:
VDD
vin + VPB1
M4 Non-
dominant
VPB2 M3 Pole
vout
Dominant Pole
VNB2 M2 CL
Non-
M1 dominant
vin + VNB1 Pole
060710-01
If the source-drain area between M1 and M2 and M3 and M4 can be minimized, the non-
dominant poles will be quite large.

Dynamically Biased, Push-Pull, Cascode Op Amp

Push-pull, cascode amplifier: M1-M2 and M3-M4
Bias circuitry: M5-M6-C2 and M7-M8-C1
Operation:
VDD VDD
+
VB2 VDD-VB2-(vin+-vin-)
M8 - M4
M7 + + M3
C1 VDD-VB2-vin+ VDD-VB2-vin+ C1
- vin- - vout
IB vin+
+ +
C2 vin+-VSS-VB1 vin+-VSS-VB1 C2
M6 - - M2
M5 + M1
VB1 VSS+VB1-(vin+-vin-)
-
VSS VSS
Equivalent circuit during the f1 clock period Equivalent circuit during the f2 clock period.
120523-07 120523-08

Dynamically Biased, Push-Pull, Cascode Op Amp - Continued

This circuit will operate on both clock phases† .
Performance (1.5µm CMOS):

• 1.6mW dissipation
• GB  130MHz (CL=2.2pF)
• Settling time of 10ns (CL=10pF)
This amplifier was used with a

28.6MHz clock to realize a 5th-order
switched capacitor filter having a
cutoff frequency of 3.5MHz.
† S. Masuda, et. al., “CMOS Sampled Differential Push-Pull Cascode Op Amp,” Proc. of 1984 International Symposium on Circuits and Systems,
Montreal, Canada, May 1984, pp. 1211-12-14.
CASCADED AMPLIFIERS USING VOLTAGE AMPLIFIERS

Bandwidth of Cascaded Amplifiers
Cascading of low-gain, wide-bandwidth amplifiers:
Ao Ao Ao
s/w1+1 s/w1+1 s/w1+1
Vin Vout
A1 A2 An
Ao n
s/w1+1 060710-02
Overall gain is Aon

-3dB frequency is,
-3dB = 1 21/n-1
If Ao = 10, 1 = 300x106 rads/sec. and n = 3, then
Overall gain is 60dB and -3dB = 0.511 = 480x106 rads/sec.  76.5 MHz

Voltage Amplifier Suitable for Cascading

VDD
VPB1 VPB1
I5 I3 I4 I6
M5 M3 Vout M4 M6
M1 - + M2
+ I1 I2
Vin
-
VNB1 I7
M7
060710-03
Voltage Gain:
Vout gm1 Kn'(W1/L1)(I3+I5)
Vin = gm3 = Kp' (W3/L3)I3
gm3
-3dB ≈ C
gs1

Ex. 27-3 - Design of a Voltage Amplifier for Cascading

Design the previous voltage amplifier for a gain of Ao = 10 and a power dissipation of no
more than 1mW. The design should permit Ao to be well defined. What is the -3dB for
this amplifier and what would be the -3dB for a cascade of three identical amplifiers?
Solution VDD
To enhance the accuracy of the gain, we replace M3 VPB1 VPB1
I5 I3 I4 I6
and M4 with NMOS transistors to avoid the M5 M3 M4 M6
Vout
variation of the transconductance parameter. This M1 - + M2
assumes a p-well technology to avoid bulk effects. + I1 I2
Vin
The gain of 10 requires, -
W1 W3 VNB1 I7
M7
L1 (I3+I5) = 100 L3 I3 060711-01
If VDD = 2.5V, then 2(I3+I5)·2.5V = 1000µW.

Therefore, I3+I5 = 200µA. Let I3 = 20µA and W1/L1 = 10W3/L3.
Choose W1/L1 = 5µm/0.5µm which gives W3/L3 = 0.5µm/0.5µm. M5 and M6 are
designed to give I5 = 180µA and M7 is designed to give I7 = 400µA.
The dominant pole is gm3/Cout.
Ex. 27-3 – Continued

Cout = Cgs3+Cbs3+Cbd1+Cbd5+Cgd1+Cgd5+Cgs1(next stage) ≈ Cgs3 + Cgs1
Using Cox = 60.6x10-4 F/m2, we get,
Cout ≈ (2.5+2.5)x10-12 m2x 60.6x10-4 F/m2 = 30.3fF  Cout ≈ 30fF
gm3 = 2·120·1·20 µS = 69.3µS
 Dominant pole ≈ 69.3µS/30fF = 23.1x108 rads/sec. f-3dB = 368MHz
The bandwidth of three identical cascaded amplifiers giving a low-frequency gain of
60dB would have a f-3dB of
f-3dB(Overall) = f-3dB 21/3-1 = 368 MHz (0.5098) = 187 MHz.
Pdiss = 3mW dB
3 cascaded stages
60
2 cascaded stages -60dB/dec.
40
Single stage -40dB/dec.
20
187MHz -20dB/dec.
0 log10(f)
368MHz 060711-02
CASCADED AMPLIFIERS USING CURRENT FEEDBACK AMPLIFIERS

Advantages of Using Current Feedback
Why current feedback?
• Higher GB
• Less voltage swing  more dynamic range
What is a current amplifier?
Requirements:
io = Ai(i1-i2)
Ri1 = Ri2 = 0
Ro = 
Ideal source and load requirements:
Rsource = 
RLoad = 0

Bandwidth Advantage of a Current Feedback Amplifier

Consider the inverting voltage amplifier
shown using a current amplifier with negative
current feedback:
The output current, io, of the current
amplifier can be written as
io = Ai(s)(i1-i2) = -Ai(s)(iin + io)
The closed-loop current gain, io/iin, can be found as
io -Ai(s)
iin = 1+Ai(s)
However, vout = ioR2 and vin = iinR1. Solving for the voltage gain, vout/vin gives
vout ioR2 -R2  Ai(s) 
  
vin = iinR1 =  R1  1+Ai(s)
Ao
If Ai(s) = , then
(s/A) + 1
vout -R2  Ao   A(1+Ao)  -R2Ao
=     Av(0) =
vin  R1  1+Ao s + A(1+Ao) R1(1+Ao)
and -3dB = A(1+Ao)

Bandwidth Advantage of a Current Feedback Amplifier - Continued

The unity-gainbandwidth is,
R2 A o R2 R2
GB = |Av(0)| -3dB = R (1+A ) · A(1+Ao) = R Ao·A = R GBi
1 o 1 1
where GBi is the unity-gainbandwidth of the current amplifier.
Note that if GBi is constant, then increasing R2/R1 (the voltage gain) increases GB.
Illustration:
Note that GB2 > GB1 > GBi

The above illustration assumes that the GB of the voltage amplifier realizing the voltage
buffer is greater than the GB achieved from the above method.
Current Feedback Amplifier

In a current mirror implementation of the current amplifier, it is difficult to make the
input resistance sufficiently small compared to R1.
This problem can be solved using a transconductance input stage shown in the following
block diagram:
RF
+
Vin GM
- Ai Vout
060711-04
Vout -GMRFAi
Vin = 1 +Ai

Differential Implementation of the Current Feedback Amplifier

VDD
VPB1
VPB2
Rin
Vin+ Vin-
M1 R Iin M2
F RF
+ Vout -
I nI nI
I
VNB2
nIin nIin
1:n 1:n
150504-03
gm1 Vin+- Vin- n (2RF)

Iin = 1+ 0.5g R   , Iin = (1+n)I, and Vout = 1+n Iin
m1 in  2 
Vout 2nRF
∴ V ≈ (1+n)R
in in
A 20dB Voltage Amplifier using a Current Amplifier

The following circuit is a programmable voltage amplifier with up to 20dB gain:
VDD
R1
vin+ vin-
M1 M2
R2 R2
+1 + vout - +1
VBias
x4 x2 x1 VSS x1 x2 x4
=1/8 = 1/4 =1/2 =1/2 = 1/4 =1/8
Fig. 7.2-135A
R1 and the current mirrors are used for gain variation while R2 is fixed.

Frequency Response of a 60dB PGA

Includes output buffer:

SUMMARY
• Increasing the GB of an op amp requires that the magnitude of all non-dominant poles
are much greater than GB from the origin of the complex frequency plane
• The practical limit of GB for an op amp is approximately 5-10 times less than the
magnitude of the smallest non-dominant pole (≈ 100MHz)
• To achieve high values of GB it is necessary to eliminate the non-dominant poles
(which come from parasitics) or increase the magnitude of the non-dominant poles
• The best way to achieve high-bandwidth amplifiers is to cascade high-bandwidth
voltage amplifiers
• If the gain of the high-bandwidth voltage amplifiers is well defined, then it is not
necessary to use negative feedback around the amplifier
• Amplifiers with well-defined gains are achievable with a -3dB bandwidth of 100MHz

Lecture 28 – Differential-In, Differential-Out Op Amps (6/25/14) Page 28-1
LECTURE 28 – DIFFERENTIAL-IN, DIFFERENTIAL-OUT OP

AMPS
Outline
• Introduction
• Examples of differential output op amps
• Common mode output voltage stabilization
• Summary
Pages 386-397

INTRODUCTION
Why Differential Output Op Amps?
• Cancellation of common mode signals including clock feedthrough
• Increased signal swing
v1
A v1-v2
2A
t
v2 -A t
A
t -2A Fig. 7.3-1
-A
• Cancellation of even-order harmonics
Symbol:

Common Mode Output Voltage Stabilization

If the common mode gain not small, it may cause the common mode output voltage to
be poorly defined.
Illustration:
vod vod vod
VDD VDD VDD
0 t 0 t 0 t
VSS VSS VSS
CM output voltage properly defined, CM output voltage too large, CM output voltage too small,
Vcm = 0 Vcm= 0.5VDD Vcm= 0.5VSS 070506-01
Remember that:
vOUT = Avd(vID) ± Acm(vCM)

EXAMPLES OF DIFFERENTIAL OUTPUT OP AMPS (OTA’S)

Two-Stage, Miller, Differential-In, Differential-Out Op Amp
VDD
Note that the +
VBP
upper ICMR is M8 - M6
Cc Rz
M3 M4
Rz Cc
VDD - VSGP + VTN vo1
vo2
vi1 M1 M2 vi2
M5
M9 + M7
VBN
-
VSS Fig. 7.3-3
(OCMR) = VDD+ |VSS| - VSDP(sat) - VDSN(sat)
The maximum peak-to-peak output voltage  2·OCMR
Conversion between differential outputs and single-ended outputs:

Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Push-Pull Output

VDD
+
VBP
M3 -
M4
M13 M6
M7 M14
vo1 Cc Rz Rz C c vo2
vi1 vi2
M1 M2
M5
M9 M10 + M12 M8
VBN
-
VSS Fig. 7.3-6
Comments:
• Able to actively source and sink output current
• Output quiescent current poorly defined

Folded-Cascode, Differential Output Op Amp

VDD
VPB1
I4 I5
M4 M5
I6 VPB2 I7
I1 I2 M6 M7
CL - vOUT +
M1 M2 CL
+ VNB2
vIN
- M8 M9
M3 VNB1
VNB1 I3 M11
M10
060717-01
• No longer has the low-frequency asymmetry in signal path gains.

• Class A

Enhanced-Gain, Folded-Cascode, Differential Output Op Amp

VDD What about the A amplifier?
VPB1
M10 M11 Below is the upper A amplifier:
VPB1 VDD
M3
+A - VPB1
+ - +
M7 M8
vIN M8 M9
- - vOUT + M10
M1 M2 VPB2M9 vin+ vin- VPB2
M6 M7
M2 M3
- + vout-
M1 M4 vout+
+ A- VNB1 VBias
M12
M11 M5 M6
M4 060718-02
VNB1 M5
Note that VBias controls the dc voltage at the
060718-01
input of the A amplifier through the negative
feedback loop.
• Balanced inputs
• Class A
Push-Pull Cascode Op Amp with Differential-Outputs

VDD
M7 M3 M4 M6 M8
M5
M21 M20
M9 M10
vi1 M1 M2 vi2 M19
vo1 R2 M22 R1 vo2
M15 M16
M17
VBias M18
M23
M13 M12
M11 M14
VSS Fig. 7.3-8
• Output quiescent currents are well defined

• Self-biased circuits can be replaced with VNB2 and VPB2

Folded-Cascode, Push-Pull, Differential Output Op Amp

VDD
VPB1 VPB1
I14 I15 I I7
0.5gm2vin 6
M14 M15 M6 M7
I16 VPB2 I17 I 1 I2 I4 0.5g v I8 VPB2 I9
m4 in
M16 M17 I3 M8 M9
+
vIN M1 M2 M3 M4 0.5gm4vin
- 0.5gm2vin
M5 CL - vOUT + CL
VNB1 I5
0.5gm3vin
0.5gm1vin
0.5gm1vin
VNB2 VNB2
0.5gm3vin
M18 M10 M11
M19
M20 M12 M13
M21
060717-02
I6 = I7 = I14 = I15 > 0.5I5
I5 = I1 + I2 + I3 + I4
Av = gmRout(diff)
Enhanced-Gain, Folded-Cascode with Push-Pull Outputs

VDD
VPB1 VPB1
M10 M11 M6 M7
VPB2
M12 M13 +A -
+ - +
vIN M1 M2 M3 M4
- M8 M9
M5
VNB1 CL - vOUT + CL
M15 M18
VNB2 - + VNB2
M14 +A - M19
M16 M17 M20 M21

060718-06
• Gain approaches gm3rds3

Cross-Coupled Differential Amplifier Stage

The cross-coupled input stage allows the push-pull output quiescent current to be well
defined.
i1 i2
+ M1 M2 +
VGS1 vGS1 vGS2 VGS2
- -
vi1 vi2
+ +
VSG3 vSG3 vSG4 VSG4
- -
M3 M4
i2 i1
Fig. 7.3-9
Operation:
Voltage loop vi1 - vi2 = -VGS1+ vGS1 + vSG4 - VSG4 = VSG3 - vSG3 - vGS2 + VGS2
Using the notation for ac, dc, and total variables gives,
vi2 - vi1 = vid = (vsg1 + vgs4) = -(vsg3 + vgs2)
If gm1 = gm2 = gm3 = gm4, then half of the differential input is applied across each
transistor with the correct polarity.
gm1vid gm4vid gm2vid gm3vid
 i1 = 2 = and i2 = - 2 = - 2
2
Class AB, Differential Output Op Amp using a Cross-Coupled Differential Input

Stage
VDD
M9 M7 M8 M10
M25
M26
M13 M24
vi1 vi2
M1 M2
M21 M22 R1
M14
vo1
vo2
M19 M3 M4 M20
M15 R2
M16
M27
M17 M18
M23
M28 +
VBias
M11 M12
- M5 M6
VSS Fig. 7.3-10
Quiescent output currents are defined by the current in the input cross-coupled
differential amplifier.
COMMON MODE OUTPUT VOLTAGE STABILIZATION

Common Mode Feedback Circuits
Because the common mode gain is undefined, any common mode signal at the input
can cause the output common mode voltage to be improperly defined. The common
mode output voltage is stabilized by sensing the common mode output voltage and using
negative feedback to adjust the common mode voltage to the desired value.
Model for the Output of Differential Output Op Amps:
VDD VDD
io1(source) Ro1 Ro2 io2(source) io1(source) Ro1 Ro2 io2(source)

vo1 vo2 vo1 vo2
Io1(sink) Ro3 Ro4 Io2(sink) io1(sink) Ro3 Ro4 io2(sink)
Class A Output Push-Pull Output 060718-08
Roi represents the self-resistance of the output sink/sources.

1.) If the common mode output voltage increases the sourcing current is too large.
2.) If the common mode output voltage decreases the sinking current is too large.

Conceptual View of Common-Mode Feedback
Function of the common-mode feedback circuit:

1.) If the common-mode output voltage increases, decrease the upper currents sources or
increase the lower current sink until the common-mode voltage is equal to VCMREF.
2.) If the common-mode output voltage decreases, increase the upper currents sources or
decrease the lower current sink until the common-mode voltage is equal to VCMREF.

Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Common-Mode

Feedback
VDD
+
M10 VBP M11
M7 - M6
Cc Rz
M3 M4
Rz Cc vo2
vo1
vi1 M1 M2 vi2
M5
M9 + M8
VBN
-
VSS Fig. 7.3-12
Comments:
• Simple
• Unreferenced – value of common mode output voltage determined by the circuit
characteristics

Common Mode Feedback Circuits

Implementation of common mode feedback circuit:
VDD
M3 M4
IBias MC3
Common- I MC4 vo1 I3 I4 vo2
C3 IC4 Ro1 Ro2
mode feed-
back circuit
MC1 MC2A
vi1 vi2
VCM M1 M2
MC2B
MC5
MB M5
060718-10
This scheme can be applied to any differential output amplifier.
CM Loop Gain = -gmC1Ro1 which can be large if the output of the differential output
amplifier is cascaded or a gain-enhanced cascode.
The common-mode loop gain may need to be compensated for proper dynamic
performance.

Common Mode Feedback Circuits – Continued

The previous circuit suffers when the input common mode voltage is low because the
transistors MC2A and MC2B have a poor negative input common mode voltage.
The following circuit alleviates this disadvantage:
VDD
M3 M4
IBias MC3
MC4 vo1 I3 I4 vo2
Common-
IC3 IC4
mode feed-
back circuit
RCM1 RCM2
MC1 MC2
vi1 vi2
VCM M1 M2
MC5 M5
MB
060718-11

An Improved Common-Mode Feedback Circuit

The resistance loading of the previous circuit can be avoided in the following CM
feedback implementation:
VDD
M5 M6
CM Correction Circuitry
vo1 M1 M2 M3 M4 vo2
RCM RCM
VCMREF
060718-12
This circuit is capable of sustaining a large differential voltage without loading the
output of the differential output op amp.

Frequency Response of the CM Feedback Circuit

Consider the following CM feedback circuit implementation:
VDD
VPB1
M12
M4 M5
VPB2
M6 M7
vOUT
- +
M1 M2
+
vIN M13 M14
- Cc
M3 VNB2 VCMREF
Cc
VNB1 M8 M9
M11
M10 M15 M16
070506-02
The CM feedback path has two poles – one at the gates of M10 and M11 and the
dominant output pole of the differential output op amp.
Can compensate with Miller capacitors as shown.

Improved CM Feedback Frequency Response

The circuit on the previous page can be modified to eliminate the pole at the gates of
M10 and M11 as follows:
VDD
VPB1
M12
M4 M5
VPB2
M6 M7
vo1 M13 M14
vo2
M1 M2
+ VNB2
VCMREF
vin
- M8 M9 VNB2
M3 VNB1 M19 M18
VNB1
M10 M11 M15
M17 M16
060718-14
• The need for compensation of the common mode loop no longer exists since there is
only one dominant pole
• The dominant pole of the differential amplifier becomes the dominant pole of the
common mode feedback
Implications of the Common Mode Feedback Correction Bandwidth

We have seen from the previous slides that the bandwidth of the common mode feedback
correction circuit can be equal, less, or larger than the bandwidth of the differential gain
of the op amp.
Common mode feedback BW < Differential mode BW:
- Common mode feedback correction circuit responds slower than the differential
output voltage changes
- It is possible that the CM feedback correction circuit will not correct for the
highest frequency CM disturbances and the differential output signal may be
saturated or clipped
Common mode feedback BW ≈ Differential mode BW:
- The CM feedback correction circuit should be able to correct for all CM
disturbances
- The compensation of the differential mode can be used for the CM feedback
correction circuit
Common mode feedback BW > Differential mode BW:
- The CM feedback correction circuit will be able to correct for all CM disturbances
- Difficult to keep stable because of higher BW and can amplify noise
A Common Mode Feedback Correction Scheme for Discrete Time Applications

Correction Scheme:
Operation:
1.) During the 1 phase, both Ccm are charged to the desired value of Vocm and CMbias
= Vocm.
2.) During the 2 phase, the Ccm capacitors are connected between the differential
outputs and the CMbias node. The average value applied to the CMbias node will be
Vocm.

Example of a Common-Mode Output Voltage Stabilization Scheme for Discrete-

Time Applications
Common mode VDD
adjustment phase: VPB1 M15
Switches S1, S2 and S3 Discrete time common
M4 M5
are closed. C1 and C2 VPB2
mode correction circuit
are charged to the value M6 M7 S4 S1
necessary for I12 and I13 C1 S2
- vOUT +
to keep the common M1 M2
+ C2
vIN
mode output voltage at -
M3 VNB2 S5 S3
VCM. V M8 M9
NB1 I12 VCM
Amplification phase: I13
VNB1 M12 M13 M14
Switches S4 and S5 are M10 M11
closed. If the common
mode output voltage is 070506-03
not at VCM, the currents I12 and I13 will change to force the value of the common mode
output voltage back to VCM.

Correction of Channel Charge and Clock Feedthrough

In the discrete-time common mode correction schemes, the switches can introduce
error due to channel charge and clock feedthrough.
Through simulation, these errors can be predicted and corrected by applying a
correction signal superimposed upon the error signal to achieve the desired (target)
common mode voltage.
General principle:

SUMMARY
• Advantages of differential output op amps:
- 6 dB increase in signal amplitude
- Cancellation of even harmonics
- Cancellation of common mode signals including clock feedthrough
• Disadvantages of differential output op amps:
- Need for common mode output voltage stabilization
- Compensation of common mode feedback loop
- Difficult to interface with single-ended circuits
• Most differential output op amps are truly balanced
• For push-pull outputs, the quiescent current should be well defined
• Common mode feedback schemes include,
- Continuous time
- Discrete time

Lecture 29 – Low Power and Low Noise Op Amps (6/25/14) Page 29-1
LECTURE 29 – LOW POWER AND LOW NOISE OP AMPS

Outline
• Review of subthreshold operation
• Low power op amps
• Review of MOSFET noise modeling and analysis
• Low noise op amps
• Summary
Pages 398-419

REVIEW OF SUBTHRESHOLD OPERATION

Subthreshold Operation
Most micropower op
amps use transistors in
the subthreshold region.
Subthreshold
characteristics:
The model that has been developed for the large signal sub-threshold operation is:
iD = It L exp nV 1 + V  where vDS > 0 and VDS(sat) = VON = VGS -VT = 2nVt
 t  A
Small-signal model:
diD | W It vGS-VT vDS ID qID ID Cox
gm = =I exp 1 + = = =
dvGS Q t L nVt  nV t  V A nV t nkT Vt Cox+Cjs
diD | ID
gds = dv 
DS Q VA

Boundary Between Subthreshold and Strong Inversion

It is useful to develop a means of estimating when a MOSFET is making the transition
between subthreshold and strong inversion to know when to use the proper model.
The relationship developed is based on the following concept:
iD
We will solve for the value of vGS
(actually vGS -VT) and find the drain iD = K‘W( vGS-VT)2
2L
current where these two values are
equal [vGS(tran.) -VT)]. IW vGS-VT
i = t exp( ) D L nVt
The large signal expressions for each iD(tran.)
region are: vGS
070507-01 VT vGS(tran.)
Subthreshold-
W vGS-VT  iD   It(W/L)
iD ≈ It L exp nV   vGS-VT = nVt ln I (W/L) ≈ nVt 1 - i
  
 t   t   D 
if (ItW/L)/iD < 0.5.
Strong inversion-
K'W 2iD
iD = 2L vGS-VT2  vGS-VT = K'(W/L)
Boundary Between Subthreshold and Strong Inversion - Continued

Equating the two large signal expressions gives,
 It(W/L) 2iD  It(W/L)2 2iD
nVt 1 - i =  n Vt 1 - i
2 2  =
 D  K'(W/L)  D  K'(W/L)
Expanding gives,
It2(W/L)2 2 It(W/L)  2iD
2 2
n Vt  -  2 2
+ 1 ≈ n Vt = K'(W/L) if (ItW/L)/iD < 0.5
2 i
 iD D 
Therefore we get,
K'W 2 2
iD(tran.) = n Vt
2L
For example, if K’ = 120µA/V2, W/L = 100, and n = 2, then at room temperature the
value of drain current at the transition between subthreshold and strong inversion is
120µA/V2100 2 = 16.22µA
iD(tran.) = 4·(0.026)
2
One will find for UDSM technology, that weak inversion or subthreshold operation can
occur at large currents for large values of W/L.

Extraction of Weak Inversion Model Parameters

Model:
W
 
vGS- VT  iD 
iD = It  L  exp nV (1+ vDS) and vGS = VT - nVt lnI (W/L)
   t  t 
Extraction circuit and results for low threshold NMOS:
ID
+ VDS
VBS VGS
-
111130-03
1.) Extraction of It (W/L=2.5).

W  L
Set VGS = VT to get ID = I L  which gives It = ID W = 204nA (0.4) = 81.6 nA

t
  
2.) Extraction of n:
Take the log of the current relationship to get,
 W
 
vGS- VT d(ln iD) 1 1  VGS2 - VGS1 
ln (iD) = ln It L  + nV → dv = nV → n = V ln(I ) - ln(I )
  t GS t t D2 D1 
1  0.14151-0.088567 
n = 0.0259 ln(223.38nA) - ln(52.966nA) = 1.418
 
LOW POWER OP AMPS

Two-Stage, Miller Op Amp Operating in Weak Inversion
VDD
M6
M3 M4 Cc
vout
- M1 M2 CL
vin
+
+ M7
VBias M5
-
VSS Fig.7.4-1
Low frequency response:
 ro2ro4   ro6ro7  1 1
Avo = gm2gm6   = (No longer  )
 o2
r + ro4  o6
r + ro7 n n
2 6 (kT/q) 2 (  2 +  4 )( 6 +  7 ) I D
GB and SR:
ID1 ID5 ID1  kT

GB = and SR = =2 = 2GB n1  = 2GBn1Vt
(n1kT/q)C C C  q

Example 29-1 Gain and GB Calculations for Subthreshold Op Amp.

Calculate the gain, GB, and SR of the op amp shown above. The currents are ID5 =
200 nA and ID7 = 500 nA. The device lengths are 1 m. Values for n are 1.5 and 2.5 for
p-channel and n-channel transistors respectively. The compensation capacitor is 5 pF.
The channel length modulation parameters are N = 0.06V-1 and P = 0.08V-1. Assume
that the temperature is 27 C. If VDD = 1.5V and VSS = -1.5V, what is the power
dissipation of this op amp?
Solution
The low-frequency small-signal gain is,
1
Av = = 20,126 V/V
(1.5)(2.5)(0.026)2(0.06 + 0.08)(0.06 + 0.08)
The gain bandwidth is
100x10-9
GB = = 307,690 rps  49.0 kHz
2.5(0.026)(5x10-12)
The slew rate is
SR = (2)(307690)(2.5)(0.026) = 0.04 V/s
The power dissipation is,
Pdiss = 3(0.7µA) =2.1µW

Push-Pull Output Op Amp in Weak Inversion

First stage gain is, VDD
gm2 ID2n4Vt ID2n4
Avo = g = I n V = I n  1
m4 D4 2 t D4 2 M3 M4
M8 M6
Total gain is, vi2
M1 M2
gm1(S6/S4) (S6/S4) vout
Avo = =
(gds6 + gds7) (6 + 7)n1Vt Cc
At room temperature (Vt = 0.0259V) and + M5
VBias
for typical device lengths, gains of 60dB M9 M7
can be obtained. -
The GB is, VSS Fig. 7.4-2
gm1 S6 gm1b

GB =  =
C S4 C
where b is the current ratio between M4:M6 and M3:M8.

Increasing the Gain of the Previous Op Amp

1.) Can reduce the currents in M3 and M4 and introduce gain in the current mirrors.
2.) Use a cascode output stage (can’t use self-biased cascode, currents are too low).
VDD
+
M8 M3 M4 M6
VT+2VON
-
M13 M10
M14
vi2 vi1
M1 M2 vout
Cc
M5 I5
M12 M15 + M11
gm1+gm2 +
Av =  R VBias
VT+2VON
 2  out M9 M7
I5 - -
VSS Fig. 7.4-3A
2nnVt  I5   1 
 
I72n2 I72p2 2I7 nnVt2(nnn2+npp2)
= =
+
I7 I7
nnVt npVt
Can easily achieve gains greater than 80dB with power dissipation of less than 1µW.

Increasing the Output Current for Weak Inversion Operation

A significant disadvantage of the weak inversion is that very small currents are available
to drive output capacitance so the slew rate becomes very small.
Dynamically biased differential amplifier input stage:
Note that the sinking current for M1 and M2 is

Isink = I5 + A(i2-i1) + A(i1-i2) where (i2-i1) and (i1-i2) are only positive or zero.
If vi1>vi2, then i2>i1 and the sinking current is increased by A(i2-i1).
If vi2>vi1, then i1>i2 and the sinking current is increased by A(i1-i2).
Dynamically Biased Differential Amplifier - Continued

How much output current is available from this circuit if there is no current gain from the
input to output stage?
Assume transistors M18 through M21 are equal to M3 and M4 and that transistors M22
through M27 are all equal.
W28 W26 W29 W27
Let    
L28 = A  L26  and L29 = A  L27 
The output current available can be found by assuming that vin = vi1-vi2 > 0.
 i1 + i2 = I5 + A(i2-i1)
The ratio of i2 to i1 can be expressed as
i2  vin 
 
i1 = expnVt
If the output current is iOUT = b(i2-i1) then combining the above two equations gives,
  vin  
bI5expnV  - 1
  t  vin
iOUT =  iOUT =  when A = 2.16 and nV = 1
 vin  t
(1+A) - (A-1)exp 
nVt
where b corresponds to any current gain through current mirrors (M6-M4 and M8-M3).
Overdrive of the Dynamically Biased Differential Amplifier

The enhanced output current is 2
accomplished by the use of positive
feedback (M28-M2-M19-M28).
A=2
The loop gain is,
gm28gm19 gm19
LG =  g g =A
 m4  m26 gm4 = A A = 1.5
Note that as the output current increases, IOUT 1 A=1

the transistors leave the weak inversion I5
A = 0.3
region and the above analysis is no
longer valid. A=0
0
0 1 2
vIN nVt Fig. 7.4-5

Increasing the Output Current for Strong Inversion Operation

An interesting technique is to bias the output transistor of a current mirror in the active
region and then during large overdrive cause the output transistor to become saturated
causing a significant current gain.
Illustration:
530µA VGS
i1 i2
Current
i2 for W2/L2 = 5.3(W1/L1)
M1 M2 +
i2 for W2/L2 = W1/L1
+ Vds2
VGS 100µA VGS
- -
Volts
0.1Vds2(sat) Vds1(sat)=Vds2(sat)
070507-02

Example 29-2 Current Mirror with M2 operating in the Active Region

Assume that M2 has a voltage across the drain-source of 0.1Vds(sat). Design the
W2/L2 ratio so that I1 = I2 = 100µA if W1/L1 = 10. Find the value of I2 if M2 is
saturated.
Solution
Using the value of KN’ = 120µA/V2, we find that the saturation voltage of M2 is
2I1 200
Vds1(sat) = KN’ (W2/L2) = 120·10 = 0.408V
Now using the active equation of M2, we set I2 = 100µA and solve for W2/L2.
100µA = KN’(W2/L2)[Vds1(sat)·Vds2 - 0.5Vds22]
= 120µA/V2 (W2/L2)[0.408·0.0408 - 0.5·0.04082]V2 = 1.898x106(W2/L2)
Thus,
W2
100 =1.898(W2/L2) → L = 52.7 ≈ 53
2
Now if M2 should become saturated, the value of the output current of the mirror with
100µA input would be 530µA or a boosting of 5.3 times I1.
Implementation of the Current Mirror Boosting Concept

VDD
M8
M17 M10
M7
M9 M18
M21 i1 i2 M22 M14
M13 vi1 vi2
M1 M2
M29 M30
ki1 ki2
vo1 M28 vo2
i1 i2 M27 M3 M4 i1 i2
ki2 ki1
M25 M26
+ i2 i1
M15 M23 VBias M5 M24 M16
M11 M20
M19 M12
- M6
VSS Fig.7.4-7
k = overdrive factor of the current mirror

A Better Way to Achieve the Current Mirror Boosting

It was found that when the current mirror boosting idea illustrated on the previous slide
was used that when the current increased through the cascode device (M16) that VGS16
increased limiting the increase of VDS12. This can be overcome by the following circuit.
VDD
iin+IB iin IB
kiin
M3
50/1
M5 M4
1/1 1/1
M1 M2
1/1 210/1
Fig. 7.4-7A

REVIEW OF MOSFET NOISE MODELING AND ANALYSIS

Transistor Noise Sources (Low-Frequency)
Drain current model:
D D
M1 M1
2
G G in1
M1 is M1 is
noisy S noiseless S Fig. 7.5-0A
2 8kTgm (KF)ID 2 8kTgm(1+) (KF)ID

in =  3 + 2  or in =  + 2  if vBS  0
 fC L
ox   3 fC L
ox 
gmbs
Recall that  = g
m
Gate voltage model assuming common source operation:
2 D D
2 i N  8kT KF  M1
2
en1
M1
en = 2 =  +  or
gm 3gm 2fCoxWLK’ G G *
2  8kT KF  M1 is M1 is
en =  + 2fC WLK’ if vBS  0 noiseless S
3g m (1+) ox 
noisy S
Fig. 7.5-0C

Minimization of Noise in Op Amps

1.) Maximize the signal gain as close to the input as possible. (As a consequence, only
the input stage will contribute to the noise of the op amp.)
2.) To minimize the 1/f noise:
a.) Use PMOS input transistors with appropriately selected dc currents and W and L
values.
b.) Use lateral BJTs to eliminate the 1/f noise.
c.) Use chopper stabilization to reduce the low-frequency noise.
Noise Analysis
1.) Insert a noise generator for each transistor that contributes to the noise. (Generally
ignore the current source transistor of source-coupled pairs.)
2.) Find the output noise voltage across an open-circuit or output noise current into a
short circuit.
3.) Reflect the total output noise back to the input resulting in the equivalent input noise
voltage.

LOW NOISE OP AMPS

A Low-Noise, Two-Stage, Miller Op Amp
VDD VDD
2
VSG7 en7
M10 M7 I5
M5 2
en1 2
en2 * M7
+ * M1 M2 *
vin eto2
2 2
-
M1 M2 Cc en8 M8 M9 en9
vout
M11 * *
VBias 2 VBias
+ en6
VBias M8 M9 2 2
- M6 en3 en4 M6
*
M3 M4 M3 * * M4
VSS VSS Fig. 7.5-1
2
The total output-noise voltage spectral density, eto, is as follows where gm8(eff)  1/rds1,
2  2 2  2 2 2 2 2 2 
eto = gm62RII2en6+en7 +RI2gm12en1+gm22en2+gm32en3+gm42en4 + (en8/rds12) + (en9/rds22)
2
Divide by (gm1RIgm6RII)2 to get the eq. input-noise voltage spectral density, eeq, as
2  gm32en3
2 eto
2
2en6
2 2 2
en8  2  gm32en32 
eeq = (g g R R )2 = g 2R 2 + 2en11+g   2  + 2 2en11+gm1  2 
 m1 e
m1 m6 I II m1 I g   n1 m12rds1 en1
2  en1
2 = e 2 , e 2 = e 2 , e 2 = e 2 and e 2 = e 2 and g R is large.
where en6 n7 n3 n4 n1 n2 n8 n9 m1 I
1/f Noise of a Two-Stage, Miller Op Amp

Consider the 1/f noise:
Therefore the noise generators are replaced by,
2 B 2 2BK’Ii
eni = fW L (V2/Hz) and ini = fL 2 (A2/Hz)
i i i
Therefore, the approximate equivalent input-noise voltage spectral density is,
2 2  KN’BNL12
eeq = 2en1 1 +  K ’B L   (V2/Hz)
  P P  3 
Comments;
2
• Because we have selected PMOS input transistors, en1 has been minimized if we
choose W1L1 (W2L2) large.
• Make L1<<L3 to remove the influence of the second term in the brackets.

Thermal Noise of a Two-Stage, Miller Op Amp

Let us focus next on the thermal noise:
The noise generators are replaced by,
2 8kT 2 8kTgm
eni ≈ 3g 2
(V /Hz) and ini ≈ 3 (A2/Hz)
m
where the influence of the bulk has been ignored.
The approximate equivalent input-noise voltage spectral density is,
2 2  gm32 n3
 e
2
2  KNW3L1 
eeq = 2en11+g   2  = 2en1 1 +  (V2/Hz)
 KPW1L3 
  m1 en1
Comments:
• The choices that reduce the 1/f noise also reduce the thermal noise.
Noise Corner:
Equating the equivalent input-noise voltage spectral density for the 1/f noise and the
thermal noise gives the noise corner, fc, as
3gmB
fc = 8kTWL

Example 29-3 Design of A Two-Stage, Miller Op Amp for Low 1/f Noise
Use the model parameters of KN’ = 120µA/V2, KP’ = 25µA/V2, and Cox = 6fF/µm2
along with the value of KF = 4x10-28 F·A for NMOS and 0.5x10-28 F·A for PMOS and
design the previous op amp with ID5 = 100µA to minimize the 1/f noise. Calculate the
corresponding thermal noise and solve for the noise corner frequency. From this
information, estimate the rms noise in a frequency range of 1Hz to 100kHz. What is the
dynamic range of this op amp if the maximum signal is a 1V peak-to-peak sinusoid?
Solution
1.) The 1/f noise constants, BN and BP are calculated as follows.
KF 4x10-28F·A
BN = = = 1.33x10-22 (V·m)2
2CoxKN’ 2·60x10 F/m ·120x10 A/V
-4 2 -6 2
and
KF 0.5x10-28F·A
BP = 2C K ’ = -4 2 -6 2 = 1.67x10-22 (V·m)2
ox P 2·60x10 F/m ·25x10 A/V
2.) Now select the geometry of the various transistors that influence the noise
performance.
2 small, let W = 100µm and L = 1µm. Select W = 10µm and L =
To keep en1 1 1 3 3
20µm and letW8 and L8 be the same as W1 and L1 since they little influence on the
noise.

Of course, M1 is matched with M2, M3 with M4, and M8 with M9.
2 BP 1.67x10-22 1.67x10-12
 en1 = fW L = f·100µm·1µm = (V 2/Hz)
1 1 f
2 1.67x10-12  120·1.33  1  
 2 2 3.33x10-12 3.452x10-12 2
eeq = 2x 1 +      = 1.0365 = (V /Hz)
f   25·1.67  20  f f
Note at 100Hz, the voltage noise in a 1Hz band is  3.45x10-14V2(rms) or
0.186µV(rms).
3.) The thermal noise at room temperature is
2 8kT 8·1.38x10-23·300
en1 = 3g = -6 = 2.208x10-17 (V2/Hz)
m 3·500x10
which gives
2  120·10·1 
eeq = 2·2.208x10-171 +  = 4.416x10-17·1.155= 5.093x10-17 (V2/Hz)
 25·100·20 


2
4.) The noise corner frequency is found by equating the two expressions for eeq to get
3.452x10-12
fc = = 67.8kHz
5.093x10-17
This noise corner is indicative of the fact that the thermal noise is much less than the 1/f
noise.
5.) To estimate the rms noise in the bandwidth from 1Hz to 100,000Hz, we will ignore
the thermal noise and consider only the 1/f noise. Performing the integration gives
105
3.452x10-12
Veq(rms) = 
2 df = 3.452x10 -12[ln(100,000) - ln(1)]
 f
1
= 0.408x10-10 Vrms2 = 6.39 µVrms
The maximum signal in rms is 0.353V. Dividing this by 6.39µV gives 55,279 or
94.85dB which is equivalent to more than 15 bits of resolution.
6.) Note that the design of the remainder of the op amp will have little influence on the
noise and is not included in this example.

Low-Noise Op Amp using Lateral BJT’s at the Input
10
Experimental noise
performance: 8
Eq. input noise voltage of low-noise op amp
Noise (nV/ Hz)
4
Voltage noise of lateral BJT at 170 mA
2
0
10 100 1000 104 105
Frequency (Hz) Fig. 7.5-7
Summary of Experimental Performance for the Low-Noise Op Amp

Experimental Performance Value
Circuit area (1.2µm) 0.211 mm2
Supply Voltages ±2.5 V
Quiescent Current 2.1 mA
-3dB frequency (at a gain of 20.8 dB) 11.1 MHz
en at 1Hz 23.8 nV/ Hz
en (midband) 3.2 nV/ Hz
fc(en) 55 Hz
in at 1Hz 5.2 pA/ Hz
in (midband) 0.73 pA/ Hz
fc(in) 50 Hz
Input bias current 1.68 µA
Input offset current 14.0 nA
Input offset voltage 1.0 mV
CMRR(DC) 99.6 dB
PSRR+(DC) 67.6 dB
PSRR-(DC) 73.9 dB
Positive slew rate (60 pF, 10 k load) 39.0 V/µS
Negative slew rate (60 pF, 10 k load) 42.5 V/µS
Chopper-Stabilized Op Amps - Doubly Correlated Sampling (DCS)

Illustration of the use of chopper stabilization to remove the undesired signal, vu, form
the desired signal, vin.
Vu(f) Clock
+1
Vin(f) t
-1
f
vu T =1
fc
f vA vB vC vout
vin A1 A2
VA(f)
f
0 fc 2fc 3fc
VB(f)
f
0 fc 2fc 3fc
VC(f)
f
0 fc 2fc 3fc Fig. 7.5-8

Chopper-Stabilized Amplifier

Example of a Two-Stage, Chopper-Stablized Op Amp

VDD
clkb clkb
M3 M4 M6
vnn clk clkb vnp
vnp Cc vout vnn
clk clkb clk clk
clk clk
vnn M1 M2 vnp
VDD VDD
vnp vnn
VNB1 M5
M7
clkb clkb
070507-03

Experimental Noise Response of the Chopper-Stabilized Amplifier

1000
Without chopper
With chopper
fc = 16kHz
nV/ Hz
100
With chopper fc = 128kHz
10
0 10 20 30 40 50
Frequency (kHz) Fig. 7.5-11
Comments:
• The switches in the chopper-stabilized op amp introduce a thermal noise equal to kT/C
where k is Boltzmann’s constant, T is absolute temperature and C are capacitors
charged by the switches (parasitics in the case of the chopper-stabilized amplifier).
• Requires two-phase, non-overlapping clocks.
• Trade-off between the lowering of 1/f noise and the introduction of the kT/C noise.
Improved Chopper Operation

In some cases, there are spurious signals in the neighborhood of the chopping
frequencies and its harmonics. These spurious signals such as common-mode
interference can mix to the baseband since the chopper amplifier is a time variant system
and therefore inherently nonlinear.
fc
A bandpass filter centered at the
Input Output
clock frequency can be used to Amplifier Amplifier
eliminate the aliasing of the spurious vin vout
signals and achieve a reduction in
Input fo Output
effective offset.
Modulator Bandpass Filter Modulator
fc - fo 041006-03
Let  = f and  be a given bound
o
of . It can be shown† that the achievable effective offset reduction, EOR, and the
optimum Q for the bandpass filter, Qopt, is
8Q
EOR = ,  <<1 and Qopt = 1/ 8
(1 + 8Q2)
Improvements of 14dB reduction in effective offset are possible for  = 0.8%.
† C. Menolfi and Q. Huang, “A Fully Integrated, Untrimmed CMOS Instrumentation Amplifier with Submicrovolt Offset,” IEEE J. of Solid-State
Circuits, vol. 34, no.8, March 1999, pp. 415-420.
SUMMARY
• Operation of transistors for low power op amps is generally in weak inversion
• Boosting techniques are needed to get output sourcing and sinking currents that are
larger than that available during quiescent operation
• Be careful about using circuits at weak inversion, i.e. the self-biased cascode will
cause the resistor to be too large
• Primary sources of noise for CMOS circuits is thermal and 1/f
• Noise analysis:
1.) Insert a noise generator for each transistor that contributes to the noise.
(Generally ignore the current source transistor of source-coupled pairs.)
2.) Find the output noise voltage across an open-circuit or output noise current into a
short circuit.
3.) Reflect the total output noise back to the input resulting in the equivalent input
noise voltage.
• Noise is reduced in op amps by making the input stage gain as large as possible and
reducing the noise of this stage as much as possible.
• The input stage noise can be reduced by using lateral BJTs (particularily the 1/f noise)
• Doubly correlated sampling can transfer the noise at low frequencies to the clock
frequency (this technique is used to achieve low input offset voltage op amps).
Lecture 30 – Low Voltage Op Amps (6/25/14) Page 30-1
LECTURE 30 – LOW VOLTAGE OP AMPS

Outline
• Introduction
• Low voltage input stages
• Low voltage gain stages
• Low voltage bias circuits
• Low voltage op amps
• Summary
Pages 419-436

INTRODUCTION
Implications of Low-Voltage, Strong-Inversion Operation
• Reduced power supply means decreased dynamic range
• Nonlinearity will increase because the transistor is working close to VDS(sat)
• Large values of  because the transistor is working close to VDS(sat)
• Increased drain-bulk and source-bulk capacitances because they are less reverse biased.
• Large values of currents and W/L ratios to get high transconductance
• Small values of currents and large values of W/L will give small VDS(sat)
• Severely reduced input common mode range
• Switches will require charge pumps

What are the Limits of Power Supply?

The limit comes when there is no signal range left when the dc drops are subtracted from
VDD. VDD
Minimum power supply (no signal swing range): + +
VPB1 M2 M3
VON
VT+VON
- -
VDD(min.) = VT + 2VON + V +
NB1
VON VT+VON
M1 - M4 -
For differential amplifiers, the minimum power 060802-01
supply is:
VDD
VDD(min.) = 3VON M3 M4 +
However, to have any input common mode range, the VPB1 VON
-
effective minimum power supply is, M1 + M2
VDD(min.) = VT + 2VON VON
+ +
VT+VON - VT+VON
- -
M5 +
VNB1 VON
-
060802-02

Minimum Power Supply Limit – Continued

The previous consideration of the differential amplifier did not consider getting the
signal out of the amplifier. This will add another VON.
VDD
M3 M4 +
VPB1 VON VPB1 M9
-
M1 +M2 V M6 +
PB2
VON VON
+ + -
VT+VON - VT+VON
- -
M5 + + VT
VNB1 VON VT+VON
- - M7
M8
060802-03
Therefore,
VDD(min.) = VT + 3VON
This could be reduced to 3VON with the floating battery but its implementation probably
requires more than 3VON of power supply.
Note the output signal swing is VT + VON while the input common range is VON.

LOW VOLTAGE INPUT STAGES

Input Common Mode Voltage Range
Minimum power supply (ICMR = 0): VDD
+
VBias
VDD(min) = VSD3(sat)-VT1+VGS1+VDS5(sat) V (sat) -
SD3
= VSD3(sat)+VDS1(sat)+VDS5(sat) M3 M4
-VT1
Input common-mode range: vicm M1 M2
Vicm(upper) = VDD - VSD3(sat) + VT1 VGS1
Vicm(lower) = VDS5(sat) + VGS1
VDS5(sat) +
VBias M5
-
Fig. 7.6-3
If the threshold magnitudes are 0.7V, VDD =
1.5V and the saturation voltages are 0.3V, then
Vicm(upper) = 1.5 - 0.3 + 0.7 = 1.9V
and
Vicm(lower) = 0.3 + 1.0 = 1.3V
giving an ICMR of 0.6V.
Increasing ICMR using Parallel Input Stages VDD
Turn-on voltage for the n-channel input: M6 MN3 MP5

MN4
Vonn = VDSN5(sat) + VGSN1

Turn-on voltage for the p-channel input: IBias
Vicm
MP1 MP2
Vicm
Vonp = VDD - VSDP5(sat) - VSGP1 MN1 MN2
The sum of Vonn and Vonp equals the minimum

M7 MP4
power supply. MP3 MN5
Regions of operation: Fig. 7.6-4
VDD > Vicm > Vonp: (n-channel on and p-channel off) gm(eq) = gmN
Vonp  Vicm  Vonn: (n-channel on and p-channel on) gm(eq) = gmN + gmP
Vonn > Vicm > 0 : (n-channel off and p-channel on) gm(eq) = gmP
where gm(eq) is the equivalent input transconductance of the above input stage, gmN is
the input transconductance for the n-channel input and gmP is the input trans-
conductance for the p-channel input.
gm(eff)
gmN+gmP
gmP gmN
n-channel off Vonn n-channel on Vonp n-channel on
p-channel on p-channel on p-channel off
Vicm
0 VSDP5(sat)+VGSN1 VDD-VSDP5(sat)+VGSN1 VDD Fig. 7.6-5
Removing the Nonlinearity in Transconductances as a Function of ICMR

Increase the bias current in the differential VDD
3:1
amplifier that is on when the other differential Ib
amplifier is off.
Three regions of operation depending on the Inn Ip
VB2 Vicm MP1 MP2 Vicm VB1
value of Vicm:
MB2 MB1
1.) Vicm < Vonn: n-channel diff. amp. off MN1 MN2
and p-channel on with Ip = 4Ib: In Ipp

KP’WP
gm(eff) = LP 2 Ib Ib
1:3
Fig. 7.6-6
2.) Vonn < Vicm < Vonp: both on with
In = Ip = Ib
KN’WN KP’WP
gm(eff) = Ib + Ib
LN LP
3.) Vicm > Vonp: p-channel diff. amp. off and n-channel on with In = 4Ib:
KN’WN
gm(eff) = LN 2 Ib
How Does the Current Compensation Work?

Set VB1 = Vonn and VB2 = Vonp.
VDD
If vicm <Vonp then Ip = Ib and Inn=0
Ib
vicm vicm If vicm >Vonp then Ip = 0 and Inn=Ib
MB1
Inn Ip
MN1 MN2
Vonn
In Ipp vicm MP1 MP2 v
icm
MB2
If vicm >Vonn then In = Ib and Ipp=0
Ib Vonp
If vicm <Vonn then In = 0 and Ipp=Ib
Fig. 7.6-6A
Result: gm(eff)
gmN=gmP
0 Vicm
0 Vonn Vonp VDD Fig. 7.6-7
The above techniques and many similar ones are good for power supply values down to
about 1.5V. Below that, different techniques must be used or the technology must be
modified (natural devices).
Natural Transistors
Natural or native NMOS transistors normally have a threshold voltage around 0.1V
before the threshold is increased by increasing the p concentration in the channel.
If these transistors are characterized, then they provide a means of achieving low voltage
operation.
Minimum power supply (ICMR = 0):
VDD(min) = 3VON
Input common mode range:
Vicm(upper) = VDD – VON + VT(natural)
Vicm(lower) = 2VON + VT(natural)
If VT(natural) ≈ VON = 0.1V, then
Vicm(upper) = VDD
Vicm(lower) = 3VON = 0.3V
Therefore,
ICMR = VDD - 3VON = VDD – 0.3V  VDD(min) ≈ 1V
Matching tends to be better (less doping and magnitude is smaller).
Bulk-Driven MOSFET
A depletion device would permit large ICMR even with very small power supply
voltages because VGS is zero or negative.
When a MOSFET is driven from the bulk with the gate held constant, it acts like a
depletion transistor.
Cross-section of an n-channel vBS VDS VGS VDD
bulk-driven MOSFET: Bulk Drain Gate Source Substrate
Channel
p+ n+ n+ n+
QP
Depletion p-well
Region QV
n substrate
Large signal equation: Fig. 7.6-8
KN’W
iD = 2L VGS - VT0 -  2|F| - vBS +  2|F|2
Small-signal transconductance:
 (2KN’W/L)ID
gmbs =
2 2|F| - VBS
Bulk-Driven MOSFET - Continued

Transconductance characteristics: 2000
Bulk-source driven
Drain Current (mA)

1500
1000
Saturation: VDS > VBS – VP gives,
VBS = VP + VON 500
IDSS
Gate-source
 VBS2
iD = IDSS 1 - V  driven
 P 0
-3 -2 -1 0 1 2 3
Comments: Gate-Source or Bulk-Source Voltage (Volts)
Fig. 7.6-9
• gm (bulk) > gm(gate) if VBS > 0 (forward biased )

• Noise of both configurations are the same (any differences comes from the gate versus
bulk noise)
• Bulk-driven MOSFET tends to be more linear at lower currents than the gate-driven
MOSFET
• Very useful for generation of IDSS floating current sources.

Bulk-Driven, n-channel Differential Amplifier

What is the ICMR?
Vicm(min) = VSS + VDS5(sat) + VBS1 = VSS + VDS5(sat) - |VP1| + VDS1(sat)
Note that Vicm can be less than VSS if |VP1| > VDS5(sat) + VDS1(sat)
Vicm(max) = ?
VDD
As Vicm increases, the current through M3 M4
M1 and M2 is constant so the source M7
increases. However, the gate voltage stays
constant so that VGS1 decreases. Since the vi1 vi2
current must remain constant through M1 IBias + + +
V
VBS1 M1 GS V
and M2 because of M5, the bulk-source - - M2 -BS2
voltage becomes less negative causing VTN1
M6 M5
to decrease and maintain the currents
through M1 and M2 constant. If Vicm is
VSS Fig. 7.6-10
increased sufficiently, the bulk-source
voltage will become positive. However, current does not start to flow until VBS is
greater than 0.3 volts so the effective Vicm(max) is
Vicm(max)  VDD - VSD3(sat) - VDS1(sat) + VBS1.
Illustration of the ICMR of the Bulk-Driven, Differential Amplifier

250nA
200nA
Bulk-Source Current
150nA
100nA
50nA
-50nA
-0.50V -0.25V 0.00V 0.25V 0.50V
Input Common-Mode Voltage Fig. 7.6-10A
Comments:
• Effective ICMR is from VSS to VDD -0.3V
• The transconductance of the input stage can vary as much as 100% over the ICMR
which makes it very difficult to compensate
Reduction of VT through Forward Biasing the Bulk-Source

The bulk can be used to reduce the threshold sufficiently to permit low voltage
applications. The key is to control the amount of forward bias of the bulk-source.
Current-Driven Bulk Technique†:
S S Gate
IE p+ p+
B B
G G
n+
D ICD ICS
D Source Drain
IBB IBB
n-well
p- substrate
Reduced Threshold MOSFET Parasitic BJT Layout Fig. 7.6-19
Problem:
Want to limit the BJT current to some value called, Imax.
Therefore,
Imax
IBB =
CS + CD + 1
†T. Lehmann and M. Cassia, “1V Power Supply CMOS Cascode Amplifier,” IEEE J. of Solid-State Circuits, Vol. 36, No. 7, 2001.
VDD
Current-Driven Bulk Technique
Bias circuit for keeping Imax defined VBias1
M7
independent of BJT betas. M3
IS,E =1.3ID
Note:
ID,C = ICD + ID M6 ID IE IR
IS,E = ID + IE + IR R
IBB M1 M2
The circuit feedback causes a bulk bias ID,C =1.1ID ICD M5
M4
current IBB and hence a bias voltage VBIAS M8 +
such that VBias
IR =
IS,E = ID + IBB(1+CS + CD) + IR VBias2
0.1ID
-
Use VBias1 and VBias2 to set ID,C  1.1ID, VSS
130418-01
IS,E  1.3ID and IR  0.1ID which sets IBB at 0.1ID assuming we can neglect ICS with
respect to ICD. This is illustrated as follows,
IS,E ≈ ID + IBB(1+CD) + IR = ID + IBB + ICD + IR = ID + IBB + 0.1ID + 0.1ID = 1.3ID
For this circuit to work, the following conditions must be satisfied:
VBE < VTN + IRR and |VTP| + VDS(sat) < VTN + IRR
If |VTP| > VTN, then the level shifter IRR can be eliminated.
LOW VOLTAGE GAIN STAGES

Cascade Stages
Simple cascade of inverters:
VDD
VPB1 M2 M3
VPB1 M5 M7
-gm1 -gm2 -gm3 -gm4

VNB1 VNB1
R1 R2 R3 R4
M1 M4 M6 M8
060803-01
The problem with this approach is the number of poles that occur (one per stage) if the
amplifier is to be used in a closed loop application. Instability or poor transient response
will result.

Nested Miller Compensation

Cm3
Principle: Use Miller compensation
to split the poles within a feedback Cm2 Cm1
loop.
p1 p2 p3 p4 vout
Compensating Results: vin -g m1 -gm2 -gm3 -gm4
1) Cm1 pushes p4 to higher R1 R2 R3 RL CL
frequencies and p3 down to lower
060812-01
frequencies
2) Cm2 pushes p2 to higher frequencies and p1 down to lower frequencies
3) Cm3 pushes p3 to higher frequencies (feedback path) & pulls p1 further to lower
frequencies
Equations:
GB  gm1/C m3 p2  gm2/Cm3 p3  gm3Cm3/(Cm1Cm2) p4  gm4/CL
The objective is to get all poles larger than GB:
GB < p2, p3, p4

Illustration of the Nested Miller Compensation Technique
This approach is complicated by the feedforward paths which create RHP zeros.

Elimination of the RHP Zeros

The following are least three ways in which the RHP zeros can be eliminated.
1.) Nulling resistor. 2.) Feedback only – buffer. 3.) Feedback only – gain.
VDD VDD VDD VDD VDD
VPB1 VPB1 VPB1 M3

M2 M2 M2
Cc1
Cc1 VPB2
Cc1
M3 M4
Rz1
M1 M1 VNB1 M1
VPN1 M5
060803-02
060803-04
060803-03
1 Increases the minimum power Increases the pole and

z1 =
Cc1(1/gm1 − Rz1) supply by VON. increases the minimum
power supply by VON.

Use of LHP Zeros to Compensate Cascaded Amplifiers

Principle: Feedforward around a noninverting stage creates a LHP zero or inverting
feedforward around an inverting stage also creates a LHP zero.
Example of Multipath, Nested Miller Compensation†:
CM2 VDD
CM1 VPB1M5 M6 M11 M14
Vin Vout Vout

+gm1 +gm2 -gm3 CM1
CM2
R1 R3 C3 M13 C3
Vin
M9 M10
M1 M3 VRef2
+gm4 M4 M2
VRef1
VNB1
R2,4 M12
060803-05 M7 M8
Unfortunately, the analysis becomes quite complex - for the details refer to the reference
below.
† R. Hogervorst and J. H. Huijsing, Design of Low-Voltage, Low-Power Operational Amplifier Cells, Kluwer Academic Publishers, 1996, pp. 127-
131.
LOW VOLTAGE BIAS CIRCUITS

A Low-Voltage Current Mirror with Wide Input and Output Swings
The current mirror below requires a power supply of VT+3VON and has a Vin(min) =
VON and a Vout(min) = 2VON (less for the regulated cascode output mirror).
VDD VDD
I1-IB IB IB I2 I1 IB1 IB2 IB1 I2

iin iout iin iout
M7
M3 M4 M7 M3 M4
or
M6 M6 M5
M1 M2 M1
M5 IB2 M2
Fig. 7.6-13A

Low-Voltage Current Mirrors using the Bulk-Driven MOSFET

The biggest problem with current mirrors is the large minimum input voltage required
for previously examined current mirrors.
If the bulk-driven MOSFET is biased with a current that exceeds IDSS then it is
enhancement and can be used as a current
mirror.
VDD VDD
iin iin iout
M4
iout M3
+ + +
VGS3 VBS3 VGS4
- -M2
M1 M2 - M1
+ + + + + +
VGS V BS VGS VGS1 VBS1 VGS2
- - - - - -
Simple bulk-driven Cascodebulk-driven
current mirror current mirror. Fig.7.6-11
The cascode current mirror gives a minimum input voltage of less than 0.5V for currents
less than 100µA
Bandgap Topologies Compatible with Low Voltage Power Supply

VDD VDD VDD VDD
VDD VDD VDD
IPTAT IVBE
IVBE INL IPTAT
VRef VRef
VRef R2
VPTAT IPTAT
INL R3
VBE
R1
Voltage-mode bandgap topology. Current-mode bandgap topology. Voltage-current mode bandgap topology.
Fig. 7.6-14

Technique for Canceling the Bandgap Curvature

VDD
1:K2 1:K3
M2 active M2 sat.
M1 M2 M3 M4 M3 off M3 on
Current
K2IVBE K1IPTAT
I2 INL K3INL
INL
IVBE K1IPTAT
Temperature
Circuit to generate nonlinear correction term, INL. Illustration of the various currents.
Fig. 7.6-16
 0 , K2IVBE > K1IPTAT
INL = 
 K1IPTAT - K2IVBE , K2IVBE < K1IPTAT
The combination of the above concept with the previous slide yielded a curvature-
corrected bandgap reference of 0.596V with a TC of 20ppm/C° from -15C° to 90C°
using a 1.1V power supply.† In addition, the line regulation was 408 ppm/V for
1.2VDD10V and 2000 ppm/V for 1.1VDD10V. The quiescent current was 14µA.
† G.A. Rincon-Mora and P.E. Allen, “A 1.1-V Current-Mode and Piecewise-Linear Curvature-Corrected Bandgap Reference,” J. of Solid-State
Circuits, vol. 33, no. 10, October 1998, pp. 1551-1554.
LOW VOLTAGE OP AMPS

A Low Voltage Op Amp using Normal Technology
VDD(min) = 3VON + VT (ICMR = VON):
VDD
VPB1 M3 M4
M11
VPB2 vOUT
Cc
+ M1 M2
vIN M6 M7
-
VNB1
M5 M8 M9 M10
060804-01
Performance:
Gain ≈ gm2rds2
Miller compensated
Output swing is VDD -2VON
Max. CM input = VDD
Min. CM input = 2VON + VT
A Low-Voltage, Wide ICMR Op Amp

VDD(min) = 4VON + 2VT (ICMR = VDD):
Performance:
Gain ≈ gm2rds2, self compensated, and output swing is VDD -4VON

An Alternate Low-Voltage, Wide ICMR Op Amp

VDD(min) = 4VON + 2VT (ICMR = VDD):
VDD
VPB1 3:1
VPB2 VPB2
+ - vOUT
VNB2 VNB2
VNB1
1:3
060804-02

A 1-Volt, Two-Stage Op Amp

Uses a bulk-driven differential input amplifier.

Performance of the 1-Volt, Two-Stage Op Amp

Specification (VDD=0.5V, VSS=-0.5V) Measured Performance (CL = 22pF)
DC open-loop gain 49dB (Vicm mid range)
Power supply current 300µA
Unity-gainbandwidth (GB) 1.3MHz (Vicm mid range)
Phase margin 57° (Vicm mid range)
Input offset voltage ±3mV
Input common mode voltage range -0.475V to 0.450V
Output swing -0.475V to 0.491V
Positive slew rate +0.7V/µsec
Negative slew rate -1.6V/µsec
THD, closed loop gain of -1V/V -60dB (0.75Vp-p, 1kHz sinewave)
-59dB (0.75Vp-p, 10kHz sinewave)
THD, closed loop gain of +1V/V -59dB (0.75Vp-p, 1kHz sinewave)
-57dB (0.75Vp-p, 10kHz sinewave)
Spectral noise voltage density 367nV/ Hz @ 1kHz
181nV/ Hz @ 10kHz,
81nV/ Hz @ 100kHz
444nV/ Hz @ 1MHz
Positive Power Supply Rejection 61dB at 10kHz, 55dB at 100kHz, 22dB at 1MHz
Negative Power Supply Rejection 45dB at 10kHz, 27dB at 100kHz, 5dB at 1MHz
A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique

VDD
VBiasP M11 M12
M6 M13
Cx M9 M10
M17
+
vin M1 M2 vout
-
CL
M7 M8
VBiasN M3 M5 M4 M14
M15
M16
VSS Fig. 7.6-21
Transistors with forward-biased bulks are in a shaded box.

For large common mode input changes, Cx, is necessary to avoid slewing in the input
stage.
To get more voltage headroom at the output, the transistors of the cascode mirror have
their bulks current driven.
A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique -

Continued
Experimental results:
0.5µm CMOS, 40µA total bias current (Cx = 10pF)
Supply Voltage 1.0V 0.8V 0.7V
Common-mode input 0.0V-0.65V 0.0V-0.4V 0.0V-0.3V
range
High gain output range 0.35V-0.75V 0.25V-0.5V 0.2V-0.4V
Output saturation limits 0.1V-0.9V 0.15V-0.65V 0.1V-0.6V
DC gain 62dB-69dB 46dB-53dB 33dB-36dB
Gain-Bandwidth 2.0MHz 0.8MHz 1.3MHz
Slew-Rate (CL=20pF) 0.5V/µs 0.4V/µs 0.1V/µs
Phase margin 57° 54° 48°
(CL=20pF)
The nominal value of bulk current is 10nA gives a 10% increase in differential pair
quiescent current assuming a BJT  of 100.

SUMMARY
• Integrated circuit power supplies are rapidly decreasing (today 2-3Volts)
• Classical analog circuit design techniques begin to deteriorate at 1.5-2 Volts
• Approaches for lower voltage circuits:
- Use natural NMOS transistors (VT  0.1V)
- Drive the bulk terminal
- Forward bias the bulk
- Use depeletion devices
• The dynamic range will be compressed if the noise is not also reduced
• Fortunately, the threshold reduction continues to allow the techniques of this section to
be used in today’s technology

Lecture 31 – Open-Loop Comparators (6/26/14) Page 31-1
LECTURE 31 – OPEN-LOOP COMPARATORS

Outline
• Characterization of comparators
• Dominant pole, open-loop comparators
• Two-pole, open-loop comparators
• Summary
Pages 444-466

CHARACTERIZATION OF COMPARATORS
What is a Comparator?
The comparator is a circuit that compares one analog signal with another analog signal or
a reference voltage and outputs a binary signal based on the comparison.
The comparator is basically a 1-bit analog-to-digital converter:
Reference Analog Comparator

1-Bit ADC
Voltage Input 1
1-Bit 1-Bit
Quantizer Encoder
Analog 1-Bit 1-Bit 1-Bit
Analog
Input Quantizer Encoder Digital
Input 2
Output
060808-01
Comparator symbol:

Noninverting and Inverting Comparators

The comparator output is binary with the two-level outputs defined as,
VOH = the high output of the comparator
VOL = the low level output of the comparator
Voltage transfer function of a Noninverting and Inverting Comparator:
vo vo
VOH VOH
vP-vN vP-vN
VOL VOL
Noninverting Comparator Inverting Comparator
Fig. 8.1-2A

Infinite Gain Comparator

Voltage transfer function curve:
vo
VOH
vP-vN
VOL Fig. 8.1-2
Model:
vP
+ +
vP-vN f0(vP-vN) vO
- -
vN
Comparator
VOH for (vP-vN) > 0
f0(vP-vN) =
VOL for (vP-vN) < 0 Fig. 8.1-3
VOH-VOL
Gain = Av = lim where V is the input voltage change
V
V0

Finite Gain Comparator

Voltage transfer curve: vo
VOH
VIL
vP-vN
VIH
VOL
Fig. 8.1-4
where for a noninverting comparator,

VIH = smallest input voltage at which the output voltage is VOH
VIL = largest input voltage at which the output voltage is VOL
Model:
vP
+ +
VOH − VOL
vP-vN f1(vP-vN) vO The voltage gain is Av = V − V
-
IH IL
-
vN
Comparator
VOH for (vP-vN) > VIH
f1(vP-vN) = Av(vP-vN) for VIL< (vP-vN)<VIH
VOL for (vP-vN) < VIL Fig. 8.1-5

Input Offset Voltage of a Comparator

Voltage transfer curve:
vo
VOS VOH
VIL
vP-vN
VIH
VOL Fig. 8.1-6
VOH+VOL
VOS = the input voltage necessary to make the output equal when vP = vN.
2
Model:
vP
+vP' +
±VOSv '-v ' f1(vP'-vN') vO
P N
-v ' -
vN N
Comparator Fig. 8.1-7
Other aspects of the model:
ICMR = input common mode voltage range (all transistors remain in saturation)
Rin = input differential resistance
Ricm = common mode input resistance
Comparator Noise
vo
Noise of a comparator is modeled as if the VOH
comparator were biased in the transition region. Rms Noise
vP-vN
Noise leads to an uncertainty in the transition
region causing jitter or phase noise. VOL
Transition Uncertainty Fig. 8.1-8

Input Common Mode Range

Because the input is analog and normally differential, the input common mode range of
the comparator is also important.
Input common mode range (ICMR):
ICMR = the voltage range over which the input common-mode signal can vary
without influence the differential performance
As we have seen before, the ICMR is defined by the common-mode voltage range over
which all MOSFETs remain in the saturation region.

Propagation Delay Time

Rising propagation delay time:
vo
VOH
V +V
vo = OH OL
2 t
VOL
vi = vP-vN
VIH
V +V
tpr vi = IH IL tpf
2
t
VIL
070509-01
Propagation delay time =

Rising propagation delay time + Falling propagation delay time tpr + tpf
=
2 2

Linear Frequency Response – Dominant Single-Pole

Model:
Av(0) Av(0)
Av(s) = s = s +1
c
 + 1
c
where
Av(0) = dc voltage gain of the comparator
1
c =  = -3dB frequency of the comparator or the magnitude of the pole
c
Step Response:
vo(t) = Av(0) [1 - e-t/c]Vin
where
Vin = the magnitude of the step input.
Maximum slope of the step response:
dvo(t) Av(0)
= e-t/cVin
dt c
The maximum slope occurs at t = 0 giving,
dvo(t) | Av(0)
dt t=0 = c Vin
Propagation Time Delay

The rising propagation time delay for a single-pole comparator is:
VOH-VOL
c]V  1 
2 = A v (0) [1 - e -tp / in → tp = c ln  VOH -VOL
1 - 2Av(0)Vin 
 
Define the minimum input voltage to the comparator as,
VOH -VOL
tp = c ln  1 
Vin(min)
Vin(min) = →
Av(0)
1- 2Vin 
 
Define k as the ratio, Vin, to the minimum input voltage, Vin(min),
Vin  2k 
k = V (min) → tp = c ln 2k-1
in  
Thus, if k = 1, tp = 0.693c.
vout
Illustration:
Vin > Vin(min)
VOH
Obviously, the more overdrive vin + vout VOH+VOL
2
applied to the input, the smaller - VOL Vin = Vin(min)
the propagation delay time. 0 t t (max) t
0 p p Fig. 8.1-10
Dynamic Characteristics - Slew Rate of a Comparator

If the rate of rise or fall of a comparator becomes large, the dynamics may be limited by
the slew rate.
Slew rate comes from the relationship,
dv
i=C
dt
where i is the current through a capacitor and v is the voltage across it.
If the current becomes limited, then the voltage rate becomes limited.
Therefore for a comparator that is slew rate limited we have,
V VOH- VOL
tp = T = SR = 2·SR
where
SR = slew rate of the comparator.
If SR < |maximum slope|, then the comparator is slewing.

Example 31-1 - Propagation Delay Time of a Comparator

Find the propagation delay time of an open loop comparator that has a dominant pole
at 103 radians/sec, a dc gain of 104, a slew rate of 1V/µs, and a binary output voltage
swing of 1V. Assume the applied input voltage is 10mV.
Solution
The input resolution for this comparator is 1V/104 or 0.1mV. Therefore, the 10mV
input is 100 times larger than vin(min) giving a k of 100. Therefore, we get
1  2·100  200
tp = 3 ln2·100-1 = 10-3 ln199 = 5.01µs
10    
For slew rate considerations, we get

104
Maximum slope = -3 ·10mV = 105 V/sec. = 0.1V/µs.
10
Therefore, the propagation delay time for this case is limited by the linear response and
is 5.01µs.

DOMINANT POLE, OPEN-LOOP COMPARATORS

Dominant Pole Comparators
Any of the self-compensated op amps provide a straight-forward implementation of an
open loop comparator without any modification.
The previous characterization gives the relationships for:
1.) The static characteristics
• Gain
• Input offset
• Noise
2.) The dynamic characteristics
• Linear frequency response
• Slew rate response

Single-Stage Dominant Pole Comparator

VDD
M3 M4
VPBias2
MC3 MC4 vo
CL
MC1 MC2
vp M1 M2 v
VBias n
-
+ M5
VNBias1
-
060808-02
• Gain ≈ gm2rds2
• Slew rate = I5/CL
• Dominant pole = -1/(RoutCL) = -1/(gmrds2CL)

Folded-Cascode Comparator
VDD
VPB1
M4 M5
VPB2
M6 vOUT
vP M7
M1 M2 VNB2
vN
M8 M9 CL
M3
VNB1 I3 M11
M10
060808-03
• Gain ≈ gm2rds2
• Dominant pole = -1/(RoutCL) ≈ -1/(gmrds2CL)
• Slightly improved ICMR

Enhanced-Gain, Folded-Cascode Comparator

VDD
M10 M11
VPB1 M3
vP -A
M8 M9
vOUT
vN M1 M2
M6 M7 CL
-A -A
VNB1 M4
M5
060808-04
• Gain ≈ gm1Rout
• Rout ≈ [Ards7gm7(rds1||rds5)]|| (Ards9gm9rds11)
• Dominant pole = -1/(RoutCL)
TWO-POLE, OPEN-LOOP COMPARATORS

Two-Stage Comparator
The two-stage op amp without compensation is an excellent implementation of a
high-gain, open-loop comparator.
VDD
M3 M4
M6
vn vout
M1 M2
vp CL
+ M7
VNB1 M5
-
060808-05
• Much faster linear response – the two poles of the comparator are typically much larger
than the dominant pole of the self-compensated type of comparator.
• Be careful not to close the loop because the amplifier is uncompensated.
I7 I6-I7
• Slew rate: SR = C and SR = C
- +
II II
Performance of the Two-Stage, Open-Loop Comparator

We know the performance should be similar to the uncompensated two-stage op amp.
Emphasis on comparator performance:
• Maximum output voltage
 8I7 
VOH = VDD - (VDD-VG6(min)-|VTP|)1 - 1- 
  (V -V
6 DD G6 (min)-|V TP|) 2

• Minimum output voltage
VOL = VSS
• Small-signal voltage gain
 gm1  gm6 
Av(0) =   
 ds2 ds4 ds6 ds7
g +g g +g
• Poles
Input: Output:
-(gds2+gds4) -(gds6+gds7)
p1 = CI p2 = CII
• Frequency response
Av(0)
Av(s) =
s  s 
p - 1p - 1
 1  2 
Example 31-2 - Performance of a Two-Stage Comparator

Evaluate VOH, VOL, Av(0), Vin(min), p1, p2, VDD = 2.5V
M3 M4 M6
for the two-stage comparator shown. The 15µm
1µm
15µm
1µm
94µm
1µm
large signal model parameters are KN’ =
vout
110µA/V2, KP’ = 50µA/V2, VTN = |VTP| = 30µA
-
M1
3µm 3µm
M2 CI = 0.2pF
CII = 5pF
1µm 1µm
95µA
0.7V, N = 0.04V-1 and P = 0.05V-1.
vin
+
Assume that the minimum value of VG6 = 30µA
4.5µm 14µm
1µm 4.5µm 1µm
0V and that CI = 0.2pF and CII = 5pF. M8 M5 1µm M7
VSS = -2.5V 070509-02
Solution
Using the above relations, we find that
 8·234x10-6 
VOH = 2.5 - (2.5-0-0.7) 1 -1-  = 2.2V
 50x10-6·38(2.5-0-0.7)2 
VOL is -2.5V. The gain can be found as Av(0) = 7696. Therefore, the input resolution is
Vin(min) = (VOH-VOL)/Av(0) = 4.7V/7,696 = 0.611mV
Next, we find the poles of the comparator, p1 and p2.
p1 = -(gds2 + gds4)/CI = 15x10-6(0.04+0.05)/0.2x10-12 = -6.75x106 (1.074MHz)
and
p2 = -(gds6 + gds7)/CII) =(95x10-6)(0.04+0.05)/5x10-12 = -1.71x106 (0.272MHz)
Linear Step Response of the Two-Stage Comparator

The step response of a circuit with two real poles (p1  p2) is,
 p2etp1 p1etp2
vout(t) = Av(0)Vin1 + p -p - p -p 
 1 2 1 2
Normalizing gives,
vout(t) m -t 1 -mt p2
vout’(tn ) = A (0)V = 1 - m-1e n + m-1e n where m = p  1 and tn = -tp1
v in 1
If p1 = p2 (m=1), then vout’(tn) = 1 - etp1 + tp1etp1 = 1 - e-tn - tne-tn
1
m=4
Normalized Output Voltage
0.8
m=2 m = 1 m = 0.5
m = 0.25
0.6
0.4
p2
m= p
1
0.2
0
0 2 4 6 8 10
CMOS Analog Circuit Design Normalized Time (tn = -tp1 ) Fig. 8.2-2 © P.E. Allen - 2016
Linear Step Response of the Two-Stage Comparator - Continued

The above results are valid as long as the slope of the linear response does not exceed the
slew rate.
• Slope at t = 0 is zero
• Maximum slope occurs at (m )
ln(m)
tn(max) = m-1
and is
dvout’(tn(max)) m  -ln(m) 
 ln(m)
= m-1exp m-1  - exp-m m-1 
dtn     
• For the two-stage comparator using NMOS input transistors, the slew rate is
I7
-
SR = C
II
I6-I7 0.56(VDD-VG6(min)-|VTP|)2 - I7
SR+ = C =
II CII

Example 31-3 - Step Response of Ex. 31-2

Find the maximum slope of Ex. 31-2 and the time it occurs if the magnitude of the
input step is vin(min). If the dc bias current in M7 is 100µA, at what value of load
capacitance, CL would the transient response become slew limited? If the magnitude of
the input step is 100vin(min), what is the new value of CL at which slewing would occur?
Solution
The poles of the comparator were given in Ex. 31-2 as p1 = -6.75x106 rads/sec. and
p2 = -1.71x106 rads/sec. This gives a value of m = 0.253. From the previous
expressions, the maximum slope occurs at tn(max) = 1.84 secs. Dividing by |p1| gives
t(max) = 0.272µs. The slope of the transient response at this time is found as
dvout’(tn(max))
= -0.338[exp(-1.84) - exp(-0.253·1.84)] = 0.159 V/sec
dtn
Multiplying the above by |p1| gives dvout’(t(max))/dt = 1.072V/µs. If the slew rate is less
than 1.072V/µs, the transient response will experience slewing. Therefore, if CL ≥
100µA/1.072V/µs or 93.3pF, the comparator will slew.
If the input is 100vin(min), then we must unnormalize the output slope as follows.
dvout’(t( max)) vin dvout’(t( max))
= v (min) = 100·1.072V/µs = 107.2V/µs
dt in dt
Therefore, the comparator will slew with a load capacitance greater than 0.933pF.
Propagation Delay Time (Non-Slew)

To find tp, we want to set 0.5(VOH-VOL) equal to vout(tn). However, vout(tn) given as
 m -t 1 -mt 

vout(tn) = Av(0)Vin 1 - m-1e n + m-1e n
 
can’t be easily solved so approximate the step response as a power series to get
 m  tn2  1  m2tn2 
vout(tn)  Av(0)Vin 1 - m-1 1-tn+ 2 + ··· + m-1 1-mtn+ 2 +··· 
   
    
mtn2Av(0)Vin
2
Therefore, set vout(tn) = 0.5(VOH-VOL)
VOH-VOL mtpn2Av(0)Vin

2 2
or
VOH-VOL Vin(min) 1
tpn  mAv(0)Vin = =
mVin mk
This approximation is particularly good for large values of k.

Example 31-4 - Propagation Delay Time of a Two-Pole Comparator (Non-Slew)

Find the propagation time delay of Ex. 31-2 if Vin = 10mV, 100mV and 1V.
Normalized Output Voltage (vn = v\k)

Solution 1
m=4
From Ex. 31-2 we know that
Vin(min) = 0.611mV and m = 0.8
m=2 m = 1 m = 0.5
0.253. For Vin = 10mV, k = 16.366 m = 0.25
0.6
which gives tpn   mk = 0.491.
The propagation time delay is equal 0.4
to 0.491/6.75x106 or 72.9nS. p2
m= p
1
In the figure shown, tpn, occurs 0.2
VOH-VOL 1 1 = 0.031
when vn is equal to 2A (0)V = 2k  2k 0
v in 0 2 4 6 8 10
0.52 Normalized Time (tn = tp1 = t/t1)
This corresponds well with the tp = 0.52 = 77ns
120524-01 6.75x106
figure shown where the normalized
propagation time delay is the time at which the amplitude is 1/2k or 0.031which
corresponds to tpn of approximately 0.52 compared with 0.491 of above.
Similarly, for Vin = 100mV and 1V we get a propagation time delay of 23ns and
7.3ns, respectively.
Initial Operating States for the Two-Stage, Open-Loop Comparator

What are the initial operating states for the two-stage, open-loop comparator? The
following table summarizes the results for the two-stage, open-loop comparator shown.
Conditions Slew? Initial State of vo1 Initial State of vout
vG1>VG2, i1<ISS and i2>0 No VDD-VSD4(sat) < vo1 < VDD VSS
vG1>>VG2, i1=ISS and i2=0 Yes VDD VSS
vG1<VG2, i1>0 and i2<ISS No vo1=VG2-VGS2,act(ISS/2), VSS if M5 act. VOH, see below.
vG1<<VG2, i1>0 and i2<ISS No VSS VOH, see below.
vG2>VG1, i1>0 and i2<ISS No VS2(ISS/2)<vo1<VS2(ISS/2)+VDS2(sat) VOH, see below.
vG2>>VG1, i1>0 and i2<ISS No VG1-VGS1(ISS/2) , VSS if M5 active VOH, see below.
vG2<VG1, i1<ISS and i2>0 No VDD-VSD4(sat) < vo1 < VDD VSS
vG2<<VG1, i1=ISS and i2=0 Yes VDD VSS
VDD
i3 i4
VOH = VDD – (VDD-VG6(min)-|VTP|)
M3 M4 vo1
M6
 8I7  i1 i2 CI
×1 - 1-  vout
 6(VDD-VG6(min)-|VTP|)2  vG1 M1 M2 vG2
CII
ISS
+ M7
VBias M5
CMOS Analog Circuit Design - © P.E. Allen - 2016
VSS 120524-02
Trip Point of an Inverter VDD

In order to determine the propagation delay time, it is
necessary to know when the second stage of the two-stage + M6
vin i6
comparator begins to “turn on”. - vout
Second stage: i7
M7
VBias
Trip point:
VSS Fig. 8.2-4
Assume that M6 and M7 are saturated. (We know that the
steepest slope occurs for this condition.)
Equate i6 to i7 and solve for vin which becomes the trip point.
KN(W7/L7)
 vin = VTRP = VDD - |VTP| - KP(W6/L6) (VBias- VSS -VTN)
Example:
If W7/L7 = W6/L6, VDD = 2.5V, VSS = -2.5V, and VBias = 0V the trip point for the
circuit above is
VTRP = 2.5 - 0.7 - 110/50 (0 +2.5 -0.7) = -0.870V

Propagation Delay Time of a Slewing, Two-Stage, Open-Loop Comparator

Previously we calculated the propagation delay time for a nonslewing comparator.
If the comparator slews, then the propagation delay time is found from
dvi vi
ii = Ci dt = Ci t
i i
where
Ci is the capacitance to ground at the output of the i-th stage
The propagation delay time of the i-th stage is,
 Vi
ti = ti = Ci I
i
The propagation delay time is found by summing the delays of each stage.
tp = t1 + t2 + t3 + ···

Example 31-5 - Propagation Time Delay of a Two-Stage, Open-Loop Comparator

VDD = 2.5V
For the two-stage comparator shown
M3 M4 M6
assume that CI = 0.2pF and CII = 5pF. Also, 4.5mm 4.5mm 38mm
1mm 1mm 1mm
assume that vG1 = 0V and that vG2 has the vo1
vout
waveform shown. If the input voltage is large 30mA vG1 M1 3mm 3mm M2 CI =
0.2pF CII =
enough to cause slew to dominate, find the 1mm 1mm 5pF
vG2
propagation time delay of the rising and 234mA
falling output of the comparator and give the 4.5mm 30mA

35mm
propagation time delay of the comparator. 1mm 4.5mm 1mm
M8 M5 1mm M7
vG2 VSS = -2.5V Fig. 8.2-5A
2.5V
0V 0.2 0.4 t(ms)

0 0.6
-2.5V
Solution Fig. 8.2-5
1.) Total delay = sum of the first and second stage delays, t1 and t2
2.) First, consider the change of vG2 from -2.5V to 2.5V at 0.2µs.
The last row of table on Slide 31-26 gives vo1 = +2.5V and vout = -2.5V
3.) tf1, requires CI, Vo1, and I5. CI = 0.2pF, I5 = 30µA and V1 can be calculated by
finding the trip point of the output stage.

4.) The trip point of the output stage by setting the current of M6 when saturated equal
to 234µA.
6 234·2
(V -|V |) 2 = 234µA → V = 0.7 +
2 SG6 TP SG6 50·38 = 1.196V
Therefore, the trip point of the second stage is VTRP2 = 2.5 - 1.196 = 1.304V
Therefore, V1 = 2.5V - 1.304V = VSG6 = 1.196V. Thus the falling propagation time
delay of the first stage is
1.196V
tfo1 = 0.2pF  30µA  = 8 ns
 
5.) The rising propagation time delay of the second stage requires CII, Vout, and I6. CII
is given as 5pF, Vout = 2.5V (assuming the trip point of the circuit connected to the
output of the comparator is 0V), and I6 can be found as follows:
VG6(guess)  0.5[VG6(I6=234µA) + VG6(min)]
2·15
VG6(min) = VG1 - VGS1(ISS/2) + VDS2  -VGS1(ISS/2) = -0.7 - 110·3 = -1.00V
VG6(guess)  0.5(1.304V-1.00V) = 0.152V
6 38·50
Therefore VSG6 = 2.348V and I6 = 2 (VSG6-|VTP|)2 = 2
2 (2.348 - 0.7) = 2,580µA

6.) The rising propagation time delay for the output can expressed as
 2.5V 
trout = 5pF 2580µA-234µA = 5.3 ns

 
Thus the total propagation time delay of the rising output of the comparator is
approximately 13.3 ns and most of this delay is attributable to the first stage.
7.) Next consider the change of vG2 from 2.5V to -2.5V at 0.4µs. We shall assume that
vG2 has been at 2.5V long enough for the conditions of the table on Slide 31-26 to be
valid. Therefore, vo1  VSS = -2.5V and vout  VDD. The propagation time delays for the
first and second stages are calculated as 3V
vout
1.304V-(-1.00V)
tro1 = 0.2pF  
 = 15.4 ns
2V
VTRP6 = 1.304V
 30µA 
 2.5V  1V
tfout = 5pF 234µA = 53.42ns 0V

 
vo1
8.) The total propagation time delay of the falling -1V
output is 68.82 ns. Taking the average of the rising -2V Falling prop.
Rising prop. delay time
and falling propagation time delays gives a delay time
-3V
propagation time delay for this two-stage, open- 200ns 300ns 400ns
Time
500ns 600ns
Fig. 8.2-6
loop comparator of about 41.06ns.
SUMMARY
• The two-stage, open-loop comparator has two poles which should as large as possible
• The transient response of a two-stage, open-loop comparator will be limited by either
the bandwidth or the slew rate
• It is important to know the initial states of a two-stage, open-loop comparator when
finding the propagation delay time
• If the comparator is gainbandwidth limited then the poles should be as large as
possible for minimum propagation delay time
• If the comparator is slew rate limited, then the current sinking and sourcing ability
should be as large as possible

Lecture 32 – Improved Open-Loop Comparators and Latches (6/26/14) Page 32-1
LECTURE 32 – IMPROVED OPEN-LOOP COMPARATORS AND

LATCHES
Outline
• Autozeroing
• Hysteresis
• Simple Latches
• Summary
Pages 469-488

AUTOZEROING
Principle of Autozeroing
Use the comparator as an op amp to sample the dc input offset voltage and cancel the
offset during operation.
Comments:
• The comparator must be stable in the unity-gain mode (self-compensating comparators
are ideal, the two-stage comparator would require compensation to be switched in
during the autozero cycle.)
• Complete offset cancellation is limited by charge injection
Differential Implementation of Autozeroed Comparators

Single-Ended Autozeroed Comparators

Noninverting:
Inverting:
Comment on autozeroing:
Need to be careful about noise that gets sampled onto the autozeroing capacitor and
is present on the comparison phase of the process.

HYSTERESIS
Influence of Input Noise on the Comparator
Comparator without hysteresis: Comparator with hysteresis:
Comparator vin vin
threshold VTRP+
t t
VTRP-
vout vout
VOH VOH
t t
VOL Fig. 8.4-6A VOL
Fig. 8.4-6B
Voltage Regulator with input voltage having too large of source resistance, RS:
+ -
RS
+ Enable Voltage
VIN - Regulator
VON CL RL
150604-01

Use of Hysteresis for Comparators in a Noisy Environment

Transfer curve of a comparator with hysteresis:
vOUT vOUT
VOH VOH
VTRP+ R1(V -V )
R2 OH OL VTRP+
vIN 0 vIN
0
VTRP- VTRP-
VOL VOL
Counterclockwise Bistable Clockwise Bistable Fig. 8.4-5
Hysteresis is achieved by the use of positive feedback

• Externally
• Internally

Noninverting Comparator using External Positive Feedback

Circuit:
Upper Trip Point:

Assume that vOUT = VOL, the upper trip point occurs when,
 R1   R2  R1
0= VOL +  VTRP+ → VTRP = - VOL
+
R1+R2 R1+R2 R2
Lower Trip Point:
Assume that vOUT = VOH, the lower trip point occurs when,
 R1   R2  R1
0 = R +R VOH + R +R VTRP- → VTRP = - R VOH
-
 1 2  1 2 2
Width of the bistable characteristic:

R1
Vin = VTRP -VTRP =   VOH -VOL
+ -
R2
Inverting Comparator using External Positive Feedback

Circuit:
Upper Trip Point:

 R1 
vIN = VTRP+ = R +R VOH
 1 2
Lower Trip Point:
 R1 
vIN = VTRP- = R +R VOL
 1 2
Width of the bistable characteristic:
 R1 
Vin = VTRP+-VTRP- =   VOH -VOL
R1+R2

Horizontal Shifting of the CCW Bistable Characteristic

Circuit:
Upper Trip Point:

 R1   R2  R1+R2 R1
VREF = R +R VOL + R +R VTRP+ → VTRP+ =  R VREF - R VOL
 1 2  1 2  2  2
Lower Trip Point:

 R1   R2  R1+R2 R1
VREF =   VOH +  VTRP- → VTRP- =  VREF - VOH
 1 2
R +R  1 2
R +R  R2  R2
Shifting Factor:
R1+R2
± R  VREF
 2 

Horizontal Shifting of the CW Bistable Characteristic

Circuit:
Upper Trip Point:

 R1   R2 
vIN = VTRP+ = R +R VOH + R +R VREF
 1 2  1 2
Lower Trip Point:
 R1   R2 
vIN = VTRP- =  VOL +  VREF
 1 2
R +R  1 2
R +R
Shifting Factor:
 R2 
±R +R  VREF
 1 2
Example 32-1 Design of an Inverting Comparator with Hysteresis

Use the inverting bistable to design a high-gain, open-loop comparator having an
upper trip point of 1V and a lower trip point of 0V if VOH = 2V and VOL = -2V.
Solution
Putting the values of this example into the above relationships gives
 R1   R2 
1= 2+ VREF
R +R
 1 2 R +R
 1 2
and
 R1   R2 
0 = R +R  (-2) + R +R VREF
 1 2  1 2
Solving these two equations gives 3R1 = R2 and VREF = (2/3)V.

Hysteresis using Internal Positive Feedback

Simple comparator with internal positive feedback:
VDD
IBias M3 M6 M7 M4
vo1 vo2
vi1 M1 M2 vi2
M8 M5
Fig. 8.4-11
VSS

Internal Positive Feedback - Upper Trip Point

VDD
Assume that the gate of M1 is on ground and the
input to M2 is much smaller than zero. The
resulting circuit is: M3 M6 M7 M4
vo1 vo2
M1 on, M2 off → M3 on, M6 on (active), M4
and M7 off.
 vo2 is high. M1 M2
i1 = i3 i 2 = i6
W6/L6 vin
M6 wants to source the current i6 = W /L i1 M5
3 3 I5
As vin begins to increase towards the trip point, the
Fig. 8.4-12A
current flow through M2 increases. When i2 = i6, VSS
the upper trip point will occur.
W6/L6   W6/L6 I5
 I5 = i1+i2 = i3+i6 = i3+ i3 = i3 1 +  → i1 = i3 =
W /L
 3 3  W /L
3 3 1 + [(W6/L6)/(W3/L3)]
Also, i2 = I5 - i1 = I5 - i3
Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives
2i2 2i1
+
VTRP = vGS2 - vGS1 = + VT2 - - VT1
2 1
Internal Positive Feedback - Lower Trip Point

VDD
Assume that the gate of M1 is on ground and the input
to M2 is much greater than zero. The resulting circuit
is: vo1 M3 M6 M7 M4
vo2
M2 on, M1 off → M4 and M7 on, M3 and M6 off.
 vo1 is high. vi1 vi1
M1 M2
W7/L7 i1 = i7 i2 = i4
M7 wants to source the current i7 = W /L i2 vin
4 4
I5
M5
As vin begins to decrease towards the trip point, the Fig. 8.4-12B
VSS
current flow through M1 increases. When i1 = i7, the lower trip point will occur.
W7/L7   W7/L7 i5
 i5 = i1+i2 = i7+i4 =  i4 +i4 = i4 1 +  → i2 = i4 =
W4 /L4   W4 /L4  1 + [(W7/L7)/(W4/L4)]
Also, i1 = i5 - i2 = i5 - i4
Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives
2i2 2i1
-
VTRP = vGS2 - vGS1 =  + VT2 -  - VT1
2 1
Example 32-2 - Calculation of Trip Voltages for a Comparator with Hysteresis

Consider the circuit shown. If KN’ = 110µA/V2, VDD
KP’ = 50µA/V2, and VTN = |VTP| = 0.7V,
IBias M3 M6 M7 M4
calculate the positive and negative threshold
vo1
points if the device lengths are all 1 m and the vo2
widths are given as: W1 = W2 = W6 = W7 = 10 m

and W3 = W4 = 2 m. The gate of M1 is tied to vi1 M1 M2 vi2
ground and the input is the gate of M2. The

current, i5 = 20 A M8 M5
Solution Fig. 8.4-11
VSS
To calculate the positive trip point, assume
that the input has been negative and is heading positive.
(W/L)6 i5 20 A
i6 = (W/L) i3 = (5/1)(i3) → i3 = 1 + [(W/L) /(W/L) ] = i1 = 1 + 5 = 3.33 A
3 6 3
2i11/2  2·3.33  1/2
i2 = i5 − i1 = 20 − 3.33 = 16.67 A → vGS1 =    +VT1 = (5)110 +0.7 = 0.81V
 1  
2i21/2 2·16.671/2
vGS2 =    + VT2 =  
 + 0.7 = 0.946V
 2  (5)110 
 VTRP+  vGS2−vGS1 = 0.946−0.810 = 0.136V

Determining the negative trip point, similar analysis yields
i4 = 3.33 A
i1 = 16.67 A
vGS2 = 0.81V
vGS1 = 0.946V
VTRP-  vGS2 − vGS1 = 0.81 − 0.946 = −0.136V
PSPICE simulation results of this circuit are shown below.
2.6
2.4
Remember the simple
2.2
SAH model does not do
a good job of modeling 2
the knee or saturation vo2
1.8
(volts)
voltage.
1.6
1.4
1.2
1
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
vin (volts) Fig. 8.4-13
Complete Comparator with Internal Hysteresis

VDD
IBias M3 M6 M7 M4
M9 M8
vi1 vi2
M1 M2 vout
M10 M11
M8 M5 2.6
2.4
VSS Fig. 8.4-14 2.2
2
vout
1.8
(volts)
1.6
1.4
1.2
1
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
vin (volts) 120524-03

Schmitt Trigger
The Schmitt trigger is a circuit that has better defined switching points.
Consider the following circuit:
VDD How does this circuit work?
Assume the input voltage, vin, is low and the output voltage,
M5
vout , is high.
M4 M3, M4 and M5 are on and M1, M2 and M6 are off.
vin M3 vout When vin is increased from zero, M2 starts to turn on causing M3
M2 to start turning off. Positive feedback causes M2 to turn on
M6
further and eventually both M1 and M2 are on and the output is at
zero.
M1 The upper switching point, VTRP+ is found as follows:
120524-04
When vin is low, the voltage at the source of M2 (M3) is
vS2 = VDD-VTN3
VTRP+ = vin when M2 turns on given as VTRP+ = VTN2 + vS2
VTRP+ occurs when the input voltage causes the currents in M3 and M1 to be equal.

Schmitt Trigger – Continued

Thus, iD1 = ( VTRP+ - VTN1)2 = ( VDD - vS2- VTN3) 2 = iD3
which can be written as, assuming that VTN2 = VTN3,
VTN1 + 3/1 VDD
( VTRP+ - VTN1 )2 = ( VDD – VTRP +)2  VTRP+ =
1 + 3/1
The switching point, VTRP- is found in a similar manner and is:
5/6(VDD- VTP5)
( VDD - VTRP- - VTP5)2 = ( VTRP-)2  VTRP- =
1+ 5/6
vout
The bistable characteristic is,
VDD
0 0 vin
VTRP- VTRP+ VDD
Fig. 8.4-16
SIMPLE LATCHES
Regenerative Comparators
Regenerative comparators use positive feedback to accomplish the comparison of two
signals. Latches can have a faster switching speed than the previous comparators.
NMOS and PMOS latch:
VDD VDD
I1 I2 M1 M2
vo1 vo2 vo1 vo2
M1 M2 I1 I2
NMOS latch PMOS latch

Fig. 8.5-3

Operating Modes of the Latch

The latch has two modes of operation – enable or latch and Enable (enable_bar) or
Latch (latch_bar).
1.) During the Enable_bar, the latch is turned off (currents are removed) and the
unknown inputs are applied to it. The parasitic capacitance at the latch nodes hold the
unknown voltage.
2.) During Enable, the latch is turned on, and the positive feedback acts on the applied
inputs and causes one side of the latch to go high and the other side to go low.
Enable_bar:
VDD VDD
I1 I2 M1 M2
Enable Enable Enable Enable
Vo1ʼ Vo2ʼ Vo1ʼ Vo2ʼ
M1 M2 I1 I2
NMOS latch PMOS latch 060808-09
The inputs are initially applied to the outputs of the latch.

Vo1’ = initial input applied to vo1

Step Response of a Latch (Enable)

VDD VDD
Circuit:
Ri and Ci are the I1 I2
+ + +
resistance and capacitance vo2 C1 C2
vo1 Vo2 Vo1 Vo2
seen to ground from the Vo1' Vo2'
M1 M2 gm1Vo2 R1 s gm2Vo1 R2 s
i-th transistor. - - -
Nodal equations: Fig. 8.5-4
 Vo1’
gm1Vo2+G1Vo1+sC1Vo1- s  = gm1Vo2+G1Vo1+sC1V o1-C1Vo1’ = 0
 
 Vo2’
gm2Vo1+G2Vo2+sC2 Vo2- s  = gm2Vo1+G2Vo2+sC2V o2-C2Vo2’ = 0

 
Solving for Vo1 and Vo2 gives,
R1C1 gm1R1 1 gm1R1
Vo1 = sR C +1 Vo1’ - sR C +1 Vo2 = Vo1’ - Vo2
1 1 1 1 s1 +1 s1 +1
R2C2 gm2R2 2 gm2R2
Vo2 = sR C +1 Vo2’ - sR C +1 Vo1 = V ’- V
2 2 2 2 s2+1 o2 s2+1 o1
Defining the output, Vo, and input, Vi, as
Vo = Vo2-Vo1 and Vi = Vo2’-Vo1’
Step Response of the Latch - Continued

 gmR
Solving for Vo gives, Vo = Vo2-Vo1 = Vi + V o
s+1 s+1
or
 V i
  Vi 1-gmR ’ Vi
V o = = =
s+(1-gmR) s s’+1
+ 1
1-gmR
where

’ = 1-g R
m
Taking the inverse Laplace transform gives
vo(t) = Vi e-t/’ = Vi e-t(1-gmR) /  egmRt/Vi, if gmR >>1.
Define the latch time constant as
 C 0.67WLCox WL3
L = |’|  g R = g = = 0.67Cox 2K’I
m m 2K’(W/L)I
if C  Cgs.
 Vout(t) = et/L Vi
Step Response of a Latch - Continued

Normalize the output voltage by (VOH-VOL) to get
Vout(t) V i
et/L
VOH-VOL = VOH-VOL
which is plotted as,
VOH- VOL
The propagation delay time is tp = L ln  
 2  V i 
Note that the larger the Vi, the faster the response.
Example 32-3 - Time Domain Characteristics of a Latch.

Find the propagation time delay for the NMOS if the W/L of the latch transistors is
5µm/0.5µm and the latch dc current is 10µA when Vi = 0.1(VOH-VOL) and Vi =
0.01(VOH-VOL).
Solution
The transconductance of the latch transistors is
gm = 2·120·10·10 = 155µS
The output conductance is 0.6µS which gives gmR of 93V/V. Since gmR is greater than
1, we can use the above results. Therefore the latch time constant is found as
WL3 (5·0.5)x10-24
L = 0.67Cox 2K’I = 0.67(60.6x10 -4)
2·120x10-6·10x10-6
= 0.131ns
Since the propagation time delay is the time when the output is 0.5(VOH-VOL), then
using the above results or Fig. 8.5-5 we find for Vi = 0.01(VOH-VOL) that tp = 3.91L =
0.512ns and for Vi = 0.1(VOH-VOL) that tp = 1.61L = 0.211ns.

Comparator using a Latch with a Built-In Reference†

How does it operate?
1.) Devices in shaded region operate in the triode region.
2.) When the latch/reset goes high, the upper cross-coupled inverter-latch regenerates.
The drain currents of M5 and M6 are steered to obtain a final state determined by the
mismatch between the R1 and R2 resistances.
1  W1 W2 
 + - 
R1 = KN  L (vin - VT) + L (VREF - VT) 
and
1  W1 W2 
 - + 
R2 = KN  L (vin - VT) + L (VREF - VT) 
3.) The input voltage which causes R1 = R2 is vin(threshold) = (W2/W1)VREF

W2/W1 = 1/4 generates a threshold of ±0.25VREF.
Performance → 20Ms/s & 200µW
†T.B. Cho and P.R. Gray, “A 10b, 20Msamples/s, 35mW pipeline A/D Converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, March
1995.
Simple, Low Power Latched Comparator†
Dissipated 50µW when clocked at 2MHz.

Self-referenced
†A. Coban, “1.5V, 1mW, 98-dB Delta-Sigma ADC”, Ph.D. dissertation, School of ECE, Georgia Tech, Atlanta, GA 30332-0250.
Tail-Referenced Latch
The previous two latches experience poor input offset VDD
voltage characteristics because the input devices are Latch Latch
working in the linear region during the latch phase.
vout- vout+
The latch below keeps the input devices in the sat-
uration region. The resulting larger gain of the input
devices reduces the input offset voltage as shown.
vin+ Vref+ Vref- vin-
The input offset voltage of the tail referenced M1 M2
latch is compared between two latches with the
referenced latch for 100 samples. The x-axis is the Latch
All transistors are
3.5µm/0.4µm except
deviation from the mean of the first latch and the y- 070511-01 M1 and M2
axis is the deviation of the mean of the second latch.

CMOS Latch
Circuit:
Input offset voltage distribution:

CMOS Latch with Different Inputs and Outputs
When Latch_bar is high, M5 and M6 are off, M7 is on, and the latch is disabled and the
outputs are shorted together.
When Latch_bar is low, the input voltages stored at the sources of M1 and M2 will cause
one of the latch outputs to be high and the other to be low.
The source of M1 and M2 that is higher will have a larger source-gate voltage
resulting in a larger transconductance and more gain than the other transistor.
Metastability
Metastability is the condition where the latch cannot make a decision in the time
allocated. Normally due to the fact that the input is small (within the input resolution
range).
Metastability can be improved (reduced) by increasing the gain of the comparator by
preceding it with an amplifier to keep the signal input to the latch as large as possible
under all conditions. The preamplifier also reduced the input offset voltage.

SUMMARY
• The performance of open-loop comparators can be improved by the use of autozeroing
and hysteresis
• Discrete-time comparators must work with clocks
• Regenerative comparators (latches) use positive feedback
• The propagation delay of the regenerative comparator is slow at the beginning and
speeds up rapidly as time increases
• The highest speed comparators will use a combination of open-loop comparators and
latches

Lecture 33 – High Speed Comparators (6/26/14) Page 33-1
LECTURE 33 – HIGH SPEED COMPARATORS

Outline
• Speed limitations of comparators
• High speed comparators
• Summary
Pages 466-469 and 488-492

SPEED LIMITATIONS OF COMPARATORS

Speed Limitations of Comparators
The speed of a comparator is limited by either:
• Linear response – response time is inversely proportional to the magnitude of poles
jw Gain vout Propagation
Increase for Time Delay
speed s VOH
Increase
bandwidth w
060810-01 VOL t
• Slew rate – delay is proportional to capacitance and inversely proportional to

current sinking or sourcing capability
VDD
Propagation
ISource vout
Time Delay
VOH
+ dvout = I
ISink CL vout dt CL
- VOL t
060810-02

Maximizing the Linear Response

Consider the amplifier of Example 27-3 given below:
VDD
VPB1 VPB1
I5 I3 I4 I6
M5 M3 Vout M4 M6
M1 - + M2
+ I1 I2
Vin
-
VNB1 I7
M7
060711-01
One stage of this amplifier had a gain of 10 and a dominant pole at 551MHz. The
response of this amplifier to a step input is
Vout(t) = 10Vin (1-e-p1t)
If the output signal swing is 1V and the step is 0.1V, the propagation time delay is,
Vin(min) = 1/10 = 0.1V  k = 1
2k    2 
 1   
 tp = ln  = ln = 0.20 ns
p 2k-1 2π·551x106 2-1




Trading Speed for Sensitivity (Gain)

In the previous example, the gain was too small for good sensitivity. To enhance the
sensitivity, cascade three of the
gain of 10 stages. The result is, + + + + + +
Vin A1 A2 A3 Vout
The frequency response of this - - - - - -
amplifier is, 10V/V 10V/V 10V/V
Vout(s) 1000 p1=551MHz p1=551MHz p1=551MHz
=
Vin(s) (1 + s/p1)3
The step response of this amplifier is
Ao Ao Ao
3
vout(t) = 2 Vinp1 t e2 -p1 t ≈ 2 Vinp1 t [1 - p1t + p1 t - ···] ≈ 2 Vinp13t2 if p1t<1
3 2 2 2
The propagation delay time is for k = 100 is

VOH-VOL 1 1
2
tp = =  tp = 0.491x10 -15 sec. !!!
Ao Vinp13 kp13
The speed of the amplifier will be limited by the slew capability.
Note: Slew rate ≈ 1V/10-15 sec = 1015 V/sec → iRequired for 1fF ≈ C(dV/dt) = 1A!!!

Maximizing Speed for Slew Rate Limitation

The key is to make the sourcing/sinking current large and the capacitance small.
Best possible sinking/sourcing circuit in CMOS is:
VDD
M2
ISource
vIN vOUT
M1 ISink
CL
060810-03
Assuming a W/L ratio of 42 for M1 and 200 for M2, if the input can swing to VDD
(=2.5V) and ground, the sourcing and sinking currents are:
Kp'W 25·200
ISourcing = (VDD – |VTP|)2 = (2.5V-0.5)2 µA = 10.0 mA
2L 2
Kn'W 120·42
ISinking = 2L (VDD – VTN)2 = 2 (2.5V-0.5)2 µA = 10.1 mA
If larger currents are required, cascaded stages can be used to optimize the delay versus
the current output.
Driver Delay of a Push-Pull Inverter

If too much current is required, the device sizes become large and the driver delay
increases. For the previous example, the input capacitance for the driver assuming Cox ≈
6fF/µm2 and the channel lengths are 0.5µm, is,
Cin = Cgs1 + Cgs2 = 2·(2/3) Cox(W1L1 + W2L2)
= 1.33·6fF/µm2(121µm2) = 0.968 pF
M2
Driver 200µm
0.5µm
M1
Cin 42µm CLoad
0.5µm
070510-02
If the effective resistance of the driver is 30k, then the delay is 29 ns which is much too
large.

Optimizing the Delay of a Chain of Push-Pull Inverters

For a series of N inverters as shown below, the W/L is increased by a factor of f for each
succeeding stage.
W/L = 1 f f2 f N-2 f N-1
Cin CLoad = fNCin

070510-01
ln(CLoad /Cin)
From the above figure we see that CLoad = f NCin → N = ln f
The delay of a single, push-pull inverter can be expressed as,
 Cj 
tinv = invC + inv
 j-1 
where
inv = ReffCin (Reff is the effective output resistance of the inverter)
Cself Cjunction
inv = C = C (Cjunction is the bulk-drain capacitances)
in in

Optimizing the Delay of a Chain of Push-Pull Inverters – Continued

The total delay of the chain of inverters is
 Cj 
ttotal = N invC + inv
 j-1 
Cj
Setting f = C gives
j-1
ln(CLoad /Cin)
ttotal = ln f inv (f + inv)
Plotting the total delay versus f for various values
of inv shows that the optimum value of f lies in
the range of 2.5 to 4†.
† D.A. Hodges, H.G. Jackson, and R.A. Saleh, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, 3rd ed.,
McGraw-Hill Book Co., 2004, Chapter 6.
Example 33-1 – Finding the Optimum Delay for a Chain of Inverters

Assume that CLoad is 5pf, Cin = 50fF, inv = 10ps , and inv = 0.5. If f = 3.6, find the
optimal number of stages and the total delay of this chain of inverters.
Solution
From above we get the optimal number of stages as,
ln(CLoad /Cin) ln(100)
N= = ln 3.6 = 3.59
ln f
If we choose N = 4, then f can be recomputed as
1
ln f = 4 ln(100)  f = 3.16
The total delay is,
 Cj 
ttotal = N inv + inv = 4·10ps(3.16 + 0.5) = 146ps
Cj-1 

Self-Biased Differential Amplifier†

Not as good as the push-pull inverter but interesting.
VDD
VDD
VBias M6 Extremely
M6 large sourcing
M3 M4 current
M3 M4
vout
vin+ vin- vin+ vin-
M1 M2
M1 M2
M5
VBias M5
VSS Fig. 8.3-4
VSS
Advantage:
Large sink or source current with out a large quiescent current.
Disadvantage:
Poor common mode range (vin+ slower than vin-)
†M. Bazes, “Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 2,
Feb. 1991, pp. 165-168.
Comparators that Can Drive Large Capacitive Loads

VDD
M8 M10
M3 M4
M6
vn
M1 M2 vout
vp CL
+ M7 M9 M11
VNB1 M5
-
060808-08
Comments:
• Slew rate = 3V/µs into 50pF
• Linear rise/fall time = 100ns into 50pF
• Propagation delay time  1µs
• Loop gain  32,000 V/V
• The quiescent dc currents in the output stages are not well defined
• Use the principle of optimizing the delay in cascaded inverters
HIGH SPEED COMPARATORS

A Study in Exponentials
The step response of an amplifier with a gain of Ao and a dominant pole at A is,
vout(t) = Ao[1 – exp(-At)] Vin
vout
Slow rising
AoVin
Fast rising
0 t
060810-04
The latch response to a step input of Vin is,

t
vout(t) = Vin expt  vout
 L
Fast rising
2.72Vin
Slow rising
0 t
tL 060810-05
A High-Speed Comparator Architecture

Cascade an amplifier with a latch to take advantage of the exponential characteristics of
the previous slide.
Preamplifier
+ + +
Vin Ao Vo1 Latch Vout
- - -
060810-06
In order to keep the bandwidth of the amplifier large, the gain will be small. To achieve
Preamplifier 1 Preamplifier 2 Preamplifier n
+ + + + + +
Vin Ao1/n Vo1 Ao1/n Vo2 Von-1 Ao1/n Von Latch Vout
- - - - - -
Gain = Ao 060810-08
Therefore, the question is how many stages of the amplifier and what is the gain of each
stage for optimum results?

Example 33-2 – Optimizing the Propagation Time Delay

A comparator consists of an amplifier cascaded with a latch as shown below. The
amplifier has a voltage gain of 10V/V and f-3dB = 100MHz and the latch has a time
constant of 1ns. The maximum and minimum voltage swings of the amplifier and latch
are VOH and VOL. When should the latch be enabled after the application of a step input to
the amplifier of 0.05(VOH-VOL) to get minimum overall propagation time delay? What is
the value of the minimum propagation time delay?
vin = 0.05(VOH-VOL) voa
Amplifier
Latch vout
Av(0)=10V/V
tL=1ns
t=0 f-3dB=100MHz vil
Comparator
070606-01
Enable
Solution
The solution is based on the figure shown.
Amplifier
We note that, VOH
voa(t) = 10[1-e--3dBt]0.05(VOH-VOL). Latch
x(VOH-VOL)
If we define the input voltage to the latch as,
t2
vil = x·(VOH-VOL) VOL t
t1 S01E3S1
then we can solve for t1 and t2 as follows:

x·(VOH-VOL) = 10[1-e--3dBt1]0.05(VOH-VOL) → x = 0.5[1-e--3dBt1]
This gives,
1  1 
t1 = ln 1-2x
-3dB  
From the propagation time delay of the latch we get,

VOH-VOL 1
t2 = L ln  2v  = L ln 2x
 il   
1 
1  1 dtp
 + L ln 
  
 tp = t1 + t2 = ln   → =  gives
-3dB 1-2x  2x dx
2L-3dB 
2x = = = 0.3859 (x = 0.1930)
2+2L-3dB 2+
10ns  1 
t1 = ln 1-0.3859 = 1.592ns·0.4875 = 0.7762 ns
2  
 1 

and t2 = 1ns ln 0.3859= 0.9522ns
 
 tp = t1 + t2 = 0.776 ns + 0.952 ns = 1.728 ns

Minimizing the Propagation Delay Time in Comparators

Facts:
• The input signal is equal to Vin(min) for worst case
• Amplifiers have a step response with a negative argument in the exponential
• Latches have a step response with a positive argument in the exponential
• If the amplifiers rise too quickly, they will be slew limited
Approach:
• Use a cascade of low-gain, wide-bandwidth amplifiers to take a small input signal and
amplify it without suffering slew limit
• Use a latch to take the amplified input and quickly reach 0.5(VOH-VOL)

Minimization of the Propagation Delay Time

Minimization of tp:
Q. If the preamplifer consists of n stages of gain A having a single-pole response, what is
the value of n and A that gives minimum propagation delay time?
A. n = 6 and A = 2.62 but this is a very broad minimum and n is usually 3 and A  6-7
to save area.
Preamplifier 1 Preamplifier 2 Preamplifier 3
+ + + + +
Vin Ao1/3 Vo1 Ao1/3 Vo2 Ao1/3 Vo3 Latch Vout
- - - - -
Gain = Ao 070509-06

Fully Differential, Three-Stage Amplifier and Latch Comparator

Circuit:
Comments:
• Autozero and reset phase followed by comparison phase
• In the autozero phase, switches labeled “Reset” and “FB” are closed.
• In the sample phase, switches labeled “Sample” and “ FB ” are closed.
• Can run as high as 200Msps

Preamplifier and Latch Circuits

VDD
Gain:
gm1 gm2 KN’(W1/L1) M3 M4
Av = - g = - g = -
m3 m4 Kp’(W3/L3) Q
FB Reset
Dominant Pole:
gm3 gm4 Q
FB
|pdominant| = C = C M1
M5 M6
M2
where C is the capacitance seen from the
output nodes to ground. Enable Latch
Preamplifier Latch
If (W1/L1)/(W3/L3) = 100 and the bias
VBias
current is 100µA, then A = -3.85 and the
Fig. 8.6-4
bandwidth is 15.9MHz if C = 0.5pF.
Comments:
• If a buffer is used to reduce the output capacitance, one must take into account the loss
of the buffer.
• The use of a preamplifier before the latch reduces the latch offset by the gain of the
preamplifier so that the offset is due to the preamplifier only.
An Improved Preamplifier
Circuit:
VDD
VBiasP VBiasP
M3 M4
vout- M5 M6 vout+
Reset
M10 M12
FB M11 FB
M7 M8
VBias
vin+ vin-
M1 M2
VBiasN
M9
Fig. 8.6-5
Gain:
gm1 KN’(W1/L1)I1 KN’(W1/L1) I5
Av = - g = - =- 1+I
m3 KP’(W3/L3)I3 KP’(W3/L3) 3
If I5 = 24I3, the gain is increased by a factor of 5
Improved Frequency Response of the Amplifier

If the ratio of transconductance W/L is much larger than the load W/L, the frequency
response will suffer. Using the technique of the previous slide, we can keep the ratio of
the W/Ls to a more reasonable value. The result is higher frequency response.
Amplifier of Example 27-3:
VDD
VPB1 VPB1
I5 I3 I4 I6
M5 M3 Vout M4 M6
M1 - + M2
+ I1 I2
Vin
-
VNB1 I7
M7
060711-01
Gain = 20dB
f-3dB = 551MHz

High-Speed CMOS Comparator

The comparator used in a 12-bit, 200 Msps ADC is shown below†. The comparator is
used in each of the 4-bit pipeline stages which requires 15 comparators.
The comparators consist of three stages including (a.) differential input pairs, (b.) a
cross-coupled latch, and (c.) an SR latch to hold the comparator output until the next
clock cycle.
VDD VDD
f1 f1
iout1
vout1 S
iout2
f1 R Q
vout2
iin1 Q
vin1 vin2 iin2
f2
Vref1 Vref2
VNB1
NMOS Input Pair Latch SR-Latch 070511-01
†T. Liechti, “Design of a High-Seed 12-bit Differential Pipelined A/D Converter,” Diploma Project, Feb. 2004, Microelectronic Systems
Laboratory, Swiss Federal Institute of Technology, Lausanne.
High Speed CMOS Comparator – Continued

Schematic of the fully differential comparator:
Clock waveforms:
Mean comparator power
dissipation is 140µW
under typical conditions

SUMMARY
• Comparators are limited in speed either by bandwidth or slew rate
• Increasing the magnitude of the poles improves the bandwidth limitations
• Increasing the current sinking/sourcing ability improves the slew rate limitation
• Most high speed comparators use a combination of preamplifier followed by a latch
- The preamplifier uses bandwidth to quickly build up the input
- The latch uses positive feedback to take the signal to its final state

Lecture 34 – Characterization of DACs and Current and Voltage Scaling DACs (7/10/15) Page 34-1
LECTURE 34 – CHARACTERIZATION OF DACS AND CURRENT

AND VOLTAGE SCALING DACS
Outline
• Introduction
• Static characterization of DACs
• Dynamic characterization of DACs
• Testing of DACs
• Current scaling DACs
• Voltage scaling DACs
• Summary
Pages 499-517

INTRODUCTION
Importance of Data Converters in Signal Processing

Digital-Analog Converters
Digital Signal Characteristics:
Processing
System • Can be asynchronous or
Microprocessors DIGITAL- synchronous
Compact disks ANALOG Filter Analog
Amplifier
Read only memory
CONVERTER Output • Primary active element is
Random access memory
Digital transmission the op amp
Disk outputs
Digital sensors • Conversion time can vary
from fast (one clock period,
Reference Fig. 10.1-01 T) to slow (2No. of bits*T)
Analog-Digital Converters
Characteristics:
Digital Signal
Processing • Can only be synchronous (the analog
ANALOG- System signal is sampled and held during
Analog Sample Microprocessors
and
DIGITAL Compact disks conversion)
Input CONVERTER Read only memory
Hold Random access memory
Digital transmission
• Primary active element is the
Disk outputs
Digital sensors
comparator
• Conversion time can vary from fast
060922-01 Reference (one clock period, T) to slow (2No. of
bits*T)
STATIC CHARACTERISTICS OF DIGITAL-ANALOG CONVERTERS

Block Diagram of a Digital-Analog Converter
Voltage VREF Scaling DVREF Output vOUT =

Reference Network Amplifier KDVREF
Binary Switches
b0 b1 b2 bN-1 Figure 10.1-3
b0 is the most significant bit (MSB)

The MSB is the bit that has the most (largest) influence on the analog output
bN-1 is the least significant bit (LSB)

The LSB is the bit that has the least (smallest) influence on the analog output

Input-Output Characteristics
Ideal input-output characteristics of a 3-bit DAC
1.000
0.875
Infinite Resolution
Analog Output Value Normalized to VREF Characteristic
0.750
0.625 1 LSB
0.500
Vertical Shifted
0.375 Characteristic
0.250
0.125
0.000
000 001 010 011 100 101 110 111
Digital Input Code Fig. 10.1-4

Definitions
• Resolution of the DAC is equal to the number of bits in the applied digital input word.
• The full scale (FS):
FS = Analog output when all bits are 1 - Analog output all bits are 0
VREF  1 
FS = (VREF - N ) - 0 = VREF1 - N 
2  2 
• Full scale range (FSR) is defined as
FSR = N∞lim (FS) = V
REF
• Quantization Noise is the inherent uncertainty in digitizing an analog value with a finite
resolution converter.
Quantization Noise
1LSB
0.5LSB
Digital
0LSB Input
000 001 010 011 100 101 110 111
Code
-0.5LSB Fig. 10.1-5

More Definitions
• Dynamic Range (DR) of a DAC is the ratio of the FSR to the smallest difference that
can be resolved (i.e. an LSB)
FSR FSR
DR = LSB change = N = 2N
(FSR/2 )
or in terms of decibels
DR(dB) = 6.02N (dB)
• Signal-to-noise ratio (SNR) for the DAC is the ratio of the full scale value to the rms
value of the quantization noise.
T
1  t  LSB FSR
2   2
rms(quantization noise) = T LSB T - 0.5 dt = 12 = 2N 12
0
vOUT(rms)
 SNR =
(FSR/ 12 2N)
• Maximum SNR (SNRmax) for a sinusoid is defined as
vOUTmax(rms) FSR/(2 2) 6 2N
SNRmax = = = 2
(FSR/ 12 2N) FSR/( 12 2N)
or in terms of decibels
 62N
SNRmax(dB) = 20log10 2  = 10 log10(6)+20 log10(2N)-20 log10(2)= 1.76 + 6.02N dB
 
Even More Definitions

• Effective number of bits (ENOB) can be defined from the above as
SNRActual - 1.76
ENOB = 6.02
where SNRActual is the actual SNR of the converter.
Comment:
The DR is the amplitude range necessary to resolve N bits regardless of the amplitude
of the output voltage.
However, when referenced to a given output analog signal amplitude, the DR required
must include 1.76 dB more to account for the presence of quantization noise.
Thus, for a 10-bit DAC, the DR is 60.2 dB and for a full-scale, rms output voltage, the
signal must be approximately 62 dB above whatever noise floor is present in the output
of the DAC.

Accuracy Requirements of the i-th Bit

• The output of the i-th bit of the converter is expressed as:
VREF 2n
The output of the i-th bit = 2i+1 2n = 2n-i-1 LSBs
 
• The uncertainty of each bit must be less than ±0.5 LSB (assuming all other bits are ideal.
Must use ±0.25 LSB if each bit has a worst case error.)
• The accuracy of the i-th bit is equal to the uncertainty divided by the output giving:
±0.5 LSB 1 100
Accuracy of the i-th bit = 2n-i-1 LSB = 2n-i = 2n-i %
Result: The highest accuracy requirement is always the MSB (i = 0).

The LSB bit only needs ±50% accuracy.
Example:
What is the accuracy requirement for each of the bits of a 10 bit converter?
Assuming all other bits are ideal, the accuracy requirement per bit is given below.
Bit Number 0 1 2 3 4 5 6 7 8 9
Accuracy % 0.098 0.195 0.391 0.781 1.563 3.125 6.25 12.5 25 50
(If all other bits are worst case, the numbers above must be divided by 2.)
Offset and Gain Errors

An offset error is a constant difference between the actual finite resolution
characteristic and the ideal finite resolution characteristic measured at any vertical jump.
A gain error is the difference between the slope of the actual finite resolution and the
ideal finite resolution characteristic measured at the right-most vertical jump.
1 1
Analog Output Value Normalized to VREF

Analog Output Value Normalized to VREF
Actual Gain
7/8 7/8
Characteristic Error
6/8 6/8 Actual
5/8 Characteristic
5/8
Offset
4/8 Error 4/8
Infinite Infinite
3/8 Resolution 3/8 Resolution
Characteristic Characteristic
2/8 2/8
Ideal 3-bit Ideal 3-bit
1/8 Resolution 1/8 Resolution
Characteristic Characteristic
0 0
000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
Digital Input Code Digital Input Code
Offset Error in a 3-bit DAC Gain Error in a 3-bit DAC
Fig. 10.1-6

Integral and Differential Nonlinearity

• Integral Nonlinearity (INL) is the maximum difference between the actual finite
resolution characteristic and the ideal finite resolution characteristic measured vertically
(% or LSB).
• Differential Nonlinearity (DNL) is a measure of the separation between adjacent levels
measured at each vertical jump (% or LSB).
Vcx - Vs Vcx 
DNL = Vcx – Vs =  V  Vs =  V -1 LSBs
 s   s 
where Vcx is the actual voltage change on a bit-to-bit basis and Vs is the ideal LSB
8
change of (VFSR/2N) 8 Infinite Resolution Characteristic
7
Example of a 3-bit DAC: 8
+1.5 LSB DNL
Analog Output Voltage
6
8
5 Nonmonotonicity
8
-1 LSB INL
4
8 +1.5 LSB INL A
3 -1.5 LSB DNL
8
2 Ideal 3-bit Characteristic
8
1
8 Actual 3-bit Characteristic
0
8 000 001 010 011 100 101 110 111
Example of INL and DNL of a Nonideal 4-Bit Dac

Find the ±INL and ±DNL for the 4-bit DAC shown.
15/16
14/16
13.16
12/16
Analog Output (Normalized to Full Scale)
11/16 -2 LSB DNL

Ideal 4-bit DAC -1.5 LSB
10/16
Characteristic INL
9/16
+1.5 LSB DNL
8/16
-2 LSB DNL
7/16
Actual 4-bit DAC
6/16 Characteristic
+1.5 LSB INL
5/16
4/16
3/16
2/16
1/16
0/16
b0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
b1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
b2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
b3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

DYNAMIC CHARACTERISTICS OF DIGITAL-ANALOG CONVERTERS

Dynamic characteristics include the influence of time.
Definitions
• Conversion speed is the time it takes for the DAC to provide an analog output when the
digital input word is changed.
Factor that influence the conversion speed:
Parasitic capacitors (would like all nodes to be low impedance)
Op amp gainbandwidth
Op amp slew rate
• Gain error of an op amp is the difference between the desired and actual output voltage
of the op amp (can have both a static and dynamic influence)
 Loop Gain 
Actual Gain = Ideal Gain x 1 + Loop Gain
 
Ideal Gain-Actual Gain 1

Gain error = =
Ideal Gain 1+Loop Gain

Example 34-1 – Influence of Op Amp Gain Error on DAC Performance

Assume that a DAC using an op amp in the inverting configuration with C 1 = C2 and
Avd(0) = 1000. Find the largest resolution of the DAC if VREF is 1V and assuming worst
case conditions.
Solution
C2
The loop gain of the inverting configuration is LG = C +C Avd(0) = 0.51000 = 500.
1 2
The gain error is therefore 1/501  0.002. The gain error should be less than the
quantization noise of ±0.5LSB which is expressed as
VREF VREF
Gain error x VREF = 501 ≈ 0.002VREF ≤ N+1
2
Therefore the largest value of N that satisfies this equation is N = 7.

Influence of the Op Amp Gainbandwidth

Single-pole response:
vout(t) = ACL[1 - e-Ht]vin(t)
where
ACL = closed-loop gain
 R1   C2 
H = GB   or GB  
R1+R2 C1+C2
To avoid errors in DACs (and ADCs), vout(t) must be within ±0.5LSB of the final value
by the end of the conversion time.
Multiple-pole response:
Typically the response is underdamped like the following (see Appendix D of text).

Example 34-2 – Influence of GB and Settling Time on DAC Performance

Assume that a DAC uses a switched capacitor noninverting amplifier with C1 = C2
using an op amp with a dominant pole and GB = 1MHz. Find the conversion time of an
8-bit DAC if VREF is 1V.
Solution
From the results in Appendix E.2 of the text, we know that
 C2 
H =   GB = (2)(0.5)(106) = 3.141x106
C +C
 1 2
and ACL = 1. Assume that the ideal output is equal to VREF. Therefore the value of the
output voltage which is 0.5LSB of VREF is
1
1 - N+1 = 1 - e-H T
2
or
2N+1 = eH T
Solving for T gives
N+1 N+1  9 
T =    ln(2) = 0.693    = 
    
 0.693 = 1.986µs
 H   H   3.141 

TESTING OF DACs
Input-Output Test
Test setup:
ADC
Digital N-bit Vout
ADC with Output
Digital Digital
Word DAC more resolution
Subtractor Error
Input under than DAC
(N+2 bits) Output
test (N+2 bits)
(N+2 bits) (N+2 bits)
Fig. 10.1-9
Comments:
Sweep the digital input word from 000...0 to 111...1.
The ADC should have more resolution by at least 2 bits and be more accurate than the
errors of the DAC
INL will show up in the output as the presence of 1’s in any bit.
If there is a 1 in the Nth bit, the INL is greater than ±0.5LSB
DNL will show up as a change between each successive digital error output.
The bits which are greater than N in the digital error output can be used to resolve the
errors to less than ±0.5LSB
Spectral Test
Test setup:
Comments:
Digital input pattern is selected to
have a fundamental frequency which
has a magnitude of at least 6N dB
above its harmonics.
Length of the digital sequence
determines the spectral purity of the
fundamental frequency.
All nonlinearities of the DAC (i.e. INL and DNL) will cause harmonics of the
fundamental frequency
The THD can be used to determine the SNR dB range between the magnitude of the
fundamental and the THD. This SNR should be at least 6N dB to have an INL of less
than ±0.5LSB for an ENOB of N-bits.
Note that the noise contribution of VREF must be less than the noise floor due to
nonlinearities.
If the period of the digital pattern is increased, the frequency dependence of INL can
be measured.
CURRENT SCALING DIGITAL-ANALOG CONVERTERS

Classification of Digital-Analog Converters
Digital-Analog Converters
Serial Parallel
Charge Current Voltage Charge
Voltage and Charge
Slow Fast Fig. 10.2-1

General Current Scaling DACs
The output voltage can be expressed as

VOUT = -RF(I0 + I1 + I2 + ··· + IN-1)
where the currents I0, I1, I2, ... are binary weighted currents.

Binary-Weighted Resistor DAC

Circuit:
Comments:
1.) RF can be used to scale the gain of the DAC. If RF = KR/2, then
-KRb0 b1 b2 bN-1 
vOUT=-RFIO = 2  R + 2R + 4R +···+ 2N-1RVREF
 
b0 b1 b2 bN-1
 vOUT=-K 2 + 4 + 8 +···+ 2N VREF

 
where bi is 1 if switch Si is connected to VREF or 0 if switch Si is connected to ground.
RMSB R 1
2.) Component spread value = R = 2N-1R = 2N-1
LSB
3.) Attributes:
Insensitive to parasitics  fast Large component spread value

Trimming required for large values of N Nonmonotonic

R-2R Ladder Implementation of the Binary Weighted Resistor DAC

Use of the R-2R concept to
avoid large element spreads:
How does the R-2R ladder work? 8I 4I 2I I

“The resistance seen to the right of any of VREF
the vertical 2R resistors is 2R.” R R 2R
4I 2I I
Attributes: 2R 2R 2R
Fig. 10.2-4(2R-R)
• Not sensitive to parasitics
(currents through the resistors never change as Si is varied)
• Small element spread. Resistors made from same unit (2R consist of two in series or R
consists of two in parallel)
• Not monotonic
Current Scaling Using Binary Weighted MOSFET Current Sinks

Circuit:
Operation:
vOUT = R2(bN-1·I + bN-2·2I + bN-3·4I + ··· + b0·2N-1·I)
VREF b0 b1 b2 bN-3 bN-2 bN-1
If I = IREF = N , then vOUT =  2 + 4 + 8 + ··· + N-2 + N-1 + N VREF
2 R2  2 2 2 
Attributes:
Fast (no floating nodes) and not monotonic
Accuracy of MSB greater than LSBs
High-Speed Current DACs

Current scaling DAC using current switches:
VDD
RL RL
+
vOUT
-
b0 b0 b1 b1 b2 b2 bN-1 bN-1
I I I I
2 4 8 2N
060926-01
b0 b1 b2 bN-1
vOUT = IRL 2 + 4 + 8 + ··· + + N 
 2 
where
+1 if the bit is 1
bi = 
 -1 if the bit is 0
A single-ended DAC can be obtained by replacing the left RL by a short.

High-Speed, High-Accuracy Current Scaling DACs

The accuracy is increased by using the same value of current for each switch as shown.
VDD
RL RL
+
vOUT
-
d0 d0 d1 d1 d2 d2 d3 d3 d 4 d4 d2N d2N
I I I I I I
2N 2N 2N 2N 2N 2N
d0 d1 d2 d3 d4 d2N
N to 2N Encoder
b0 b1 b2 bN 060926-02
For a 4 bit DAC, there would be 16 current switches.

The MSB bit would switch 8 of the current switches to one side.
The next-MSB bit would switch 4 of the current switches to one side.
Etc.
Increasing the Accuracy of the Current Switching DAC

The accuracy of the previous DAC can be increased by using dynamic element matching
techniques. This is illustrated below where a butterfly switching element allows the
switch control bits, di, to be “randomly” connected to any of the current switches.
VDD
RL RL
+
vOUT
-
q0 q0 q1 q1 q2 q2 q3 q3 q 4 q4 q2N q2N
I I I I I I
2N 2N 2N 2N 2N 2N
q0 q1 q2 q3 q4 q2N
Butterfly Randomizer - Any di can be connected to any qi

according to the dynamic element matching algorithm selected.
d0 d1 d2 d3 d4 d2N
N to 2N Encoder
b0 b1 b2 bN 060926-03

VOLTAGE SCALING DIGITAL-ANALOG CONVERTERS

General Voltage Scaling Digital Analog Converter
Digital Input Word
V1
V2
Voltage
VREF V3 Decoder
Scaling vOUT
Logic
Network
V2N
Fig. 10.2-6
Operation:
Creates all possible values of the analog output then uses a decoding network to
determine which voltage to select based on the digital input word.

3-Bit Voltage Scaling Digital-Analog Converter

VREF VREF
The voltage at any tap can be expressed as: vOUT = 8 (n − 0.5) = 16 (2n − 1)
Attributes: VREF Input = 101
• Guaranteed R/2 b2 b2 b1 b1 b0 b0
VREF
monotonic 8
7VREF
R
• Compatible with 7
8
6VREF
CMOS technology 11 V R 8
16 REF 6 5V REF
• Large area if N is R 8
vOUT
5 4V REF
large R 8
3VREF
• Sensitive to 4 vOUT
8
R 2VREF
parasitics 3 8
R V REF
• Requires a buffer 2 8
• Large current can R
1
0
000 001 010 011 100 101 110 111
flow through the R/2
Digital Input Code
resistor string.
(a.) (b.)
Figure 10.2-7 - (a.) Implementation of a 3-bit voltage scaling DAC. (b.) Input-output
characteristics of Fig. 10.2-7(a.)

Alternate Realization of the 3-Bit Voltage Scaling DAC

VREF
R/2 b2 b1 b0
8
R
7
R 3-to-8 Decoder
6
R
5
R
4
R
3
R vOUT
2
R
1
R/2
Fig. 10.2-8

INL and DNL of the Voltage Scaling DAC

Find an expression for the INL and DNL of the voltage scaling DAC using a worst-case
approach. For an n-bit DAC, assume there are 2n resistors between VREF and ground and
that the resistors are numbered from 1 to 2n beginning with the resistor connected to
VREF V
REF and ending with the resistor connected to ground.
R1
Integral Nonlinearity Differential Nonlinearity
1
R2
The voltage at the i-th resistor from the top is, The worst case DNL is
2 (2n-i)R DNL = vstep(act) - vstep(ideal)
v i = V
R3 (2n-i)R + iR REF Substituting the actual and
3
where there are i resistors above vi and 2n-i below. ideal steps gives,
i-2
Ri-1 For worst case, assume that i = 2n-1 (midpoint). (R±R)VREF R VREF
= - 2 nR
i-1 Define Rmax = R + R and Rmin = R - R. 2 n R
Ri
The worst case INL is R±R R VREF
i =  R - R 2n
Ri+1 INL = v2n-1(actual) - v2n-1(ideal)  
i+1 Therefore, ±R VREF
=
2n-2 Vi 2 (R+R)VREF
n-1 VREF R R 2n
R2n-1 INL = n-1 - 2 = 2R VREF Therefore,
2n-1
2 (R+  R) + 2n-1(R-R)
R2n 2n R R VREF R ± R

2n INL= n  2R  VREF=2 n-1   =2 n-1   LSBs DNL = LSBs
Fig. 10.2-085 2     2 
R n  
R R
Example 34-3 – Accuracy Requirements of a Voltage-Scaling DAC

If the resistor string of a voltage scaling digital-analog converter consists of 2n
polysilicon resistors having a relative accuracy of ±1%, what is the largest number of bits
that can be resolved and keep the worst case INL within ±0.5 LSB? For this number of
bits, what is the worst case DNL?
Solution
From the previous page, we can write that
R  1 
  1
2n-1   = 2 100 ≤ 2
n-1
R  
This inequality can be simplified

2n ≤ 100
which has a solution of n = 6.
The value of the DNL for n = 6 is found from the previous page as
±1
DNL = LSBs = ±0.01LSBs
100
(This is the reason the resistor string is monotonic.)

SUMMARY
• DACs scale a voltage reference as an analog output according to a digital word input
• Quantization noise is an inherent ±0.5 LSB uncertainty in digitizing an analog value with
a finite resolution converter
• The MSB requires the greatest accuracy with the LSB requiring the least accuracy
(% or LSB)
measured at each vertical jump (% or LSB)
• The limits to DAC speed include the parasitic capacitors, the op amp gain-bandwidth,
and the op amp slew rate
• Current scaling DACs scale the reference voltage into binary-weighted currents that are
summed into to a resistor to obtain the analog output voltage.
• Current scaling DACs are generally fast but have large element spreads and are not
monotonic
• The voltage scaling DAC creates all possible analog voltages and selects which one
corresponds to the digital input. The voltage scaling DAC is a monotonic converter.

Lecture 35 – Parallel DACs, Improved Resolution DACs and Serial DACs (6/26/14) Page 35-1
LECTURE 35 – PARALLEL DACS, IMPROVED DAC

RESOLUTION AND SERIAL DACS
Outline
• Charge scaling DACs
• Extending the resolution of parallel DACs
• Serial DACs
• Summary
Pages 517-539

CHARGE SCALING DIGITAL-ANALOG CONVERTERS

General Charge Scaling Digital-Analog Converter
Digital Input Word
Charge
VREF Scaling vOUT
Network
Fig. 10.2-9
General principle is to capacitively attenuate the reference C1

voltage. Capacitive attenuation is simply: +
VREF C2 Vout
Calculate as if the capacitors were resistors. For example, -

Fig. 10.2-9b
1
C2 C1
Vout = 1 1 VREF = C1 + C2 VREF
+
C1 C2

Binary-Weighted, Charge Scaling DAC

Circuit:
Operation:
1.) All switches connected to
ground during 1.
2.) Switch Si closes to VREF if bi = 1 or to ground if bi = 0.
Equating the charge in the capacitors gives,
 b1C b2C bN-1C

VREFCeq = VREF b0C + 2 + 22 + ... + N−1  = Ctot vOUT = 2C vOUT
 2 
which gives
vOUT = [b02-1 + b12-2 + b22-3 + ... + bN-12-N]VREF
Equivalent circuit of the binary-weighted, charge scaling DAC is:
Attributes: Ceq.
• Accurate
+
• Sensitive to parasitics
VREF 2C - Ceq. vOUT
• Not monotonic
• Charge feedthrough occurs at turn on of switches -
Fig. 10.2-11

Integral Nonlinearity of the Charge Scaling DAC

Again, we use a worst case approach. Assume an n-bit charge scaling DAC with the
MSB capacitor of C and the LSB capacitor of C/2n-1 and the capacitors have a tolerance
of C/C.
The ideal output when the i-th capacitor only is connected to VREF is
C/2i-1 VREF 2n 2n
vOUT (ideal) = 2C VREF = 2i 2n = 2i LSBs
 
The maximum and minimum capacitance is Cmax = C + C and Cmin = C - C.

Therefore, the actual worst case output for the i-th capacitor is
(C±C)/2i-1 VREF C·VREF 2n 2nC
vOUT(actual) = VREF = 2i ± 2iC = 2i ± 2iC LSBs
2C
Now, the INL for the i-th bit is given as
±2nC 2n-iC
INL(i) = vOUT(actual) - vOUT(ideal) = 2iC = C LSBs
Typically, the worst case value of i occurs for i = 1. Therefore, the worst case INL is
C
INL = ± 2n-1 C LSBs
Differential Nonlinearity of the Charge Scaling DAC

The worst case DNL for the binary weighted capacitor array is found when the MSB
changes. The output voltage of the binary weighted capacitor array can be written as
Ceq.
vOUT = (2C-C ) + C VREF
eq. eq.
where Ceq are capacitors whose bits are 1 and (2C - Ceq) are capacitors whose bits are 0.
The worst case DNL can be expressed as
vstep(worst case) vOUT(1000....) - vOUT(0111....) 
DNL = - 1 =  - 1  LSBs
vstep(ideal)  1 LSB 
The worst case choice for the capacitors is to choose C1 larger by C and the remaining
capacitors smaller by C giving,
1 1 1 1
C1=C+C, C2 = 2(C-C),...,Cn-1= n-2(C-C), Cn= n-1(C-C), and Cterm= n-1(C-C)
2 2 2
n
Note that Ci + Cterm = C2+ C3+···+ Cn-1+ Cn+ Cterm = C-C
i=2

Differential Nonlinearity of the Charge Scaling DAC - Continued

 C+C  C+C 
 vOUT(1000...) =  VREF =  V 
(C+C)+(C-C)   2C REF
C+C  2n C+C
=  2C VREF n = 2n 2C  LSBs
 2  
and
1
 (C-C) -Cterm  (C- C) - (C-C)
2n-1
vOUT(0111...) =  VREF = VREF
 (C+ C)+(C- C)  (C+  C)+(C-  C)
C-C 2  2nC-C 2  C-C  2 
=  2C 1 - 2nVREF = n 2C 1 - 2nVREF = 2n  2C 1 - 2n LSBs
   2      
vOUT(1000...) - vOUT(0111...)  C+C C-C  2  C

 -1  LSBs = 2n -2n 1- n-1 = (2n-1)
 1 LSB   2C   2C  2  C LSBs
C
Therefore, DNL = (2n - 1) C LSBs

Example 35-1 - DNL and INL of a Binary Weighted Capacitor Array DAC
If the tolerance of the capacitors in an 8-bit, binary weighted, charge scaling DAC are
±0.5%, find the worst case INL and DNL.
Solution
For the worst case INL, we get from above that
INL = (27)(±0.005) = ±0.64 LSBs
For the worst case DNL, we can write that
DNL = (28-1)(±0.005) = ±1.275 LSBs

Example 35-2 - Influence of Capacitor Ratio Accuracy on Number of Bits

Use the data shown to estimate the number of bits possible for a charge scaling DAC
assuming a worst case approach for INL and that the worst conditions occur at the
midscale (1 MSB).
Solution
Assuming an INL of ±0.5 LSB, we can write that
C 1 C 1
INL = ±2N-1 C ≤ ± 2 →  C  = N
  2
Let us assume a unit capacitor of 50 µm by 50 µm
and a relative accuracy of approximately ±0.1%.
Solving for N in the above equation gives
approximately 10 bits. However, the ±0.1% figure
corresponds to ratios of 16:1 or 4 bits. In order to get
a solution, we estimate the relative accuracy of
capacitor ratios as
C
C ≈ 0.001 + 0.0001N
Using this approximate relationship, a 9-bit
digital-analog converter should be realizable.

Binary Weighted, Charge Amplifier DAC
Attributes:
• No floating nodes which implies insensitive to parasitics and fast
• No terminating capacitor required
• With the above configuration, charge feedthrough will be Verror  -(COL/2CN)V
• Can totally eliminate parasitics with parasitic-insensitive switched capacitor circuitry
but not the charge feedthrough

EXTENDING THE RESOLUTION OF PARALLEL DIGITAL-ANALOG

CONVERTERS
Background
Technique:
N
Divide the total resolution N into k smaller sub-DACs each with a resolution of k .
Result:
Smaller total area.
More resolution because of reduced largest to smallest component spread.
Approaches:
• Combination of similarly scaled subDACs
Divider approach (scale the analog output of the subDACs)
Subranging approach (scale the reference voltage of the subDACs)
• Combination of differently scaled subDACs

COMBINATION OF SIMILARLY SCALED SUBDACs

Analog Scaling - Divider Approach VREF
Example of combining a m-bit
m-bit
and k-bit subDAC to form a m-MSB + vOUT
MSB S
bits +
m+k-bit DAC. DAC
VREF
k-bit
k-LSB LSB ¸ 2m
bits DAC
Fig. 10.3-1
b0 b1 bm-1  1 bm bm+1 bm+k-1

vOUT =  2 + 4 + ··· + m VREF +  m 2 + 4 + ··· + VREF
 2   
2  2 k 
b0 b1 bm-1 bm bm+1 bm+k-1
vOUT = 2 + 4 + ··· + m + m+1 + m+2 + ··· + m+k VREF

 2 2 2 2 

Example 35-3 - Illustration of the Influence of the Scaling Factor

Assume that m = 2 and k = 2 in Fig. 10.3-1 and find the transfer characteristic of
this DAC if the scaling factor for the LSB DAC is 3/8 instead of 1/4. Assume that VREF =
1V. What is the ±INL and ±DNL for this DAC? Is this DAC monotonic or not?
Solution
The ideal DAC output is given as
b0 b1 1b2 b3 b0 b1 b2 b3
vOUT = 2 + 4 + 4 2 + 4  = 2 + 4 + 8 + 16 .
 
The actual DAC output can be written as
b0 b1 3b2 3b3 16b0 8b1 6b2 3b3
vOUT(act.) = + + + = + + +
2 4 16 32 32 32 32 32
The results are tabulated in the following table for this example.


Ideal and Actual Analog Output for the DAC in Ex. 35-3,
Input vOUT(act.) vOUT vOUT(act.) Change in
The table contains all the
Digital - vOUT vOUT(act) -
Word information we are seeking.
2/32
0000 0/32 0/32 0/32 -
An LSB for this example is
0001 3/32 2/32 1/32 1/32 1/16 or 2/32. The fourth
0010 6/32 4/32 2/32 1/32 column gives the +INL as
0011 9/32 6/32 3/32 1/32 1.5LSB and the -INL as 0LSB.
0100 8/32 8/32 0/32 -3/32 The fifth column gives the
0101 11/32 10/32 1/32 1/32 +DNL as 0.5LSB and the -DNL
0110 14/32 12/32 2/32 1/32 as -1.5LSB. Because the -DNL
0111 17/32 14/32 3/32 1/32 is greater than -1LSB, this
1000 16/32 16/32 0/32 -3/32 DAC is not monotonic.
1001 19/32 18/32 1/32 1/32
1010 22/32 20/32 2/32 1/32
1011 25/32 22/32 3/32 1/32
1100 24/32 24/32 0/32 -3/32
1101 27/32 26/32 1/32 1/32
1110 30/32 28/32 2/32 1/32
1111 33/32 30/32 3/32 1/32

Reference Scaling - Subranging Approach

Example of combining a m-bit and k-bit subDAC to form a m+k-bit DAC.
VREF
m-bit
m-MSB + vOUT
MSB S
bits +
DAC
VREF/2m
k-bit
k-LSB LSB
bits DAC
Fig. 10.3-2
b0 b1 bm-1 bm bm+1 bm+k-1VREF 

vOUT =  2 + 4 + ··· + m VREF +  2 + 4 + ··· +  
 2   2k  2m 
b0 b1 bm-1 bm bm+1 bm+k-1
vOUT =  + + ··· + m + m+1 + m+2 + ··· + m+k VREF
2 4 2 2 2 2 
Accuracy considerations of this method are similar to the analog scaling approach.
Advantage: There are no dynamic limitations associated with the scaling factor of 1/2m.

Current Scaling Dac Using Two SubDACs

Implementation:
b0 b1 b2 b3 1 b4 b5 b6 b7

vOUT = RFI  + + +  +  + + + 
 2 4 8 16  16  2 4 8 16

Charge Scaling DAC Using Two SubDACs

Implementation:
Design of the scaling capacitor, Cs:

The series combination of Cs and the LSB array must terminate the MSB array or
equal C/8. Therefore, we can write
C 1 1 8 1 16 1 15
= or = - = - =
8 1 1 Cs C 2C 2C 2C 2C
Cs + 2C

Equivalent Circuit of the Charge Scaling Dac Using Two SubDACs
Simplified equivalent circuit:
where the Thevenin equivalent voltage of

the MSB array is
 1 
 
 1/2 
 
 1/4 
 
 1/8 
 

 16 b0 b1 b2 b3 
V1 = 15/8 b0 + 15/8 b1 + 15/8 b2 + 15/8 b3VREF = 15  2 + 4 + 8 + 16 VREF
          
and the Thevenin equivalent voltage of the LSB array is
1/1
 
1/2
 
1/4
 
1/8
 


b4 b5 b6 b7 
V2 =  2  b4 +  2  b5 +  2  b6 +  2  b7VREF =  2 + 4 + 8 + 16 VREF
          
Combining the elements of the simplified equivalent circuit above gives
 1 +15   8 
vOUT=
 2 2 
V1+
 15  V2= 
 15+15·15 
 

 16 

V1+ V2=
1 +15 + 8  1 +15 + 8  15+15·15+16 15+15·15+16
2 2 15 2 2 15
15 1 7 bV
V 1 + V 2  b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7  i REF
16 vOUT =  2 + 4 + 8 + 16 + 32 + 64 + 128 + 256VREF = 
16
  2i+1
CMOS Analog Circuit Design i=0 © P.E. Allen - 2016

Charge Amplifier DAC Using Two Binary Weighted Charge Amplifier SubDACs
Implementation:
Attributes:
• MSB subDAC is not dependent upon the accuracy of the scaling factor for the LSB
subDAC.
• Insensitive to parasitics, fast
• Limited to op amp dynamics (GB)
• No ICMR problems with the op amp

COMBINATION OF DIFFERENTLY SCALED SUBDACs

Voltage Scaling MSB SubDAC And Charge Scaling LSB SubDAC
Implementation: m-MSB bits v OUT
m-bit, MSB voltage SF
scaling subDAC Ck = Ck-1 = C2 C1
C
2k-1C 2k-2C =2C =C
m-to-2m Decoder A
Bus A
R1 R2 R 3 R2m-2 R2m-1 R2m Sk,A Sk-1,A S2A S1A
Sk,B Sk-1,B S2B S1B

VREF
m-to-2m Decoder B
Bus B k-bit, LSB charge
SF scaling subDAC
Operation: m-MSB bits Fig. 10.3-7
1.) Switches SF and S1B through Sk,B discharge all capacitors.

2.) Decoders A and B connect Bus A and Bus B to the top and bottom, respectively, of
the appropriate resistor as determined by the m-bits.
3.) The charge scaling subDAC divides the voltage across this resistor by capacitive
division determined by the k-bits.
Attributes:
• MSB’s are monotonic but the accuracy is poor
• Accuracy of LSBs is good
Voltage Scaling MSB SubDAC And Charge Scaling LSB SubDAC - Continued
Equivalent circuit of the voltage scaling (MSB) and charge scaling (LSB) DAC:
Ck = Ck-1 = C2 C1 Bus A
C
Bus A 2k-1C 2k-2C =2C =C Ceq.
vOUT 2-mVREF 2kC - Ceq. v'OUT
Sk,A Sk-1,A S2A S1A Bus B
2-mVREF vOUT
Sk,B Sk,B S2B S1B
V'REF
Bus B
V'REF
where, Fig. 10.3-8
b0 b1 bm-2 bm-1

V’REF = VREF 21 + 22 + ··· + 2m-1 + 2m 

 
and
VREF bm bm+1 bm+k bm+k-1  bm bm+1 bm+k bm+k-1
v’OUT = 2m 2 + 22 + ··· + 2k-1 + 2k = VREF 2m+1 + 2m+2 + ··· + 2m+k-1 + 2m+k 
  
   
Adding V’REF and v’OUT gives the DAC output voltage as
b0 b1 bm-2 bm-1 bm bm+1 bm+k bm+k-1
vOUT = V’REF + v’OUT = VREF 1+ 2+···+ m-1+ m + m+1+ m+2+···+ m+k-1+ m+k 
2 2 2 2 2 2 2 2 
which is equivalent to an m+k bit DAC.

Charge Scaling MSB SubDAC and Voltage Scaling LSB SubDAC
C1 = C2 = Cm-1 Cm Cm R1
2m C 2m-1C =21C =C =C
R2
vOUT
S1,A S2,A Sm-2A Sm-1A k- R3
VREF vk VREF
to-
S1,B S2,B Sm-2B Sm-1B
2k
Decoder R2k-2
m-bit, MSB charge scaling subDAC
R2k-1
k-bit,
R2k LSB
voltage
Fig. 10.3-9A
scaling
k-LSB bits subDAC
b0 b1 bm-2 bm-1 vk bm bm+1 bm+k bm+k-1
vOUT = 21+22+···+2m-1+ 2m VREF+2m where vk = 21 + 22 +···+ 2k-1 + 2k VREF
  
   
b0 b1 bm-2 bm-1 bm bm+1 bm+k bm+k-1
 vOUT =21 + 22 + ··· + 2m-1 + 2m + 2m+1 + 2m+2 + ··· + 2m+k-1 + 2m+k  VREF
 
Attributes:
• MSBs have good accuracy
• LSBs are monotonic, have poor accuracy - require trimming for good accuracy

Tradeoffs in SubDAC Selection to Enhance Linearity Performance

Assume a m-bit MSB subDAC and a k-bit LSB subDAC.
MSB Voltage Scaling SubDAC and LSB Charge Scaling SubDAC (n = m+k)
INL and DNL of the m-bit MSB voltage-scaling subDAC:
 2n  R R ± R  2n  ± R
 
INL(R) = 2m-1 m = 2n-1 LSBs and DNL(R) = = 2k LSBs
2  R R R 2m R
INL and DNL of the k-bit LSB charge-scaling subDAC:
C C
INL(C) = 2 C LSBs
k-1 and DNL(C) = (2 -1) C LSBs
k
Combining these relationships:

 n-1 R C 

INL = INL(R) + INL(C) = 2 + 2k-1
 R C  LSBs

 k R C 
and DNL = DNL(R) + DNL(C) = 2 R + (2k-1) C  LSBs 
 
MSB Charge Scaling SubDAC and LSB Voltage Scaling SubDAC

 k-1 R C 

INL = INL(R) + INL(C) = 2 n-1
 R +2 C  LSBs
R C  

and DNL = DNL(R) + DNL(C) = R + (2n-1) C  LSBs 
 
Example 35-4 – DAC with Voltage Scaling for MBSs and Charge Scaling for LSBs
Consider a 12-bit DAC that uses voltage scaling for the MSBs charge scaling for the
LSBs. To minimize the capacitor element spread and the number of resistors, choose m =
5 and k = 7. Find the tolerances necessary for the resistors and capacitors to give an INL
and DNL equal to or less than 2 LSB and 1 LSB, respectively.
Solution
Substituting n = 12 and k = 7 into the previous equations gives
11
R 6 C 7
R 7
C
2=2 R +2 C and 1 = 2 R + (2 -1) C
Solving these two equations simultaneously gives
C 24-2 C
C = 211 - 26 - 24 = 0.0071  C = 0.71%
R 28 - 26 -2 R
= 18 13 11 = 0.0008  = 0.075%
R 2 -2 -2 R
We see that the capacitor tolerance will be easy to meet but that the resistor tolerance will
require resistor trimming to meet the 0.075% requirement. Because of the 2n-1
multiplying R/R in the relationship, we are stuck with approximately 0.075%.
Therefore, choose m = 2 (which makes the 0.075% easier to achieve) and let k = 10
which gives R/R = 0.083% and C/C = 0.12%.
Example 35-5 - DAC with Charge Scaling for MBSs and Voltage Scaling for LSBs
Consider a 12-bit DAC that uses charge scaling for the MSBs voltage scaling for the
LSBs. To minimize the capacitor element spread and the number of resistors, choose m =
7 and k = 5. Find the tolerances necessary for the resistors and capacitors to give an INL
and DNL equal to or less than 2 LSB and 1 LSB, respectively.
Solution
Substituting the values of this example into the relationships developed on a previous
slide, we get
R C R C
2 = 24 R + 211 C and 1 = R + (212-1) C
Solving these two equations simultaneously gives
C 24-2 C R 3 R
= = 0.000221  = 0.0221% and  = 0.0968 
C 216-211-24 C R 25-1 R = 9.68%
For this example, the resistor tolerance is easy to meet but the capacitor tolerance will
be difficult. To achieve accurate capacitor tolerances, we should decrease the value of m
and increase the value of k to achieve a smaller capacitor value spread and thereby
enhance the tolerance of the capacitors. If we choose m = 4 and k = 8, the capacitor
tolerance is 0.049% and the resistor tolerance becomes 0.79% which is still reasonable.
The largest to smallest capacitor ratio is 8 rather than 64 which helps to meet the
capacitor tolerance requirements.

Based on the previous slide, we need to minimize the number of MSB bits as capacitors
to enhance the accuracy. This puts pressure on the resistors. A good compromise is:
MSB subdac: 2 bits capacitive scaling.
LSB subdac: A 10 bit, R-2R ladder.
With this design, the tolerances become,
R C R C
2 = 29 + 211 and 1= + (212-1)
R C R C
giving,
C 1-2-8 C R C R
= =0.000243  =0.0243% and −(2 12-1) =0.00388 
C 212-1-2-3 C R C R =0.388%
Possible realization:

SERIAL DIGITAL-ANALOG CONVERTERS

Serial DACs
• Typically require one clock pulse to convert one bit
• Types considered here are:
Charge-redistribution
Algorithmic
Charge Redistribution DAC
Implementation:
S2 S1
VREF S3 C1 C2 S4 vC2
Operation: Fig. 10.4-1
Switch S1 is the redistribution switch that parallels C1 and C2 sharing their charge
Switch S2 precharges C1 to VREF if the ith bit, bi, is a 1
Switch S3 discharges C1 to zero if the ith bit, bi, is a 0
Switch S4 is used at the beginning of the conversion process to initially discharge C2
Conversion always begins with the LSB bit and goes to the MSB bit.
Example 35-6 - Operation of the Serial, Charge Redistribution DAC

Assume that C1 = C2 and that 1 1
the digital word to be converted 3/4 13/16 3/4 13/16
vC2/VREF
vC1/VREF
is given as b0 = 1, b1 = 1, b2 = 0, 1/2 1/2
and b3 = 1. Follow through the 1/4 1/4
sequence of events that result in 0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
the conversion of this digital t/T t/T Fig. 10.4-2
input word.
Solution
1.) S4 closes setting vC2 = 0.
2.) b3 = 1, closes switch S2 causing vC1 = VREF.
3.) Switch S1 is closed causing vC1 = vC2 = 0.5VREF.
4.) b2 = 0, closes switch S3, causing vC1 = 0V.
5.) S1 closes, the voltage across both C1 and C2 is 0.25VREF.
7.) S1 closes, the voltage across both C1 and C2 is (1+0.25)/2VREF = 0.625VREF.
9.) S1 closes, the voltage across both C1 and C2 is (0.625+1)/2VREF = 0.8125VREF =
(13/16)VREF.
Pipeline DAC
The pipeline DAC is simply an extension of the sub-DACs concept to the limit where the
bits converted by each sub-DAC is 1.
Implementation:
Vout(z) = [b0z-1 + 2-1b1z-2 + ··· + 2-(N-2)bN-2z-(N-1) + bN-1z-N]VREF

where bi is either ±1 if the ith bit is high or low. The z-1 blocks represent a delay of one
clock period between the 1-bit sub-DACs.
Attributes:
• Takes N+1 clock cycles to convert the digital input to an analog output
• However, a new analog output is converted every clock after the initial N+1 clocks

Algorithmic (Iterative) DAC

Implementation:
Closed form of the previous series expression is,

biz-1VREF
Vout(z) = 1 - 0.5z-1
Operation:
Switch A is closed when the ith bit is 1 and switch B is closed when the ith bit is 0.
Start with the LSB and work to the MSB.

Example 35-7 - Digital-Analog Conversion Using the Algorithmic Method

Assume that the digital word to be converted is 11001 in the order of MSB to LSB.
Find the converted output voltage and sketch a plot of vOUT/VREF as a function of t/T,
vOUT/VREF
where T is the period for one conversion.
2.0
Solution
1.) The conversion starts by zeroing the 19/16
1.0
output (not shown on Fig. 10.4-4).
2.) The LSB = 1, switch A is closed and VREF 3/8
is summed with zero to give an output of 0 t/T
0 1 2 3 4 5
+VREF. -1/2
3.) The next LSB = 0, switch B is closed and -1.0

-5/4
vOUT = -VREF+0.5VREF = -0.5VREF.
Fig. 10.4-5
4.) The next LSB = 0, switch B is closed and -2.0
vOUT = -VREF+0.5(-0.5VREF) = -
1.25VREF.
5.) The next LSB = 1, switch A is closed and vOUT = VREF+0.5(-1.25VREF) = 0.375VREF.

6.) The MSB = 1, switch A is closed and vOUT = VREF + 0.5(0.375VREF) = 1.1875VREF =
(19/16)VREF. (Note that because the actual VREF of this example if ±VREF or 2VREF, the
analog value of the digital word 11001 is 19/32 times 2VREF or (19/16)VREF.)

SUMMARY
• Voltage scaling DACs are monotonic, use equal resistors but are sensitive to capacitve
parasitics
• Charge scaling DACs are fast with good accuracy but have large element spread and are
nonmonotonic
• DAC resolution can be increased by combining several subDACs with smaller
resolution
• Methods of combining include scaling the output or the reference of the non-MSB
subDACs
• SubDACs can use similar or different scaling methods
• Tradeoffs in the number of bits per subDAC and the type of subDAC allow
minimization of the INL and DNL
• Serial, charge redistribution DAC is simple and requires minimum area but is slow and
requires complex external circuitry
• Pipeline DAC has a latency of N+1 clock cycles but gives an analog output for each
clock
• Serial, algorithmic DAC is simple and requires minimum area but is slow and requires
complex external circuitry
Lecture 36 – Characterization of ADCs and Sample and Hold Circuits (6/26/14) Page 36-1
LECTURE 36 – CHARACTERIZATION OF ADCS AND SAMPLE

AND HOLD CIRCUITS
Outline
• Introduction to ADCs
• Static characterization of ADCs
• Dynamic characteristics of ADCs
• Sample and hold circuits
• Design of a sample and hold
• Summary
Pages 539-557

INTRODUCTION
General Block Diagram of an Analog-Digital Converter
Digital
x(t) y(kTN)
Processor
Prefilter Sample/Hold Quantizer Encoder Fig.10.5-1
• Prefilter - Avoids the aliasing of high frequency signals back into the baseband of the
ADC
• Sample-and-hold - Maintains the input analog signal constant during conversion
• Quantizer - Finds the subrange that corresponds to the sampled analog input
• Encoder - Encoding of the digital bits corresponding to the subrange

Nyquist Frequency Analog-Digital Converters

The sampled nature of the ADC places a practical limit on the bandwidth of the input
signal. If the sampling frequency is fS, and fB is the bandwidth of the input signal, then
fB < 0.5fS Continuous time frequency response of the analog input signal.
which is simply the Nyquist
relationship which states that
to avoid aliasing, the -fB 0 fB fS f
sampling frequency must be Sampled data equivalent frequency response where fB < 0.5fS.
greater than twice the highest
signal frequency.
f
-fB 0 fB fS fS-fB fS fS+fB 2fS-fB 2fS 2fS+fB
2
Case where fB > 0.5fS causing aliasing.
f
-fB 0 fS fS 2fS
2
Use of an antialiasing filter to avoid aliasing.
Antialiasing
Filter
f
-fB 0 fB fS fS Fig. 10.5-2
2

Classification of Analog-Digital Converters

Analog-digital converters can be classified by the relationship of fB and 0.5fS and by their
conversion rate.
• Nyquist ADCs - ADCs that have fB as close to 0.5fS as possible.
• Oversampling ADCs - ADCs that have fB much less than 0.5fS.
Classification of Analog-to-Digital Converter Architectures

Conversion Nyquist ADCs Oversampled ADCs
Rate
Slow Integrating (Serial) Very high resolution <14-16 bits
Successive Approximation
Medium 1-bit Pipeline Algorithmic Moderate resolution <10-12 bits
Flash Multiple-bit Pipeline
Fast Folding and interpolating Low resolution < 6-8 bits

STATIC CHARACTERIZATION OF ANALOG-TO-DIGITAL CONVERTERS

Input-Output Characteristics
Ideal input-output characteristics of a 3-bit ADC
111
Infinite Resolution
110 Characteristic
Digital Output Code
101
1 LSB
100
Ideal 3-bit
011 Characteristic
010
1 LSB
001
000
Quantization
1.0
Noise LSBs
0.5
vin
0.0 VREF
-0.5
0 1 2 3 4 5 6 7 8
8 8 8 8 8 8 8 8 8
Analog Input Value Normalized to VREF
CMOS Analog Circuit Design Figure 10.5-3 Ideal input-output characteristics of a 3-bit ADC. © P.E. Allen - 2016
Definitions
• The dynamic range, signal-to-noise ratio (SNR), and the effective number of bits
(ENOB) of the ADC are the same as for the DAC
• Resolution of the ADC is the smallest analog change that distinguishable by an ADC.
• Quantization Noise is the ±0.5LSB uncertainty between the infinite resolution
characteristic and the actual characteristic.
• Offset Error is the difference between the ideal finite resolution characteristic and
actual finite resolution characteristic
• Gain Error is the difference 111 111
Gain Error = 1.5LSBs
between the ideal finite 110 Ideal 110 Ideal

Digital Output Code
Digital Output Code

101 Characteristic 101 Characteristic
resolution characteristic and
100 100
actual finite resolution 011 011
Actual
Characteristic
characteristic measured at 010
Offset = 1.5 LSBs
010
full-scale input. This 001

vin
001
vin
000 000
difference is proportional to 0 1 2 3 4 5 6 7 8 VREF 0 1 2 3 4 5 6 7 8 VREF
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
the analog input voltage. (a.) (b.)
Figure 10.5-4 - (a.) Example of of fset error for a 3-bit ADC. (b.) Example of gain
error for a 3-bit ADC.

Integral and Differential Nonlinearity

The integral and differential nonlinearity of the ADC are referenced to the vertical
(digital) axis of the transfer characteristic.
(% or LSB)
measured at each vertical step (% or LSB).
DNL = (Dcx - 1) LSBs
where Dcx is the size of the actual vertical step in LSBs.
Note that INL and DNL of an analog-digital converter will be in terms of integers in
contrast to the INL and DNL of the digital-analog converter. As the resolution of the
ADC increases, this restriction becomes insignificant.

Example of INL and DNL
111 Ideal
Characteristic
110
INL =
Digital Output Code
101
+1LSB Actual
100 Characteristic
INL = DNL =
011
-1LSB +1LSB
010
001 DNL =
0 LSB vin
000
0 1 2 3 4 5 6 7 8 VREF
8 8 8 8 8 8 8 8 8
Example of INL and DNL for a 3-bit ADC.) Fig.10.5-5
Note that the DNL and INL errors can be specified over some range of the analog input.

Monotonicity
A monotonic ADC has all vertical jumps positive. Note that monotonicity can only be
detected by DNL.
Example of a nonmonotonic ADC:
111
Actual
110 Characteristic
Digital Output Code
101
100
DNL =
011 -2 LSB
Ideal
010 Characteristic
001
vin
000
0 1 2 3 4 5 6 7 8 VREF
8 8 8 8 8 8 8 8 8
Fig. 10.5-6L
If a vertical jump is 2LSB or greater, missing output codes may result.
If a vertical jump is -1LSB or less, the ADC is not monotonic.
Example 36-1 - INL and DNL of a 3-bit ADC

Find the INL and DNL for the 3-bit ADC shown on the previous slide.
Solution
With respect to the digital axis:
1.) The largest value of INL for this 3-bit ADC occurs between 3/16 to 5/16 or 7/16 to
9/16 and is 1LSB.
2.) The smallest value of INL occurs
between 11/16 to 12/16 and 111
Actual
is -2LSB. 110 Characteristic
Digital Output Code

3.) The largest value of DNL occurs at INL =
101 -2LSB
3/16 or 6/8 and is +1LSB.
100 INL =
4.) The smallest value of DNL occurs DNL =
+1LSB
at 9/16 and is -2LSB which is 011 -2 LSB
Ideal
where the converter becomes 010 Characteristic
nonmonotonic. DNL =
001 +1 LSB
vin
000
0 1 2 3 4 5 6 7 8 VREF
8 8 8 8 8 8 8 8 8
Fig. 10.5-6DL

DYNAMIC CHARACTERISTICS OF ADCs

What are the Important Dynamic Characteristics for ADCs?
The dynamic characteristics of ADCs are influenced by:
• Comparators
- Linear response
- Slew response
• Sample-hold circuits
• Circuit parasitics
• Logic propagation delay

Comparator
The comparator is the quantizing unit of ADCs.
Open-loop model:
Nonideal aspects:
• Input offset voltage, VOS (a static characteristic)
• Propagation time delay
- Bandwidth (linear)
Av(0) Av(0)
Av(s) = s =
sc + 1
+1
c
- Slew rate (nonlinear)
C·V V
T = I (I constant) = Slew Rate
SAMPLE AND HOLD CIRCUITS

Requirements of a Sample and Hold Circuit
The objective of the sample and hold circuit is to sample the unknown analog signal and
hold that sample while the ADC decodes the digital equivalent output.
The sample and hold circuit must:
100%
1.) Have the accuracy required for the ADC resolution, i.e. accuracy = N
2
2.) The sample and hold circuit must be fast enough to work in a two-phase clock. For an
ADC with a 100 Megasample/second sample rate, this means that the sample and hold
must perform its function within 5 nanoseconds.
3.) Precisely sample the analog signal at the same time for each clock. An advantage of
the sample and hold circuit is that it removes the precise timing requirements from the
ADC itself.
4.) The power dissipation of the sample and hold circuit must be small. Unfortunately,
the above requirements for accuracy and speed will mean that the power must be
increased as the bits are increased and/or the clock period reduced.

Sample-and-Hold Circuit
Waveforms of a sample-and-hold S/H Command
Hold Sample Hold
circuit:
Output of S/H
Definitions:
Amplitude
ta ts valid for ADC
vin*(t)
• Acquisition time (ta) = time required conversion
to acquire the analog voltage vin*(t)

vin(t)
• Settling time (ts) = time required to vin(t)
settle to the final held voltage to within Time Fig.10.5-9
an accuracy tolerance
1
 Tsample = ta + ts → Maximum sample rate = fsample(max) = T
sample
Other consideratons:
• Aperture time= the time required for the sampling switch to open after the S/H
command is initiated
• Aperture jitter = variation in the aperture time due to clock variations and noise
Types of S/H circuits:
• No feedback - faster, less accurate
• Feedback - slower, more accurate
Open-Loop, Buffered S/H Circuit

Circuit:
Attributes:
• Fast, open-loop
• Requires current from the input to charge CH
• DC voltage offset of the op amp and the charge feedthrough of the switch will create dc
errors

Settling Time
Assume the op amp has a dominant pole at -a and a second pole at -GB.
GB2
The unity-gain response can be approximated as, A(s) ≈ 2
s + GB·s + GB2
 4   3 
The resulting step response is, vout(t) = 1 -  e -0.5GB·t sin  GB·t + 
 3   4 
Defining the error as the difference between the final normalized value and vout(t), gives,
4 -0.5GB·t
Error(t) =  = 1 - vout(t) = 3e
In most ADCs, the error is equal to ±0.5LSB. Since the voltage is normalized,
1 4 -0.5GB·ts 0.5GB·ts = 4 2N
= e → e
2N+1 3 3
Solving for the time, ts, required to settle with ±0.5LSB from the above equation gives
2 4  1
ts = GB ln 2N = GB [1.3863N + 1.6740]
 3 
Thus as the resolution of the ADC increases, the settling time for any unity-gain buffer
amplifiers will increase. For example, if we are using the open-loop, buffered S/H circuit
in a 10 bit ADC, the amount of time required for the unity-gain buffer with a GB of
1MHz to settle to within 10 bit accuracy is 2.473µs.
Open-Loop, Switched-Capacitor S/H Circuit

Circuit:
• Delayed clock used to remove input dependent feedthrough.

• Differential version has better CMRR, cancellation of even harmonics, and reduction of
charge injection and clock feedthrough
True differential version: f1
C
+ f1 f2 -
+ -
vin C vout
-+
f1
- C +
f2 f1
120524-06

Open-Loop, Diode Bridge S/H Circuit

Diode bridge S/H circuit:
VDD
Clock IB Blowthru Capacitor

D1 D2 rd rd
vIN(t) vOUT(t) vIN(t) vOUT(t) vIN(t) vOUT(t)
D3 D4 CH rd rd CH CH
RON = rd ROFF = ¥
Clock IB
Sample phase - diodes Hold phase - diodes
060927-01 forward biased. reversed biased.
MOS diode bridge S/H circuit:
VDD
Clock IB
Blowthru Capacitor
1 1
gm gm
vIN(t) M1 M2 vOUT(t) vIN(t) vOUT(t) vIN(t) vOUT(t)
M3 M4
1 1
CH gm gm CH CH
RON = 1/gm ROFF = ¥
Clock IB
Sample phase - MOS Hold phase - MOS
060927-02 diodes forward biased. diodes reversed biased.
Practical Implementation of the Diode Bridge S/H Circuit
During the hold mode, the diodes D5 and D6 become forward biased and clamp the upper
and lower nodes of the sampling bridge to the sampled voltage.

Closed-Loop S/H Circuit

Circuit:
Attributes:
• Accurate
• First circuit has signal-dependent feedthrough
• Slower because of the op amp feedback loop

Closed-Loop, Switched Capacitor S/H Circuits

Circuit:
Attributes:
• Accurate
• Signal-dependent feedthrough eliminated by a delayed clock
• Differential circuit keeps the output of the op amps constant during the 1 phase
avoiding slew rate limits

Current-Mode S/H Circuit

Circuit:
Attributes:
• Fast
• Requires current in and out
• Good for low voltage implementations

Aperature Jitter in S/H Circuits

Illustration:
If we assume that vin(t) =

Vpsint, then the
maximum slope is equal
to Vp.
Therefore, the value of V
is given as
dvin
V =  dt  t = Vpt .
 
The rms value of this noise is given as
dvin Vpt
V(rms) =  dt  t = .
  2
The aperature jitter can lead to a limitation in the desired dynamic range of an ADC. For
example, if the aperature jitter of the clock is 100ps, and the input signal is a full scale
peak-to-peak sinusoid at 1MHz, the rms value of noise due to this aperature jitter is
111µV(rms) if the value of VREF = 1V.
DESIGN OF A SAMPLE AND HOLD AMPLIFIER

Specifications
Accuracy = 10 bits
Clock frequency is 10 MHz
Power dissipation ≤ 1mW
Signal level is from 0 to 1V
Slew rate ≥ 100V/µs with CL = 1pF
Use 0.25µm CMOS
Technology Parameters (Cox = 60.6x10-4 F/m2):
Parameter Typical Parameter Value Units
Symbol Parameter Description
N-Channel P-Channel
VT0 Threshold Voltage 0.5± 0.15 -0.5 ± 0.15 V
(VBS = 0)
K' Transconductance Para-meter (in 120.0 ± 10% 25.0 ± 10% µA/V2
saturation)
Bulk threshold
 0.4 0.6 (V)1/2
parameter
Channel length 0.32 (L=Lmin) 0.56 (L=Lmin)
 (V)-1
modulation parameter 0.06 (L ≥2Lmin) 0.08 (L ≥2Lmin)
Surface potential at strong inversion 0.7
2|F| 0.8 V

Op Amp Design
Gain:
1 1
Gain error = 1+Loop Gain ≤ 0.5 LSB = 11
2
Therefore, the op amp gain ≥ 211 = 2048 V/V
Choose the op amp gain as ≥ 5000 V/V
Gainbandwidth:
For a dominant pole op amp with unity-gain feedback, the relationship between the
gain-bandwidth (GB), accuracy (N) and speed (ts) is
N+1 N+1
ts = GB  ln(2) = 0.693  GB 



  
Therefore, if ts ≤ 0.5 Tclock = 50 ns (choose ts = 10 ns). For N = 10, the gain-bandwidth

is
GB = 0.762x109 = 120 MHz
Dominant pole is 24 kHz and with an output capacitance of 1pF this means the output
resistance of the op amp must be ≥ 6.6 M.

Op Amp Design – Continued

The previous specifications suggest a VDD = 2.5V
M3
self-compensated op amp. The gain and VPB1 M10 M11
output resistance should be easy to achieve I3 VPB2
with a cascaded output. A folded-cascode -
vIN M8 M9
vOUT
op amp is proposed for the design. In +
M1 M2
order to have the 0-1V signal range, a p- I6 VNB2 I7
CL
channel, differential input is selected. This I1 I2 M6 M7
will give the input 0-1V range. The output
will effectively be 0-1V with the unity I4 VNB1 I5
gain feedback around the op amp. M4 M5
061021-01
Bias Currents:
The 100V/µs slew rate requires I3 = 100µA. Setting I4 = I5 = 125µA gives a power
dissipation of 0.875mW with VDD = 2.5V.


Transistor sizes:
Design M4-M7 to give a saturation voltage of 0.1V with 125µA.
W4 W5 W6 W7 2ID 2·125
 L = L =L =L = 2 = ≈ 200
4 5 6 7 Kn'·VDS(sat) 120·0.01
Since the upper swing is not as important, choose a saturation voltage of 0.25 for M8 –
M11.
W8 W9 W10 W11 2ID 2·125
 L = L =L =L = 2 = = 160
8 9 10 11 Kp'·VDS(sat) 25·0.0625
To get the GB of 120 MHz, this implies the gm of M1 and M2 is
gm = GB·CL = (120x106·2π)(10-12) = 762 µS
W1 W2 gm2 762·762
 L = L = 2I K ' = 2·25·50 = 232
1 2 D p
Let the upper input common mode voltage be 1.5V which gives the W/L of M3 as,
W3
1V = VSG1 + VSD3 = 0.631 + VSD3  VSD3 = 0.369V  L ≈ 60
3

We now need to check the output resistance and the gain to make sure the specifications
are satisfied. Let us choose twice minimum channel length to keep the capacitive
parasitics minimized and not have the output resistance too small. Therefore at quiescent
conditions,
rds5 = 133k, rds7 = 222k, gm7 = 1.935mS and rds2 = 250k
 Routdown ≈ (rds5||rds2)gm7rds7 = 37.29M
rds9 =rds11 = 167k, and gm11 = 1.697mS
 Routup ≈ rds11gm9rds9 = 47.33M
 Rout ≈ 20.86M
The low frequency gain is,
Av ≈ gm1Rout
= 762µS·20.86M = 15,886 V/V
The frequency response will be as shown:

Op Amp Bias Voltages

We also need to design the bias voltages VNB1, VNB2, VPB1 and VPB2. This can be done
using the following circuit:
VDD
Note, the W/L of M3, M4 and M7 will be 6 so that
VPB1
a current of 10µA gives 100µA in M3 of the op
amp. Also, W/L of M1 and M5 will be 16 so a M3 M4 10µA M7 VPB2
10µA 10µA
current of 10µA gives 125µA in M4 and M5 of the M6
op amp. M1 M2 M8 VNB2
10µA
If M2 is 4 times larger than M1, which gives a W/L M5 VNB1
of 64 for M2. Under these conditions, R
1 106
I2 = I1 = 2  R= = 5.1k 061021-02
2ß1R 2·120·16·10
The extra 40µA brings the power dissipation to 0.975mW which is still in specification.
The W/L of M6 and M8 are designed as follows:
2·10 W8
VGS8 = VT + 2VON  VGS8 - VT = 0.2V =  L =
120·(W8/L8) 8
4.167

2·10 W6
VSG6 = |VT| + 2VON  VSG6 - |VT| = 0.5V =  L =
25·(W6/L6) 6
3.20

Switch and Hold Capacitor Design

Switch:
Since the signal amplitude is from 0 to 1V, a single NMOS switch should be
satisfactory. The resistance of a minimum size NMOS switch is,
1 106
RON(worst case) ≈ K '(W/L)(V -V ) = 120(1)(1.5-0.5) = 8.33k
n GS T
For a CH = 1pf, the time constant is 8 ns. This is too close to the 50 ns so let us increase
the switch size to 0.5µm/0.25µm which gives a time constant of 4ns.
Therefore, the W/L ratio of the NMOS switch is 0.5µm/0.25µm and the hold capacitor is
1pf.
Check the error due to channel injection and clock feedthrough-
If we assume the clock that rises and falls in 1ns, then a 0.5µm/0.25µm switch works in
the fast transition region. The channel/clock error can be calculated as:
W·CGDO + Cchannel  3 
 2    VHT  W·CGDO
Verror = -  VHT - 6U·C  - C (VS+2VT -VL)
 C L  L L

Switch and Hold Capacitor Design – Continued

Assuming CGDO is 200x10-12 F/m we can calculate VHT as 0.8131V. Thus,
Verror =
100x10-18+0.5(7.57x10-16) 0.105x10-3 100x10-18
- 0.8131- - (1+1-0) = -0.586mV
 1x10 -12  15x10  1x10-12
-3
For a 1volt signal with 10 bit accuracy, the error must be less than 1LSB which is
0.967mV. The channel/clock error is close to this value and one may have to consider
using a CMOS switch or a dummy switch to reduce the error.
Summary:
At this point, the analog designer understands the weaknesses and strengths of the design.
The next steps will not be done but are listed below:
1.) Simulation to confirm and explore the hand-calculated performance
2.) Layout of the op amp, hold capacitor and switch.
3.) Verification of the layout
4.) Extraction of the parasitics from the layout
5.) Resimulation of the design.
6.) Check for sensitivity to ESD and latchup.
7.) Select package and include package parasitics in simulation.
SUMMARY
• An ADC is by nature a sampled data circuit (cannot continuously convert analog into
digital)
• Two basic types of ADCs are:
- Nyquist – analog bandwidth is as close to the Nyquist frequency as possible
- Oversampled – analog bandwidth is much smaller than the Nyquist frequency
• The active components in an ADC are the comparator and the sample and hold circuit
• A sample and hold circuit must have at least the accuracy of 100%/2N
• Sample and hold circuits are divided into two types:
- Open loop which are fast but not as accurate
- Close loop which are slower but more accurate
• An example of designing a sample and hold amplifier was given to illustrate the
electrical design process for CMOS analog circuits

Lecture 37 – Testing of ADCs and Moderate Speed Nyquist ADCs (6/26/14) Page 37-1
LECTURE 37 – TESTING OF ADCS AND MODERATE SPEED

NYQUIST ADCS
Outline
• Introduction
• Testing of ADCs
• Serial ADCs
• Successive approximation ADCs
• Single-bit/stage pipeline ADCs
• Iterative ADCs
• Self calibration techniques
• Summary
Pages 557-572

TESTING OF ADCs
Input-Output Test for an ADC
Test Setup:
The ideal value of Qn should be within ±0.5LSB

Can measure:
• Offset error = constant shift above or below the 0 LSB line
• Gain error = contant increase or decrease of the sawtooth plot as Vin is increased
• INL and DNL (see following page)

Illustration of the Input-Output Test for a 4-Bit ADC
2.0 LSB
1.5 LSB
Quantization Noise (LSBs)
+2LSB
1.0 LSB INL
0.5 LSB -2LSB

DNL
0.0 LSB
-0.5 LSB
+2LSB
-1.0 LSB DNL
-1.5 LSB -2LSB

INL
-2.0 LSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Analog Input Normalized to VREF Fig.10.5-18

Measurement of Nonlinearity Using a Pure Sinusoid

This test applies a pure sinusoid to the input of the ADC. Any nonlinearity will
appear as harmonics of the sinusoid. Nonlinear errors will occur when the dynamic range
(DR) is less than 6N dB where N = number of bits.
Comments:
• Input sinusoid must have less distortion that the required dynamic range
• DAC must have more accuracy than the ADC

FFT Test for an ADC

Test setup:
Clock
fc
Pure Analog- FFT

Sinusoidal Fast RAM Frequency
Digital Post-
Input, fin Buffer Spectrum
Converter processor
Fig.10.5-19B
Comments:
• Stores the digital output codes of the ADC in a RAM buffer
• After the measurement, a postprocessor uses the FFT to analyze the quantization noise
and distortion components
• Need to use a window to eliminate measurement errors (Raised Cosine or 4-term
Blackmann-Harris are often used)
• Requires a spectrally pure sinusoid

Histogram Test for an ADC

The number of occurences of each digital output code is plotted as a function of the
digital output
Occurances
code.
Number of
Sinusoidal Input
Illustration: Triangular Input
Output
0
0 Mid Full Code
Scale Scale
Comments: Fig.10.5-20
• Emphasizes the time spent at a given level and can show DNL and missing codes
• DNL
Width of the bin as a fraction of full scale H(i)/Nt
DNL(i) = Ratio of the bin width to the ideal bin width -1 = P(i) -1
where
H(i) = number of counts in the ith bin
Nt = total number of samples
P(i) = ratio of the bin width to the ideal bin width
• INL is found from the cumulative bin widths
Comparison of the Tests for Analog-Digital Converters

Other Tests
• Sinewave curve fitting (good for ENOB)
• Beat frequency test (good for a qualitative measure of dynamic performance)
Comparison
Test → Histogram Sinewave Beat
Error or FFT Test Curve Frequency
 Code Test Fit Test Test
DNL Yes (spikes) Yes (Elevated Yes Yes
noise floor)
Missing Codes Yes (Bin counts with zero Yes (Elevated Yes Yes
counts) noise floor)
INL Yes (Triangle input gives Yes (Harmonics Yes Yes
INL directly) in the baseband)
Aperature No Yes (Elevated Yes No
Uncertainty noise floor)
Noise No Yes (Elevated Yes No
noise floor)
Bandwidth No No No Yes (Measures
Errors analog bandwidth)
Gain Errors Yes (Peaks in distribution) No No No
Offset Errors Yes (Offset of distribution No No No
average)
Bibliography on ADC Testing

1.) D. H. Sheingold, Analog-Digital Conversion Handbook, Analog Devices, Inc.,
Norwood, MA 02062, 1972.
2.) S.A. Tretter, Introduction to Discrete-Time Signal Processing, John Wiley & Sons,
New York, 1976.
3.) J. Doernberg, H.S. Lee, and D.A. Hodges, “Full-Speed Testing of A/D Converters,”
IEEE J. of Solid-State Circuits, Vol. SC-19, No. 6, December 1984, pp. 820-827.
4.) “Dynamic performance testing of A to D converters,” Hewlett Packard Product Note
5180A-2.

INTRODUCTION TO MODERATE SPEED ADCS

Moderate Speed ADC Topics
• Serial ADCs - require 2NT for conversion where T = period of the clock
Types:
- Single-slope
- Dual-slope
• Successive approximation ADCs – require NT for conversion where T = the clock
period
• 1-bit per stage, pipeline ADCs – require T for conversion after a delay of NT
• Iterative ADCs – require NT for conversion
• Self-calibration techniques

SERIAL ANALOG-DIGITAL CONVERTERS

Single-Slope ADC
Block diagram:
Attributes:
• Simplicity of operation
• Subject to error in the ramp generator
• Long conversion time ≤ 2NT

Dual-Slope ADC
vin
Block diagram: Waveforms: VREF+Vth t1 = NREFT NREFT
vin'''
vin''' > vin'' > vin'.
vin''
vin'
Vth
0 t
0 t2'
Operation: Reset t0(start) t2''
t2'''
Fig.10.6-3 t2= NoutT
*
1.) Initially vint = 0 and vin is sampled and held (vIN > 0).
2.) Reset the positive integrator by integrating a positive voltage until vint (0) = Vth.
3.) Integrate vin* for NREF clock cycles to get,
NREFT

vint(t1) = K  vin* dt + vint(0) = KNREFTvin* + Vth
0
4.) After NREF counts, the carry output of the counter closes switch 2 and-VREF is
applied to the positive integrator. The output of the integrator at t = t1+t2 is,
NoutT

vint(t1+t2) = vint(t1)+K  (−VREF)dt =Vth → KNREFTvin*+Vth -KNoutTVREF = Vth
t
1
5.) Solving for Nout gives, Nout = NREF (vin*/VREF)
Comments: Conversion time ≤ 2(2N)T and the operation is independent of Vth and K.
SUCCESSIVE APPROXIMATION ANALOG-DIGITAL CONVERTERS

Introduction
Successive Approximation Algorithm:
1.) Start with the MSB bit and work toward the LSB bit.
2.) Guess the MSB bit as 1.
3.) Apply the digital word 10000.... to a DAC.
4.) Compare the DAC output with the sampled analog input voltage.
5.) If the DAC output is greater, keep the guess of 1. If the DAC output is less, change
the guess to 0.
6.) Repeat for the next MSB.
vguess
VREF
0.75VREF
0.50VREF
0.25VREF
0 t
0 1 2 3 4 5 6 T
Fig.10.7-2

Block Diagram of a Successive Approximation ADC†
†R. Hnatek, A User's Handbook of D/A and A/D Converters, John Wiley and Sons, Inc., New York, NY, 1976.
5-Bit Successive Approximation ADC

vIA vOA
Comp- 5-bit Digital-Analog Converter VREF
Analog
In arator
+ - MSB LSB
Analog Analog Analog Analog Analog
Switch Switch Switch Switch Switch
1 2 3 4 5
MSB LSB
0 1 0 1 0 1 0 1 0 1
Gate FF1 FF2 FF3 FF4 FF5
R RD S R RD S R RD S R RD S R RD S
-1
Delay
G1 G2 G3 G4 G5
Delay
Clock pulses
1 1 1 1 1
SR1 SR2 SR3 SR4 SR5
Start pulse
The delay allows for the circuit transients to Shift Register
settle before the comparator output is sampled. Fig.10.7-3

m-Bit Voltage-Scaling, k-Bit Charge-Scaling Successive Approximation ADC

Operation:
1.) With the two SF
switches closed, all
capacitors are paralleled
and connected to Vin*
which autozeros the
comparator offset
voltage.
2.) With all capacitors
still in parallel, a suc-
cessive approximation
search is performed to
find the resistor segment
in which the analog
signal lies.
3.) Finally, a successive approximation search is performed on charge scaling subDAC
to establish the analog output voltage.

Voltage-Scaling, Charge-Scaling Successive Approximation ADC - Continued

Autozero Step
Removes the influence of the offset voltage of the comparator.
The voltage across the capacitor is given as,
vC = Vin* - VOS
Successive Approximation Search on the Resistor String
The voltage at the comparator input is
vcomp = VRi - Vin*
If vcomp > 0, then VRi > Vin*, if vcomp < 0, then VRi < Vin*
Successive Approximation Search on the Capacitor SubDAC
The input to the comparator is written as,
Ceq 2kC-Ceq
vcomp = (VRi+1 - Vin* ) 2kC + (VRi - Vin* ) 2kC
However, VRi+1 = VRi + 2-mVREF
Combining gives,
Ceq 2kC-Ceq
vcomp = (VRi + 2-mVREF -VIN *) + (V Ri -V *)
IN
2C
k 2k C
Ceq
* -m
= VRi - VIN + 2 VREF k
2 C
SINGLE-BIT/STAGE, PIPELINE ANALOG-DIGITAL CONVERTERS

Single-Bit/Stage Pipeline ADC Architecture
Implementation:
Operation:
• Each stage multiplies its
input by 2 and adds or Vi/VREF
subtracts VREF depending 1.0
upon the sign of the input. bi+1

=+1
• i-th stage, 0 Vi-1/VREF
-1.0 -0.5 0 0.5 1.0
Vi = 2Vi-1 - biVREF bi+1
where bi is given as =-1
-1.0
+1 if Vi-1>0 bi = -1 bi = +1
bi =  -1 if V <0
 i-1 [bi,bi+1] [0,0] [0,1] [1,0] [1,1] Fig.10.7-10

Example 37-1 - Illustration of the Operation of the Pipeline ADC

Assume that the sampled analog input to a 4-bit pipeline analog-digital converter is 2.00
V. If VREF is equal to 5 V, find the digital output word and the analog equivalent voltage.
Solution
Stage No. Input to the ith stage, Vi-1 Vi-1 > 0? Bit i
1 2V Yes 1
2 (2V·2) - 5 = -1V No 0
3 (-1V·2) + 5 = 3V Yes 1
4 (3V·2) - 5 = 1V Yes 1
Illustration:

1 1 1 1 

Vanalog = 5 2 − 4 + 8 + 16

 
= 5(0.4375) = 2.1875
where bi = +1 if the ith-bit is 1

and bi = -1 if the ith bit is 0

Achieving the High Speed Potential of the Pipeline ADC

If shift registers are used to store the output bits and align them in time, the pipeline ADC
can output a digital word at every clock cycle with a latency of NT.
Illustration:

Errors in the Pipeline ADC

Types of errors:
• Gain errors – x2 amplifier or summing junctions
• Offset errors – comparators or summing junctions
Illustration of errors:
Vo/VREF Vo/VREF Vo/VREF
1 1 1
2DAi 2VOSi
-1 0 -1 0 -1 0
0 1 Vi/VREF 0 1 Vi/VREF 0 1 Vi/VREF
2DAi -1 2VOSi
-1 -1
060927-04 2VOCi
Gain error, Ai. System offset error, VOSi. Comparator offset error, VOCi.
An error will occur if the output voltage of one stage exceeds ±VREF (saturates).

Digital Error Correction

In the previous slide, we noted that if the analog output to the next stage exceeds ±VREF
that an error occurs. This error can be detected by adding one more bit to the following
stage for the purposes of detecting the error.
Illustration (2nd bit not used for error correction):
Input/output characteristics of a 1-bit stage Input/output characteristics of a 2-bit stage
Vout(i) Vout(i)
0 0 1 1 00 01 10 11
VREF VREF 11
1 Input Input
-VREF Vin(i) Range -VREF 10 Vin(i) Range
VREF for next VREF for next
01
0 Stage Stage
-VREF -VREF 00
[0010]
[0110]
[1010]
[1110]
[0000]
[0001]
[0011]
[0100]
[0101]
[0111]
[1000]
[1001]
[1011]
[1100]
[1101]
[1111]
[00] [01] [10] [11]
060930-01

Digital Error Correction – Continued

If the gain of 4 amplifier is reduced back to 2, the input/output characteristics of the 2-bit
stage become:
Vout(i)
00 01 10 11
VREF 11
Input
-VREF 10 Vin(i) Range
VREF for next
01
Stage
-VREF 00
[0010]
[0110]
[1010]
[1110]
[0001]
[0101]
[1001]
[1101]
060930-02
The output bits can be used to determine the error. If these bits are 00, then 0.5LSB must
be added to get the correct digital output. If the bits are 11, then 0.5LSB must be
subtracted to get the correct digital output.

Modified Digital Error Correction (1.5 bits per stage)

In the previous slide, it was necessary sometimes to perform digital subtraction which is
not easy to implement. To avoid this problem, a 0.5LSB shift has been added to the
input/output characteristic resulting in the following.
Movement of all comparator thresholds Removal of the comparator at 0.75 LSB.
to the right by 0.5LSB.
Vout(i) Vout(i)
00 01 V 10 11 00 01 10
REF
11 -VREF VREF V
REF
10 Input 4 4 10 Input
VREF Vin(i) Range VREF Vin(i) Range
-VREF 01 -VREF 01
for next for next
Stage Stage
-VREF 00 -VREF 00
[0001]
[0010]
[0101]
[1001]
[0000]
[0100]
[1000]
[1010]
[0001]
[0010]
[0101]
[1001]
[0110]
[0000]
[0100]
[1000]
[1010]
[0110]
[1100]
[1101]
060930-03
To obtain code 11 out of the stage after correction, the correction logic must increment
the output of the stage.
To obtain code 00 from this stage after correction, the correction logic need do nothing.
Therefore, only two comparators are needed to produce outputs of (00, 01, 10) as shown
on the right-hand characteristic.
How Does the 1.5 Bit Stage Correct Offset Errors?

Consider a ±0.25VREF comparator offset shift in the input-output characteristics of the
1.5 bit stage.
Vout(i) Vout(i)
VREF VREF
Comparator shift Comparator shift
from 0.25VREF 1 from 0.25VREF 1
to 0VREF 0.5 Input to 0.5VREF 0.5 Input
Vin(i) Range Vin(i) Range
0 VREF for next 0 VREF for next
-0.5 Stage -0.5 Stage
-1 -1
-1 - 3 - 42 - 41 0 1 2
4
3
4 1 -1 - 3 - 42 - 41 0 1 2
4
3
4 1
4 4 4 4 061001-01
When the shift is to the left, the comparator will not be in error until the shift is greater
than 0.25 VREF. This is because the comparator thresholds were shifted to the right by
0.5 VREF.
When the shift is to the right, the input to the next stage will be greater than 0.50VREF.
This will cause the output code 10 which indicates that the digital word should be
incremented by 1 bit.
The range of correction ±VREF /2B+1 where B is the number of bits per stage.
Implementation of the 1.5 Bit Stage

C 1 if
vin f1 f1 V
f2 vin ≥ + REF C C f1
4
C -
-VREF f1
f1 f2 f2
4
f2 + - vout
f1
1 if VREF + f1
V
C vin <- REF
-vin 4
f1 f1
f2
C - VREF
V
- REF f1
4
f2 +
Multiplying
Sub-ADC Sub-DAC
061001-03
The multiplying Sub-DAC must implement the following equation:

2·vin - VREF if vin > VREF/4
Vout = 2·vin if -VREF/4 ≤ vin ≤ VREF/4
2·vin + VREF if vin < -VREF/4

Example 37-2 - Accuracy requirements for a 5-bit pipeline ADC

Show that if Vin = VREF, that the pipeline ADC will have an error in the 5th bit if the gain
of the first stage is 2-(1/8) =1.875 which corresponds to when an error will occur. Show
the influence of Vin on this result for Vin of 0.65VREF and 0.22VREF.
Solution
For Vin = VREF, we get the results shown below. The input to the fifth stage is 0V
which means that the bit is uncertain. If A1 was slightly less than 1.875, the fifth bit
would be 0 which is in error. This result assumes that all stages but the first are ideal.
i Vi(ideal) Bit i (ideal) Vi(A1=1.875) Bit i (A1=1.875)
1 1 1 1.000 1
2 1 1 0.875 1
3 1 1 0.750 1
4 1 1 0.500 1
5 1 1 0.000 ?
Now let us repeat the above results for Vin = 0.65VREF. The results are shown below.
1 +0.65 1 0.6500 1
2 +0.30 1 0.2188 1
3 -0.40 0 -0.5625 0
4 +0.20 1 -0.1250 0
5 -0.60 0 0.7500 1

Next, we repeat for the results for Vin = 0.22VREF. The results are shown below. We
see that no errors occur.
1 +0.22 1 0.2200 1
2 -0.56 0 -0.5875 0
3 -0.12 0 -0.1750 0
4 +0.76 1 0.6500 1
5 +0.52 1 0.3000 1
Note the influence of Vin in the fact that an error occurs for A1= 1.875 for Vin =
0.65VREF but not for Vin = 0.22VREF. Why? Note on the plot for the output of each
stage, that for Vin = 0.65VREF, the output of the fourth stage is close to 0V so any small
error will cause problems. However, for Vin = 0.22VREF, the output of the fourth stage is
at 0.65VREF which is further away from 0V and is less sensitive to errors.
 The most robust values of Vin will be near -VREF , 0 and +VREF or
when each stage output is furthest from the comparator threshold, 0V.

ITERATIVE ANALOG-DIGITAL CONVERTERS

Iterative (Cyclic) Algorithmic Analog-Digital Converter
The pipeline ADC can be reduced to a single stage that cycles the output back to the
input.
Implementation:
Operation:
1.) Sample the input by connecting switch S1 to Vin*.
2.) Multiply Vin* by 2.
3.) If Va > VREF, set the corresponding bit = 1 and subtract VREF from Va.
If Va < VREF, set the corresponding bit = 0 and add zero to Va.
4.) Repeat until all N bits have been converted.
Example 37-3 - Conversion Process of an Iterative, Algorithmic Analog-Digital

Converter
The iterative, algorithmic analog-digital converter is to be used to convert an analog
signal of 0.8VREF. The figure below shows the waveforms for Va and Vb during the
process. T is the time for one iteration cycle.
1.) The analog input of 0.8VREF givesVa = 1.6VREF and Vb = 0.6VREF and the MSB as 1.
2.) Vb is multiplied by two to give Va = 1.2VREF. The next bit is also 1 and Vb = 0.2VREF.
3.) The third iteration givesVa = 0.4VREF, making the next bit is 0 and Vb = 0.4VREF .
4.) The fourth iteration gives Va = 0.8VREF, giving Vb = 0.8VREF and the fourth bit as 0.
5.) The fifth iteration gives Va = 1.6VREF, Vb = 0.6VREF and the fifth bit as 1.
The digital word after the fifth iteration is 11001 and is equivalent to an analog voltage of
0.78125VREF. Va/VREF Vb/VREF
2.0 2.0
1.6 1.6
1.2 1.2
0.8 0.8
0.4 0.4
0.0 t/T 0.0 t/T
CMOS Analog Circuit Design 0 1 2 3 4 5 0 1 2 3 4 5 © P.E. Allen - 2016
Fig. 10.7-14.
SELF-CALIBRATION TECHNIQUES
Self-Calibrating Analog-Digital Converters
Self-calibration architecture for a m-bit charge scaling, k-bit voltage scaling successive
approximation ADC
Comments:
• Self-calibration can be accomplished during a calibration cycle or at start-up
• In the above scheme, the LSB bits are not calibrated
• Calibration can extend the resolution to 2-4 bits more that without calibration
Self-Calibrating Analog-Digital Converters - Continued

Self-calibration procedure starting with the MSB bit:
1.) Connect C1 to VREF and the remaining
capacitors (C2+C3+···+Cm +Cm = C1 ) to
ground and close SF.
2.) Next, connect C1 to ground and C1 to VREF.
 C1 -C1 
3.) The result will be Vx1 =  
 VREF. If C1 = C1 , then Vx1 = 0.
C1 + C1 
4.) If Vx1  0, then the comparator output will be either high or low. Depending on the
comparator output, the calibration circuitry makes a correction through the calibration
DAC until the comparator output changes. At this point the MSB is calibrated and the
MSB correction voltage, V1 is stored.
5.) Proceed to the next MSB with C1 out of the array and repeat for C2 and C2 . Store
the correction voltage, V2, in the data register.
6.) Repeat for C3 with C1 and C2 out of the array. Continue until all of the capacitors of
the MSB DAC have been corrected.
Note: For normal operation, the circuit adds the correct combined correction voltage.
SUMMARY
• Tests for the ADC include:
- Input-output test
- Spectral test
- FFT test
- Histogram test
• Moderate Speed ADCs:
Type of ADC Advantage Disadvantage
Serial ADC High resolution Slow
Voltage-scaling, charge- High resolution Requires
scaling successive considerable digital
approximation ADC control circuitry
Successive approximation Simple Slow
using a serial DAC
Pipeline ADC Fast after initial
Accuracy depends
latency of NT
on input
Iterative algorithmic ADC Simple
Requires other
digital circuitry
• Successive approximation ADCs also can be calibrated extending their resolution 2-4
bits more than without calibration.
Lecture 38 – High Speed Nyquist ADCs (6/26/14) Page 38-1
LECTURE 38 – HIGH SPEED NYQUIST ADCS

Outline
• Parallel/flash ADCs
• Interpolating and averaging
• Folding
• High-speed, high-resolution ADCs
• Time-interleaved ADCs
Pages 573-588

PARALLEL/FLASH ADCs
Parallel/Flash ADC Architecture
Analog Sample
vin(t)
Input and Hold
VREF Circuit
vin*(t)
V1 d1
Voltage
V2 d2 b1
Scaling
V3 d3 b2
Network
V4 2N-1 d4 2N-1 b3 Digital
creating Word
Compar to N
all possible Output
ators Decoder
discrete bN
analog V2N-1 d2N-1
voltages
Phase 1 Phase 2
060928-01 One Clock Period, T
• The notation, vin*(t), means the signal is sampled and held.
• The sample and hold function can be incorporated into the comparators
• The digital words designated as di form a thermometer code

A 3-bit, parallel ADC

VREF Vin*=0.7VREF
General Comments: R - 1
0.875VREF +
• Fast, in the first phase of the clock the
R - 1
analog input is sampled and applied to the 0.750VREF +
comparators. In the second phase, the R - 0
digital encoding network determines the 0.625VREF + 2N-1 Output
correct output digital word. R to N Digital
- 0 encoder
0.500VREF + Word
• Number of comparators required is 2N-1
R - 0 101
which can become large if N is large 0.375VREF +
• The offset of the comparators must be less R - 0
than ±VREF/2N+1 0.250VREF +
R - 0
• Errors occur as “bubbles” in the 0.125VREF +
thermometer code and can be corrected R
with additional circuitry
Fig.10.8-1
• Typical sampling frequencies can be as
high as 1000MHz for 6-bits in sub-micron CMOS technology.

Example 38-1 - Comparator Bandwidth Limitations on the Flash ADC

The comparators of a 6-bit, flash ADC have a dominant pole at 104 radians/sec, a dc
gain of 104 a slew rate of 10V/µs, and a binary output voltage of 1V and 0V. Assume
that the conversion time is the time required for the comparator to go from its initial state
to halfway to its final state. What is the maximum conversion rate of this ADC if VREF =
1V? Assume the resistor ladder is ideal.
Solution:
The output of the i-th comparator can be found by taking the inverse Laplace
transform of,
  Ao  Vin*-VRi 
L Vout(s) = (s/104) + 1· s  → vout(t) = Ao(1 - e-104t)(Vin* - VRi).
-1  
   
The worst case occurs when
Vin*-VRi = 0.5VLSB = VREF/27 = 1/128
 0.5V = 104(1 - e-104T)(1/128) → 64x10-4 = 1- e-104T
or, e-104T = 1 - 64x10-4 = 0.9936 → T = 10-4 ln(1.0064) = 0.6421µs
1
 Maximum conversion rate = = 1.557x106 samples/second
0.6421µs
Checking the slew rate shows that it does not influence the maximum conversion rate.
V
SR = 10V/µs → = 10V/µs → V = 10V/µs(0.6421µs) = 6.421V > 1V
T
Signal Delay in High Speed Converters

Assume that clocked comparators are used in a 500MHz sampling frequency ADC
of 8-bits. If the input frequency is 250MHz with a peak-to-peak value of VREF, the
clock accuracy must be
V VREF/2N+1 1
t  = = ≈ 2.5ps
Vp 2f(0.5VREF) 29··f
Since electrical signals travel at approximately 50µm/ps for metal on an IC, each metal
path from the clock to each comparator must be equal to within 125µm to avoid LSB
errors due to clock skew. Therefore, must use careful layout to avoid ADC inaccuracies
at high frequencies.
An equal-delay clock distribution system for a 4-bit parallel ADC:
Clock
Generator
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CMOS Analog Circuit Design Comparators © P.E. Allen - 2016

Fig.10.8-2B
Other Errors of the Parallel ADC

• Resistor string error - if current is drawn from the taps to the resistor string this will
create a “bowing” effect on the voltage. This can be corrected by applying the correct
voltage to various points of the resistor string.
• Input common mode range of the comparators - the comparators at the top of the string
must operate with the same performance as the comparators at the bottom of the string.
• Kickback or flashback - influence of rapid transition changes occurring at the input of a
comparator. Can be solved by using a preamplifier or buffer in front of the
comparator.
• Metastability - uncertainty of the comparator output causing the transition of the
thermometer code to be undetermined.

INTERPOLATING AND AVERAGING

Illustration of a 3-bit interpolating ADC using a factor of 4 interpolation
Volts
VDD
V2
V2a
V2b
V2c
1 2 3 4 5 6 7 8 Comparator
Vth
Threshold
V1c
V1b
V1a
V1
0 Vin
0 0.5VREF VREF
Fig.10.8-4
Comments:
• Capacitive loading at the input is reduced from 8 comparators to two amplifiers.
• The comparators no longer need a large ICMR
• V1 and V2, are interpolated through the resistor string and applied to the comparators.
• Because of the amplification of the input amplifiers and a single threshold, the
comparators can be simple and are often replaced by a latch.
• If the dots in Fig. 10.8-4 are not equally spaced, INL and DNL will result.
A 3-Bit Interpolating ADC with Equalized Comparator Delays

One of the problems in voltage (passive) interpolation is that the delay from the amplifier
output to each comparator can be different due to different source resistance.
Solution:

Active Interpolation
Example of a 3 level current interpolation:
This type of interpolation works well with current processing, i.e., current comparators.

Interpolation using Amplifiers
Vin Interpolating
Preamplifiers Amplifiers
++ ++
Vy Vo2
VR,j+1 - - - -
Aj+1
++
Vo3
- -
++ ++
Vx Vo1
VR,j - - - -
Aj
060928-03
Vo3 = K(Vy – Vx) which is between Vy and Vx.

Averaging†
VDD VDD VDD
In many cases, the comparators
Termination Termination Termination
consist of a number of pre- Resistors Resistors Resistors
amplifiers followed by a latch.
A11 A12 A13
Averaging is the result of
interconnecting the outputs of
each stage of amplifiers so that
the errors in one amplifier A21 A22 A23
chain are balanced out by
adjacent amplifier chains.
Result: The offsets are reduced

allowing the transistors to be AN-2,1 AN-2,2 AN-2,3
made smaller and therefore
reducing the parasitics
increasing the speed of the AN-1,1 AN-1,2 AN-1,3
ADC.
Termination Termination Termination
Resistors Resistors Resistors
060928-04
†
P.C.S. Scholtens and M. Vertregt, “A 6-b 1.6-Gsample/s Flash ADC in 0.18 µm CMOS Using Averaging Termination, IEEE J. of Solid-State
Circuits, vol. 37, no. 12, Dec. 2002, pp. 1599-1609.
Analog Front End of an ADC using Averaging

FOLDING
Folding Analog-Digital Converters
Allows the number of comparators to be reduced below the value of 2 N-1.
Architecture for a folded ADC:
n1
Coarse bits
Preprocessor Quantizer n1+n2
bits Digital
Encoding
v*in Output
n2 Logic
Folding Fine bits
Preprocessor Quantizer
Operation: 120525-01
The input is split into two or more parallel paths.
• First path uses a coarse quantizer to quantize the signal into 2 n1 values
• The second path maps all of the 2n1 subranges onto a single subrange and applies this
analog signal to a fine quantizer of 2n2 subranges.
Thus, the total number of comparators is 2n1-1 + 2n2-1 compared with 2n1+n2-1 for a
parallel ADC.
I.e., if n1 = 2 and n2 = 4, the folding ADC requires 3 + 15 = 18 compared with 63
comparators.
Example of a Folding Preprocessor

Folding characteristic for n1 = 2 and n2 = 3.
VREF
Preprocessing
After Analog
No
n1 = 2 Folding
n2 = 3
32
VREF Folding
4
8
0 VREF
0 Analog Input
MSBs = 00 01 10 11 Fig.10.8-9
Problems:
• The sharp discontinuities of the folder are difficult to implement at high speeds.
• Fine quantizer must work at voltages ranging from 0 to VREF/4 (subranging).
• The actual frequency of the folding signal is F times the input frequency where F is the
number of folds
Modified Folding Preprocessors

The discontinuity problem can be removed by the following folding preprocessors:
Folder that removes discontinuity problem.

Vout
VREF
8
0 Vin
0 VREF
-VREF
8
Multiple folders shifted in voltage.

Vout
VREF
8
0 Vin
0 VREF
-VREF
8 060928-04
In the second case, the reference voltage for all comparators is identical which removes
any ICMR problems.

A 5-Bit Folding ADC Using 1-Bit Quantizers (Comparators)

Block diagram:
Comments:
• Number of comparators is 7 for the fine quantizer and 3 for the coarse quantizer
• The zero crossings of the folders must be equally spaced to avoid linearity errors
• The number of folders can be reduced and the comparators simplified by use of
interpolation
Folding Circuits
+VREF
Implementation R/8
R/8
VDD
R/8
of a times 4 R/8 RL RL Folding
R/8 Outputs
+V To com-
folder used R/8 - out parator
R/8 I
in a 3-bit R/8 V8
R/8
quantizer: R/8
R/8 V3
R/8 I V1 I V2 I V7 I V8
R/8
R/8
R/8 Vin
R/8
R/8 Vout
R/8 V2 +IRL
R/8
R/8
R/8
R/8 0 Vin
V1 V2 V3 V4 V5 V6 V7 V8 VREF
R/8
R/8
R/8 V1
Comments: -IRL 060928-06
• Horizontal shifting is achieved by connecting V1 through V8 to different points on the

voltage scaling resistor string.
• Folding and interpolation ADCs offer the most resolution at high speeds (≈8 bits at
500MHz)
HIGH-SPEED, HIGH-RESOLUTION ADCs

Multiple-Bit, Pipeline Analog-Digital Converters
A compromise between speed and resolution is to use a pipeline ADC with multiple
bits/stage.
i-th stage of a k-bit per stage pipeline ADC with residue amplification:
Clock Residue Clock Residue

Vi-1 + Vi + Vi+1
S/H S S/H S
VREF VREF - VREF VREF -
Av =2k Av =2k
k-bit k-bit k-bit k-bit
ADC DAC i-th stage ADC DAC i+1-th stage
061002-02
k-bits k-bits
b0 b1 bk-2 bk-1

Residue voltage = Vi-1 -  2 + 2 + ··· + k-1 + k  VREF
 2 2 2 
Potential specifications range from 100-300 Msps and 10 to 14 bits.

A 3-Stage, 3-Bit Per Stage Pipeline ADC

Illustration of the operation:
Stage 1 Stage 2 Stage 3
VREF
111 111 111
110 110 110
Voltage
101 101 101
VREF 100 100 100
2 011 011 011
010 010 010
001 001 001
0 000 000 000 Time
Clock 1 Clock 2 Clock 3
Digital output = 011 111 001
MSB LSB Fig.10.8-14
Converted word is 011 111 001
Comments:
• Only 21 comparators are required for this 9-bit ADC
• Conversion occurs in three clock cycles
• The residue amplifier will cause a bandwidth limitation,
50MHz
GB = 50MHz → f-3dB =  6MHz
23
Multiple-Bit, Pipeline Analog-Digital Converters - Subranging

The amplification of Av = 2k for each stage places a bandwidth limitation on the
converter. The subranging technique shown below eliminates this problem.
Clock Residue Clock Residue

Vi-1 + Vi + Vi+1
S/H
VREF(i)=VREF(i-1)/2k S S/H
VREF(i+1)=VREF(i)/2k S
- -
VREF(i)=VREF(i-1)/2k VREF(i+1)=VREF(i)/2k
k-bit k-bit k-bit k-bit

i-th stage ADC DAC i+1-th stage ADC DAC
k-bits k-bits 061002-03
Note: the reference voltage of the previous stage (i-1) is divided by 2k to get the
reference voltage for the present stage (i), VREF(i), and so forth.

Subranging, Multiple-Bit, Pipeline ADCs

Illustration of a 2-stage, 2-bits/stage pipeline ADC:
Stage 1 Stage 2
VREF
11
0.7500VREF
10
Comments:
Voltage
0.5000VREF
• Resolution of the 0.4375VREF
11
comparators for the 0.3750VREF 01 10
0.3125VREF 01
following stages increases 0.2500VREF
00
but fortunately, the
tolerance of each stage 00
decreases by 2k for every 0 Time
additional stage. Clock 1 Clock 2
Digital output word = 01 10 Fig.10.8-15
• Removes the frequency
limitation of the amplifier

Implementation of the DAC in the Multiple-Bit, Pipeline ADC

Circuit: Comments:
• A good compromise between area and speed
• The ADC does not need to be a flash or
parallel if speed is not crucial
• Typical performance is 10 bits at
50Msamples/sec

Example 38-2 - Examination of error in subranging for a 2-stage, 2-bits/stage

pipeline ADC
The stages of the 2-stage,
2-bits/stage pipeline ADC
shown below are ideal.
However, the second
stage divides VREF by 2
rather than 4. Find the ±INL and ±DNL for this ADC.
Solution
Examination of the first stage shows that its output, Vout(1) changes at
Vin(1) 1 2 3 4
VREF = 4, 4, 4, and 4 .
Vout(1) b0 b1
The output of the first stage will be VREF = 2 + 4 .
Vin(2) 1 2 3 4
The second stage changes at VREF = 8, 8, 8, and 8
where
Vin(2) = Vin(1) - Vout(1).
The above relationships permit the information given in the following table.

Output digital word for Ex. 38-2:
Vin(1) b0 b1 Vout(1) Vin(2) b2 b3 Ideal Ouput 1111
VREF VREF VREF b0 b1 b2 b3 1110

1101
0 0 0 0 0 0 0 0 0 0 0 Ideal Finite Characteristic
1100
1/16 0 0 0 1/16 0 0 0 0 0 1
1011
2/16 0 0 0 2/16 0 1 0 0 1 0
1010
Digital Output Code

3/16 0 0 0 3/16 0 1 0 0 1 1
INL=0LSB
4/16 0 1 4/16 0 0 0 0 1 0 0 1001
-DNL=0LSB
5/16 0 1 4/16 1/16 0 0 0 1 0 1 1000
6/16 0 1 4/16 2/16 0 1 0 1 1 0 0111

7/16 0 1 4/16 3/16 0 1 0 1 1 1 0110
8/16 1 0 8/16 0 0 0 1 0 0 0 -INL=2LSB
0101
9/16 1 0 8/16 1/16 0 0 1 0 0 1 0100
10/16 1 0 8/16 2/16 0 1 1 0 1 0 0011
11/16 1 0 8/16 3/16 0 1 1 0 1 1 0010
+DNL=2LSB
12/16 1 1 12/16 0 0 0 1 1 0 0 0001

13/16 1 1 12/16 1/16 0 0 1 1 0 1
0000
14/16 1 1 12/16 2/16 0 1 1 1 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
15/16 1 1 12/16 3/16 0 1 1 1 1 1 Analog Input Voltage
Comparing the actual digital output word with the ideal output word gives the following:
+INL = 0LSB, -INL = 0111-0101 = -2LSB, +DNL = (1000-0101) - 1LSB = +2LSB,
and -DNL = (0101-0100) - 1LSB = 0LSB.
Example of a Multiple-Bit, Pipeline ADC

Two-stages with 5-bits per stage resulting in a 10-bit ADC with a sampling rate of
5Msamples/second.
Architecture:
Vin Vin* MSB
S/H MSBs
ADC
Increment
DAC by 1
Vr1
LSB
ADC LSBs
Vr2
Fig.10.8-21
DAC
Features:
• Requires only 2n/2-1 comparators
• LSBs decoded using 31 preset charge redistribution capacitor arrays
• Reference voltages used in the LSBs are generated by the MSB ADC
• No op amps are used
Example of a Multiple-Bit, Pipeline ADC - Continued

MSB Conversion:
Operation:
1.) Sample Vin* on
each 32C
capacitance
autozeroing the
comparators
2.) Connect each

comparator to a node
of the resistor string
generating a
thermometer code.

Example of a Multiple-Bit, Pipeline ADC - Continued

LSB Conversion: Operation:
1.) MSB comparators are preset to each
of the 31 possible digital codes.
2.) Vr1 and Vr2 are derived from the
MSB conversion.
3.) Preset comparators will produce a
thermometer code to the encoder.
Comments:
• Requires two full clock cycles
• Reuses the comparators
• Accuracy limited by resistor string
and its dynamic loading
• Accuracy also limited by the capacitor
array
• Comparator is a 3-stage, low-gain,
wide-bandwidth, using internal
autozeroing
Digital Error Correction

Like many of the accuracy enhancing techniques, there are particular applications where
certain correcting techniques are useful. In the pipeline, analog-digital converter, a
technique called digital error correction is used to remove the imperfections of the
components.
Pipeline ADC:
vIN* Stage 1 Stage 2 Stage K
B bits B bits B bits
Digital KB
Logic bits
041007-11
Operation:
1.) Stage 1 resolves the analog input signal to within one of B subranges which
determines the first B bits.
2.) Stage 1 then creates the analog residue (analog input – quantized analog output) and
passes on to Stage 2 by either amplifying or subranging.
3.) Stage 2 repeats this process which ends with Stage K.
Example of Digital Error Correction in a Pipeline ADC

Subranging Pipeline ADC Example (B =2, K = 3) using Digital Error Correction.
No correction (error in first comparator): Digital error correction (extra bit in stage 2):
Comments:
• Adds a correcting bit to the following stage to correct for errors in the previous stage.
• The subranging or amplification of the next stage does not include the correcting bit.
• Correction can be done after all stages of the pipeline ADC have converted or after
each individual stage.
12-Bit Pipeline ADC with Digital Error Correction & Self-Calibration†

Digital Error vin
S/H DAC DAC DAC DAC
Correction:
• Avoids saturation
ADC ADC ADC ADC ADC
of the next stage
3 bits 3 bits 3 bits 3 bits 4 bits
• Reduces the
number of
missing codes
• Relaxed
specifications for Clock
the comparators 12 bits
• Compensates for Digital Error Correction Logic
wrong decisions Fig. 11-30
in the coarse quantizers

Self-Calibration:
• Can calibrate the effects of the DAC nonlinearity and gain error
• Can be done by digital or analog methods or both
†J. Goes, et. al., CICC’96

TIME-INTERLEAVED ADC CONVERTERS

Time-Interleaved Analog-Digital Converters
Slower ADCs are used in parallel for area reduction or fast ADCs in parallel for speed.
T1
Illustration:
S/H N-bit ADC No. 1
T2
S/H N-bit ADC No. 2 Digital

Vin word
out
TM
S/H N-bit ADC No. M
N-bit ADC No. 1

T N-bit ADC No. 2
T= C
M
N-bit ADC No. M
Comments: t
T1 T2 TM T1+TC T2+TC TM+TC Fig.10.8-20
• Can get the same throughput with less chip area
• If M = N, then a digital word is converted at every clock cycle
• Multiplexer and timing become challenges at high speeds
• Channels must be matched with ±0.5LSB for delay, gain, and offset.
SUMMARY
Type of ADC Primary Advantage Primary Disadvantage

Flash or parallel Fast Area is large if N > 6
Interpolating Fast Requires accurate
interpolation
Folding Fast Bandwidth increases if
no S/H used
Multiple-Bit, Increased number of bits Slower than flash
Pipeline
Time- Small area with large Precise timing and fast
interleaved throughput multiplexer
Typical Performance:
• 6-8 bits
• 500-2000 Msamples/sec.
• The ENOB at the Nyquist frequency is typically 1-2 bits less that the ENOB at low
frequencies.
• Power is approximately 0.3 to 1W

Lecture 39 – Oversampling ADCs – Part I (6/26/14) Page 39-1
LECTURE 39 – OVERSAMPLING ADCS – PART I

Outline
• Introduction
• Delta-sigma modulators
• Summary
Pages 589-596

INTRODUCTION
What is an oversampling converter?
An oversampling converter uses a noise-shaping modulator to reduce the in-band
quantization noise to achieve a high degree of resolution.
• What is the range of oversampling?
The oversampling ratio, called M, is a ratio of the sampling frequency to the Nyquist
frequency of the input signal. The Nyquist frequency is twice the bandwidth of the
input signal. This oversampling ratio can vary from 8 to 256.
- The resolution of the oversampled converter is proportional to the oversampled ratio.
- The bandwidth of the input signal is inversely proportional to the oversampled ratio.
• What are the advantages of oversampling converters?
Very compatible with VLSI technology because most of the converter is digital
High resolution
Single-bit quantizers use a one-bit DAC which has no INL or DNL errors
Provide an excellent means of trading precision for speed (16-18 bits with a signal
bandwidth of 50kHz to 8-10 bits with a signal bandwidth of 5-10MHz).
• What are the disadvantages of oversampling converters?
Difficult to model and simulate
Limited in bandwidth to the clock frequency divided by the oversampling ratio
Nyquist Versus Oversampled ADCs

Conventional Nyquist ADC Block Diagram:
x(t) Digital y(kTN)
Processor
Filtering Sampling Quantization Digital Coding

Fig.10.9-01
Oversampled ADC Block Diagram:

x(t) Decimation y(kTN)
Modulator
Filter
Filtering Sampling Quantization Digital Coding

Fig.10.9-02
Components:
• Filter - Prevents possible aliasing of the following sampling step.
• Sampling - Necessary for any analog-to-digital conversion.
• Quantization - Decides the nearest analog voltage to the sampled voltage (determines
the resolution).
• Digital Coding - Converts the quantizer information into a digital output signal.
Frequency Spectrum of Nyquist and Oversampled Converters

Definitions:
fB = analog signal bandwidth
fN = Nyquist frequency (two times fB)
fS = sampling or clock frequency
fS fS
M = f = 2f = oversampling ratio
N B
Frequency prespective:

Quantization Noise of a Conventional (Nyquist) ADC

Multilevel Quantizer:
The quantized signal y can be

represented as,
y = Gx + e
where
G = gain of the ADC, normally 1
e = quantization error
The mean square value of the quantization error is
/2
2 1  2
erms = SQ =  e(x)2dx = 12

-/2

Quantization Noise of a Conventional (Nyquist) ADC - Continued

Spectral density of the sampled noise:
When a quantized signal is sampled at fS (= 1/), then all of its noise power folds into
the frequency band from 0 to 0.5fS. Assuming that the noise power is white, the spectral
density of the sampled noise is,
2
E(f) = erms f = erms 2
S
where  = 1/fS and fS = sampling frequency. The inband noise energy no is
fB 2
2 2 2fB erms erms
no =  E (f)df = erms (2fB) = erms  f  = M
2  2
 no =
 S M
0
What does all this mean?
• One way to increase the resolution of an ADC is to make the bandwidth of the signal,
fB, less than the clock frequency, fS. In otherwords, give up bandwidth for precision.
• However, it is seen from the above that a doubling of the oversampling ratio M, only
gives a decrease of the inband noise, no, of 1/ 2 which corresponds to -3dB decrease
or an increase of resolution of 0.5 bits.
As a result, increasing the oversampling ratio of a Nyquist analog-digital converter is
not a very good method of increasing the resolution.
Oversampled Analog-Digital Converters

Classification of oversampled ADCs:
1.) Straight-oversampling - The quantization noise is assumed to be equally distributed
over the entire frequency range of dc to 0.5fS. This type of converter is represented
by the Nyquist ADC.
2.) Predictive oversampling - Uses noise shaping

plus oversampling to reduce the inband noise to
a much greater extent than the straight-
oversampling ADC. Both the signal and noise
quantization spectrums are shaped.
3.) Noise-shaping oversampling - Similar to the

predictive oversampling except that only
the noise quantization spectrum is shaped
while the signal spectrum is preserved.
The noise-shaping oversampling ADCs are also known as delta-sigma ADCs. We will
only consider the delta-sigma type oversampling ADCs.
DELTA-SIGMA MODULATORS
General block diagram of an oversampled ADC
Components of the Oversampled ADC:
1.)  Modulator - Also called the noise shaper because it can shape the quantization
noise and push the majority of the inband noise to higher frequencies. It modulates the
analog input signal to a simple digital code, normally a one-bit serial stream using a
sampling rate much higher than the Nyquist rate.
2.) Decimator - Also called the down-sampler because it down samples the high
frequency modulator output into a low frequency output and does some pre-filtering on
the quantization noise.
3.) Digital Lowpass Filter - Used to remove the high frequency quantization noise and to
preserve the input signal.
Note: Only the modulator is analog, the rest of the circuitry is digital.
First-Order, Delta-Sigma Modulator

Block diagram of a first-order, delta-sigma fS
modulator: x + y
Integrator v A/D
-
Components: u
D/A
• Integrator (continuous or discrete time) Fig.10.9-08 Quantizer
• Coarse quantizer (typically two levels)
- A/D which is a comparator for two levels
- D/A which is a switch for two levels
First-order modulator output for a sinusoidal input:
1.5
1
0.5
Volts
-0.5
-1
-1.5
0 50 100 150 200 250
Tme (Units of T, clock period) Fig.10.9-09
Sampled-Data Model of a First-Order  Modulator

q[nTs]
Writing the following relationships, x[nTs] + w[nTs] + Integrator

v[nTs] + y[nTs]
Delay
y[nTs] = q[nTs] +v[nTs] - + Quan-
tizer
v[nTs] = w[(n-1)Ts] + v[(n-1)Ts] Fig. 10.9-10
 y[nTs] = q[nTs]+w[(n-1)Ts]+v[(n-1)Ts] = q[nTs]+{x[(n-1)Ts]-y[(n-1)Ts]}+v[(n-1)Ts]

But the first equation can be written as
y[(n-1)Ts] = q[(n-1)Ts] +v[(n-1)Ts] → q[(n-1)Ts] = y[(n-1)Ts]} - v[(n-1)Ts]
Substituting this relationship into the above gives,
y[nTs] = x[(n-1)Ts] + q[nTs] - q[(n-1)Ts]
Converting this expression to the z-domain gives,
Y(z) = z-1X(z) + (1-z-1)Q(z)
Definitions:
Y(z)
Signal Transfer Function = STF = X(x) = z-1
Y(z)
Noise Transfer Function = NT F= Q(x) = 1-z-1

Higher-Order  Modulators
A second-order,  modulator:
q[nTs]
x[nTs]+ Integrator 1 Integrator 2 y[nTs]

+ + + +
Delay
- + - + Quan-
Delay tizer
070917-01
It can be shown that the z-domain output is,
Y(z) = z-1X(z) + (1-z-1)2Q(z)
The general, L-th order  modulator has the following form,
Y(z) = z-KX(z) + (1-z-1)LQ(z)
Note that noise transfer function, NTF, has L-zeros at the origin resulting in a high-pass
transfer function. K depends on the architecture where K≤L.
This high-pass characteristic reduces the noise at low frequencies which is the key to
extending the dynamic range within the bandwidth of the converter.

Noise Transfer Function

The noise transfer function can be written as,
NTFQ (z) = (1-z-1)L
Evaluate (1-z-1) by replacing z by ejTs to get
 2j ejf/fs ejf/fs - e-jf/fs
(1-z-1)= 
1-e -jTs 
   2j e-jf/fs = sin(fTs) 2j e-jf/fs

 2j ejf/fs =  2j 
|1-z-1| = (2sinfTs) → |NTFQ(f)| = (2sinfTs)L
Magnitude of the noise
transfer function,
Note: Single-loop modulators

having noise shaping charac-
teristics of the form (1-z-1)L
are unstable for L>2 unless an
L-bit quantizer is used.
In-Band Rms Noise of Single-Loop  Modulator

Assuming noise power is white, the power spectral density of the  modulator, SE(f), is
|SQ(f)|
SE(f) = |NTFQ(f)|2 f
s
2
Next, integrate SE(f) over the signal band to get the inband noise power using SQ =
12
fb
1  2  2L  1 2
 SB = f (2sinfTs)2L 12 df  2L+1 2L+112  where sinfTs  fTs for M>>1.
s  M  
-fb
Therefore, the in-band, rms noise is given as
 L  1     L  1 
n0 = SB =   L+0.5 =  L+0.5 erms
 2L+1 M  12   2L+1 M 
Note that the  is a much more efficient way of achieving resolution by increasing M.
erms
n0  L+0.5  Doubling of M leads to a 2L+0.5 decrease of in-band noise
M
resulting in an extra L+0.5 bits of resolution!
 The increase of the oversampling ratio is an excellent method of increasing the
resolution of a  oversampling analog-digital converter.
Illustration of RMS Noise Versus Oversampling Ratio for Single Loop 

Modulators
Plotting n0/erms gives,
n0  L  1 
 
erms =  2L+1ML+0.5

Dynamic Range of  Analog-Digital Converters

Oversampled  Converter:
The dynamic range, DR, for a 1 bit-quantizer with level spacing  =VREF, is
  2
 
2 Maximum signal power 2 2  3 2L+1 2L+1
DR = = =
SB(f)  2L  1 2 2 2L M
   
2L+1 M 2L+112 
Nyquist Converter:
The dynamic range of a N-bit Nyquist rate ADC is (now  becomes VREF for large N),
Maximum signal power (VREF/2 2)2 3
DR2 = = = 2 22N → DR = 1.5 2N
SQ  /12
2
Expressing DR in terms of dB (DRdB) and solving for N, gives
DRdB - 1.7609
N= or DRdB = (6.0206N + 1.7609) dB
6.0206
Example: A 16-bit  ADC requires about 98dB of dynamic range. For a second-order
modulator, M must be 153 or 256 since we must use powers of 2.
Therefore, if the bandwidth is 20kHz, then the clock frequency must be 10.24MHz.
Multibit Quantizers
A single-bit quantizer:
 = VREF
Advantage is that the DAC is inherently linear.
Multi-bit quantizer:
Consists of an ADC and DAC of B-bits.
VREF
= B fS
2 -1
Disadvantage is that the
DAC is no longer perfectly v
y
A/D
linear. To get large
resolution delta-sigma
ADCs requires highly
precise DACs. u
D/A
Dynamic range of a multibit  ADC: Quantizer

2
3 2L+1 2L+1  B 2 Fig. 10.9-14
DR = 2 2L M 2 -1

Example 39-1 - Tradeoff Between Signal Bandwidth and Accuracy of  ADCs

Find the minimum oversampling ratio, M, for a 16-bit oversampled ADC which uses
(a.) a 1-bit quantizer and third-order loop, (b.) a 2-bit quantizer and third-order loop, and
(c.) a 3-bit quantizer and second-order loop. For each case, find the bandwidth of the
ADC if the clock frequency is 10MHz.
Solution
We see that 16-bit ADC corresponds to a dynamic range of approximately 98dB.
(a.) Solving for M gives
2 DR2 2L 1/(2L+1)


M = 3 2L+1 B-1 2

 (2 ) 
Converting the dynamic range to 79,433 and substituting into the above equation gives a
minimum oversampling ratio of M = 48.03 which would correspond to an oversampling
rate of 64. Using the definition of M as fc/2fB gives fB as 10MHz/2·64 = 78kHz.
(b.) and (c.) For part (b.) and (c.) we obtain a minimum oversampling rates of M = 32.53
and 96.48, respectively. These values correspond to oversampling rates of 32 and 128,
respectively. The bandwidth of the converters is 312kHz for (b.) and 78kHz for (c.).

Z-Domain Equivalent Circuits

The modulator structures are much easier to analyze and interpret in the z-domain.
q[nTs]
x[nTs] + w[nTs] + Integrator y[nTs]

v[nTs] +
Delay
- + Quan-
tizer
Q(z)
X(z) + Integrator Y(z)

W(z) + V(z) +
z-1
- + Quan-
tizer
Q(z)
X(z) + z-1 + Y(z)
- 1-z-1
Fig.10.9-16
 z-1   1   z-1 
Y(z) = Q(z) +  -1 [X(z) - Y(z)] → Y(z)  -1 = Q(z) +  -1 X(z)
1-z  1-z  1-z 
 Y(z) = (1-z-1)Q(z) + z-1X(z) → NTFQ (z) = (1-z-1) for L = 1
Cascaded, Second-Order  Modulator

Since the single-loop architecture with order higher than 2 are unstable, it is necessary to
find alternative architectures that allow stable higher order modulators.
Q2(z)
A cascaded, second-order structure: X2(z) + z-1 +
- 1-z-1
Y2(z)
Q (z)
Y1(z) = (1-z-1)Q1(z) + z-1X(z) 1
X(z) + + Y1(z) -1 +
- + Y(z)
 z-1  z-1 z z-1 +
X2(z) =  -1  (X(z) -Y1(z) - 1-z-1
1-z  Fig.10.9-17
 z-1   z-1 
=  -1 X(z) -  -1 [(1-z-1)Q1(z) + z-1X(z)]
1-z  1-z 
 z-2   z-2 
Y2(z) = (1-z )Q2(z) + z X2(z) = (1-z )Q2(z) +  -1 X(z) - z Q1(z) -  -1 X(z)
-1 -1 -1 -2
1-z  1-z 
= (1-z-1)Q2(z) - z-2Q1(z)
Y(z) = Y2(z) - z-1Y2(z) + z-2Y1(z) = (1-z-1)Y2(z) + z-2Y1(z)
= (1-z-1)2Q2(z)-(1-z-1)z-2Q1(z)+(1-z-1)z-2Q1(z)+z-3X(z) = (1-z-1)2Q2(z)+z-3X(z)
 Y(z) = (1-z-1)2Q2(z) + z-3X(z)

Third-Order, MASH  Modulator

It can be shown that Q1(z)
X(z) + 1 + + + Y(z)
Y(z) = X(z) + (1-z-1)3Q3(z) 1-z-1 Y1(z)
- +
This results in a 3rd-order noise shaping and no z-1
+ -
delay between the input and output. -Q1(z)
Q2(z)
+ 1 + + -1
+
1-z -1 1-z
- +
Y2(z)
z-1
+ -
-Q2(z) 1-z-1
Q3(z)
+ 1 + +
1-z-1 1-z-1
-
Y3(z)
Comments: z-1 Fig. 10.9-17A
• The above structures that eliminate the noise of all quantizers except the last are called
MASH or multistage architectures.
• Digital error cancellation logic is used to remove the quantization noise of all stages,
except that of the last one.

A Fourth-Order, MASH-type Modulator using Scaling of Error Signals†

Q1(z)
Xin(z) + + D1(z) Dout(z)

The signal is
z-1 + z-1 + +
z-1 z-1
divided by 1/C as it
- 1-z-1
- 1-z-1 +
passes from the first
a1 a2
2nd-order modulator
nd
+ l1
to the second 2 -
- C
order modulator.
1/C Q2(z) The digital output
nd
+ + D2(z) of the second 2 -
z-1 + z-1 + order modulator is
-1 -1
1-z-1 1-z-1
- 1-z - 1-z
then multiplied by
b1 b2 the inverse factor of
061207-01
C.
The various transfer functions are (a1=1, a2=2, b1=1, b2=2, 1=2 and C = 4) :
D1(z) = Xin(z) + (1-z-1)2 Q1(z) and D2(z) = (1/C)(-Q1(z)) + (1-z-1)2 Q2(z)
Giving Dout(z) = Xin(z) + (1-z-1)4 Q2(z)
†U.S. Patent 5,061,928, Oct. 29, 1991.

Distributed Feedback  Modulator - Fourth-Order

Q
X + a1z-1 Y1 a2z-1 Y2 a3z-1 Y3 a4z-1 Y4 + 1-bit Y
- 1-z-1 1-z-1 1-z-1 1-z-1 + A/D
+ +
+ +
1-bit
D/A Fig.10.9-20
Amplitude of integrator outputs:

Distributed Feedback  Modulator - Fourth-Order – Continued

Q
X + a1z-1 Y1 a2z-1 Y2 a3z-1 Y3 a4z-1 Y4 + 1-bit Y
- 1-z-1 1-z-1 1-z-1 1-z-1 + A/D
+ +
+ +
1-bit
A/D Fig.10.9-20
Amplitude of integrator outputs (Integrator constants have been optimized to minimize
the integrator outputs):

Cascaded of a Second-Order Modulator with a First-Order Modulator
Comments:
• The stability is guaranteed for cascaded structures
• The maximum input range is almost equal to the reference voltage level for the
cascaded structures
• All structures are sensitive to the circuit imperfection of the first stages
• The output of cascaded structures is multi-bit requiring a more complex digital
decimator

Integrator Circuits for  Modulators

Fundamental block of the  modulator:
Vi(z) + Vo(z) Vi(z) az-1 Vo(z)
a z-1
1-z-1
+
Fig.10.9-22
Fully-Differential, Switched
Capacitor Implementation:
It can be shown that (Chapter 9 of the second

edition or Appendix E of the third edition) that,
Vout(z) Cs  z-1 
  
Vin(z) = Ci  1-z-1
becomes,
Vout(e jT) C1 e-jT T  C1   T   -jT
o
=    =    e 
o jT
Vin( e )   C2 j2 sin(  T/2) T j TC2  sin( T/2) 
or
Vout(e jT)
o
C1 I
= (Ideal)x(Magnitude error)x(Phase error) where I = TC  Ideal =
Vin( e jT)
o
2 j
Power Dissipation versus Supply Voltage and Oversampling Ratio

The following is based on the above switched-capacitor integrator:
1.) Dynamic range:
The noise in the band [-fs,fs] is kT/C while the noise in the band [-fs/2M,fs/2M] is
kT/MC. We must multiply this noise by 4; x2 for the sampling and integrating phases
and x2 for differential operation. The dynamic range is then VDD divided by this noise,
2
VDD2/2 VDDMCs
 DR = 4kT/MC = 8kT s 8kT·DR
C
2.) Lower bound on the sampling capacitor, Cs, can be written as: s = 2
VDDM
3.) Static power dissipation of the integrator: Pint = IbVDD
4.) Settling time for a step input of Vo,max:
Vo,max  Ci  Cs  CsVDD
Ib = Ci =    VDD = = CsVDD(2fs) = 2MfNCsVDD
Tsettle T C
 settle  i  Tsettle
 Pint = 2MfNCsVDD2 = 16kT·DR·fN
Because of additional feedback to the 1st integrator, power is increased by a factor of 2.
 P1st-int = 32kT·DR·fN
SUMMARY
• Oversampled ADCs allow signal bandwidth to be efficiently traded for resolution
• Noise shaping oversampled ADCs preserve the signal spectrum and shape the noise
quantization spectrum
• The modulator shapes the noise quantization spectrum with a high pass filter
• The quantizer can be single or multiple bit
- Single bit quantizers do not require linear DACs because a 1 bit DAC cannot be
nonlinear
- Multiple bit quantizers require ultra linear DACs
• Modulators consist of combined integrators with the goal of high-pass shaping of the
noise spectrum and cancellation of all quantizer noise but the last quantizer

Lecture 40 – Oversampling ADCs – Part II (7/17/15) Page 40-1
LECTURE 40 – OVERSAMPLING ADCS – PART II

Outline
• Implementation of  modulators
• Decimation and filtering
• Bandpass  modulators
• Digital-analog oversampling converters
• Summary
Pages 596-607

IMPLEMENTATION OF  MODULATORS
 Modulators – The Analog Part of the Oversampling ADC
Most of today’s delta-sigma modulators use fully differential switched capacitor circuits.
Advantages are:
• Doubles the signal swing and increases the dynamic range by 6dB
• Common-mode signals that may couple to the signal through the supply lines and
substrate are canceled
• Charge injected by the switches are canceled to a first-order
Example:
First integrator
dissipates the most
power and requires the
most accuracy.

1.5V, 1mW, 98db  Analog-Digital Converter†

a E
X a1 a2 a3 a4 1-bit Y
S z - 1 y1 z - 1 y2 S z - 1 y3 S z - 1 y4 A/D
b1 b2
S
1-bit
Fig. 10.10-06
D/A
where a1 = 1/3, a2 = 3/25, a3 = 1/10, a4 = 1/10, b1= 6/5, b2= 1 and  = 1/6
Advantages:
• The modulator combines the advantages of both DFB and DFF type modulators:
Only four op amps are required. The 1st integrator’s output swing is between ±VREF
for large input signal amplitudes (0.6VREF), even if the integrator gain is large (0.5).
• A local resonator is formed by the feedback around the last two integrators to further
suppress the quantization noise.
• The modulator is fully pipelined for fast settling.
†A.L. Coban and P.E. Allen, “A 1.5V, 1mW Audio  Modulator with 98dB Dynamic Range, “Proc. of 1999 Int. Solid-State Circuits Conf., Feb.
1999, pp. 50-51.
1.5V, 1mW, 98dB  Analog-Digital Converter - Continued

Integrator power dissipation vs. integrator gain
DR = 98 dB
BW = 20 kHz
Cs = 5 pF
0.5 µm CMOS
1.5V, 1mW, 98db  Analog-Digital Converter - Continued

Modulator power dissipation vs. oversampling ratio
OSR = 64
OSR = 32
OSR = 16
OSR = 8
Suppy Voltage (V)

DR = 98 dB
BW = 20 kHz
Integrator gain = 1/3
0.5µm CMOS

Circuit Implementation:
Capacitor Values 1
Capacitor Integrator 1 Integrator 2 Integrator 3 Integrator 4
Cs 5.00pF 0.15pF 0.30pF 0.10pF 1d
Ci 15.00pF 1.25pF 3.00pF 1.00pF 2
Ca - - 0.05pF - 2d
Cb1 - - - 0.12pF Fig.10.9-25
Cb2 - - - 0.10pF


Microphotograph of the  modulator.


Measured SNR and SNDR versus input level of the modulator.


Measured 4th-Order  Modulator Characteristics:

DECIMATION AND FILTERING

Delta-Sigma ADC Block Diagram
The decimator and filter are implemented digitally and consume most of the area and the
power.
fS fD<<fS
Analog DS Digital Decimation Digital

Input Modulator PPM Filter PCM Filter Output
Digital/Decimation Filter 150717-01
Function of the digital filter and digital decimator are;

1.) To attenuate the quantization noise above the baseband
2.) Bandlimit the input signal
3.) Suppress out-of-band spurious signals and circuit noise

Digital Filter
Implements a low pass filter by sampling the modulator stream of the 1-bit or multi-bit
code (PPM)
First-order averaging filter:
Modulator Delay Delay Delay
Input (PPM)
b1 b2 b3 bi
150717-02
Output
S S S
Comments: (PCM)
• The low pass filter removes the quantization noise

• With the quantization noise reduced, the output is now a high resolution digital version
of the input signal
• However, the output rate is too fast to be practical
- To use the output samples would require a very fast controller or processor
- Since a low pass filter has been applied, most of the fast samples don’t provide any
useful information
Implementation of Digital Filters†

Digital filter structures:
x(n) h(0) y(n) y(n) h(0) x(n)
Input Output Output Input
z-1 z-1
h(1) h(1)
z-1 z-1
h(2) h(2)
z-1 z-1
h(3) h(3)
z-1 z-1
h(N-1) h(N-1)
Direct-form structure Transposed direct-form

for an FIR digital filter. FIR filter structure.
Fig.10.9-29
†S.R. Norsworthy, R. Schreier, and G.C. Temes, Delta-Sigma Data Converters-Theory, Design, and Simulation, IEEE Press, NY, Chapter 13, 1997.
Digital Decimator
The purpose of the decimator is to:
1.) Reduce the sample rate from fS down to the Nyquist frequency, 2fB.
2.) Help to remove the quantization noise.
3.) Perform the anti-aliasing filtering.
Challenges for the decimator:
1.) The input sampling rate is very high which makes it difficult to implement an efficient
digital decimation filter.
2.) Higher-order modulators produce highly shaped noise and require the filter to remove
this noise with not much frequency transition region.
3.) Should not distort the magnitude and phase characteristics of the input signal in the
baseband.
Goal:
Implement the digital decimator in a minimum amount of logic and make it feasible for
integrated circuit implementation.

A Multi-Stage Decimation Filter

To reduce the number of stages, the decimation filters are typically implemented in
several stages.
Typical multi-stage decimation filter:
fs fs/D 2fN fN fN
L+1-th First-half Second-half Droop
order band filter band filter correction
Fig.10.9-26
1.) For  modulators with (1-z-1)L noise shaping comb filters are very efficient.
• Comb filters are suitable for reducing the sampling rate to four times the Nyquist
rate.
• Designed to suppress the quantization noise that would otherwise alias into the
signal band upon sampling at an intermediate rate of fs1.
2.) The remaining filtering is performed in stages by FIR or IIR filters.
• Suppresses out-of-band components of the signal
3.) Droop correction - may be required depending upon the ADC specifications
Comb Filters
A comb filter that computes a running average of the last D input samples is given as
1 D-1
y[n] = D  x[n-i]
0
i=0 -20
K=1
where D is the decimation factor given as
|HD(f)| dB
-40
K= 2
fs
D=f -60
K=3
s1
-80
The corresponding z-domain expression is,
D -100
1 1 - z-D fs 2 fs 3 fs 4 fs
HD(z) =  z-i = D 1 - z-1
0 fb
D D D D
Frequency Fig.10.9-27
i=1
The frequency response is obtained by evaluating HD(z) for z = ej2fTs,
1 sinfDTs -j2fT /D
HD(f) = D e s
sinfTs
where Ts is the input sampling period (=1/fs). Note that the phase response is linear.
For an L-th order modulator with a noise shaping function of (1-z-1)L, the required
number of comb filter stages is L+1. The magnitude of such a filter is,
 1 sinfDTs K
|HD(f)| = D 
 sinfTs 
Implementation of a Cascaded Comb Filter

Implementation:
Numerator Section
X + + +
z-1 z-1 z-1
- - - fs/D
K = L +1 Integrators
Denominator Section
+ + +
Y
- - -
z-1 z-1 z-1
K = L +1 Differentiators Fig.10.9-28
Comments:
1.) The L+1 integrators operating at the sampling frequency, fs, realize the denominator
of HD(z).
2.) The L+1 differentiators operating at the output rate of fs1 (= fs/D) realize the
numerator of HD(z).
3.) Placing the integrator delays in the feedforward path reduces the critical path from
L+1 adder delays to a single adder delay.
Digital Lowpass Filter

Example of a typical digital filter used in removal of the quantization noise at higher
frequencies
10
-20
Magnitude (dB)
-50
-80
-110 4000 Frequency (Hz)

Illustration of the Delta-Sigma ADC in Time and Frequency Domain

fS fD<<fS
Analog DS PPM Digital PCM Decimation Digital

Input Modulator Filter Filter Output
Time Time Time Time
Put nulls at aliased

frequency bands
f0 fB Freq. f0 fB 0.5fS Freq. f0 fB Freq. f0 fB fS 2fS 3fS 4fS Freq.

D D D D
150717-01

BANDPASS DELTA-SIGMA MODULATORS

Bandpass  Modulators
fS
Block diagram of a bandpass modulator:
x + y
Resonator v A/D
Components: -
u
• Resonator - a bandpass filter of order D/A
Fig.10.9-27A Quantizer
2N, N= 1, 2,....
• Coarse quantizer (1 bit or multi-bit)
The noise-shaping of the bandpass oversampled ADC has the following interesting
characteristics:
Center frequency = fs ·(2N-1)/4
Bandwidth = BW = fs /M dB
Illustration of the Frequency Spectrum (N=1): BW BW

Attenuation
Application of the bandpass  ADC is for

systems with narrowband signals (IF frequencies) 0 fs 3fs fs Frequency
4 4 Fig. 11-32

A Second-Order  Bandpass Modulator

Bandpass Resonator:
V(z) = z-1 [X(z) - z-1V(z)] = z-1X(z) - z-2V(z)

V(z) z-1
V(z) (1+z-2) = z-1X(z) → =
X(z) 1+z-2
Modulator:
Q(z)
X(z) + z-1 + Y(z)
- 1+z-2
Fig.10.9-27B
 z-1   1+z-2   z-1 

Y(z) = Q(z) + [X(z) - Y(z)]  -2  → Y(z) =  Q(z) + X(z)
1+z  1+ z-1-z-2 1+ z-1-z-2
 1+z-2 
NTFQ (z) =  
1+ z-1-z-2
The NTFQ (z) has two zeros on the j axis.

Fourth-Order Bandpass  Modulator

Block diagram:
Comments:
• Designed by applying a lowpass to bandpass transform to a second-order lowpass 
modulator
• The stabilty and SNR characteristics are the same as those of a second-order lowpass
modulator
• The z-domain output is given as,
Y(z) = z-4X(z) + (1+z-2)2Q(z)
• The zeros are located at z = ±j which corresponds to notches at fs/4.

Resonator Circuit Implementation

Block diagram of z-2/(1+z-2):
Fully differential switch-capacitor implementation:

Power Spectral Density of the Previous Fourth-Order Bandpass  Modulator

Simulated result:

DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTERS

Principles
The principles of oversampling and noise shaping are also widely used in the
implementation of  DACs.
Simplified block diagram of a delta-sigma DAC:
Input N-bit Interpolat- N-bit Digital 1-bit Analog Output

delta-sigma DAC lowpass
fN ion filter Mf MfN
N modulator MfN filter
Digital Section Analog Section
Fig10.9-29
Operation:
1.) A digital signal with N-bits with a data rate of fN is sampled at a higher rate of MfN by
means of an interpolator.
2.) Interpolation is achieved by inserting “0”s between each input word with a rate of
MfN and then filtering with a lowpass filter.
3.) The MSB of the digital filter is applied to a DAC which is applied to an analog
lowpass filter to achieve the analog output.

Block Diagram of a  DAC
Operation:
1.) Interpolate a digital word at the conversion rate of the converter (fN) up to the sample
frequency, fs.
2.) The word length is then reduced to one bit with a digital sigma-delta modulator.
3.) The one bit PDM signal is converted to an analog signal by switching between two
reference voltages.
4.) The high-frequency quantization noise is removed with an analog lowpass filter
yielding the required analog output signal.
Sources of error:
• Device mismatch (causes harmonic distortion rather than DNL or INL)
• Component noise
• Device nonlinearities
• Clock jitter sensitivity
• Inband quantization error from the - modulator
Frequency Viewpoint of the  DAC

Frequency spectra at different points of the delta-sigma ADC:
Magnitude
Input
-0.5fN 0 0.5fN fN (M-1)fN MfN Frequency

Interpolation
filter output
-0.5fN 0 0.5fN MfN Frequency

Delta-sigma
modulator
output
Lowpass
filter Quantization noise after
filtering
output

Fig10.9-33

A Third-Order,  Modulator for a DAC

A digital equivalent of the third-order MASH  modulator is shown below.
The m-bit accumulators consist of an m-bit adder and m-bit latches.

The 8-state digital output is converted to an analog through means of an analog filter.
Spectral outputs:

1-BitDAC for the  Digital-to-Analog Converter - The Analog Part

The MSB output from the digital filter is used to drive a 1-bit DAC.
Possible architectures:
A multi-bit output would consist of more parallel, controlled current sources and sinks.

Switched-Capacitor DAC and Filter

Typically, the DAC and the first stage of the lowpass filter are implemented using
switched-capacitor techniques.
It is necessary to follow the switched-capacitor filter by a continuous time lowpass filter

to provide the necessary attenuation of the quantization noise.

SUMMARY
Comparison of the Various Types of ADCs
Speed Area Dependence
A/D Converter Type Maximum (Expressed in terms on the number of
Practical Number of T a clock period) bits, N, or other
of Bits (±1) ADC parameters
Dual Slope 12-14 bits 2(2NT) Independent
Successive Approximation 12-15 bits NT N
with self-correction
1-Bit Pipeline 10 bits T (After NT delay ) N
Algorithmic 12 bits NT Independent
Flash 6 bits T  2N
Two-step, flash 10-12 bits 2T  2N/2
Multiple-bit, M-pipe 12-14 bits MT  2N/M
- Oversampled (1-bit, L
loops and M= oversampling
ratio = f clock/2fb) 15-17 bits MT L

ADC Performance Survey 1997-2015

Professor Boris Murmann, Stanford University has compiled a survey of the performance
of converters presented at ISSCC and VLSI from 1997 to 2015. This survey is found at
http://www.stanford.edu/~murmann/adcsurvey.html
Notes on the primary raw data:
Power (P) - Taken as specified by the authors. Sometimes this number includes power
for clocks, references, etc; sometimes it doesn't. For delta-sigma modulators, the power
for the decimation filter is not included. This is fair since the Nyquist converter data also
does not include any power typically needed for anti-alias filtering.
THD, (peak) SNDR, (peak) SNR, SFDR are tabulated as the values measured near fs/2
for a Nyquist converter. When this data was not available, data for lower input
frequencies is used instead. Fortunately, in recent years most Nyquist converters are
properly evaluated up to fs/2. Only older data points (before ~2003) tend to suffer from
"low frequency only" issues. Multi-GHz converters tend to roll off for frequencies much
lower than fs/2. For these designs, the SNDR at the highest reasonable/usable fin is used
(example: ISSCC 2003, paper 18.2, fs = 20GHz, SNDR measured at fin=6GHz).
DR is the measured "instantaneous dynamic range" of the converter, i.e. this metric does
not contain any extra dBs obtained through variable gain.

ADC Performance Survey - Continued

Energy versus resolution:
1.E+07
1.E+06
1.E+05
1.E+04
P/fsnyq [pJ]
1.E+03
1.E+02
ISSCC 2015
VLSI 2015
1.E+01
ISSCC 1997-2014
VLSI 1997-2014
1.E+00
FOMW=5fJ/conv-step
FOMS=175dB
1.E-01
10 20 30 40 50 60 70 80 90 100 110 120
SNDR @ fin,hf [dB]

ADC Performance Survey - Continued

Bandwidth versus resolution:
1.E+11
ISSCC 2015
VLSI 2015
1.E+10
ISSCC 1997-2014
VLSI 1997-2014
1.E+09
Jitter=1psrms
Jitter=0.1psrms
fin,hf [Hz]
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
10 20 30 40 50 60 70 80 90 100 110 120
SNDR @ fin,hf [dB]

CONCLUDING THOUGHTS
• What is analog circuit design?
The complex process of creating circuit solutions using analog circuit techniques.
• What is the analog integrated circuit design process?
The even more complex process of combining analog design with IC technology
which includes electrical, physical and test design.
• What are the key principles, concepts and techniques for analog IC design?
Key principles – Fundamental laws
Key concepts – Important relationships and ideas
Key techniques – Tools that allow simplification
or insight
• How can the analog IC designer enhance creativity
Technology changes but principles, concepts
and solve new problems in today’s industrial and techniques remain the same.
environment?
Learn the key principles, concepts and techniques
of analog circuit design
Learn from mistakes
Learn the technology
Always try to understand the concept and operation
of the circuit, never rely on a computer or someone else for this understanding
Lecture 01 – (8/9/18) Page 1-1
LECTURE 1 – CMOS PHASE LOCKED LOOPS

OVERVIEW
Objective
Understand the principles and applications of phase locked loops using integrated circuit
technology with emphasis on CMOS technology.
Topics
• Background
• Fundamentals
Organization Systems Types of PLLs PLL
Perspective and PLL Measurements Applications and Examples
Circuits PLL
Perspective Components
Technology CMOS
Perspective Technology
CMOS Phase Locked Loops 140418-02 © P.E. Allen - 2018

Lecture 01 – (8/9/18) Page 1-2
Suggested References
Phase Locked Loops:
1. F.M Gardner, Phaselock Techniques, 2nd ed., John-Wiley & Sons, Inc., NY, 1979.
2. B. Razavi (ed.), Monolithic Phase-Locked Loops and Clock Recovery Circuits, IEEE
Press, 1997.
3. R.E. Best, Phase-Locked Loops: Design, Simulation, and Applications, 4th edition,
McGraw-Hill, 1999
4. A. Hajimiri and T.H. Lee, The Design of Low Noise Oscillators, Kluwer Academic
Publishers, 1999.
5. B. Razavi, Design of ICs for Optical Communications, McGraw-Hill, 2003.
6. T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edition,
Cambridge University Press, NY, 2004.
7. C. Quemada, et al, Design Methodology for RF CMOS Phase Locked Loops, Artech
House, Norwood, MA, 2009.
CMOS Phase Locked Loops © P.E. Allen - 2018

Lecture 01 – (8/9/18) Page 1-3
OPERATING PRINCIPLES OF PLLs

What is a PLL?
A PLL contains three basic components as shown below:
Input Error
Signal Phase Signal Loop
Frequency Filter
Detector
Oscillator
Output Contolling
Voltage Voltage
Signal
Controlled
Oscillator 140418-01
• Phase/frequency detector determines the difference between the phase and/or frequency
of two signals
• The loop filter removes the high-frequencies from the voltage-controlled oscillator
(VCO) controlling voltage
• The VCO produces and output frequency controlled by a voltage

Lecture 01 – (8/9/18) Page 1-4
More Detailed PLL Block Diagram
vin(t) – The input or reference signal

in – The radian frequency of the input signal
vosc(t) – The output of the VCO
osc – The radian frequency of the VCO
vd(t) – The detector output voltage = Kde
e – Phase error between vin(t) and vout(t) = in - osc
vc(t) – The output voltage of the loop filter and the control voltage for the VCO

Lecture 01 – (8/9/18) Page 1-5
The Phase Detector and VCO in more Detail

Phase Detector:
vd(t) = Kde = Kd(in - osc)
where
Kd is the gain of the phase detector
in = phase shift of the input voltage
osc = phase shift of the VCO output voltage
The units of Kd are volts/radians or simply volts assuming all phase shifts are in
radians and not degrees.
Voltage Controlled Oscillator:

osc = o + Ko vc(t)
where Ko is the VCO gain and o is the free-running radian frequency.
The units of Ko are rads/sec·V or simply (sec·V)-1 assuming all phase shifts are in
radians and not degrees.

Lecture 01 – (8/9/18) Page 1-6
PLL Operation
Locked Operation:
• The loop is locked when the frequency of the VCO is exactly equal to the average
frequency of the input signal.
• The PLL has the inherent ability to suppress noise superimposed on its input signal.
• To maintain the control voltage needed for locked conditions, it is generally necessary
for the output of the phase/frequency detector to be nonzero.
Unlocked Operation:
• The VCO runs at a frequency called the free running frequency, o, which corresponds
to zero control voltage.
• The capture process is the means by which the loop goes from unlocked, free-running
state to that of the locked state.

Lecture 01 – (8/9/18) Page 1-7
Transient Response of the PLL

Assume the input frequency is increased vin(t)
by an amount .
1.) in increases by  at to.
vosc(t) t
2.) The input signal leads the VCO and vd
begins to increase.
3.) After a delay due to the loop filter, the
VCO increases osc. t
4.) As osc increases, the phase error vd(t) Instantaneous values of vd

reduces.
5.) Depending on the loop filter, the final t
win
phase error will be reduced to zero or
wo Dw
to a finite value.
t
wosc
wo Dw
to t
140420-06

Lecture 01 – (8/9/18) Page 1-8
CLASSIFICATION OF PLL TYPES

Types of PLLs
PLL Type Phase Detector Loop Filter Controlled Oscillator

Linear PLL (LPLL) Analog multiplier RC passive or active Voltage
Digital PLL (DPLL) Digital detector RC passive or active Voltage
All digital PLL Digital detector Digital filter Digitally controlled
(ADPLL)
Software PLL Software multiplier Software filter Software oscillator
(SPLL)
The digital PLL (DPLL) has been the mainstay of most PLLs and is called the “classical”
digital PLL.

Lecture 01 – (8/9/18) Page 1-9
The Linear PLL (LPLL)
Input Error
Signal Signal Analog
Analog
Loop
Multiplier
Filter
Oscillator
Output Controlling
Voltage Voltage
Signal
Controlled
• Uses a analog multiplier for the PDF

• Loop filter is active or passive analog
• VCO is analog

Lecture 01 – (8/9/18) Page 1-10
The Digital PLL (DPLL)
Input
Signal Error Controlling
Signal Analog
Digital Voltage
Loop
Detector
Filter
Oscillator
Output
¸N Signal Voltage
Counter Controlled
(optional) Oscillator 140418-05
• Phase detector is digital

• Loop filter is passive of active analog
• VCO is analog
• Called the “Classical Digital PLL”

Lecture 01 – (8/9/18) Page 1-11
The All-Digital PLL (ADPLL)
Input Digital
Signal Error
Digital Signal Digital Loop
Detector Filter
Oscillator Controlling
Output Digital Signal
Digitally
Signal
Controlled
Oscillator
Fixed
Oscillator
(Clock) 140418-06
• Phase detector is digital

• Loop filter is digital
• VCO is digital
• Compatible with modern CMOS technology

Lecture 01 – (8/9/18) Page 1-12
The Software PLL (SPLL)
Input Output
Signal Analog- Software Digital- Signal
Digital PLL Analog
Converter Converter
Clock
140418-07
• Phase detector is implemented in software

• Loop filter is implemented in software
• Oscillator is implemented in software driven by an external clock
• Requires analog to digital conversion at the input and digital to analog conversion at
the output
• Software permits reconfiguring of the PLL

Lecture 01 – (8/9/18) Page 1-13
SYSTEMS PERSPECTIVE OF LINEAR PHASE LOCK LOOPS (LPLLs)

Introduction
Objective:
Understand the operating principles and classification of LPLLs.
Organization:
Systems Types of PLLs PLL

Circuits PLL
Technology CMOS
140418-08

Lecture 01 – (8/9/18) Page 1-14
Outline
• LPLL Blocks
• Locked State
• Order of the LPLL System
• The Acquisition Process - Unlocked State
• Noise in the LPLL
• LPLL System Design
• Simulation of LPLLs

Lecture 01 – (8/9/18) Page 1-15
LPLL BLOCKS
Building Blocks of the LPLL
v1(t) w1
Phase
vd(t) Low Pass
w2 Detector
Filter
(Multiplier)
v2(t) Voltage vf(t)

Controlled
v1(t) = Input signal, generally sinusoidal

v2(t) = VCO output signal, may be sinusoidal or square wave
vd(t) = Phase detector output signal
vf(t) = Loop filter output signal and controlling signal to the VCO
1 = Frequency of the input signal
2 = Frequency of the VCO

Lecture 01 – (8/9/18) Page 1-16
Loop Filters
In the PLL, there are many high frequencies including noise that must be removed by
the use of a low pass filter in order to achieve optimum performance.
Types of Loop Filters:
1.) Passive lag filter (lag-lead)
1 + s2
F(s) = where 1 = R1C and 2 = R2C
1 + s(1 + 2)
|F(jw)| dB
R1
0dB
+ + -20 dB/decade
R2
Vd Vf
C t2
- - t1+t2 dB
1 1 log10(w)
140419-01 t1+t2 t2
Pole is at 1/(1+2) and the zero at 1/2.

• Since the pole is smaller than the zero, the filter is lag-lead
• Passive filters should have no amplitude nonlinearity
Lecture 01 – (8/9/18) Page 1-17
Loop Filters - Continued

2.) Active Lag filter
1 + s2 C1
F(s) = Ka where 1 = R1C1, 2 = R2C2 and Ka = - C
1 + s1 2
• Easier to make lead-lag

• Can have gain (not necessarily desirable)
• Limited by the linearity and noise of the op amp

Lecture 01 – (8/9/18) Page 1-18
Loop Filters - Continued

3.) Active Proportional-Integral (PI) Filter
1 + s2
F(s) = where 1 = R1C and 2 = R2C
s1
• Has large open loop gain at low frequencies  Large hold range
• Limited by the linearity and noise of the op amp
• Gain limits at the op amp open loop gain
Stability:
To keep the loop stable, it is important to pick the loop filter so that it does not
introduce more than a 90° phase shift in the loop.

Lecture 01 – (8/9/18) Page 1-19
Phase Signals
It is important to remember that frequency and phase are related as
d
dt =  →  =  ·dt
Transfer functions:
V2(s)
H(s) = V (s)
1
where V2(s) and V1(s) are the Laplace transforms of v2(t) and v1(t).
To examine phase signals, let us assume that,

v1(t) = V10 sin[1t + 1(t)] and v2(t) = V20 sin[2t + 2(t)]
For phase signals, the information is carried only in (t).
Next, we consider some simple phase signals that are used to excite a PLL.

Lecture 01 – (8/9/18) Page 1-20
Phase Signals – Continued v1(t)

1.) A step phase shift which is an example of phase
modulation. t
1(t) =  u(t)
q1(t)
DF
t
140419-04
2.) A step frequency change assuming that 1(t) = o v1(t)

for t < 0. We may express v1(t) as,
v1(t) = V10 sin[ot +  ·t] t
= V10 sin[ot + 1(t)] w1(t)

 1(t) =  ·t Dw
t
(the phase becomes a ramp signal)
q1(t)
Dw
t
140419-05

Lecture 01 – (8/9/18) Page 1-21
Phase Signals – Continued

3.) Frequency ramp
v1(t)
 (t) =  + · ·t
1 o
where · is the rate of change of the angular t

frequency.
t  w1(t)
  
 v1(t) = V10 sin (o +· )d
wo .
0  Slope = Dw
 t
· t2  q1(t)
= V10 sinot + 2 
 
· t2
1(t) =  2 t
140419-06

Lecture 01 – (8/9/18) Page 1-22
SUMMARY
• LPLL blocks are:
1.) Multiplying phase detector
2.) Low pass filter
3.) Voltage controlled oscillator
• Locked state: Input frequency = VCO frequency
The phase response is low pass
The phase error response is high pass

Lecture 02 – (8/9/18) Page 2-1

Topics
• Locked state of the LPLL
• Order of the LPLL
Organization:

Circuits PLL
Technology CMOS
140418-02

Lecture 02 – (8/9/18) Page 2-2
LOCKED STATE OF THE LPLL

Transfer Function of the Phase Detector
Input sinusoidal and VCO sinusoidal:
v1(t) = V10 sin[1t + 1(t)] and v2(t) = V20 cos[2t + 2(t)]
 vd(t) = v1(t)· v2(t) = V10V20 sin[1t + 1(t)]cos[2t + 2(t)]
V10V20 V10V20
= 2 sin[1t + 1(t) - 2t - 2(t)] - 2 sin[1t + 1(t) + 2t + 2(t)]
If the loop is locked, then 1 = 2 and
V10V20 V10V20
vd(t) = sin[1(t) -2(t)] - sin[21t + 1(t) + 2(t)]
2 2
Ignoring the high-frequency terms gives,
V10V20 V10V20
vd(t)  2 sin[1(t) -2(t)] = 2 sine(t) = Kd sine(t)  Kd e(t)
if e(t) is small.
V10V20
Kd = detector gain = 2
 vd(t)  Kd e(t)  Vd(s)  Kd e(s)

Lecture 02 – (8/9/18) Page 2-3
Transfer Function of the Phase Detector – Continued

Input signals when VCO output is a square wave:
v1(t) = V10 sin[1t + 1(t)]
4 4 
v2(t) = V20 sgn[2t + 2(t)] = V20 cos[2t + 2(t)] + cos[32t + 2(t)] + ···
 3 
 vd(t) = v1(t)· v2(t)
4 4 
= V10V20 sin[1t + 1(t)]  cos[2t + 2(t)] + cos[32t + 2(t)] + ···
 3 
4V10V20
=

 1 
sin[1t + 1(t)]cos[2t + 2(t)] + 3 cos[2t + 2(t)]cos[32t + 2(t)] + ···


 
When the loop is locked,

2V10V20 
sin[1(t) -2(t)] + sin[21t + 1(t) + 2(t)]+ ···

vd(t) =

2V10V20
 sine(t) = Kd sine(t) → vd(t)  Kd e(t)

where the detector gain is Kd = 2V10V20/ (a little better than sinusoidal inputs only)
CMOS Phase Locked Loops Vd(s) © P.E. Allen - 2018
The transfer function is Vd(s)  Kd e(s) or = Kd
e(s)
Lecture 02 – (8/9/18) Page 2-4
VCO Transfer Function

The angular frequency of the VCO was expressed as,
2(t) = o + 2(t) = o + Ko vf(t)
where Ko is the VCO gain in units of radians/sec or simply sec -1.
However, what we want is the phase of the VCO output.
 2(t) = 2 dt = Kovf(t)dt

|Q2(jw)|
Taking the Laplace transform gives,
Ko 2(s) Ko
2(s) = L[2(t)] = s Vf(s) → V (s) = s
f
1 w
Ko
140419-07

Lecture 02 – (8/9/18) Page 2-5
Linear Model of the LPLL

Phase Detector
Vd(s) = Filter
Q1(s) + Qe(s) KdQe(s)
Kd F(s)
- Q2(s)
VCO
K
Q2(s) = o Vf(s) Ko Vf(s) =F(s)Vd(s)
s
s
140419-08
Phase transfer function:
2(s)
H(s) = =?
1(s)
Ko Ko KoKd KoKd
2(s) = s Vf(s) = s F(s)Vd(s) = s F(s)e(s) = s F(s)[1(s) - 2(s)]
s2(s) = KoKdF(s)[1(s) - 2(s)] → 2(s)[s + KoKdF(s)] = KoKdF(s)1(s)
2(s) KoKdF(s) e(s) s
 H(s) = = s + K K F(s) Also, He(s) = = 1- H(s) = s + K K F(s)
1(s) o d 1(s) o d

Lecture 02 – (8/9/18) Page 2-6
LPLL Transfer Function for Various Loop Filters

1.) Passive lag filter.
1+s2
KoKd 
1 + s2 1+2 
F(s) = → H(s) =
1 + s(1 + 2) 1+ KoKd2 KoKd
s + s
2 +
 1 2  1+2
+ 
2.) The active lag filter.
1+s2 
KoKdKa 
1 + s2 
 1 
F(s) = Ka → H(s) =
1 + s1 1+ KoKdKa2 KoKdKa
s2 + s +
 1  1
3.) The active PI filter.
1+s2
KoKd 
1 + s2 
 1 
F(s) = → H(s) =
s1 KoKd2 KoKd
s + s
2 +
 1  1+2

Lecture 02 – (8/9/18) Page 2-7
Normalized Form of the Transfer Functions

The normalized form of the denominator of a second-order transfer function is
D(s) = s2 + 2ns + n2
where n is the natural frequency and  is the damping factor.
KoKd n  1 
n = and  = 2 2 + K K 
1+2  o d
2.) Active lag filter.
KoKdKa n  1 
n = and  = 2 2 + K K K 
1  o d a
3.) Active PI filter.
KoKd n2
n = and = 2
1

Lecture 02 – (8/9/18) Page 2-8
Normalized Phase Functions

 n 
sn2 - K K  + n2
 o d
H(s) =
s2 + 2ns + n2
2.) Active lag filter.
 n 
sn2 -  + n2
 KoKdKa 
H(s) =
s2 + 2ns + n2
3.) Active PI filter.
2sn + n2
H(s) = 2
s + 2ns + n2
If KdKo >> n or KdKoKa >> n (high loop gain), then all of the above transfer functions
simplify to,
2sn + n2 s2
H(s) ≈ 2 and He(s) ≈
s + 2ns + n2 s2 + 2ns + n2

Lecture 02 – (8/9/18) Page 2-9
Frequency Response of H(s)

Bode diagram:
10
z = 5.0
0
z = 3.0
|H(jw)| dB
-10
z = 0.3
z = 0.5
-20
z = 0.707
z = 1.0
-30
-40
0.1 1 w 10 100
wn 140419-10
Frequency response is normalized to /n.

Lecture 02 – (8/9/18) Page 2-10
Phase Step Response


Assume that 1(t) =  ·u(t) → 1(s) = s
Phase error:
 s2
e(s) = He(s) s = 2
s(s + 2ns + n2)
  
2 t e-nt ,  < 1
e(t) = L-1[e(s)] =  cos 1- 2nt - sin 1-
1-
n
 2 
= (1 - nt)e-nt,  =1
  2-1 t e-nt ,  > 1
=  cosh  2-1nt - sinh  n
  2-1 
Steady state error:
e() = lim se(s) = 0
s→0

Lecture 02 – (8/9/18) Page 2-11
Phase Step Response - Continued

Plot of the phase step response:
e(t)

nt

Lecture 02 – (8/9/18) Page 2-12
Frequency Step Response

Assume that 1(t) = o +  · u(t)

However, 1(t) =  ·t → 1(s) = s2
Phase error:
 s2 
e(s) = He(s)1(s) = He(s) s2 = 2 2 =
s (s + 2ns + n2) s2 + 2ns + n2
  1  - t
e(t) = L-1[e(s)] =   n , <1
n  1 -  2 n e
sin 1- 2 t


= (nt)e-nt,  =1
n
  1 2-1  t e-nt,  > 1
=  sinh 
n   2-1 n

Steady state error:
e() = lim se(s) = 0 (high gain loops, KdKo or KdKoKa >>n)
s→0

e() = K K F(0) (low gain loops)
d o

Lecture 02 – (8/9/18) Page 2-13
Frequency Step Response - Continued

Plot of the frequency step response:
e(t)
/n
nt

Lecture 02 – (8/9/18) Page 2-14
Example 1 – Frequency Step Response

Phase Detector
A linear model of a PLL is shown. (a.) Solve for LPF VCO
win + wout
the closed-loop transfer function of out(s)/in(s). Kd 1 Ko
- 1+st
Compare this transfer function with the following
transfer function and identify , H, n, and . 1
s 140420-01
out(s) Hn2
=
in(s) s2 + 2n s + n2
(b.) If  < 1, the step response to in(t) = ·µ(t) is given as
 1 
nt sinn 1-2t +   where  = sin-1 1-2
out(t) = H·µ(t)1 - e-
 1-2 
Assume that Kv = KoKd = 63.58x103 rads/sec. and  = 8µsec. If the output frequency is to
be changed from 901 MHz to 901.2 MHz, how long does the PLL output frequency take
to settle with 100 Hz of its final value? Simplify your analysis by assuming worst case
conditions (i.e. Maximum value of sin(x) = 1).
Solution
Find the transfer function in terms of phase and then convert to frequency.
Ko 1   Kv  Kv
out(s) =  s   K [ (s)-out(s)] → out(s)1+ = in(s)
 s+1 d in  s(s+1)  s(s+1)

Lecture 02 – (8/9/18) Page 2-15
Example 1 - Continued
where Kv = KoKd. Solving for the phase transfer function gives,
out(s) out(s) Kv/
= =
in(s) in(s) s2 + (s/) + (Kv/)
Kv 1
Therefore, n = = 89.148 krads/sec. = = 0.701 and H =1
 2 Kv
(b.) The frequency response can be written as
 1 
nt sinn 1-2t + µ(t)
fout(t) = 200kHz 1 - e-
 1-2 
Setting fout(ts) = 200kHz – 100Hz, gives
 1 
nts sinn 1-2ts +  
200x103-100 = 200x1031 - e-
 1-2 
This equation simplifies to the following assuming the value of the sin (x) is 1.
100Hz 1 1
= e-nts sinn 1-2ts +   e-nts
200kHz 1-2 1-2
2000 1
e n t s = = 2800 → ts = ln(2800) = 2( 7.9375) = 127µsec.
1-2 n

Lecture 02 – (8/9/18) Page 2-16
Frequency Ramp Response

Assume that  (t) =  + · ·t
1 o
· t2 ·
However, 1(t) =  2 → 1(s) = s3
Phase error:
· · s2 ·
e(s) = He(s) s3 = 3 2 =
s (s + 2ns + n2) s(s2 + 2ns + n2)
· ·   
e(t) = L-1[e(s)] = 2 - 2 cos 1- 2nt + sin 1- 2 t e-nt ,  < 1
n n  1+2 n

· ·
= 2 - 2 (1 + nt)e-nt,  =1
n n
· ·   
2-1 t e-nt ,  > 1
= 2 - 2 cosh  2-1nt + sinh 
n n   2-1
n

Steady state error:
· · t ·
e() = lim se(s) = 2 (High loop gain) e() = K K F(0)2 + 2 (Low loop gain)
s→0 n d o n
Lecture 02 – (8/9/18) Page 2-17
Frequency Ramp Response

Plot of the frequency ramp step response:
e(t)
· /n2
nt

Lecture 02 – (8/9/18) Page 2-18
THE ORDER OF A LPLL SYSTEM

Definition of Order
The number of roots in the denominator (poles) of the PLL transfer function
determines the order.
Generally, the order of a PLL is one greater than the order of F(s).
Implication of the order:
• Greater than 2 will be unstable unless corrected by zeros
• Less than 2 will have poor noise suppression.

Lecture 02 – (8/9/18) Page 2-19
First-Order PLL
A first–order PLL occurs when F(s) = 1. From previous results we have,
2(s) KoKd s
H(s) = = Also, He(s) = 1- H(s) = s + K K
1(s) s + KoKd o d
The –3dB bandwidth of H(s) is KoKd.
Comments:
• F(s) causes the –3dB bandwidth to be reduced in higher-order systems which means
that the first-order PLL has a wider bandwidth
• The hold range of the first-order PLL will be larger than for higher-order PLLs
• The first-order PLL will track the signal variations more quickly than higher-order
PLLs
• The first-order PLL does not suppress noise superimposed on the input signal to the
extent of higher-order PLLs.

Lecture 02 – (8/9/18) Page 2-20
Higher-Order PLLs
Comments:
• Generally F(s) has a pole and a zero in order to get better noise rejection without
sacrificing speed.
Open Loop Gain
-20dB/decade
-40dB/decade First-order
Bandwidth
0 dB
Pole Zero
-20dB/decade
140420-02
• If the phase shift of the open loop system is more than 90°, the stability of the loop may
be poor ( is small).

Lecture 02 – (8/9/18) Page 2-21
Example 2- Buffering the PLL Output

In many practical applications, it is necessary to buffer the VCO output signal. Assume
that the buffer has a voltage gain of 1 and its output is corrupted by an additive white
noise voltage of Vb,n. LPF VCO Buffer Vb,n
qin + qout' +
(a.) Find the output phase, out(s), as a 1 Ko
s +1
+ qout
st+1
function of the input phase in(s) and the -
output noise of the buffer, Vb,n, for the 140420-03
PLL shown with the buffer outside of the PLL loop. Give an approximate sketch for
magnitude response of out(j)/Vb,n assuming  = 0.707.
Buffer Vb,n
(b.) Find the output phase, out(s), as a qin LPF VCO
+
+ 1 Ko + qout
function of the input phase in(s) and - st+1 s +1
the output noise of the buffer, Vb,n, for

140420-04
the PLL shown with the buffer inside
the PLL loop. Give an approximate sketch for magnitude response of out(j)/Vb,n
assuming  = 0.707.
(c.) Which of the two PLL architectures leads to an output spectrum with less noise
assuming that the input and VCO are noise free? How would your answer change if the
input signal to the PLL was noisy? Why?
Lecture 02 – (8/9/18) Page 2-22
Example 2 – Continued
Solution
Ko KvF(s)
(a.) out’(s) = s F(s)Kd[in(s)-out’(s)] → out’(s) = s+K F(s) in(s)
v
Substituting for F(s) gives
Kv/ n2
out’(s) = 2  (s) = 2  (s)
s +(s/)+(Kv/) in s +s2n+n2 in
n2
out(s) = out’(s) + Vb,n = 2  (s) + Vb,n(s)
s +s2n+n2 in
Ko
(b.) out(s) = s F(s)Kd[in(s)-out(s)] + Vb,n(s)
 KvF(s) KvF(s)
out(s)1+ s  = s in(s) + Vb,n(s)
 
KvF(s) s Kv/ s2+(s/)
out(s)=s+K F(s) in(s)+s+K F(s) Vb,n(s) = 2 in(s)+ 2 Vb,n(s)
v v s +(s/)+(K v/ ) s +(s/)+(K v/ )
n2 s2+s2n
out(s) = 2  (s) + 2 V (s)
s +s2n+n2 in s +s2n+n2 b,n
Lecture 02 – (8/9/18) Page 2-23
The sketch for both parts (a.) and (b.) is shown below.
20
Noise from buffer (part a.)
0
Closed-loop response
-20
dB
Noise from buffer (part b.)
-40
-60
-80
0.01 0.1 1 10 100
w/wn 140420-05
(c.) Obviously, part (b.) leads to an output spectrum with less noise. Part (a.) has the
same noise contribution from the buffer regardless of the frequency. If the input is noisy
then it will have a spectrum shown above similar to the closed-loop response. When the
input noise is larger than the buffer noise, there is not much difference between the two
architectures.

Lecture 02 – (8/9/18) Page 2-24
SUMMARY
• Unlocked state:
- Hold range (H) – frequency range over which a PLL can statically maintain phase
- Pull-in range (P) - frequency range within which a PLL will always lock
- Pull-out range (PO) – dynamic limit for stable operation of a PLL
- Lock range (L) - frequency range within which a PLL locks within one single-beat
note between reference frequency and output frequency
• The order of a PLL is equal to the number of poles in the open-loop PLL transfer
function

Lecture 03 – (8/9/18) Page 3-1

Topics
• The acquisition process – unlocked state
• Noise in linear PLLs
Organization:

Circuits PLL
Technology CMOS
140418-02

Lecture 03 – (8/9/18) Page 3-2
THE ACQUISTION PROCESS – LPLL IN THE UNLOCKED STATE

Unlocked Operation
If the PLL is initially unlocked, the phase error, e, can take on arbitrarily large values
and as a result, the linear model is no longer valid.
The mathematics behind the unlocked state are beyond the scope of this presentation. In
the section we will attempt to answer the following questions from an intuitive
viewpoint:
1.) Under what conditions will the LPLL become locked?
2.) How much time does the lock-in process require?
3.) Under what conditions will the LPLL lose lock?

Lecture 03 – (8/9/18) Page 3-3
Some Definitions of Key Performance Parameters

1.) The hold range (H) is the frequency range over which an LPLL can statically
maintain phase tracking. A PLL is conditionally stable only within this range.
Hold-In Range (Static Limits of Stability)
w
wo-DwH wo wo+DwH 140421-01
2.) The pull-in range (P) is the range within which an LPLL will always become
locked, but the process can be rather slow.
Pull-in Range
w
wo-DwP wo wo+DwP 140421-02
3.) The pull-out range (PO) is the dynamic limit for stable operation of a PLL. If
tracking is lost within this range, an LPLL normally will lock again, but this process can
be slow.
(Dynamic Limits of Stability)
w
wo-DwPO wo wo+DwPO 140421-03
4.) The lock range (L) is the frequency range within which a PLL locks within one
single-beat note between reference frequency and output frequency. Normally, the
operating frequency range of an LPLL is restricted to the lock range.
Lock Range
w
wo-DwL wo wo+DwL 140421-04

Lecture 03 – (8/9/18) Page 3-4
Illustration of Static Ranges

Assume the frequency of the VCO is varied very slowly from a value below o-H to a
frequency above o+H.
wVCO
Hold-in Range
Pull-in Range
wo-DwH wo-DwP
win
wo+DwP wo+DwH
140421-05
The following pages will attempt to relate the key parameters of hold range, pull-in
range, pull-out range, and lock range to the time constants, 1 and 2 and the gain factors
Kd, Ko, and Ka.
Lecture 03 – (8/9/18) Page 3-5
Hold Range (H)

The magnitude of the hold range is calculated by finding the frequency offset of the input
that causes a phase error of ±/2.
Let,

1 = o ± H → 1(t) = H t → 1(s) =
s2
 s
 e(s) =1(s) He(s) =
s2 s + KoKdF(s)

lim  (t)
= lim se(s) = K K F(0) (valid for small values of e)
t→ e s→0 o d
For large variations, we write
H
lim sine(t) = → H = ±KoKdF(0) when e = ±/2
t→ KoKdF(0)
For the various filters-
1.) Passive lag filter: H = ±KoKd
2.) Active lag filter: H = ±KoKdKa
3.) Active PI filter: H = ±
(If H = ± the actual hold range may be limited by the frequency range of the VCO)
Lecture 03 – (8/9/18) Page 3-6
Lock Range (L)

Assume the loop is unlocked and the reference frequency is 1 = o + . Therefore,
v1(t) = V10 sin(ot +  t)
The VCO output is assumed to be
v2(t) = V20 sgn(ot)
 vd(t) = Kd sin( t) + higher frequency terms
Assuming the higher frequency terms are filtered out, the filter output is
vf(t)  Kd|F(j)| sin( t)
This signal causes a frequency modulation of the VCO output frequency as shown.
Frequency
w1
KoKd|F(jDw)|
Dw
wo
w2(t)
t
140421-06
Note: No locking occurs in the above illustration because  > KoKd |F(j)|.

Lecture 03 – (8/9/18) Page 3-7
Lock Range – Continued

Locking will take place if KoKd |F(j)| ≥ . Therefore, the lock range can be
expressed as,
L = ± KoKd |F(j)|
and is illustrated as,
Frequency
w2 = w1
KoKd|F(jDw)|
w1
w2(t) Dw
wo
t
140421-07
Locks within one cycle or beat note.

Lecture 03 – (8/9/18) Page 3-8
Lock Range - Continued

If we assume that the lock range is greater than the filter frequencies, 1/ 1 and 1/2, the
lock range for the various filters can be expressed as,
2 2
1.) Passive lag filter: L = ± KoKd |F(j)|  ± KoKd  ± KoKd
1+2 1
2
2.) Active lag filter: L = ± Ka |F(j)|  ± Ka
1
2
3.) Active PI filter: L = ± |F(j)|  ±
1
Previously, we found expressions for n and  for each type of filter. Using these
expressions and assuming that the loop gain is large, we find for all three filters that
L  ±2n
The lock-in time or settling time can be approximated as one cycle of oscillation,
1 2
TL  f =
n n

Lecture 03 – (8/9/18) Page 3-9
Pull-In Range (P)

Again assume the loop is unlocked and the reference frequency is 1 = o +  and the
VCO initially operates at the center frequency of o.
Let us re-examine the previous considerations:
Frequency
w1
Dwmin Dwmax Pull-in Effect
w2
wo
w2(t)
140421-08
t
Since min is less than max, the frequency of the positive going sinusoid is less than
the frequency of the negative going sinusoid. As a consequence, the average value of the
__
VCO output, 2 , “pulls” toward 1.

Lecture 03 – (8/9/18) Page 3-10
The Pull-In Process

For an unlocked PLL with the frequency offset, , less than the pull-in range, P, the
VCO output frequency, 2 will approach the reference frequency, 1, over a time
interval called the pull-in time, TP.
Illustration:
Frequency
w1
w2
Dw
wo w2(t)
Pull-in Time, TP t
140421-09

Lecture 03 – (8/9/18) Page 3-11
Pull-In Range (P) for Various Types of Filters

The mathematical treatment of the pull-in process is beyond the scope of this
presentation†. The results are summarized below.
Type of Filter P (Low Loop Gains) P (High Loop Gains) Pull-In Time, TP
Passive Lag 
4
2nKoKd - n
4 2 2 o2

2  nKoKd = 16
 n3
Active Lag 4 n2 4 2 2 o2Ka
 2nKoKd - K  nKoKd = 16
 a  n3
Active PI Lag → → 2 o2
= 16
n3
† R.M. Best, Phase-Locked Loops – Design, Simulation, and Applications, 4th ed., McGraw-Hill Book Co., 1999, Appendix A.
Lecture 03 – (8/9/18) Page 3-12
Example 3
A second-order PLL having a passive lag loop filter is assumed to operate at a center
frequency, fo, of 100kHz and has a natural frequency, fn, of 3 Hz which is a very narrow
band system. If  = 0.7 and the loop gain, KoKd = 2·1000 sec.-1, find the lock-in time,
TL, and the pull-in time, TP, for an initial frequency offset of 30 Hz.
Solution
1 1
TL  = = 0.333 secs.
fn 3
2 o2 44 fo2  302
TP = = = = 4.675 secs.
16 n3 16·83 fn3 32(0.7)33

Lecture 03 – (8/9/18) Page 3-13
Pull-Out Range (PO)

The pull-out range is that frequency step which causes a lock-out if applied to the
reference input of the PLL.
An exact calculation is not possible but simulations show that,
PO ≈ 1.8n ( +1)
At any rate, the pull-out range for most systems is between the pull-in range and the lock-
range,
L < PO < P

Lecture 03 – (8/9/18) Page 3-14
Steady-State Error of the PLL

The steady-state error is the deviation of the controlled variable from the set point after
the transient response has died out. We have called this error, e().
s
e() = lim se(s) = lim s1(s) s + K K F(s)
s→0 s→0 o d
Let us consider a generalized filter given as,
P(s)
F(s) =
Q(s)sN
where P(s) and Q(s) can be any polynomials in s, and N is the number of poles at s = 0.
s2sNQ(s)1(s)
 e() = lim
s→0 s·sNQ(s) + KoKdP(s)
Comments:
• Note that for the active PI filter, N = 1.
• For N >1, it becomes difficult to maintain stability.
• In most cases, P(s) is a first-order polynomial and Q(s) is a polynomial of order 0 or 1.
To find the steady-state error, the input, (s) must be known. We will consider several
inputs on the following slide.

Lecture 03 – (8/9/18) Page 3-15
Steady-State Error for Various Inputs

1.) A phase step, .

1(s) = s
s2sNQ(s)
 e() = lim = 0 for any value of N.
s→0 s[s·sNQ(s) + KoKdP(s)]
2.) A frequency step, .


1(s) =
s2 s2sNQ(s)
 e() = lim = 0 if N ≥1
s→0 s2[s·sNQ(s) + KoKdP(s)]
(The LPLL must have one pole at s = 0 for the steady-state error to be zero.)
3.) A frequency ramp, · .
·
1(s) =
s3
s2sNQ(s)·
 e() = lim = 0 if N ≥ 2
s→0 s3[s·sNQ(s) + KoKdP(s)]
For N = 2 and Q(s) =1, the order of the LPLL becomes 3 permitting a phase shift of
nearly 270° which must be compensated for by zeros to maintain stability.
Lecture 03 – (8/9/18) Page 3-16
NOISE IN LINEAR PLL SYSTEMS

Phase Noise
Illustration:
v1(t)
qn1(t)
v1(t)+qn1(t)
t
Phase error
140421-10

Lecture 03 – (8/9/18) Page 3-17
PLL for Noise Analysis

Assume that the input is band limited as shown below.
Prefilter
Attenuation (dB)
Input
Signal Phase Output
Filter
Bi Detector
f
fo
VCO
140421-11
Bi = Bandwidth of the prefilter (or system)

Some terminology:
• Power spectral density is the measure of power in a given frequency range (Watts/Hz)
or (V2/Hz). It is found by dividing the rms power by the bandwidth.
• Consider all noise signals as white noise which means the power spectrum is flat.
• Ps = input signal rms power (V1(rms)2/Rin)
• Pn = rms power of the input noise

Lecture 03 – (8/9/18) Page 3-18
Power Spectra of a PLL

Illustration of how input noise
becomes phase noise in the Area = P s
Spectral Power
frequency spectrum:
Density
Power spectra of the reference Area = P n Bi
= WiBi
signal, v1(t), and the superimposed Wi
noise signal, vn(t). fo Frequency
qn1(jw)2
Area = vn12
Spectrum of the phase noise at the F

input of the PLL. Bi/2 Frequency
|H(jw)|
Frequency response of the phase-

Function of z
transfer function, H(j).
BL Frequency
qn2(jw)2
Spectrum of the phase noise at the Area = vn22
output of the PLL.
BL Frequency
140421-12

Lecture 03 – (8/9/18) Page 3-19
Noise Relationships for a PLL

Spectral density of the input noise signal:
Pn
Wi = B (W/Hz)
i
Input rms phase noise jitter (or the square of the rms phase noise):
Pn
n1(t) → n1 = 2P2 (Comes from the assumption of white noise)
s
Signal-to-Noise Ratio (SNR):
Ps Pn 1
SNR at the input = (SNR)i  P → n1
2
= 2P = 2(SNR) (radians2)
n s i
Input phase jitter (noise) spectrum:
n1
2
n1
2 (j) =  =
B /2 (radians 2/Hz)
i
Output phase jitter (noise) spectrum:
n2
2 (j) = |H(j)|2  2 (j) = |H(j)|2
n1

Lecture 03 – (8/9/18) Page 3-20
RMS Value of the Output Phase Noise

The output phase noise is found by integrating n2(j) over the bandwidth of the PLL.

n2
2 =   2 (j2f) df
 n2
0
where n2
2 is the area under the output phase noise plot in a previous slide.
 
n2
2
= 

 |H(j)|2df =  |H(j)| d
2
0
2 0
The integral  |H(j2f)|2df = BL is called the noise bandwidth.

0
The solution of this integral is,
n  1 dBL n  1
BL = 2  +  → = 2 1 -  = 0 →  = 0.5 → BL(min) = 0.5n
 4 d  2
n1
2
Pn 2BL Pn BL BL
 n2 =  BL = B /2 BL = 2P B = P · B = (SNR) B
2
i s i s i i i

Lecture 03 – (8/9/18) Page 3-21
RMS Value of the Output Phase Noise – Continued

We noted previously that,
1 Pn Ps
n1 = 2(SNR) = 2P
2
→ (SNR)i = P
i s n
A dual relationship holds for the output,
1 P n BL Ps Bi
n2 = 2(SNR) = P · B
2 → (SNR)L = P 2B
L s i n L
where (SNR)L is the signal-to-noise ratio at the output.
Bi
 (SNR)L = (SNR)i 2B
L
This equation suggests that the PLL improves the SNR of the input signal by a factor of
Bi/2BL. Thus, the narrower the noise PLL bandwidth, BL, the greater the improvement.
Some experimental observations:
• For (SNR)L = 1, a lock-in process will not occur because the output phase noise is
excessive (0.707 radians or 40.4°).
• At an (SNR)L = 2, lock-in is eventually possible (0.5 radians or 28.6°).
• For (SNR)L = 4, stable operation is generally possible.
Note: (SNR)L = 4, n22 becomes 0.125 radians2. n2
2 = 0.353 radians  20° and the
CMOS Phase Locked Loops

limit of dynamic stability (180°) is rarely exceeded. © P.E. Allen - 2018
Lecture 03 – (8/9/18) Page 3-22
Summary of Noise Analysis of the LPLL

• Stable operation of the LPLL is possible if (SNR)L ≥ 4
• (SNR)L is calculated from
Ps Bi
(SNR)L = P 2B
n L
where Ps = signal power at the reference input
Pn = noise power at the reference point
Bi = bandwidth of the system at the input
BL = noise bandwidth of the PLL
• The noise bandwidth, BL, is a function of n and . For  = 0.7, BL = 0.53n
• The average time interval between two unlocking events gets longer as the (SNR)L
increases.

Lecture 03 – (8/9/18) Page 3-23
Pull-In Techniques for Noisy Signals

1.) The sweep technique.
When the noise bandwidth is made small, the SNR of the loop is sufficiently large to
provide stable operation. However, the lock range can become smaller than the
frequency interval  within which the input signal is expected to be. The following
circuit solves this problem by providing a direct VCO sweep.
(1.) LPLL not locked.
(2.) RUN mode starts
a positive sweep.
(3.) When the VCO
frequency
approaches the
input frequency
the loop locks.
(4.) The “In-Lock”
detector switches
the sweep switch
to the “HOLD”
position.
Lecture 03 – (8/9/18) Page 3-24
Pull-In Techniques for Noisy Signals

2.) Switched filter technique.
"In-Lock"
Detector
Rsmall(not locked)
v1(t) Phase vf(t)
Detector
Rlarge(locked)
v2(t)
Switched Loop Filter
VCO
140421-14
In the unlocked state, the filter bandwidth is large so that lock range exceeds the
frequency range within which the input is expected.
In the locked state, the filter bandwidth is reduced in order to reduce the noise.

Lecture 03 – (8/9/18) Page 3-25
SUMMARY
• Acquisition process – the PLL in the unlocked state
• Influence of noise on the linear PLL
• Pull-in techniques for noisy signals

Lecture 04 – (8/9/18) Page 4-1

Topics
• LPLL system design – design procedure
• Simulation of LPLL systems
Organization:

Circuits PLL
Technology CMOS
140418-02

Lecture 04 – (8/9/18) Page 4-2
LPLL SYSTEM DESIGN

Design Procedure
Objective: Design the parameters Ko, Kd, , and the filter F(s) of the LPLL.
Given: The phase detector and VCO and pertinent information concerning these blocks.
Steps:
1.) Specify the center frequency, o, and its range omin and omax.
2.) Select the value of . Small values give an overshoot and large values are slow.  =
0.7 is typically a good value to choose.
3.) Specify the lock range L.
a.) If noise can be neglected, then the selected value of L is chosen.
b.) If noise cannot be neglected, then use the input noise SNR, (SNR)i and the input
noise bandwidth, Bi, to find the noise bandwidth, BL. Later when we find n, the
value of L will be specified.
4.) Specify the frequency range of the LPLL as 2min and 2max as,
2min < omin - L and 2max > omax + L
Some practical limits are,
2min = omin - 1.5L and 2max = omax + 1.5L
Lecture 04 – (8/9/18) Page 4-3
Design Procedure – Continued

5.) Design of the VCO. From the power supply voltage or data sheet find the value of
Ko as shown below.
w2 w -w
Ko = v 2max - v 2min
f(max) f(min)
w2max
wo
w2min
6.) Determine the value of Kd from the
vf
data sheet. Kd will depend upon the 140421-15
vf(min) VB vf(max) VB
2
signal level. It is preferred to have a
large value of Kd.
7.) Determine the natural frequency, n.
a.) Lock range has been specified in step 3.).
L
n =
2
b.) Noise bandwidth has been specified in step 3.)
2BL
n =
 + 0.25
Lecture 04 – (8/9/18) Page 4-4

8.) Select the type of loop filter.
a.) Passive lag filter:
Solve for 1 and 2 from the following equations. Normally, 1 should be 5-10
times 2. If this is not the case, choose another type of filter.
KoKd n  1 
n = and  = 2 2 + K K 
1+2  o d
b.) Active lag filter:
Use the following equations to solve for 1, 2, and Ka. It will be necessary to
choose one of these parameters because there are only two equations.
KoKdKa n  1 
n = and  = 2 2 + K K K 
1  o d a
c.) Active PI filter:
Use the following equations to solve for 1 and 2. Because this filter has a pole
at s = 0, it is not necessary for 1 to be larger than 2.
KoKd n2
n = and = 2
1
Lecture 04 – (8/9/18) Page 4-5
LPLL Design Example

Consider the multichannel telemetry system shown where one single, voice-grade
communication line is used to transmit a number of signal channels.
Transmitters Receivers
Frequency Spectrum
S1 E1 Channel Channel Channel Channel
1 2 3 N
Bi
S2 E2
f
f01 f02 f03 f0N
300 Hz 2DwLmin 3 kHz
SN EN 140421-16
2DwLmax
Each transmitter is to transmit a binary signal with a baud rate of 50 bits/sec. The signal
is encoded in a non-return to zero format which means that the bandwidth required is half
the baud rate or 25 Hz. The spectrum of the FM-modulated carrier consists of the carrier
frequency and a number of sidebands displaced by ±25 Hz, ±2·25 Hz, etc. from the
carrier frequency.
Assuming that a narrow-band FM is used, the channel spacing will be selected as 60
Hz. The channel is assumed to be an ordinary telephone cable with a bandwidth of 300
Hz to 3000 Hz giving Bi = 2700 Hz. Therefore, the maximum number of channels is
Max. no. of channels = Bi/Channel spacing = 2700/60 = 45 channels.
Lecture 04 – (8/9/18) Page 4-6
LPLL Design Example – Continued

Design one of the receivers using the procedure outlined above assuming the carrier
frequency is 1000 Hz. Assume the VCO is an XR-215†
1.) The angular frequency, o, is 2·1000 = 6280 sec.-1.
2.) Select  = 0.7.
3.) In this problem the noise cannot be neglected. Therefore, we must find the noise
bandwidth, BL, of the loop and not the lock-range L. The input SNR is given as
Ps
(SNR)i = P
n
Because the other 44 channels act like noise to our particular channel, let Pn = 44Ps.
Ps 1
Therefore, (SNR)i = P = 44  0.023
n
To enable locking onto the carrier, the SNR of the loop should be approximately 4.
(SNR)i Bi 0.023·2700
 BL = (SNR) 2 = = 7.67 Hz
L 4·2
4.) Determine the lock range. Because the noise bandwidth, BL, is very small, the lock
range will be small and will be determined in step 7.
† Phase-Locked Loop Data Book, Exar Integrated Systems, Sunnyvale, CA, 1981.( http://www.exar.com/products/XR215A.html)
Lecture 04 – (8/9/18) Page 4-7

5.) From the data sheet of the VCO we get,
200  0.6 700
fo = C 1 + R  and Ko = C R
o  x o o
where the resistors are in k and the capacitors in µF.
Choosing Co = 0.27µF and Rx = 1.71k gives the required center frequency of 1000 Hz.
The data sheet specifies that Ro should be in the range of 1 to 10 k. Therefore, we see
that Ko can be in the range of 260 rads/sec·V to 2600 rads/sec·V. Choosing Ro as 10 k,
gives Ko = 260 rads/sec·V.
This means that the VCO can change its frequency by 260/2 = 41.4 Hz. We will have to
check in step 7 that this range is sufficient to enable locking within the L lock range.
10
Phase Comparator Conversion Gain, Kd
6.) Determine Kd. A plot of the

data sheet is shown. In the
1
application we are considering,
the input signal level is 3mV(rms). 2V/rad
 Kd  0.2 V/rad/ 0.1
High Level Input

Constant = 1Vrms
0.01
0.1 1 10 100 1000 10 4
CMOS Phase Locked Loops Low Level Input Amplitude (mV rms) 030901-08 © P.E. Allen - 2018
Lecture 04 – (8/9/18) Page 4-8

7.) n is calculated from BL and  and is,
2BL 2·7.67
n = = 0.7·1.25 = 17.53 sec.-1
 + 0.25
The lock-in range is found as,
L = 2n = 24.54 sec.-1
8.) Solve for 1 and 2 from the equations below.
KoKd n  1 
n = and  = 2 2 + K K 
1+2  o d
2 1
2 = - = 60.6 ms
n KoKd
KoKd
1 + 2 = 2 = 169.2 ms → 1 = 108.6 ms
n
The resistor R1 is already integrated on the chip as 6 k.
9.) Finally, determine R1, R2, and C of the filter. The data sheet shows that the resistor,
R1, is already integrated on the chip as 6 k. (Note: Two passive lag filters are needed.)
1 108.6 ms 2 60.6 ms
 C=R = = 18.1 µF and R2 = C = 18.1 µF = 3.35 k
1 6 k
Lecture 04 – (8/9/18) Page 4-9
Simulation of the LPLL Design Example

The open loop transfer function is,
Kv 1+s1  52 1+s60.6x10-3 
LG(s) = s  = 
 1+s( 1 + 2 
) s 1+s169.2x10-3
Cutoff frequency:
c = n 2 2 + 4 4+1 = 17.53 2·0.72 + 4·0.74+1 = 27.045 rads/sec (4.3 Hz)
The phase margin can be written as,
PM = 180° - 90° + tan-1(c·60.6x10-3) - tan-1(c·169.2x10-3)
= 90° + 58.61° - 77.67° = 70.94°
PSPICE Input File:
LPLL Design Problem-Open Loop Response
VS 1 0 AC 1.0
R1 1 0 10K
* Loop bandwidth = Kv =52 sec.-1 Tau1=60.6E-3 Tau2=108.6E-3
ELPLL 2 0 LAPLACE {V(1)}= {(52/(S+0.00001))*((1+60.6E-3*S)/(1+169.2E-3*S))}
R2 2 0 10K
*Steady state AC analysis
.AC DEC 20 0.01 100
.PROBE
.END

Lecture 04 – (8/9/18) Page 4-10
Simulation of the LPLL Design Example - Continued

Open Loop Response
100
Phase + 180°
dB or Degrees 80
60 Phase
Margin
40  79°
20
Magnitude
0 Cutoff
-20 Frequency
 5Hz
-40
0.01 0.1 1 10 100
Frequency (Hz)
Cutoff frequency  5Hz
Phase margin  79°

Lecture 04 – (8/9/18) Page 4-11

Implementation of the FSK Demodulator:
C= C=
Phase 18.1 mF 18.1 mF Rx
Co = 0.27mF
Detector R2 = 5kW
R2 =
Outputs 3.35kW Timing
3.35kW
Capacitor
VCC
Phase 16 2 3
+15V Detector Range 10 13 14
0.1mF Inputs R1=6kW Select

4 Phase
R =6kW VCO Output
FM Input 0.1mF Detector 1 VCO 15
6
10kW
2.2kW
4.7kW 2.2kW Op Amp VCO
XR-215 -
Output Sweep
5 Op Amp + VCO
Phase Input
Comparator Input Gain
4.7kW 0.1mF 9 2 1 8 12 11
Bias VEE PD 4.7kW 100kW 10kW Control
Out
68nF Demodulated Output Signal

Lecture 04 – (8/9/18) Page 4-12
LPLL SYSTEM SIMULATION

Approaches
At least two methods are available:
1.) Behavioral modeling of PSPICE (illustrated on the previous example)
2.) PC-based simulator developed by R.M. Best
PSPICE
The Laplace transform behavioral model of PSPICE uses controlled voltage sources to
implement linear frequency domain transfer functions in the linear domain.
General Form:
E <name> <(+)node> <(-)node> LAPLACE {<expression>} = {<transform>}
Example:
V2 Kv 1+s1  52 1+s60.6x10-3 
Plot LG(s) = V = s  = 
1 1+s( 1 + 2 
) s 1+s169.2x10-3
VS 1 0 AC 1.0
R1 1 0 10K
* Loop bandwidth = Kv =52 sec.-1 Tau1=60.6E-3 Tau2=108.6E-3
ELPLL 2 0 LAPLACE {V(1)}= {(52/(S+0.00001))*((1+60.6E-3*S)/(1+169.2E-3*S))}
R2 2 0 10K
.AC DEC 20 0.01 100
.PROBE
.END
Lecture 04 – (8/9/18) Page 4-13
PC-Based PLL Simulation Program

A PC-based simulation program developed by R.M. Best and found as part of the 4th
edition is used as an example of PLL simulation at the systems level. The description of
how to use this program is found on the CD or described in the text, Phase-Locked
Loops-Design, Simulation, and Applications, 4th ed., 1999, McGraw-Hill Book Co.
The simulation flow chart is show below and follows the previous design procedure.
Start
Step 6 - Determine reference signal

Step 1 - Specify wo and the range of wo. level, v1, and phase detector gain, Kd
Step 2 - Specify z No Yes

Noise can be neglected
No Yes Step 7.1 - Calculate Step 7.2 - Calculate
Noise can be neglected
wn from BL and z wn from z and DwL
Step 3.1 - Secify the Step 3.2 - Secify the
noise bandwidth, BL lock range, DwL
Step 8 - Select type of loop filter. Calculate
loop filter parameters t1, t2 and (Ka)
Step 4 - Specify frequency range of VCO
Step 5 - Specify VCO characteristic. Calculate Step 9 - Determine the extenal

Ko. Determine external components of the VCO components of the loop filter
End Fig. 2.1-24

Lecture 04 – (8/9/18) Page 4-14
Example of LPPL Simulation

PLL selected is:
1.) Architecture - LPLL, Passive Lag, and VCO
2.) Parameters –
Power supply = +5V and 0V
Phase detector: Kd = 1.0, Vsat+ = 4.5V and Vsat- = 0.5V
Loop filter: 1 = 500 µsec. and 2 = 50 µsec.
Oscillator: Ko = 130,000 rads/sec·V, Vsat+ = 4.5V and Vsat- = 0.5V
The simulator program calculates n = 15,374.12 rads/sec. and  = 0.443.
Using the developed formulas, we can compute the key LPLL parameters as:
1.) Lock range: L = 13,621 rads/sec. → fL = 2169 Hz
2.) Pull-out range: PO = 39,932 rads/sec. → fPO = 6358 Hz
3.) Pull-in range: P = 53,597 rads/sec. → fP = 8534 Hz
n
(The ratio K K = 0.12 and can be considered a high-gain loop)
o d
4.) Hold range: H = 130,000 rads/sec. → fL = 20,700 Hz
On the following pages, we attempt to verify these values by simulation.
Lecture 04 – (8/9/18) Page 4-15
Pull-out Range of the LPLL (2kHz Frequency Step)
vd(t)
mV
vf(t)

Lecture 04 – (8/9/18) Page 4-16
Linearity of the LPLL (Frequency Step Doubled from 2kHz to 4kHz)
vd(t) The LPLL is not linear

because doubling the
frequency step did not
double the output.
mV
The flat topped response for
vd(t) indicates that the phase
vf(t) error is close to /2.
Loop is still locked.

Lecture 04 – (8/9/18) Page 4-17
Pull-out Range of the LPLL (Frequency = 5kHz)
The dip in the response of

vd(t) the detector output implies
that the phase error has
exceeded /2.
V
vf(t) The loop is still locked.

Lecture 04 – (8/9/18) Page 4-18
Finding the Pull-out Range (Frequency step = 5700Hz)
The loop has not yet pulled

out and is still locked.
vd(t)
vf(t)
V

Lecture 04 – (8/9/18) Page 4-19
Finding the Pull-out Frequency (Frequency step = 5800Hz)
From this simulation, we

vd(t) see that the pull-out
frequency is close to
5800Hz which is compared
vf(t) with the predicted value of
6358Hz (10% error).
V Because the frequency step
applied to the LPLL is
smaller than the pull-in
range, the loop locks again
after a short time.

Lecture 04 – (8/9/18) Page 4-20
Finding the Pull-in Frequency (Frequency step = 7000Hz)
vd(t) The frequency step of

7000Hz causes the LPLL to
pull-out again. However,
the pull-in process takes
vf(t)
longer than before.

Lecture 04 – (8/9/18) Page 4-21
Finding the Pull-in Frequency (Frequency step = 8000Hz)
vd(t) The frequency step of

vf(t) pull-out again. However,
the pull-in process takes
even longer than before.
V We can estimate the lock
range by observing that vf(t)
Loop begins gets slowly “pumped up”.
to lock When it reached about 2.8V,
the PLL became locked
within one oscillation of
vd(t). The value of vf(t) at
lock is 2.9V. The 0.1V
difference corresponds to a
lock range of 2000Hz.

Lecture 04 – (8/9/18) Page 4-22
Finding the Pull-in Frequency (Frequency Step = 9000Hz)

vd(t)
The frequency step of

pull-out and is no longer
vf(t) able to pull back in.
Further simulation showed
V that the LPLL cannot pull
back in for a frequency step
of 8500Hz.
 The pull-in frequency is
near 8500Hz compared with
a predicted value of
8534Hz.

Lecture 04 – (8/9/18) Page 4-23
SUMMARY
• LPLL design –Design the parameters Ko, Kd, , and the filter F(s) of the LPLL for a
given performance specification
• PLL system simulation methods include:
1.) Behavioral modeling of PSPICE (illustrated on the previous example)
2.) PC-based simulator developed by R.M. Best

Lecture 05 – (8/9/18) Page 5-1
LECTURE 5 –DIGITAL PHASE LOCK LOOPS (DPLLs)

INTRODUCTION
Topics
• Building Blocks of the DPLL
• Dynamic Performance of the DPLL
Organization:

Lecture 05 – (8/9/18) Page 5-2
BUILDING BLOCKS OF THE DPLL

Block Diagram of the DPLL
v1, w1
Digital vd Analog vf v2, w2
v2', w2' Phase Lowpass VCO
Detector Filter
¸N Counter
(Optional)
Fig. 2.2-01
• The only digital block is the phase detector and the remaining blocks are similar to the
LPLL
• The divide by N counter is used in frequency synthesizer applications.
2
2’ = 1 = N → 2 = N 1

Lecture 05 – (8/9/18) Page 5-3
DIGITAL PHASE DETECTORS

Introduction
Key assumption in digital phase detectors: v1(t) and v2(t) are square waves. This may
require amplification and limiting.
vin(t) vout vin(t)
VOH VOH
VIH
VIL
t vin t
VIL VIH
VOL VOL
Fig. 2.2-02
Types of digital phase detectors:

1.) EXOR gate
2.) The edge-triggered JK flip-flop
3.) The phase-frequency detector

Lecture 05 – (8/9/18) Page 5-4
The EXOR Gate
v1 v1 v2’ vd
vd
G1 0 0 0
v2' 0 1 1
Fig. 2.2-03
1 0 1
1 1 0
Zero Phase v1
Error: t
v2'
t
vd
vd
t Fig. 2.2-04
Positive Phase v1
Error: t
v2'
t
qe>0
vd
vd
t Fig. 2.2-05
Lecture 05 – (8/9/18) Page 5-5
EXOR Gate – Continued

Assume that the average value of vd, is shifted to zero for zero phase error, e. vd can be
plotted as,
vd
VOH
-p V -V
2
p qe Kd = OHp OL
-p p
2
VOL Fig. 2.2-06
If v1 and v2’ are asymmetrical (have different duty cycles), then vd becomes,
vd
VOH
v1
t
-p
2
v2' -p p p qe
t 2
vd
vd
VOL Fig. 2.2-07
t
The effect of waveform asymmetry is to reduce the loop gain of the DPLL and also
results in a smaller lock range, pull-in range, etc.

Lecture 05 – (8/9/18) Page 5-6
JK Flip-Flop
The JK Flip-Flop is not sensitive to waveform asymmetry because it is edge-triggered.
v1 v2’ Qn+1
vd 0 0 Qn
v1 J Q
FF 0 1 0
v2' K Q 1 0 1
Zero Phase Error (Assume Fig. 2.2-08 rising edge 1 1
triggered): Qn
v1
t
v2'
t
vd
vd
t Fig. 2.2-09
Positive Phase Error:
v1
t
v2'
qe>0 t
vd
vd
t Fig. 2.2-10

Lecture 05 – (8/9/18) Page 5-7
JK Flip-Flop Phase Detector – Continued

Input-Output Characteristic:
vd
VOH
V -VOL
qe Kd = OH
-p p 2p
VOL
Fig. 2.2-11
Comments:
• Symmetry of v1 and v2’ is unimportant
• Both the EXOR and the JK flip-flop have a severely limited pull-in range if the loop
filter does not have a pole at zero.

Lecture 05 – (8/9/18) Page 5-8
The Phase-Frequency Detector (PFD)

The PFD can detect both the phase and frequency difference between v1 and v2’.
Conceptual diagram:
PD LPF1 VLPF1
Phase Feedback
Vin Vout
wout VCO
win
Frequency Feedback
FD LPF2 VLPF2
The output signal of the PFD depends on the phase error in the locked state and on the
frequency error in the unlocked state.
Consequently, the PFD will lock under any condition, irrespective of the type of loop
filter used.

Lecture 05 – (8/9/18) Page 5-9
The PFD – Continued

PFD implementation:
VDD
No AND Gate With AND Gate

D QA Up PFD QA QB QA QB
FFA Q
v1 (A) Clk R 0 0 1 0→State=+1
1 0 0 0→State = 0
D R QB Dn 0 1 0 1→State=-1
FF Q 1 1
v2' (B) Clk B Fig. 2.2-12A
State Diagram:
State II B State 0 A State I
QA= 0 QA= 0 QA= 1

B A
QB= 1 QB= 0 QB= 0
A B Fig. 2.2-13A
Unlike the EXOR gates and the R-S latches, the PFD generates two outputs which are not
complementary.

Lecture 05 – (8/9/18) Page 5-10
Illustration of a PFD
PFD (A = B):
A QA
PFD
B QB
(Rising edge triggered) Fig. 2.2-14
fA>fB: fA<fB:
A A
B B
QA QA
QB QB
Time Time
Fig. 2.2-15

Lecture 05 – (8/9/18) Page 5-11
Illustration of the PFD- Continued
wA<wB: wA>wB:
A A
B B
QA QA
QB
QB
Time Time
Fig. 2.2-16

Lecture 05 – (8/9/18) Page 5-12
PFD – Continued
Plot of the PFD output versus phase error:
vd
VOH
-4p -2p
qe
2p 4p
VOL
Fig. 2.2-17
When e exceeds ±2, the PFD behaves as if the phase error recycled at zero.
VOH-VOL
 Kd =
4
Average Duty Cycle
A plot of the averaged duty cycle of vd
versus 1/2’ (A/B) in the unlocked 1
Fraction of time state
of the DPLL: 0.5 QA=1 and QB=0
(+1 state)
0
w1/w2'
1 2
Fraction of time
-0.5 QA=0 and QB=1
(-1 state)
-1
Fig. 2.2-18

Lecture 05 – (8/9/18) Page 5-13
CHARGE PUMPS
What is a Charge Pump?
A charge pump consists of two switched current sources controlled by QA and QB
which drive a capacitor or a combination of a resistor and a capacitor to form a filter for
the PLL with a pole at the origin.
A
VDD
I1 B
QA X QA and QB are
A S1 Vout QA simultaneously
PFD QB high for the
B S2 QB duration given
Y Cp
I1=I2=I by the delay
Vout
I2 of the AND gate
and the reset path
of the flip-flops.
t Fig. 2.2-19
A > B or A = B but A > B: S1 is on and Vout increases.
A < B or A = B but A < B: S2 is on and Vout decreases.

Lecture 05 – (8/9/18) Page 5-14
A Charge-Pump PLL
Block diagram:
VDD
I1
x(t) QA
S1 y(t)
PFD VCO
QB
S2
Cp
I2
Fig. 2.2-20
The charge pump and capacitor Cp serve as the loop filter for the PLL.
The charge pump can provide infinite gain for a static phase shift.

Lecture 05 – (8/9/18) Page 5-15
Step Response of a Charge Pump PLL

Assume that the period of the input A
is T1 and the charge pump provides a
current of ±Ip to the capacitor Cp. B
T1
QA
QB qe
Detector gain? Vout

Ip
Since the steady-state gain = , it is Slope =
Cp T1 IpT1qe
more meaningful to define Kd as Increase/period =
2pCp
t
follows, Fig. 2.2-195
Ip e Ip T1e
Amount of vd(t) increase per period (T1) = C x =
p 2/T1 2Cp
Ip T1e 1 Ip e
Average slope per period = x =
2Cp T1 2Cp
Ip
vd(t) = Average Slope· = · µ(t)
2Cp e
Ip e Ip V
Taking the Laplace transform gives, Vd(s) = → Kd =
2Cp s 2Cp rads
Lecture 05 – (8/9/18) Page 5-16
A Charge-Pump PLL – Continued

Y(s) V2(s)
X(s) = V1 (s) = ?
Ko KoKd Y(s) KoKd
Y(s) = s Vd(s) = 2 [X(s) – Y(s)] → X(s) = 2
s s + KoKd
which has poles at ±j KoKd . To avoid instability, a zero must be
VDD
introduced by the resistor in series with Cp.
I  1  I Kd I1
Vd(s) = R+ = (sRCp +1) = s (sp +1)
2  sCp s2Cp
S1 Vout
Ko KoKd
 Y(s) = s Vd(s) = 2 (sp +1) [X(s) – Y(s)]
s S2 Cp
 KoKd  KoKd
Y(s) 1 + 2 (sp +1) = 2 (sp +1)X(s) I2 R
 s  s
Y(s) KoKd(sp +1)
Fig. 2.2-21
X(s) = s2 + KoKdps + KoKd
Equating to the standard second-order denominator gives,
np
n = KoKd and  = 2

Lecture 05 – (8/9/18) Page 5-17
Nonideal Effects of Charge-Pumps vd
1.) Dead zone. Dead

A dead zone occurs when QA or QB do not reach their full logic Zone
qe
levels. This is due to delay differences in the AND gate and the
flip-flops. It is removed by proper synchronization of the delays.
Fig. 2.2-22
2.) Mismatch between I1 and I2.

A
To eliminate the dead zone, QA and QB can be simultaneously
B
high for a small time. If I1 ≠ I2, the output varies even though e
QA
= 0. (Can introduce spurs.)
QB
vd
3.) Charge injection. t
Fig. 2.2-23
When the S1 and S2 switches turn off, they can inject/remove
VDD
charge from Cp. Changes 2.
I1
Cx
X
4.) Charge sharing. S1 vd
If X → VDD and Y = 0 when S1 and S2 are off, the VCO will Cy

S2
Y Cp
experience a jump when S1 or S2 turns on. This periodic effect I2
introduces sidebands (spurs) at the output. Fig. 2.2-24

Lecture 05 – (8/9/18) Page 5-18
DYNAMIC PERFORMANCE OF THE DPLL

Types of PLLs
Type I – Open-loop transfer function has one pole at the origin.
Type II – Open-loop transfer function has two poles at the origin.
The above transfer functions may also have other roots but not at the origin.
Model for the DPLL
PD LPF VCO
q1(s)
Ko q2(s)
q2'(s) Kd F(s)
s
Optional
¸ N Counter
1
N Fig. 2.2-25
Various configurations of the DPLL:

1.) Phase detector – EXOR, J-K flip-flop, or PFD
2.) Filter –
Passive lag with or without a charge pump
Active lag with or without a charge pump
Active PI with or without a charge pump

Lecture 05 – (8/9/18) Page 5-19
Loop Filters
1.) Passive lag-
1 + s2
PD → F(s) =
1 + s(1 + 2)
1 + s2
PFD → F(s) 
s(1 + 2)
Experimental results using the PFD with a passive lag filter show that the gain of the
passive filter is not constant. As a result, the filter dynamics become nonlinear.
2.) Active lag-
1 + s2
PD → F(s) = Ka
1 + s1
1 + s2
PFD → F(s) 
s1
3.) Active PI-
1 + s2
PD or PFD → F(s) =
s1

Lecture 05 – (8/9/18) Page 5-20
The Hold Range, H

The hold range, H, is the frequency range within which the PLL operation is
statically stable. The hold range for various types of DPLLs are:
Type of PD EXOR EXOR EXOR JK-FF JK-FF JK-FF PFD

Passive Active Active Passive Active Active All
Loop Filter
Lag Lag PI Lag Lag PI Filters
KoKd(/2) KoKd(/2) KoKd KoKdKa
H   
N N N N
Some Considerations of Importance

As we examine the lock range of the DPLL using EXOR, JK-FF, and PFD detectors,
the following comparison will be useful.
Vd
Slope = Kd LPLL EXOR JK
VOH
PFD qe
V
-2p -p -p -1 1 p p 2p OL
2 2 Fig. 031001-01

Lecture 05 – (8/9/18) Page 5-21
The Lock Range, L

The lock range is the offset between 1 and 2/N that causes the DPLL to acquire lock
with one beat note between 1 and 2’ = 2/N.
1.) PD = EXOR vd Recall that L(LPLL) = 2n
0.5Kdp
and L  Range of e = e
t
-0.5Kdp
But, e(EXOR)=0.5 e(LPLL)
2p/Dw
w2'  L = 0.5(2n) = n
w1
Dw
wo w2'(t)
L = n
t
Fig. 2.2-26
vd
2.) PD =JK-Flip flop Kdp
e(EXOR) =  e(LPLL)
 L = (2n)
t
-Kdp
L = 2n
2p/Dw
w2'
w1
Dw
wo w2'(t)
t
Fig. 2.2-27
3.) PD = PFD
e(PFD) = 2 e(LPLL) → L = 2(2n) → L = 4n
The lock time for all cases is Tp  2/n.
Lecture 05 – (8/9/18) Page 5-22
The Pull-In Range, p, and the Pull-In Time, Tp

The pull-in range, p, is the largest =−2’| for which an unlocked loop will lock.
The pull-in time, Tp, is the time required for the loop to lock.
EXOR as the PD:
Waveforms-
vd w2'
T1 T2 w1
0.5Kdp
Dw(t) w2'
t
wo
-0.5Kdp t
T = 2p/Dw T = 2p/Dw Fig. 2.2-28
T1 > T2 because  is smaller when vd is positive and larger when vd is negative.

Results-
Type of Filter p (Low loop gains) p (High loop gains) Pull-in Time, Tp
  4 o2
2 2nKoKd - n
Passive Lag 2 nKoKd
2 2 n3
 n2  4 o2
Active Lag 2nKoKd - K nKoKd
2 a 2 2 n3
4 o2
Active PI  
2 n3
Lecture 05 – (8/9/18) Page 5-23
The Pull-In Range, p, and the Pull-In Time, Tp-Continued

JK Flip-Flop as the PD:
Waveforms-
vd w2' w1
T1 T2
Kdp
Dw(t) w2'
t
wo
-Kdp
T = 2p/Dw t
T = 2p/Dw Fig. 2.2-29
T1 > T2 because  is smaller when vd is positive and larger when vd is negative.

Results-
Type of Filter p (Low loop gains) p (High loop gains) Pull-in Time, Tp
1 o2
Passive Lag  2nKoKd - n 2  2 nKoKd
2 n2
Active Lag n2  2 nKoKd 1 o2
 2nKoKd - K 2 n2
a
4 o2
Active PI  
2 n2

Lecture 05 – (8/9/18) Page 5-24
p and Tp for the PFD

Assume that the PFD uses a single power supply of VDD. The various waveforms are,
v1
v2'
vd
VDD
vd High
0.5VDD Impedance
State
0 t
vd(eq.)
VDD
0.5VDD
(If the filter time constant >> the duty cycle, this waveform simplifies the analysis.)
0 t
vf
VDD
w1
Dw
Ko
0.5VDD
t
TP Fig. 2.2-30
vd(eq.) is a 50% duty cycle model of the PFD to find Tp.

Lecture 05 – (8/9/18) Page 5-25
p and Tp for the PFD – Continued

Since p = , let us find Tp using the following model for the passive lag filter:
+ R1+R2 + + R1+R2 +
VDD VDD
vd C vf vd 2C vf
2 2
- - - -
PFD Filter PFD Filter
100% Duty Cycle 50% Duty Cycle Fig. 2.2-31
Use the 50% duty cycle model, solve for the time necessary to increase vf by /Ko
1.) Loop filter = Passive lag
 KoVDD/2 
Tp = 2(1+2) ln 
 o DD
K V /2 -  o
2.) Loop filter = Active lag
 KoKaVDD/2 
Tp = 21 ln 
 o a DD
K K V /2 -  o
3.) Loop filter = Active PI
21o
Tp = K V /2
o DD
For split power supplies, replace VDD with (VOH-VOL).

Lecture 05 – (8/9/18) Page 5-26
The Pull-Out Range, po

The pull-out range is the size of the frequency step applied to the reference input that
causes the PLL to lose phase tracking.
1.) EXOR: po  2.46n( + 0.65) for 0.1 <  < 3
2.) JK Flip-flop:
   1-2
po = n exp  tan 
-1  ,  < 1
 1- 2   
po = ne, =1
   1-2 po  n( + 0.5) for all 
po = n exp  tanh-1  ,  > 1
 1- 2   
3.) PFD:
   1-2
po = 2n exp  tan 
-1  ,  < 1
 1- 2   
po = 2ne, =1
   1-2 po  n( + 0.5) for all 
po = 2n exp  tanh 
-1  ,  > 1
 1- 2   

Lecture 05 – (8/9/18) Page 5-27
Example 1 – A Simple CMOS PLL

Consider the PLL shown. Assume that: 1.) the phase R2 C
detector is a simple CMOS EXOR whose logic levels qin EXOR R1 - qout
VCO
are ground and VDD = 5V, 2.) both the input to the loop PD +
and the VCO output are square waves that swing VDD
2 Part (d.)
between ground andVDD, and 3.) that the VCO has a
¸N
perfectly linear relationship between the control SU03E1P2
voltage and output frequency of 10 MHz/V. The polarities are such that an increase in
control voltage causes an increase in the VCO frequency.
(a.) Derive the expression for the open-loop transmission and the transfer function
out(s)/in(s).
(b.) Initially assume R2 = 0 and R1 = 10k What value of C gives a loop crossover
frequency of 100kHz? What is the phase margin? Assume the op amp is ideal.
(c.) With the value of C from part (b.), what value of R2 will provide a phase margin of
45° while preserving a 100 kHz crossover frequency?
(d.) Now assume that a frequency divider of factor N is inserted into the feedback path.
With the component values of part (c.), what is the largest value of N that can be tolerated
without shrinking the phase margin below 14°?

Lecture 05 – (8/9/18) Page 5-28
Solution
Ko  out(s) 5Ko  out(s)
(a.) out(s) = F(s)Kd in(s) +
  = F(s) in(s) +
 
s  N  s  N 
5V R2+(1/sC) sR2C+1 s2+1
Kd = and F(s) = - sR C = - sR C = - , 1 = R1C and 2 = R2C
 1 1 s1
5Ko s2+1 out(s)  5Kos2+1  5Kos2+1
 out(s)= -  (s) +
N  → out(s) 1 + sN  s1  = s  s1 in(s)
      
s  s1  in
5Ko
- (s2+1)
out(s) 1
=
in(s) 5Ko 2 5Ko
2
s+ s+
N 1 N1
5Ko
- (s2+1)
out(s) 1 5Kos2+1
= and the loop gain = LG = -  
in(s) 5Ko 2 5Ko sN  s1 
s2+ s+
N 1 N1
Assume N = 1 to get the answer to part (a.).

Lecture 05 – (8/9/18) Page 5-29
(b.) With R2 = 0, 2 = 0 so that the loop gain becomes,
5Ko 5·2x107 108 108
LG = - 2 = 2 = 2 = 1 → 1 = = 253.3µsec.
s 1N s 1 c 1 (2·105)2
1 = R1C → 253.3µsec. = 10kC → C = 25.3nF
The phase margin is 0°.
(c.) The phase margin is totally due to 2. It is written as,
1 1
PM = tan-1(c2) = 45° → c2 = 1 → 2 = = = 1.5915µs = R2C
c 2x105
1
 R2 = = 62.83
2x10525.3x10-9
(d.) N does not influence the phase shift so we can write,
tan-1(c2) = 14° → c’2 = 0.2493 → c’ = 0.2493c = 156,657 rads/sec.
Now the loop gain at c’ must be unity.
5Ko  (c’2)2+1 5Ko
LG = -  =1 → N= (c’2)2+1
c’N c’1  (c’) 1
2
108
N= 2 -6 (0.2493)2+1 = 16.58 = 16
(156.657krads/sec.) 253.3x10
SUMMARY
Lecture 05 – (8/9/18) Page 5-30
• The DPLL has a digital phase detector and the remainder of the blocks are analog
• Digital phase detectors
- EXOR Gate
- JK Flip-Flop
- Phase-Frequency Detector
• Charge pump – a filter implementation using currents sources and a capacitor that
works with the PFD
• Charge pumps implement a pole at the origin to result in zero phase error

Lecture 06 – (8/9/18) Page 6-1
LECTURE 6 –DIGITAL PHASE LOCK LOOPS (DPLLs)

INTRODUCTION
Topics
• Noise Performance of the DPLL
• DPLL Design Procedure
• DPLL System Simulation
Organization:

Lecture 06 – (8/9/18) Page 6-2
NOISE PERFORMANCE OF THE DPLL

Combination of Noise and Information
In the LPLL, the noise and information signals are added because of the linear
multiplier PD.
The noise supression of DPLL’s is generally better than LPLL’s but no theory of noise
exists for the DPLL.
The following pages provide some insight into the noise performance of the DPLL.

Lecture 06 – (8/9/18) Page 6-3
Noise Performance of a DPLL with an EXOR PD

qj Phase noise at
a given inband
frequency
t
v1 Ideal Input
Input with
v1j phase noise
superimposed
qj qj qj qj qj qj (phase jitter)
v2'
Detector
vd Ouput
vd vd is proportional
100% to the phase noise.
\ LPLL noise theory
50%
» DPLL noise theory.
0% t Fig. 2.2-32

Lecture 06 – (8/9/18) Page 6-4
Phase Noise in a Communication Signal

Consider the following simple noise model-

Lecture 06 – (8/9/18) Page 6-5
Input Signal-to-Noise Ratio

The input signal noise ratio of a pulse with phase jitter is defined as,
1
SNRi =
2 n12
where
W2
n12  36
where,
v1
t
W

Lecture 06 – (8/9/18) Page 6-6
Phase Noise in a DPLL with a JK Flip-Flop and a PFD

The basic difference is that the JK Flip-flop and PFD are edge-triggered.
When the input signal fades (v1→0), the reshaped signal can stick at a distinct logic
level.
Conclusion:
The noise suppression of the DPLL is about the same for all phase detectors as long as
none of the edges of the reference get lost by fading. If fading occurs, the EXOR offers
better noise performance.
Summary of DPLL Noise Performance:
Ps = input signal power
Pn = input noise power
Bi = input noise bandwidth
n  1
BL = noise bandwidth   + 
2  4
Ps
SNRi = SNR of the input signal = P
n
Bi
SNRL = SNR of the loop = SNRi 2B
L

Lecture 06 – (8/9/18) Page 6-7
DPLL DESIGN PROCEDURE

Design Procedure
Objective: Design Ko, Kd, , and F(s)
Given: Phase detector and VCO
Steps:
1.) Specify f1(min), f1(max), f2(min), and f2(max).
2.) Design N unless otherwise specified.
Given: n(min) < n < n(max) and min <  < max
For these ranges we get approximately,
n(max) Nmax max Nmax
Nmin → N = Nmean = NmaxNmin
=
n(min) Nmin and min =
3.) Determine . Typically,   0.7.
4.) If noise is of concern, continue with the next step, otherwise go to step 12.
5.) If there are missing edges in the input signal (fading), go to step 6, otherwise go to
step 7.
6.) Choose an EXOR phase detector. Continue with step 8.
VOH-VOL
Kd =


Lecture 06 – (8/9/18) Page 6-8

7.) Choose the JK Flip-flop or PFD as the phase detector.
VOH-VOL
Kd = (JK flip-flop)
2
VOH-VOL
Kd = (PFD)
4
8.) Specify BL.
Bi
BL should be chosen so that SNRi 2B ≥ 4
L
n12 → SNRi and Bi  BL
• If N changes, this can create a problem because
n  1
BL =
2 
 + 
4
and both n and  vary with N.
• Need to check that BL(min) is large enough.
• If BL is too small, then N should be increased.

Lecture 06 – (8/9/18) Page 6-9

9.) Find Ko.
2(max)-2(min)
Ko = v (max)-v (min)
f f
10.) Find n given BL and .
8BL
n =
1+4
If N is variable, use BL and  correspondingly to N = Nmean.
11.) Specify the loop filter.
Given n, , Ko, Kd, and N find 1, 2, and Ka (Ka>1).
Go to step 19.
12.) Continued from step 4.
VOH-VOL
Choose the PFD → Kd =
4
13.) Find Ko.
2(max)-2(min)
Ko = v (max)-v (min)
f f

Lecture 06 – (8/9/18) Page 6-10

14.) Specify the type of loop filter. Use the passive lag filter as the others offer no
benefits.
15.) Determine n.
a.) Fast switching (Tp). Go to step 16.
b.) DPLL does not lock out when switching from Nofref to (No+1) fref.  po < fref.
Go to step 20.
c.) Neither the pull-in time nor the pull-out range are critical. Go to step 21.
16.) Given the maximum Tp allowed for the largest frequency step, solve for 1 or 1+2.
17.) Find n.
KoKd
Loop filter is passive: n =
N(1+2)
KoKdKa
Active lag filter: n =
N1
KoKd
Active PI filter: n =
N1

Lecture 06 – (8/9/18) Page 6-11

18.) Given n and , find 2.
2
2 =
n
If the system cannot be realized (negative values of 1 or 2), modify n and 
appropriately.
19.) Given 1 and 2 (and Ka), determine the filter components.
20.) Given po and  find n.
po
n 
11.55(+0.5)
21.) Given TL, find n from n  2/TL.
22.) Given n, find 1 and 1+2.
KoKd
Passive lag filter: 1+2 =
Nn2
KoKdKa
Active lag filter: 1 =
Nn2
KoKd
Active PI filter: 1 =
Nn2
Lecture 06 – (8/9/18) Page 6-12
Flowchart of the DPLL Design Procedure
Specify the range of f1 and f2

Determine N or range of N
Determine z or range of z
Yes No
Is Noise Suppression Required?
Yes No
Are there missing edges? Choose the PFD, design the VCO and the loop filter
Use EXOR Use PFD Given TP, Dwpo, or TL
TP TL
Use TP to find t1or t1+t2 Dwpo
Specify the noise bandwidth, BL Use Dwpo and z to find wn Use TL to find wn
Design the VCO Estimate wn from t1
Use wn and z to find t1
Use BL and z to find wn
Select the loop filter and determine t1, t2, (Ka) Use wn and z to find t2
Calculate the loop filter values Fig. 2.2-37

Lecture 06 – (8/9/18) Page 6-13
Design Example – A Frequency Synthesizer Using the 74HC/HCT4076

Design a DPLL frequency synthesizer using the CMOS 74HC/HCT4076 PLL. The
frequency sythesizer should be able to produce a set of frequencies in the range of 1MHz
to 2MHz with a channel spacing of 10kHz. Use a PFD and a passive lag-lead filter.
Design:
1.) Determine the ranges of the input and output frequencies.
f1 is constant at 10kHz. f2(min) = 1MHz and f2(max) = 2MHz
2.) Choose N.
2MHz 1MHz
Nmax = 10kHz = 200 and Nmin = 10kHz = 100
 Nmean = Nmax·Nmin = 141
3.) Find . Start by choosing  = 0.7 and find max and min.
max Nmax
= = 2 and  = max·min = 0.7
min Nmin
 min2 2 =0.49 → min = 0.59 and max = 0.59 2 = 0.83
 0.59 <  < 0.83 which is consistent with our choice of .
4.) Select the PFD as the phase detector. For the 74HC/HCT4076, VOH = 5V and
VOL=0V. This gives a Kd = 5V/4 = 0.4 V/rad.

Lecture 06 – (8/9/18) Page 6-14
Design Example – Continued

5.) According to the data sheet of the 74HC4046A, the VCO operates linearly in the
voltage range of vf = 1.1V to 3.9V as shown. f2 (MHz)
2x10 x2
6
 Ko = 3.9-1.1 = 2.2x106 rads/V·sec
2
The data sheet also requires calculation of
two resistors, R1 and R2, and a capacitor, C1. 1
1.1V 3.9V
Using the graphs from the data sheet gives, vf(V)
0 1 2 3 4 5
R1 = 47k, R2 = 130k, and C1 = 100pF. Fig. 2.2-35
6.) Assume the loop should lock with 1ms.

 TL = 1ms → n = 2/TL = 6280 rads/sec.
7.) Using a passive loop filter we get,
KoKd 2.2x106·0.4
1+2 = = = 161µs
Nn2 141·62802
2 2·0.7
8.) 2 = = = 223µs!!! (The problem is that 1+2 is too small)
n 6280
Go back and choose TL = 2ms → n = 2/TL = 3140 rads/sec.
KoKd 2.2x106·0.4 2 2·0.7
1+2 = = = 633µs and 2  = 3140 = 446µs → 1 = 187µs
=
Nn2 141·31402 n
Lecture 06 – (8/9/18) Page 6-15
Design Problem – Continued

9.) Design the loop filter.
For optimum sideband supression, C should be large. Choose C = 0.33µF.
1 187x10-6 2 446x10-6
 R1 = C = = 567 and R2 = C = = 1.351
0.33x10-6 0.33x10-6
The data sheet requires that R1+R2 ≥ 470 which is satisfied.
Block diagram of the DPLL frequency synthesizer design of this example:
C1=100pF
C1A C1B
v1(10kHz) SIGin 74HC4046A Data N
PC1
COMPin (EXOR) P0····P7 PE
v2'
PC2 VCOout 74HC40102 TC v '
(PFD) PCPout VCO (40103) 2
CP
PC3
TE PL MR
(JK)
PC2out VCOin R1 R2
+5V
R1 = R2=
R1=567W
47kW 130kW
R2=1.35kW
C = 0.33mF
Fig. 2.2-36

Lecture 06 – (8/9/18) Page 6-16
Simulation of the DPLL Example

The block diagram of this example is shown below.
PD LPF VCO
q1(s)
Ko q2(s)
q2'(s) Kd F(s)
s
Optional
¸ N Counter
1
N Fig. 2.2-25
The PFD-charge pump combination can be approximated as†

Kd(1+s2)
“KdF(s)” =
s(1+2)
Therefore, the loop gain becames
KoKd(1+s2) Kv (1+s2)
LG(s) = 2 = (the factor  is used for simulation purposes)
s (1+2) (s+)2(1+2)
For this problem,
Kd = 0.4V/rad., Ko = 2.2x106, 2 = 446µs, and 2+2 = 633µs. Also choose  = 0.01.
† R.E. Best, “Phase-Locked Loops – Design, Simulation, and Applications,” 4th Ed., McGraw-Hill, NY, p. 103
Lecture 06 – (8/9/18) Page 6-17
Simulation of the DPLL Example – Continued

PSPICE Input File
DPLL Design Problem-Open Loop Response - Best
VS 1 0 AC 1.0
R1 1 0 10K
* Loop bandwidth = Kv =8.8x10E5 sec.-1 Tau1=187E-6 Tau2=446E-6 N=141
ELPLL 2 0 LAPLACE {V(1)}= {8.8E+6/(S+0.01)/141*(0.446E-3*S+1)/(S+0.01)/0.633E-3}
R2 2 0 10K
.AC DEC 20 10 100K
.PROBE
.END
100
Simulation Results:
80
60
dB or Degrees
40
LG Phase
20
Phase |LG|
0 Margin
Note that the phase is very » 84°
-20 wc
close to 0° and |LG|>>1 at
low frequencies which is -40
10 100 1000 10 4 10 5
typical of type II systems. Frequency (Hz)
Lecture 06 – (8/9/18) Page 6-18
DPLL SYSTEM SIMULATION

Examples of Case Studies using the Best Software†
PLL Parameters-
Supply voltages:
Positive supply = 5V Negative supply = -5V
Phase detector:
Vsat+ = 4.5V Vsat- = 0.5V
Loop filter:
1 = 500µs 2 = 50µs
Oscillator:
Ko = 130,000 rads/V·sec Vsat+ = 4.5V Vsat- = 0.5V
The simulation program will be used to verify the following calculated values:
n = 17,347 rads/sec. (calculated prior to simulation)
 = 0.486 (calculated prior to simulation)
fpo = 7719 Hz
fp = 13,192 Hz
† Roland E. Best, Phase-Locked Loops – Design, Simulation, and Applications, 4th ed., McGraw-Hill Book Co., 1999, New York, NY
Lecture 06 – (8/9/18) Page 6-19
Case 1 – System Benchmark
vd
vd(mV)
vf
t(µs)

Lecture 06 – (8/9/18) Page 6-20
Case 2 - f = 8000Hz
vd
Phase error

vd(V) ≥ 90° vf

Lecture 06 – (8/9/18) Page 6-21
Case 3 – Loop Just Locks Out
vf
vf
vd
vd
vd(V)
 Loop pulls out

Lecture 06 – (8/9/18) Page 6-22
Case 4 – Pull-In Range Verification
vf
4.5
4.0
3.5 vd
3.0
vd(V) 2.5
2.0
1.5
1.0
0.5
Loop will not pull back in for df > 14,200 Hz

Lecture 06 – (8/9/18) Page 6-23
Case 5 – PFD and Illustration of a Virtually Infinite Pull-In Range

fp = ±40kHz f = 35 kHz to avoid clipping of vf.
vf
vd(V) vd
Tp  1.5ms

Lecture 06 – (8/9/18) Page 6-24
Case 6 – EXOR with Active PI Filter

4.5
vf
4.0
3.5
3.0
vd(V) 2.5
2.0
vd
1.5
1.0
0.5
Tp  5ms

Lecture 06 – (8/9/18) Page 6-25
SUMMARY
• Illustrated the Noise Performance of the DPLL
• Presented a DPLL Design Procedure
• Showed how to do DPLL System Simulation
• The DPLL is much more compatible with IC technology and is the primary form of
PLL used for frequency synthesizers

PLL Problems and Solutions (9/6/03) Page 1
PLL PROBLEMS AND SOLUTIONS

Problem 1
Solve for and evaluate the series Cs = 30fF Rs = 5.3Ω
and parallel resonance
Ls = 8.4mH
frequencies of the crystal whose
model is shown. It is Cp = 6pF
suggested to make appropriate
assumptions as the exact Crystal SU03H01P1
frequencies are difficult to
achieve.
Solution
Solving the exact frequencies for this problem is very challenging. It is better to assume that
series resonance (minimum impedance) will occur approximately when the impedance of Cs
cancels the impedance of Ls. This gives series resonance as
1 1
ω s2 = L C → fs = ≈ 10.026MHz
s s 2π LsCs
The parallel resonance can be approximated by assuming that it will occur close to the frequency
when the impedance of the series branch equals the negative impedance of the parallel branch.
This condition is given as,
1 1 1 1 1 1 11 1
= ωLs + → ωp2 = L  C + C  → fp = Ls Cs + Cp
ωCp ωCs s  s p 2π
fp ≈ 10.051MHz
SPICE Simulation:
Homework H01P1 - Crystal Impedance
IIN 0 1 AC 1.0
CP 1 0 6PF
CS 1 2 30FF
LS 2 3 8.4MH
RS 3 0 5.3OHM
RBIG 1 0 1GOHM
.AC LIN 101 9.5MEG 10.5MEG
.PRINT AC V(1)
.PROBE
.END
100kΩ
Impedance
10kΩ
1kΩ
100Ω
9.6 9.8 10 10.2 10.4
Frequency (MHz) SU03H01S1
Problem 2
A simple, doubly balanced passive CMOS mixer is shown along with the local oscillator
waveform, vOL(t). Assume that vRF(t) = ARFcos(ωRFt) and vLO(t) is the waveform shown
below. (a.) Find the mixer gain, Gc, in dB if the switches are ideal. (b.) Find the mixer gain in
dB if the switches have an ON resistance of Rs/2.
vLO(t)
Rs vLO(t) vLO(t) Switch
2 ON
vRF(t) +vIF(t) -
0 t
Rs
vLO(t) vLO(t)
Rs Switch
2 OFF 1
fLO F99E2P1
Solution
Assume the switches have an ON resistance of RON and work both parts (a) and (b)
simultaneously. Also, The equation for vIF(t) can be written as,
 Rs 
vIF(t) =  2R +2R  vRF(t) · sgn[vLO(t)]
 s ON
 Rs  4 4
VIF(jω) =  2R +2R  ARFcos(ωRFt) ·  cos( ω LO t) + cos (3 ω LO t) + ···
 s ON  π 3π 
 Rs  4ARF
∴ VIF(jω) ≈  2R +2R  cos(ωRFt) · cos(ωLOt)
 s ON π
 Rs  2ARF
=  2R +2R  cos[ωRF -ωLO)t]
 s ON π
The conversion gain in general is written as
|VIF|  Rs 2
Gc = |V | =  2R +2R 
RF  s ON π
1 1
(a.) For RON = 0, Gc = → Gc = = -9.943dB
π π
2 2
(b.) For RON = 0.5Rs, G c = → Gc = = -13.465dB
3π 3π
Problem 3
Use SPICE to demonstrate that the
following circuit is a frequency doubler. 2V
If vin(t) is a sinusoid of 10kHz and 1.5V M1 M2
peak, show vin(t) and vout(t) as a 10µm
function of time. The model parameters 1µm
of the MOSFETS are K N ’ = 110µA/V2, vin(t) vin(t)
vout(t)
VTN = 0.7V, and λN = 0.04V-1.
Solution 100kΩ
The results of this problem are below. -2V SU03H01P3
SPICE Input File:
Homework H01P3 - Frequency Doubler
VIN 1 0 DC 0.0 SIN(0 1.5 10KHz)
EVIN 0 2 1 0 1.0
VDD 4 0 DC 2.0
VSS 5 0 DC -2.0
M1 4 1 3 3 NMOS1 W=10U L=1U
M2 4 2 3 3 NMOS1 W=10U L=1U
RTAIL 3 5 100K
.MODEL NMOS1 NMOS VTO=0.7 KP=110U LAMBDA=0.04
.OP
.TRAN (10U 1000U)
.PRINT TRAN V(1) V(2) V(3)
.PROBE
.END
Output Plots:
1.5V
vin(t)
1.0V
vout(t)
0.5V
-0.5V
-1.0V
-1.5V
0 200 400 600 800 1000
SU03H01S3
Time (µsec.)
Problem 4
An 10nH inductor has a Q of 5 and is used to create a tank circuit with a 10pF capacitor.
Assume the capacitor is ideal. (a.) What is the resonant frequency of this circuit? (b.) What
value of parallel negative resistance should be used to create an oscillator? (c.) If C is changed
to 20 pF, what is the new value of the parallel negative resistance?
Solution
C = 10pF:
1 26
Lp =  1+ 2 = 25 ·10nH = 10.4nH
 Q
1 1
ωo = = = 3.1623x109 radians/sec.
L pC 10.4nH·10pF
ωoLs ω oL s
Q= R → Rs = Q = 6.201Ω
s
∴ Rp = (1+Q2)Rs = 26·6.201Ω = 161.245Ω
C = 20pF:
1 1
ωo = = = 2.1926x109 radians/sec.
L pC 10.4nH·20pF
ωoLs ω oL s
Q= R → Rs = Q = 4.3853Ω
s
∴ Rp = (1+Q2)Rs = 26·4.3853Ω = 114.017Ω
Problem 5
Give a block diagram of simple brute-force coherent direct synthesizer that will generate 1.75f
from f. The input frequency f is to vary from 12 MHz to 15MHz. Since f is variable, you
cannot use frequency multipliers (integer frequency dividers and mixers are allowed) in your
design. A simple design will receive more credit. What other frequencies will be present at the
output?
Solution
Approach: fout = fxf – f/4 = 1.75f
f 2f
2f±0.25f
f
f/4
÷ 4
S03H01S5
The frequency 2.25f will also be present at the output.
Problem 6
A phase-locked loop has a center frequency of 105 rads/s, a Ko of 103 rad/V-s, and a Kd of 1
V/rad. Assume there is no other gain in the loop. Determine the loop bandwidth in the first-
order loop configuration. Determine the single-pole, loop-filter pole location to give the closed-
loop poles located on 45° radials from the origin of the complex frequency plane.
Solution
103
The loop bandwidth = Kv = KoKp = s
In order to produce poles at 45° to the axis, we add a loop filter pole at ω1 where
ω1 = 2Kv = 2000 rads/sec.
The filter transfer function becomes,
ω1 2000
F(s) = = s+2000
s+ω1
Problem 7
For the same PLL of the previous problem, design a loop filter with a zero that gives a crossover
frequency for the loop gain of 100 rads/sec. The loop phase shift at the loop crossover
frequency should be –135°.
Solution
A plot of the desired loop gain is shown below.
-20dB/dec.
Loop Gain (dB)
40dB
20dB
-40dB/dec.
0dB ω1 = ω(rads/sec)
ω2 = Kv = 1000
10 100 SU03H02S2
If ω2 (the zero frequency) is at the unity gain point, then the loop phase shift will be
–135° at this point. Therefore, we require that ω2 = 100 radians/sec.. If ω1 = 10 radians/sec.,
the requirement will be satisfied as shown in the above plot.
The design of the filter becomes, R1
1 1
ω2 = R C and ω1 = (R +R )C
2 1 2 C
ω2 R1 R2
∴ = 1 + R = 10 → R1 = 9R2
ω1 2
Now appropriate values of R1 , R2, and C can be chosen. Fig. SU03H02S2A

Problem 8
Estimate the capture range of the PLL of the previous problem assuming that it is not artificially
limited by the VCO frequency range.
Solution
For capture we need
π
|(ωi - ωo)| < 2 Kv|F(j(ωi - ωo)|
If we assume that
π
|(ωi - ωo)| = 2 Kv|F(j(ωi - ωo)|
then with ωo = 105 rads/sec and Kv = 1000 rads/sec. we get,
|(ωi - ωo)| = 1570|F(j(ωi - ωo)|
Now from the previous problem, we know that |F(jω)| is given as
|F(jω)|
1 10 100
1 ω
0.1
SU03H02S3
From this figure we can solve the above equation to find that
(ωi - ωo) = 157 rads/sec.
which is the capture range.
Problem 9
A filter for a phase locked loop is specified as C=10pF
10ω1 1,000,000 R R
|F(s)| = = s+100,000 R = 10kΩ
s+ω1
R2 Vout
and must be implemented on a CMOS chip using Vin R R
resistors no larger than 10kΩ and capacitors no larger _
than 10pF. Using the circuit shown, find the values R1
of R1 and R2 that will satisfy the component value +
constraints. SU03H02P4
Solution
Find the currents i1 and i2, C=10pF
v in R R 1 vi n v in R R
i1 = = = R = 10kΩ
RR 1 R+R 1 2RR + R 2 R T1
R + R+R 1 i2
1 R2 Vout
and Vin R R
vout R _
i2 = RR 1 R+R 1 + sCvout R1 i1
R + R+R +
1
R 2 v out vout SU03H02S4
= + sCv out R T2 + sCvout
=
2RR + R 2
2
Solving for the sum of the currents flow toward the minus op amp input terminal gives,
v in vout vout RT2 1 1
+
R T1 R T2 + sCv out = 0 → v in = -R T1 sCRT2+1 = -10 s
+1
105
10-5
∴ CRT2 = 10-5 → RT2 = -11 = 106
10
2RR 2 + R 2 R2 6
R T2 = = 2R + = 20x10 3 + 100x10 = 106
R2 R2 R2
100x106
∴ R2 = = 100Ω
106-20x103
R T2 R2 100x106
R T1 = 10 = 105 → 2R + R = 20x103 + R = 105
1 1
100x106
∴ R1 = = 1000Ω
105-20x103
This problem shows how a clever circuit technique can make a filter suitable for integrated circuit
implementation.
Problem 10
This homework is designed to provide practical inductor design experience for students. Use
ASITIC for the design and analysis. However, other tools are acceptable if they give all the
results including layout.
A 5GHz LC tank will be designed as a part of LC oscillator. C value is given as 1pF.
(a) Find L value. (b) Design and simulate a spiral inductor with this L value (± 5% range).
Optimize design parameters, W, S, D and N to get a high Q (Qmin = 5). Show L, Q, fSR value
obtained from simulation. (c) Show the layout. (d) Give a lumped circuit model with component
values.
Solution
(a) LC tank oscillation frequency is given as 5GHz.
1 1
L= 2 = 9 -12 = 1.01x10-9
ωosc ·C (2π·5x10 )(1x10 )
(b) One possible solution is
Parameters: W = 16um, S = 2um, D = 150um, N =2.5
Resulting inductor: L = 0.952nH, Q = 8.54, fSR = 19.35GHz @ 5GHz
(c) Layout
(d) Pi model from ASITIC is shown below. This is the analysis result from ‘pix’
command.
0.952nH 3.27
71.1fF 65.1fF
-1.3
3.03
Problem 11
Assume an LPLL has F(s) =1 and the PLL parameters are Kd = 0.8V/radians, Ko = 100 MHz/V,
and the oscillation frequency, fosc = 500MHz. Sketch the average control voltage at the output of
the phase detector if the input frequency jumps from 500MHz to 550MHz.
Solution
Find the transfer function from the input frequency, fin, to the
output of the phase detector, vd. ω1 vd
K d
K dK o
Vd = Kd(θ1-θ2) = Kdθ1- s Vd ω2 Ko
s
 ω1 SU03H03S1A
 K dK o
Vd1+ s  = Kdθ1 = Kd s 
Vd Kd Kd Kd ∆ω1 k1 k2
∴ = s+K K → Vd(s) = s+K K ω1(s) = s+K K s = s + s+K K
ω1 d o d o d o d o
Kd∆ω1 Kd∆ω1
By partial fraction expansion we can show that k1 = - k2 = K K = K = 0.4V
d o v
Kd∆ω1 (V/rad)(rad/sec)
Note the units of K are 1/sec =V
v
and Kv = (2π·100MHz/V)(0.8V/rad.) = 502.65x106 (1/sec.)
Kd∆ω1
∴ vd(t) = K (1-e-Kvt) = 0.4(1-e-502.65x106t)
v
A plot of vd(t) is shown below.
0.400V
0.267V
vd(t)
0.133V
0V
0 2 4 6 8 10
Time (ns) Fig. SU03H03S1B
Problem 12
A Type I PLL incorporates a VCO with Ko = 100MHz/V, a phase detector with Kd = 1V/rad,
and a first-order, lowpass filter with ωLPF = 2π x106 radians/s shown below. A divider of 100
has been placed in the feedback path to implement a frequency synthesizer. (a.) Find the value
of the natural damping frequency, ωn, and the damping factor, ζ, for the transfer function
φout(s)/φin(s), for this PLL. (b.) If a step input of ∆φin is applied at t = 0, what is the steady-
state phase error at the output of the phase detector, φe? The steady-state error is evaluated by
multiplying the desired phase by s and letting s→0.
Phase Detector Filter VCO

φin + φe 1 Vc Ko φout
Kd s
ωLPF +1 s
-
Divider
1/100
F02E2P3
Solution
Ko  1  K  φ - φ out → φ  1+ K o  Kd   K o  Kd 
(a.) φout = s  s  d in N  out sN  s  = s  s  φin
ω + 1  1 +   + 1
 LPF    ωLPF  ωLPF 
φout(s) K oK d KoKdωLPF ωn2
∴ = s  K oK d = =
φin(s) K o K d ω L P F s 2 + 2 ζω n s + ω n 2
s  1 + + 2
 ωLPF N s + ω LPF s + N
KoKdωLPF 2πx106·2πx108
Thus, ωn2 = N = 100 = 4π2x1012 → ωn = 2πx106
ωLPF ωLPF 1 NωLPF 1 100·2πx106

ζ= = =2 K oK d = 2 = 0.5
2ωn KoKdωLPF 1·2πx108
2 N
∴ ω n = 2 π x10 6 and ζ = 0.5
(b.) First we must solve for φe(s) which is found as

s  s 
s 1 +  s 1 +
 ωLPF  ωLPF KoKdωLPF
φe(s) = Ko φout(s) = Ko φ (s)
K o K d ω L P F in
s2+
ω LPF s + N
∆φin K d(s2+ ω LPF s)∆φ in
If φin(s) = s , then we can write sφe(s) =
K oK dω L P F
s 2 + ω LPF s + N
Therefore, we see that the steady-state error is φ (t= ∞ ) = 0.

Problem 13
Modify the active filter shown of Problem 9 to C2
design the lag-lead loop filter shown below. The
capacitors can be no larger than 10pF. Give the R R
values of R1, R2, C1 and C2. R = 10kΩ
|F(jω)| dB R2 Vout
Vin R R
10K 100K
0dB _
ω(rads/sec.) R1
+
SU03H03P3A
-20dB
S03H03P3
Solution
The transfer function corresponding to the above Bode plot is,
s
+1
105
F(s) = 1
+1
104 C1 C2
The modification of the filter is vd R R vc
shown where from Prob. 9,
2RR i+ R 2 - -
R Ti = RT1 RT2
Ri + +
The transfer function of this Loop Filter
filter is found as, SU03H03S2A
Vc(s)
F(s) = V (s) =
d
 R T2  sR T1 C 1 +1
⇒ RT2 = RT1 = RT , RTC1 = 10-5 and RTC2 = 10-4
 R T1 sRT2C2+1
We see if RT2 = RT1, then C2 = 10C1. Choosing C2 = 10pF gives C1 = 1pF. This gives
10-4 10-4
RT = C = -11 = 107
2 10
2RR i+ R 2 R2 100x106 100x106
RT = 3
= 2R + R = 20x10 + R 7
= 10 ⇒ R1 = 7 = 10.02Ω
Ri 1 1 10 -20x103
Therefore, R1 = R2 = 10.02Ω, C1 = 1pF and C2 = 10pF
The realization is completed by replacing each of the RT resistors with the following equivalent:
RT1 10kΩ 10kΩ
10.02Ω
SU03H03S3B
Problem 14
Using the filter of Problem 13, find the value of ωn and ζ of the PLL if Kd = 1V/radians, K o =
2Mradians/V·sec. What is the steady state phase error in degrees if a frequency ramp of 109
radians/sec.2 is applied to the PLL?
Solution
Using the definition give in the notes for the time constants of the passive lag-lead filter we get,
s
+1
105 sτ2 + 1
F(s) = 1 = ⇒ τ2 = 10-5 sec. and τ1 = 9x10-5 sec.
+1 s( τ +
1 2τ ) + 1
104
K oK d 2x106
∴ ωn = = = 2 x105 = 141.4x103 radians/sec.
τ1+τ2 10-4
ωn 1  2x105 -5 1  1 1
ζ = 2 τ2 + K K = 2 10 + = 1 + 20  = 0.742
 o d  2x106 2
Assuming the PLL has a high loop gain, then the steady-state phase error can be found as
∆ω· 109 1
θe(∞) = 2 = = 20 radians = 2.86°
ω n 2x1010
Problem 15
Solve for the crossover frequency of the PLL of Problems 13 and 14 and find the phase margin.
Use SPICE to find the open-loop frequency response of the PLL and from your plot determine
the crossover frequency and phase margin and compare with your calculated values.
Solution
The crossover frequency can be found as,
ωc = ωn 2ζ2 + 4ζ4+1 = 2 x105 2·0.742 2 + 4·0.7424+1
= 2 x105(1.6089) = 2.275x105 radians/sec. = 36.208kHz

The open loop transfer function is given as
Kv 1+sτ1 2x105 1+s10-5
LG(s) = s  = s  1+s10-4
 1+sτ2
The phase margin can be written as,
 ωc   ωc 
PM = 180° - 90° +tan-1 5 - tan-1 4 = 90° + 66.27° - 87.48° = 68.79°
10  10 
SPICE Results:
Problem H3P5-Open Loop Response of an LPLL with Lead-Lag Filter
VS 1 0 AC 1.0
R1 1 0 10K
* Loop bandwidth = Kv =2xE+6 Tau1=1E-4 Tau2=1E-5
ELPLL 2 0 LAPLACE {V(1)}=
+{(2E+6/(S+0.001))*((1+1E-5*S)/(1+1E-4*S))}
* Note: The 0.001 added to “S” in the denominator is to prevent
* blowup of the problem at low frequencies.
R2 2 0 10K
.AC DEC 20 10 100K
.PROBE
.END
100
Phase + 180°
80
dB or Degrees
60
|F(jω)| Phase
40 Margin
≈ 69°
20
0
-20
10 100 1000 104 105
SU03H03S5 Frequency (Hz) ωc ≈ 36kHz
The simulation results agree well with the calculated results.
Problem 16
For the DPLL shown assume that N = 1000 and the –3dB bandwidth is 1000 Hz. (a.) Assume
that ζ = 0.2 and solve for the natural pole frequency, ωn, the filter time constant, τ = RC, and the
phase margin. (b.) Repeat part (a.) if ζ = 0.7. (c.) Repeat part (a.) if ζ = 1. Verify your
answers with PSPICE.
VDD
I1
v1(t) QA
S1 v2(t)
PFD VCO
v2'(t) QB
S2 C
R
I2
1/N
SU03H04P1
Solution
The filter output can be written as,
Kd Kd  θ2
Vf(s) = s (sτ +1)(θ1-θ2’) = s (sτ +1)θ 1 + N  where τ = RC
Ko K oK d  θ 2  K v (s τ +1) K v (s τ +1)
θ2(s) = s Vf(s) = 2 (sτ +1)θ 1 + N  = θ 1 (s) + θ2(s)
s s2 Ns 2
The closed-loop response is given as,
θ2(s) K v (s τ +1) K v (s τ +1)
= = 2
θ1(s) K vτ K v s + 2ω nζs + ω n2
2
s + N s + N
Kv 2ζ
∴ ωn = N and τ=
ωn
We know that the loop bandwidth, ω-3dB, can be expressed as
ω-3dB
ω-3dB = ωn 2 ζ 2 +1+ (2ζ2+1)2 +1 → ωn =
2 ζ 2 +1+ (2ζ 2+1)2 +1
ζ = 0.2:
ωn = 3933 rads/sec., τ = 102µs and PM = 0°+tan-1(2000π·102µs) = 32.6°
ζ = 0.7:
ζ = 1:
Problem 16 – Continued
PSPICE Input File:
Homework4, Problem 1
VS 1 0 AC 1.0
R1 1 0 10K
ELPLL1 2 0 LAPLACE {V(1)}= {5044*5044*(1+102E-6*S)/(S+0.01)/(S+0.01)}
R2 2 0 10K
R3 3 0 10K
R4 4 0 10K
.AC DEC 20 1 100K
.PRINT AC VDB(2) VP(2) VDB(3) VP(3) VDB(4) VP(4)
.PROBE
.END
Plot of Results:
100
ζ = 0.2 ζ=1
ζ = 0.7 ζ = 0.2
dB or Degrees
50
PM PM
ζ=1 = 72° = 79°
PM
= 32°
0
ωc
-50
1 10 100 1000 10 4 10 5
Frequency (Hz) SU03H04S1
Problem 17
A type-I, second-order DPLL synthesizer is to be made with components having the following
values:
Ko = 4x108 rads/sec./V fref = 12.5 kHz Kd = 0.15 V/rad β = 2π
Design a type-I, second-order synthesizer having the following specifications:
1.) Output frequency range = 50MHz
2.) Lock range = 10MHz at the output
3.) Damping factor = 0.75.
Determine the components for the loop filter. Let C = 0.5µF. Make a sketch of your filter with
all components carefully labeled. Once your design is complete, determine the pull-in range in
Hz (at the output) and the lock time of your loop.
Solution
fout 50MHz K oK d 4x108·0.15
N = f = 12.5kHz = 4000 and Kv = N = 4000 = 15,000 sec.-1
r
∆ωH = βKvN = 2π·15x103·4000 = 377x106 rads/sec.
τ2 τ2 τ2 ∆ωL 62.8Mrads/sec 1
∆ωL = ∆ωH = 377 Mrads/sec. → = = =
τ1 τ1 τ1 ∆ωH 377Mrads/sec 6
∴ τ1 = 6τ2
1 1 1
ζ = 0.5 (1+τ2Kv) → 1.5 = (1+τ2Kv) → 2.25 = (1+τ2Kv)2
K vτ1 K vτ1 K vτ1
2.25·Kv(6τ2) = 13.5 Kvτ2 = 1 +2 Kvτ2 + (Kvτ2)2 → 0 = 1 – 11.5x + x2
11.5 1
where x = Kvτ2. Solving for x gives x = Kvτ2 = 2 ±2 11.5 2 - 4 = 0.0876
0.0876 5.84
∴ τ2 = 15,000 = 5.84µs = R2C = R2(0.5µF) → R2 = 0.5µF = 11.7Ω
35
τ1 = 6τ2 = 35µs = (R1+R2)C → R1+R2 = 0.5µF = 70.08Ω → R1 = 58.4Ω
Filter schematic:
R1 = 58.4Ω
R2 =
11.7Ω
C=
0.5µF
SU03H04S2
Kv
∆ωP = Nβ 2 2ζωnKvF(0) -ωn2 and ωn = = 20,702 rads/sec
τ1
∴ ∆ωP = 4000·2π 2 2·0.75·20,702·15,000 - (20,702)2 = 216.85 Mrads/sec.
∆ fP = 34.51 MHz
2π 6.283
TL = = 20,702 = 303.5µs
ωn
Problem 18
Given the DPLL described by
1+5x10-6s
1+τ2s
Kd = 2.2 V/rad F(s) = =
1+τ1s 1+2x10-5s
fref = 12 kHz Ko = 25 MHz/V β = 2π Ν = 15,000
Determine the type number and order of the system and then find:
(a.) The output frequency in Hz.
(b.) The crossover frequency in Hz.
(c.) The noise bandwidth (Hz).
(d.) The closed-loop phase –3dB bandwidth in Hz
(e.) The steady-state phase error in response to a phase step of 0.1 radian.
(f.) The hold range (±Hz at the output).
(g.) The lock range (±Hz at the output).
(h.) The lock time.
(i.) The pull-in range (±Hz at the output)
(j.) The steady-state phase error in radians in response to a frequency step equal to the lock
range.
Solution
This is a type-I, second-order system. The closed loop transfer function is,
 1+τ2s
K v 
KvF(s) θ2 θ2 K vF(s)  1+τ1s Kv(1+τ2s)
θ2 = s  θ 1 - N  → = K v F(s) = =
θ1  1+τ2s K v (1+ τ 2 s)
s+ N s(1+ τ s) +
Kv  1 N
 1+τ1s
s + N
Kv
(1+τ2s)
θ2 τ1 Kv(1+τ2s)
= Kv  =
K v s2+2ζω s+ω 2
θ1 s
s 2 +  1 + N τ2 + n n
τ1 τ1N
Kv 2π·25x106·2.2
∴ ωn = = = 33.94 Krads/sec
N τ1 2x10-5·15,000
N  τ2Kv 15,000  2 π ·25x10 6 ·2.2·5x10 -6

ζ = 0.5 1+ N  = 0.5 1 + 
K vτ1  2π ·25x10 6·2.2·2x10-5 15,000 
= (0.5)(1.4732)(1.115) = 0.821
(a.) fo = Nfr = 15,000·12kHz = 180MHz
ωn 33,940
(b.) fc = 2 ζ 2 + + 4ζ4+1 = 2(0.821)2+ 4(0.821)4+1 = 9,397 Hz
2π 2π
Problem 18 - Continued
ωn 1 33,940 1 
(c.) Bn = 2  ζ +  = 2  0.821 + = 19.1kHz
 4ζ   4·0.821
Nωn  N ω n
(d.) ω-3dB = ωn b + b2+1 where b = 2ζ2 + 1 - K  4 ζ - K 
v  v 
33,940·15,000  33,940·15,000
b = 2(0.821)2 + 1 -  4·0.821 - = -0.320
2π·25x106·2.2  2π·25x106·2.2
ω-3dB = 33,940 -0.320 + (-0.320)2+1 = 29,003 rads/sec. → f-3dB = 4615Hz

(e.) Because this is a Type-I, second-order system, the phase error in response to a phase step is
zero provided that ∆θ < β.
βKv
(f.) ∆ω H = β NK = β K v → ∆ fH = = (2π·25x106·2.2) = ±345.6MHz
2π
τ2  5x10-6
(g.) ∆ωL = ∆ωH → ∆fL = ±345.6MHz   = ±86.39MHz
τ1 2x10-5
2π 2π
(h.) Lock time = TL = = 33,940 =185µs
ωn
(i.) Pull-in range.
2ζωnKvF(0)
∆ωP = Nβ 2 N - ωn2 where F(0) = 1 for the filter selected.
15,000·2π 2 2·0.821·33,940·2π ·25x106·2.2

∴ ∆ fP = 15,000 - (33,940 2 ) = 243.7MHz
2π
Note that,
∆ fL < ∆ fP < ∆ fH
∆ωosc 2π·86.39x106
(j.) εss = K = = 1.57 rads < β as required
v 2π·25x106·2.2
Problem 19
Construct an accurate Bode plot of the synthesizer in Problem 18. Use this Bode plot to
determine the phase margin.
Solution
PSPICE was used to solve this problem. The input file and the results are shown below.
Problem H4P4-Open Loop Response of an DPLL with Lead-Lag Filter

VS 1 0 AC 1.0
R1 1 0 10K
ELPLL 2 0 LAPLACE {V(1)}= {23.04E+3*(1+5E-6*S)/(1+2E-
5*S)/(S+0.001)}
R2 2 0 10K
.AC DEC 20 10 100K
.PROBE
.END
100
dB or Degrees
50 Phase
Margin
= 72°
-50
10 100 1000 10 4 10 5
Frequency (Hz) SU03H04S4
Problem 20
Write the transfer functions giving: (1) The VCO phase noise in the output, (2) the reference
oscillator phase noise in the output. Use the literal form of the equations. The phase noise of the
VCO used in the synthesizer of Problem 3 is shown below. Make an accurate plot of the VCO
phase noise in the output of the synthesizer.
-50
SSB Phase Noise (dBc/Hz)
-100
-150
-200
10 100 1000 10 4 10 5 10 6 10 7
Frequency Offset from Carrier (Hz) SU03H04P6
Solution
The following block diagram will be Phase Detector
used to find the phase noise in the +
output due to the VCO phase noise. θr θe ωo
K d F(s) Ko
 K v F(s) θ o  -
θo = θ o,n - sN 
 θo' θo,n
1 θo + + 1
θo s s
= N
θ o,n K vF(s) SU03H04P5
s+ N
θo s s(1+τ1s)
= =
θ o,n K v  1+τ2s  K vτ2 K v
s+ N   s 2 τ 1 + s  1+ N  + N
 1+τ1s
From Problem 3 of this assignment we get,
Kv
(1+τ2s)
θo 1 τ1
= N Kv  Kv
θr,n s
s 2 +  1 + N τ2 +
τ1 τ1N
The following PSPICE input file gives the results plotted below.
Homework 4, Problem 5 -In/Out VCO Phase Noise, Transfer Function
.PARAM N=15000, KVCO=157.1E6, T1=2E-5, T2=5E-6, KD=2.2, E=0.001
*Input Phase Noise
vphasenoise 1 0 ac 1.0
R1 1 0 10k
EPN 2 0 freq {v(1)} = (1,-40,0) (10,-70,0) (100,-100,0)
+(1E5,-160,0) (1E6,-160,0)
RPN 2 0 10k
*VCO Noise Transfer Function
EDPLL1 3 0 LAPLACE {V(1)}=
+{S*(T1*S+1)/(S*S*T1+KD*KVCO*T2/N*S+S+KD*KVCO/N)}
RDPLL1 3 0 10K
*VCO Noise at the Output
+{S*(T1*S+1)/(S*S*T1+KD*KVCO*T2/N*S+S+KD*KVCO/N)}
RDPLL2 4 0 10K
*Reference Noise Transfer Function
+{KD*KVCO*(1+T2*S)/(S*S*T1+S+KD*KVCO/N*S+KD*KVCO/N)/N}
RDPLL3 5 0 10K
*Reference Noise at the Output
+{KD*KVCO*(1+T2*S)/(S*S*T1+S+KD*KVCO/N*S+KD*KVCO/N)/N}
RDPLL4 6 0 10K
.AC DEC 20 1 1000K
.PRINT AC VDB(2) VDB(3) VDB(4) VDB(5) VDB(6)
.PROBE
.END
VCO Output Noise (and Reference Output Noise):
50
Reference Transfer Function VCO Transfer Function
0
-50
dB or dBc
VCO Phase Noise and Output Reference Noise

-100 VCO Input and
Ouput Phase Noise
-150
VCO Output Phase Noise
-200
Output Reference Noise
-250
1 10 100 1000 10 4 10 5 10 6
Frequency (Hz) SU03H04S5B
Problem 21
Sketch the time variation and frequency spectrum of an RF signal with 75 percent amplitude
modulation. Show several cycles of the modulated wave. Make the modulation frequency 1/10
of the carrier frequency. The unmodulated carrier has a peak amplitude of 1.0V.
Solution
The expression for the general form of amplitude modulation is,
  ωct 
v(t) = 1.01 + m a cos  10   cos(ωct) = [1 + 0.75cos(0.1ωct)]cosωct
1.5
1
0.5
v(t) 0
-0.5
-1
-1.5
-2
0 π 2π 3π 4π 5π 6π 7π 8π
ωct Fig. SU03H05S1
vmax. = 1.75V and vmin. = 0.25V
Problem 22
The level of an SSB AM spur is observed to be –75 dBc. If the carrier has a peak amplitude of
1V, what is the variation of the carrier in ±V needed to produce the observed spur?
Solution
Vc = 0dBc
The observed spectrum is
Vc
 ma m = -75dBc
SSB = 20 log10 2  → ma = 2·10SSB/20 2 a
f
fc SU03H05S2
∴ ma = 2·10-75/20 = 335.6x10-6
∆v
If Vpeak = 1V, then ma = V → ∆ v = 3.35.6µV
p
Problem 23
A pair of 5 kHz PM/FM spurs appear on a 10 MHz carrier. The level of each spur is –50dBc.
(a.) What phase deviation in ±degrees is need to produce the spurs? (b.) What frequency
deviation in ±Hz is needed to produce the spurs?
Solution
(a.) The single sideband spurs can be expressed as,
 θd β
SSB = 20 log10 2  = 20 log102 
Solving for θd gives,
θd = 2·10SSB/20 = 2·10-50/20 = 2·0.003162 = 6.325 milliradians = ±0.3624°

∆ fc
(b.) We know that θd = β = f which gives
m
∆fc = βfm = θdfm = 6.325x10-3·5x10+3 = ±31.6 Hz
Problem 24
The carrier and spurs of Problem 3 above are passed through a frequency tripler. Make a sketch
of the output spectrum of the tripler. Label and show all important features of the spectrum.
Solution
After passing through a tripler, the SSB spur is increased by 20log10(3) or +9.54dB.
The resulting spectrum is shown as,
0dBc 0dBc
-50dBc+20log10(3) = -40.5dBc
5kHz -50dBc 5kHz
10MHz-5kHz x3 30MHz-5kHz
Frequency Frequency
-40.5dBc 10MHz 10MHz+5kHz 10MHz 30MHz+5kHz
-40.5dBc SU03H05S4
Problem 25
A 100 MHz carrier having a –40 dBc upper sideband at 100.002 MHz and a –47 dBc lower
sideband at 99.998 MHz is passed through an ideal limiter followed by a bandpass filter centered
at 100 MHz with a 10 kHz total bandwidth. Make a sketch of the spectrum at the output of the
filter. Label all frequencies and amplitudes.
Bandpass
Ideal Limiter Filter
10kHz
100MHz
SU03H05P5
Solution
Asymmetrical sidebands imply the presence of both AM and FM as show below.
Carrier Carrier
AM FM
-40dBc
-47dBc SA SA SF
fc-fm
f f f f
fc-fm fc fc+fm fc fc-fm fc fc+fm fc fc+fm
SF SU03H05S5
-40dBc = 10-40/20 = 0.01 and -47dBc = 10-47/20 = 4.467x10-3

Solve for SA and SF as follows,
SA + SF = Upper sideband = 0.01
SA - SF = Lower sideband = 4.467x10-3

Upper sideband + Lower sideband
SA = 2 = 7.234x10-3
Upper sideband - Lower sideband
SF = 2 = 2.767x10-3
The limiter will remove all AM sidebands and the filter removes all products other than the
sidebands at ±2kHz. Therefore the output spectrum will appear as,
Carrier
-51.16dBc
fc-fm
f
fc fc+fm
-51.16dBc SU03H05S5A
where fc = 100MHz and fm = 2kHz.
Problem 26
An LC oscillator is shown. The value of the inductors, L, are 5nH VDD
and the capacitor, C, is 5pF. If the Q of each inductor is 5, find (a.)
the frequency of oscillation, (b.) the value of negative resistance that L L
should be available from the cross-coupled, source-coupled pair (M1 C
and M2) for oscillation and (c.) design the W/L ratios of M1 and M2
to realize this negative resistance.
Solution M1 M2
(a.) The equivalent circuit seen by the negative resistance circuit is:
2L 2Rs The frequency of oscillation is given as
1/ 2LC or ωo = 2πx109 radians/sec. 2mA
C
Therefore the series resistance, R s , is found F00E2P2
as
ωL 2πx109·5x10-9
F00E2S2A Rs = Q = 5 = 2π Ω
Converting the series impedance of 2L and 2Rs into a parallel impedance gives,
1 0.5 Rs-jωL 0.5R s 0.5ωLs

Y= = · = 2 2 2-j 2 2 2
2Rs+jω2L R s +jω L R s -jω L Rs +ω L R s -ω L
The reciprocal of the conductance is the parallel resistance, Rp, given as
Rs2+ω2L2 4π 2 + 4π 2 ·25
Rp = 0.5R = = 4π(26) = 326.7Ω
s π
∴ R neg = -104π Ω = -326.7Ω
(b.) The negative resistance seen by the RLC circuit is found as follows.
iin iin = gm1vgs1 - gm2vgs2 = gm(vgs1 - vgs2) = - gmvin ∴
-1
Rin = g
m
vin
Assuming the 2mA splits evenly between M1 and M2 for the negative
resistance calculation gives,
M1 + + M2
vgs1 vgs2 1 W/L
- - Thus, gm = gm1 = gm2 = = 2mA·110x10-6 (W/L) = 2132
104π
2mA 2132  2
∴ W/L =  = 42.6 ⇒ W/L = 42.6
104π
F00E2S2B
Problem 27
An LC oscillator is shown. Find an expression for the VDD
frequency of oscillation and the value of gmRL necessary for
oscillation. Assume that the output resistance of the FET, rds, RL
can be neglected. L Vout
Solution
An open-loop, small-signal model of this oscillator is shown M1 C1
below. C2
L F99E2P4
+ +
V' gmV' RL C2 Vo
- C2 -
F99P3S2
Writing a nodal equation at the output and input gives,
V o-V' Vo-V’
gm V’+G LV o+sC2V o+ sL = 0 and sL = sC2V’ → Vo = V’(1+s2LC2)
1 V’
∴ gmV’ + G L +sC 1 + sL (1+s2LC2)V’ - sL = 0
Assuming a non-zero value of V’ gives,

1 1 1 1
gm+G L +sC 1 + sL (1+s2LC2)- L = gm+GL+sC1+ sL +s2LC2GL+s3LC1C2+sC2 - sL = 0
or (gm+GL-ω2LGLC2) + jω[C1-ω2LC1+C2] = 0
Therefore, the frequency of oscillation is,
C1+C2 1
ω osc = LC1C2 = LC1C2
C1+C2
The value of gmRL necessary for oscillation is
 C 2 C2
gm+GL = LGLC2ωosc2 = GL 1 + C  → gmRL = C
 1 1
Problem 28
A Clapp oscillator which is a version of the Colpitt’s
oscillator is shown. Find an expression for the VDD
frequency of oscillation and the value of gmRL necessary RLarge C1
for oscillation. Assume that the output resistance of the
FET, rds, and RLarge can be neglected (approach
C2
infinity). VBias
L
Solution
C3 RL
The small-signal model for this problem is IBias
shown below.
The loop gain will be defined as Vgs/Vgs’. C2 F02FEP5
C1
Therefore, - +
V gs = Vgs
gmVgs' RL C3 L
-g m V gs' RL||(1/sC 3)  1 
1 1 sC2
R L ||(1/sC 3 ) + sC + sC + s L F02FES5
1 2
RL(1/sC3) 1
-g m V gs ' R +(1/sC ) sC
L 3 2
= RL(1/sC3) 1 1
R L +(1/sC 3 ) + sC1+ sC2 + s L
-g m R L 1 -g m R L
Vgs sRLC3+1 sC2 sC2
T(s) = V = R 1 1 = 1 1
gs L
sR L C 3 + 1 + sC1+ sC2 + s L R L + (sR L C 3 +1)  sC + sC + s L
 1 2 
-g m R L
T(s) = C2
sC 2 R L + (sR L C 3 +1)(s 2 LC 2 + C + 1 )
1
-g m R L
T(s) = C 2C 3 C2
sC 2 R L +s 3 R L C 3 LC 2 + sR L C + sC 3 R L + s 2 L C 2 + C + 1
1 1
-g m R L
T(jω) = C2 C 2C 3 = 1 + j0
2 2
[1+ C - ω LC 2 ] + j ω [R L (C 2 +C 3 ) + R L C -ω R LC 3LC 2]
1 1
C2C3 1 1 1 1
∴ C2+C3 + C = ωosc2C3LC2 → ω osc = L C1 + C2 + C3
1
C2 1 1 1 C2 C2 C2
Also, gm RL = ωosc2LC2 –1 - C = C2 C + C + C  - C -1 = C → g m R L = C
1  1 2 3 1 3 3
Problem 29
The objective of this problem is to use passive LC tank and negative feedback circuit to
design an LC oscillator that meets the GSM specification. At first, show the condition that the
1
ideal circuit oscillates at ωosc = and find quality factor, Q. The transistors should be
LC
modeled with the standard small-signal model using gm and rds or rout in this part of the problem.
Second, use SPICE to obtain a transient simulation. Third, simulate the oscillator that replaces
the ideal inductor with the lumped inductor model shown, and use the program referenced below
[1] to layout the inductor. Use the model parameters given in [2] for this problem.
Fig.1. Ideal LC VCO Fig.2. Lumped Inductor Model
GSM specifications:
Frequency range = 935 ~ 960MHz vc = 0.75 ~ 1.75V
Switching time = 800µsec VDD = 2.5V
Technology parameter:
Metal sheet resistance = 35 mΩ/sq.
Substrate layer resistivity = 0.015 Ω-cm
Metal to substrate capacitance = 5.91 aF/µm2
Metal to metal capacitance = 98.0 aF/µm
Csub, Rsub, Cp can be ignored
Solution
Av1 = Av2 = Gm * (rout || L || C/2)

1 1
Av1(s) = Av2(s) = Gm 1 1 C = Gm s L L C where Gm and rout are
2
rout + Ls + 2 s 1 + s rout + s L 2
the transconductance and the output resistance of M1 and M2 transistors respectively, C/2 is the
total output capacitance at the outputs Von and Vop. For this circuit to oscillate, the gain around the
loop must be equal to negative one; therefore, each cross coupled gain stage can be presented as
Av1(s)
shown below. Hence, the total gain equation around the loop is equal to H(s) = 1 - A .
v1 (s)
Substituting for Av1(s),
Gm s L
L C
1 + s r + s2 L 2 Gm s L
out
H(s) = Gm s L = C
1 - L C 1 - s L (G m - G o u t ) + s 2 L 2
1 + s r + s2 L 2
out
1
For this circuit to oscillate at ωosc = , it is necessary for the s term in the denominator to be
C
L2
1
equal to zero; hence, Gm = r = Gout
out
By forcing Gm greater than Gout a pair of complex poles are forced in the right side plane. This is
the condition to start oscillation. Once the oscillation starts, the Geff parameter (Geff = Gm – Gout)
C
L 2 C
approaches zero and the oscillation becomes sustaining, giving a Q = L G = 2L Reff
eff
Inductor Layout:
Problem 30
A four-stage ring oscillator used as the VCO in a PLL is shown. Assume that M1 and M2 are
matched and M3 and M4 are matched. Also assume that
W
gm = 2 K' L ID where K’N = 100µA/V2 and K’P = 50µA/V2
and that rds = ∞. The parasitic capacitors to ground at the outputs are 0.1pF each.
(a.) If I =2mA, find the frequency of oscillation in Hertz. (b.) Find the W/L ratio of M1 (M2)
necessary for oscillation when I =2mA. (c.) If the current I is used to vary the frequency,
express the relationship between ωosc and I. In otherwords, find ωosc = f(I).
VDD
10µm 10µm
vi+ vo+ vi+ vo+ vi+ vo+ vi+ vo+ 1µm 1µm
vo- M3 M4 vo+
vi- vo- vi- vo- vi- vo- vi- vo- vi+ M1 M2 v -

i
F02E2P2
I
Solution
(a.) The small-signal transfer function of the stages can be written as,
Vout(s) gm1/gm3  Vout(jω)  ωC 
= → Arg   = -tan-1 
Vin(s) C gm3
s g +1  Vin(jω) 
m3
From the above, we see that each stage must contribute –45° of phase to oscillate. Therefore,
gm3 2K' 10·0.5I 2·50x10-610·10-3
ωosc = C = C = = 1010 rads/s → f osc = 1.59GHz
10-13
(b.) The gain of the 4-stage ring oscillator at ωosc should be equal to 1 so we can write,
4
 gm1/gm3 4 (gm1/gm3)
1=  = 4 → gm1 = 40.25 gm3 = 2 gm3 = 2 mS
 1+1 
2 mS = 2K' N (W/L)·1mA = 2·100x10-6 (W/L)·1mA
2mS
∴ (W/L)1 = 0.2mS = 10 → (W / L ) 1 = 1 0
(c.) From part (a.) we get,
gm3 2K' 10·0.5I 2·50x10-610·0.5I
ωosc = C = C = = 2.36x1011 I
10-13
ω osc =2.36x1011 I
Problem 31
How does the oscillation VDD
frequency depend on I SS for a
ring oscillator using the stage - M3 M4
shown? Express your answer in W4
+ W3 L4
terms of VDD, V REF , I SS , the V vo1 vo2
REF M5 L3
simple large signal model
parameters of the MOSFETs (K’, VDD vi1 M1 W M2 v
1 W2 i2
VT, λ) and the W/L values of the 0.5ISS L1 L2
MOSFETs. ISS
M7 W7
Solution M6 ISS
W8 L7
This topology uses a replica L8 W5
biasing circuit to define the on- M8 L5
resistance of M3 and M4 based SU03H07P3
on the on-resistance of M5. The
on-resistance of M5 is
V DD -V REF
R on5 = 0.5I
SS
We can either assume that the W/Ls of M3, M4 and M5 are equal or since we know that Ron is
inversely proportional to the W/L ratio, we can write that,
W 5/L5
Ron3 = Ron4 = W /L Ron5
3 3
where W3/L3 = W4/L4.
Assuming a capacitance at each output of CL, allows us to write the transfer function of the ring
oscillator stage as,
Vo2-Vo1 gm1Ron3
=
V i1-V i2 sR on3 C L + 1
The phase shift due to a stage can be written as,
θi(jω) = -tan-1(ωRon3CL)
To oscillate, this phase shift needs to be equal to some value, say k (in degrees). Therefore we
can write that,
k 0.5I SS k
ωosc = R C = W /L
on3 L 5 5
W3/L3(V DD -V REF )C L
Therefore, the oscillation frequency varies linearly with ISS.
Problem 32
In every practical oscillator, the LC tank is not the only source of phase shift. Hence, the actual
oscillation frequency may differ somewhat from the resonant frequency of the tank. Using the
time-varying model, explain why the oscillators’s phase noise can degrade if such off-frequency
oscillations occur.
Solution
If there is any off-frequency oscillations that are close to the actual oscillation frequency
or harmonics of it, we know from the LTV theory that these frequencies and their associated
noise will “fold” into the noise spectrum around the actual frequency and degrade the oscillator’s
phase noise. The following diagram illustrates the process.
in2
(ω) 1/f noise
∆f
∆ω ∆ω ∆ω
ω
∆ω ωo 2ωo 3ωo
Sφ(ω)
c0 c1 c2 c3
-∆ω ∆ω ω
Sv(ω)
Phase
Modulation
ωo 2ωo 3ωo ω
ωo-∆ω ωo+∆ω Fig. 3.4-32
Problem 33
Assume that the steady-state output
amplitude of the following oscillator is 1V. k= M
L1L2 Comparator
Calculate the phase noise in dBc/Hz at an -
offset of 100kHz from the carrier from the vout
signal coming out of the ideal comparator. 2 +
Assume that L1 = 25nH, L2 = 100nH, M = in1 L1 L2 C
10nH, and C = 100pF. Further assume that
the noise current is SU03H07P4
2 = 4kTG ∆ f
in1 eff
where 1/Geff = 50Ω. The temperature of the circuit is 300°K.

Solution
First of all, several assumptions must be made to work this problem. They are:
1.) The load on the secondary of the transformer approximates a short.
2.) The output of the comparator is a square wave of amplitude 0.5V.
Our objective is to find the value of
 i 2 /∆ f Γ 2 
L{fm} = 10log10
 n2 rms

 2qmax2(fm) 2 
First, the influence of the transformer. The equations of a general transformer are,
V1 = sL1I1 + sMI2 and V2 = sMI1 + sL2I2
M
If we assume that V2 ≈ 0, then I2 ≈ L I1 = 0.1I1. Since we are looking at the square of the
2
current, we can write that the noise injected into the tank is
2
in2 2
in2
0.04(1.381x10-23)300
= 0.01 = 0.04kTGeff = 50 = 3.314x10-24 A2/Hz
∆f ∆f
Next, we will evaluate Γrms2. From the notes (page 160-21), we see that
∞
1
Γrms2 = 2 ∑cn2 where cn are the coefficients of the ISF represented by a Fourier series.
n=0
What are the cn? We shall assume that the ISF of the LC tank is a sinusoid of the same period.
Therefore, only the c1 coefficient is important. If the peak value of the ISF is 1V (a questionable
assumption) then the rms value is 0.707. Thus Γrms2 ≈ 0.25.
qmax = Cvmax = 100pF(1V) = 10-10 coulombs.
 3.314x10-24(0.25)
∴ L{fm} = 10log10 -20 5 2  = 10log10(4.14x10-13) = -123.82 dBc/Hz
 2·10 (10 ) 
L{fm} = -123.82 dBc/Hz
Problem 34
A crystal reference oscillator and its associated transistor have the following specifications at
290°K.
Output frequency: 6.4MHz
Power output: +10 dBm
Noise figure: 2.0 dB
Flicker corner: 15 kHz
Loaded Q: 12x103
(a.) Determine and plot the SSB phase noise in dBc as a function of the frequency offset from the
carrier. Include the frequency range from 10Hz to 10MHz.
(b.) Suppose that this reference oscillator is used with a frequency synthesizer whose transfer
function from the reference to the output is
θn,o(s) N 2 ζω n s + ω n 2
=
θn,ref(s) Nref s 2 + 2 ζω n s + ω n 2
where N = 19,000, Nref = 256, ζ = 0.7, and ωn = 908 sec.-1. Make a plot of the SSB reference
noise in the output of the synthesizer.
Solution
(a.) NF = 2.0dB, F = 102.0/10 = 1.585, and Po = 10 dBm = 0.01W
 FkT 1  fo  2  fc  
L{fm} = 10 log  P  1 +  1 + fm 
 s  4Q2 f m    
 1.585·1.38x10-23·290 1  6.4x106 2  15kHz 
= 10 log     
0.01 1 +
4(12x103)2 f m   
1 + fm 
  
  71.11x10 3   1.5x10 4  
L{fm} = 10 log  6.348x10-19 1 + 2  1 + f m  
  f m  
-120
-130
-140
-150
dBc
-160
-170
-180
-190
10 100 1000 10 4 10 5 10 6 10 7
Offset from carrier, fm (Hz) SU03H07S5A
Problem 34
(b.) The VCO phase noise transfer function is
θn,o(s) N 2 ζω n s + ω n 2 1271.2s 2 + 8.245x10 5
= Nref 2 = 74.219
θ (s)
n,ref s + 2 ζω s + ω 2
n n s 2 + 635.6s + 8.245x10 5
  θn,o(jω)  2 
θn,ref(dBc) = 10 log    L{fm }
θn,ref(jω) 
Below is a plot of the above equation as well as the transfer function, θn\,o(s)/θn\,ref(s), and the
input reference noise.
50
Transfer Function
0
-50
Input Reference Noise
-100
dBc Output Noise
-150
Noise Floor
-200
This region is not possible
-250
10 100 1000 10 4 10 5 10 6 10 7
fm SU03H07S5B
Problem 35
Use the National Semiconductor website (www.national.com) to design a DPLL
frequency synthesizer for the GSM (935-960MHz) application. The channel spacing is 200kHz.
Choose an appropriate VCO from a manufacturer. Assume a 0.25µm CMOS process with a
3.3V power supply.
Your homework should show a block diagram for the resulting frequency synthesizer
with the blocks identified. Give the following parameters that you selected for your design:
1.) N, the divider ratio.
2.) ζ, the damping ratio
3.) The type of PD/PFD and the value of Kd.
4.) The type of VCO, Ko, and Vmin and Vmax.
5.) τL, the lock-in time or settling time and ωn, the natural frequency of the PLL
6.) Design of the loop filter including the time constants and component values.
Solution
The problem specifications call for the following:
• Standard : GSM
• Frequency band : 935 MHz ~ 960 MHz
• Channel spacing : 200 kHz
• Power supply : 3.3 V
• Technology : 0.25 µm CMOS
• Switching time : < 800 µs (by GSM standard)
Design
The block diagram for this design is as follows:
The central frequency to use is the geometric mean of the extreme frequencies (947 MHz).
The devices chosen for this design are:

1. A low phase noise PLL (PFD), (chip code LMX2346) from National Semiconductors.
This has a range of operation from 200 MHz to 2 GHz, so it is suitable here.
2. A VCO (chip code VCO191-947U) from Vari-L. Its frequency of operation is well-suited
for this GSM application: 934 MHz to 960 MHz.
3. A second-order loop filter. This will reduce the number of capacitors in contrast with a
higher order filter. And this can be done because the filter components are going to be
off-chip, so the needed capacitance values –relatively high– are realizable. This filter is
passive so as to avoid the non-idealities associated with an OPAMP (mainly, noise).
The comparison frequency at the input of the phase/frequency detector was chosen to be equal
to the channel spacing, i.e., 200 kHz. Therefore, the reference divider —ifusing a 10 MHz
crystal source at the input— and the feedback divider ratio can be found as:
f CRYSTAL 10 MHz
R= = = 50
f COMPARISON 200 kHz
f OUTPUT 947 MHz
N= = = 4735
f COMPARISON 200 kHz
Other parameters for this design are:
VCO
• K0 = 18 MHz/V
• Vmin = typ. 0.8 V @ 934 MHz (min. 0.4 V)
• Vmax = typ. 2.2 V @ 960 MHz (min. 2.6 V)
PFD
• Kφ (= Kd) = 4 mA ( or 4/2π [mA/rad] )
General
• Lock-in time = τL = 200 µs
The filter components were found to be (standard values given, ideal values in parenthesis):
C1 = 910 pF (943.6 pF)

C2 = 6.8 nF (6.6 nF)
R2 = 5.6 kΩ (5.7 kΩ)
Simulation Results
Simulation was performed using the computed standard values for the filter components
and are as follows:
Phase Noise performance:

• 0 dB bandwidth = 14.80 kHz
• Peak frequency = 7.40 kHz
• Phase noise peaking = 2.47 dB
• Phase noise @ 10 kHz offset = -90.56 dBc/Hz
• Phase noise @ 100 kHz offset = -118.86 dBc/Hz
• RMS phase error = 0.33°
Problem 35 — Continued
Phase Noise
––– Total noise ––– PLL noise

––– VCO noise ––– TCXO noise
––– R 2 noise
Lock-in time performance for a frequency jump from 934 MHz to 960 MHz
(worst case) with a tolerance of 500 Hz:
• Lock-in time = τL = 215.31 µs
Frequency analysis (Bode plots):
• Natural frequency = ωn = 7.06 kHz

• Phase margin = 51.74°
• Spur gain at comparison frequency = 33.68 dB
• Loop bandwidth = 11.94 kHz
• Damping factor = ζ = 0.84
Spur level estimation
Spur Offset Description Spur Gain Leakage Component Pulse Component Spur Level
(kHz) (dB) (dBc) (dBc) (dBc)
200 1st Spur 33.7 -90.5 -76.3 -76.1
400 2nd Spur 21.7 -102.4 -81.2 -81.1
600 3rd Spur 14.7 -109.4 -84.2 -84.2
Therefore, this design is suitable for use in the proposed GSM application.
Problem 36 – (10 points)

The phase noise of an oscillator is –40 dBc at 10 Hz offset and has a straight-line variation (on a
dBc vs. logf scale) variation to –85 dBc at 15 kHz offset. Determine the residual phase
modulation in the range of 300 Hz to 3 kHz.
Solution
We will solve this problem modeling the phase noise as a simple line on the dBc vs. log f
scale as y = mx + b where
y = dBc and x = logf
The slope of the curve on the dBc vs. log f scale is found as,
-85 - (-40)
m= = - 14.186 dB/dec.
log(15x103) - log(10)
The intercept, b, can be found as
-40 = (-14.186 dB/dec.)log(10) + b
b = -40 + (14.186 dB/dec)log(10) = -40 + 14.186 = -25.832 dBc
∴ y(dBc) = -14.186 dBc/dec (logf) – 25.832 dBc
Let y = L{f} dBc
We can write for both sidebands L{f} = 2(10-(25.832/10)) f -1.4186
Integrating from 300Hz to 3kHz, gives the residual PM,
3000
θrms = ⌠2[10-(25.832/10)] f -1.4186 df = 0.027 radians
⌡
300
Problem 37
On page 160-33 of the class lecture notes, the approximate rms value of the impulse sensitivity
function for single-ended ring oscillators is given as
2π2 1
Γrms ≈
3η3 N 1.5
Derive this approximate impulse sensitivity function.
Solution
This derivation follows that given in A. Hajimiri, et. al., “Jitter and Phase Noise in Ring
Oscillators,” IEEE J. of Solid-State Circuits, vol. 34, no. 6, June 1999, pp. 790-804.
The approximate waveform f(x)
and the ISF for a single-ended ring
oscillator is shown below and is 1 Slope
based on the assumptions that the
Slope = -fmax'
sensitivity during the transition is = fmax'
inversely proportional to the slope
and the rise and fall times are x
symmetrical. Γ(x) 2π
1 2
fmax' fmax'
x
2 1 2π
fmax' fmax'
SU03H08P3A
The Γrms can be estimated as,
2π 1/fmax '
1 ⌠ 2 1 ⌠ 2  1 3
Γrms2 ≈ ⌡Γ (x)dx = ⌡x2dx =
2π 0 4π 0 3π f max '
The normalized delay per stage is given as
η
^t =
D f max '
which is found from the following waveforms of the single-ended ring oscillator.
f(x) 1 1
fmax' fmax'
1 η
fmax'
η
fmax'
x
SU03H08P3B 2π
The period of the ring oscillator is 2N times larger than the normalized delay per stage and is
2Nη 1 π
2π = 2Nt^D = f ' → f max ' = N η
max
2  π  3 2π2 1
∴ Γrms2 ≈   =
3π N η  3η3 N 3
The result is obtained as,
2π2 1
Γrms ≈
3η3 N 1.5
Problem 38
A frequency synthesizer has a reference frequency of 5kHz and uses a 64/65 dual-modulus
prescaler. Determine the values of the A and M counters to give an output frequency of 555.015
MHz.
Solution
fo = Nfr
fo
N = f = 111003
r
N = MP+A
N  111003
M = Interger  P  = Interger  64  =1734, A = N –MP = 27
∴ A = 27 and M = 1734

When testing a frequency synthesizer, you observe the
frequency display shown above on a spectrum analyzer.
What important fact is obvious from the display?
Solution
Asymmetrical sidebands indicate the presence of f
fo SU03H09P2
both PM/FM and AM spurs.

What is the main advantage of a fractional-N PLL synthesizer over an ordinary PLL synthesizer?
Explain.
Solution
A fractional-N PLL synthesizer gives much high frequency resolution than possible with
an ordinary PLL synthesizer having the same reference frequency.

A 1600 MHz carrier together with a set of 20 kHz PM spurs are applied to a divide by 8
frequency divider. The power of the 200 MHz carrier frequency output of the divider is 0.2 mW
and the 20 kHz spurs have an amplitude of 20 µV. What is the phase deviation of the signal at
the input of the divider? All impedances are 50 ohms.
Solution
At the output,
Vs = 20x10-6 V and Po = 0.2x10-3 W
|Vs|2
∴ Ps = 50 = 8x10-12 W
Ps  8x10-12 
SSB = 10log10P  = 10log10  = -73.979 dB
o 0.2x10-3
At the input,
SSBinput = SSBoutput + 20log10(N) = -73.979 dB + 18.062 dB = -55.92 dB
 θd
SSBinput = 20log10 2 
  → θd = 2·10SSBinput/20 = 0.0032 radians

In the lecture notes, how a rotational frequency detector works is explained. Use explanation
and accompanying diagram to clearly explain how the rotational frequency detector works.
Solution
Rotational Frequency Detector
When referenceless frequency acquisition is desired for CDR applications, a frequency detector as
shown below can be used in a frequency locked loop for pulling the VCO frequency to the correct
data rate. Once, the VCO frequency is centered to corresponding data rate, the phase locking
loop takes over in order to sample the data at optimum sampling point.
DE-FF DE-FF up
A C
I-clk D Q D Q
data
B D down
Q-clk D Q D Q
DE-FF DE-FF
Figure 1: Rotational frequency detector. I and Q clocks come from the VCO. Data is the non-
return to zero (NRZ) data to be resampled by the clock and data recovery circuit (CDR).
The flip flops are double edge sampling FFs. States A and B hold the present sampled
I and Q clocks whereas the C and D hold the previously sampled inputs (A and B are
resampled) UP is 1 when AB CD = 00 10. DOWN is 1 when AB CD = 10 00.
A typical frequency detector waveform for data slower than VCO clock is shown below. Note that,
anytime when AB changes from 00 to 10 a DOWN pulse is generated. In this example, there is no
UP pulse since no 10 to 00 transition occurs.
data
I_clk
Q_clk
A
B
up 10 11 01 00 10 10 11 00 10 11 01 01 10 01 00 10 11 01 01 10 11 11 01 00 10
down
Figure 2: Typical FD waveform example.

In figure below, the I and Q VCO clocks are 12.5% faster than the incoming sampling clock. As a
result, the beat frequency (frequency offset between VCO and sampling clocks) vector shown,
takes 8 samples in counterclockwise direction to come to its initial position. Initially, the sampling
clock is sampling I and Q clocks when I is low and Q is high (01). Next time, it samples IQ=01 one
more time. Next two times, it samples 00. The next sampling result is 10. The decision point is 00
to 10 transition or 10 to 00 transition. In the former one, a DOWN signal is produced and in the
later case an UP pulse is produced. During the entire beat period (i.e., 8 samples) only one down
pulse is produced).
Q Q Q Q Q Q Q Q Q
01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
down
Figure 3: IQ clocks are 12.5% faster than sampling clock.
In the example below, VCO clock is 25% faster. Therefore, the beat frequency completes its full
rotation in 4 cycles. In 8 cycles there are two 00 to 10 transitions or equivalently two DOWN pulses
are produced by the frequency detector.
Q Q Q Q Q Q Q Q Q
01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
down down
Now, let s look at what happens if the VCO clock is 37.5% faster than the sampling clock. The beat
frequency rotation vector comes to its starting position in 8 cycles, and during which only one 00 to
10 transition is made. Note that from the 4th position to 5th position, the beat frequency vector, skip
the quadrant 00. Therefore, the past state of the sampling state CD and present sampling state
AB which goes to the four input AND signals are 01 and 10. As a result, both outputs remain at 0.
No UP and DOWN generated when one of the decision quadrants are skipped.
Q Q Q Q Q Q Q Q Q
01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
down
When the speed difference is 50%, there is no 00 to 10 transition. As a result no UP/DOWN pulses
generated.
Q Q Q Q Q Q Q Q Q
01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
Figure 6: IQ clocks are 50% faster (or slower) than sampling clock.
The case where VCO is 62.5% percent faster than the sampling clock: During the 8 sampling
period in which the beat frequency vector comes to its initial starting point, there is only one
transition between quadrants 3 and 4. This transition, however is on the reverse direction. That is
CD=10 to AB=00. The AND gates in this case generate an UP pulse. To the frequency detector,
VCO appears to be 37.5% slower instead of 62.5% faster. A wrong pulse is generated.
Q Q Q Q Q Q Q Q Q
01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
up
Figure 7: IQ clocks are 50% faster (frequency detector interprets this as VCO is 37.5% slower)
than sampling clock.
The above examples is for the case when VCO is faster. The case in which the VCO is slower can
be plotted similarly. When VCO is slow, the beat frequency vector traverses the IQ quadrant
planes in clockwise direction. In the light of above vector diagrams, the following frequency detector
output vs. frequency input waveform can be plotted.
Normalized frequncy
+1 detector gain
fc 3fc fc fc
4 2 4 frequency
0 fc fc 3fc fc error
4 2 4
-1
Figure 8: Frequency detector characteristics when the sampling input is clock instead of
NRZ data.
Note that, the pulling range of this frequency detector is +/-50% when a full rate clock signal is
rising (or falling) edge samples the I and Q VCO clocks, instead of data sampling the I and Q clocks
at both rising and falling edges. This case is explained below.
From Figure 8, the detector gain is maximum for +/-25% frequency offset. (Two DOWN pulses in
Figure 4 above). Above +/-50% frequency offset, the output changes polarity and VCO frequency
is pulled to the wrong direction. The useful range is, therefore only +/-50%.
The above phase diagram example is for the case if the frequency detector input is a full-rate clock
instead of NRZ data. We further assumed that, I and Q clocks are sampled only at one edge of
the clock (either rising or falling). A pseudo random NRZ data resembles to a clock with 1/4th of the
full speed clock as far as the transition density is concerned. If this fact is combined with the
double edge sampling nature of the actual frequency detector, the data sampling the I and Q
clocks can be assumed as half the full speed clock. That is, in above phasor diagrams, the IQ
clocks are effectively sampled every other time. In this case, the frequency detector characteristics,
changes polarity when VCO range exceeds +/-25% of the data rate. For actual data inputs,
therefore the frequency characteristics resembles to the following figure. The rounded edges of
the gain characteristics is due to the pseudo random nature of the input bit sequence (PRBS).
Normalized frequncy
+1 detector gain
f data fdata 3fdata f data

frequency
2 4 8 8 error
0 f data f data 3fdata f data
8 4 8 2
-1
Figure 10: Rotational frequency detector characteristics for PRBS NRZ data.

CMOS Analog Circuit Design (Allen-2016)

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CMOS Analog Circuit Design (Allen-2016)

Uploaded by

Copyright:

Available Formats

CMOS ANALOG CIRCUIT DESIGN LECTURES

Lecture Section Topic

LECTURE 01 - INTRODUCTION TO CMOS ANALOG CIRCUIT

CMOS Analog Circuit Design © P.E. Allen - 2016

CMOS Analog Circuit Design © P.E. Allen - 2016

CMOS Analog Circuit Design © P.E. Allen - 2016

Course Organization – Based on 3rd Ed. of CMOS Analog Circuit Design

Chapter 6 Chapter 7 Chapter 8

CMOS Analog Circuit Design © P.E. Allen - 2016

CMOS Analog Circuit Design © P.E. Allen - 2016

WHAT IS ANALOG DESIGN?

CMOS Analog Circuit Design © P.E. Allen - 2016

What is Electrical Design?

specifications Circuit Design +

DC Currents Fig. 1.1-3

CMOS Analog Circuit Design © P.E. Allen - 2016

Steps in Electrical Design

CMOS Analog Circuit Design © P.E. Allen - 2016

What is Physical Design?

n+ p+ Metal Poly p-well n-substrate

CMOS Analog Circuit Design © P.E. Allen - 2016

What is the Layout Process?

CMOS Analog Circuit Design © P.E. Allen - 2016

Other considerations of packaging:

†Rao Tummala, “Fundamentals of Microsystems Packaging,” McGraw-Hill, NY, 2001.

What is Test Design?

Objective: To compare the experimental performance with the specifications and/or

ANALOG INTEGRATED CIRCUIT DESIGN SKILLSET

CMOS Analog Circuit Design © P.E. Allen - 2016

CMOS Analog Circuit Design © P.E. Allen - 2016

Electronic Equations, Prediction or

CMOS Analog Circuit Design © P.E. Allen - 2016

Key Principles, Concepts and Techniques of Analog IC Design

(Webster – A comprehensive and

CMOS Analog Circuit Design © P.E. Allen - 2016

Complexity in Analog Design

CMOS Analog Circuit Design © P.E. Allen - 2016

CMOS Analog Circuit Design © P.E. Allen - 2016

WHERE IS ANALOG IC DESIGN TODAY?

CMOS Analog Circuit Design © P.E. Allen - 2016

Analog IC Design Challenges

CMOS Analog Circuit Design © P.E. Allen - 2016

Digitally Assisted Analog Circuits

A New Paradigm for IC Design?

• New Paradigm (shaped by the internet)

– No $ invested until the product is sold

NOTATION, TERMINOLOGY AND SYMBOLOGY

Signal Definition Quantity Subscript Example

CMOS Analog Circuit Design © P.E. Allen - 2016

MOS Transistor Symbols

CMOS Analog Circuit Design © P.E. Allen - 2016

Other Schematic Symbols

CMOS Analog Circuit Design © P.E. Allen - 2016

(a.) (b.) (c.)

CMOS Analog Circuit Design © P.E. Allen - 2016

CMOS Analog Circuit Design © P.E. Allen - 2016

LECTURE 02 - SUBMICRON CMOS TECHNOLOGY

CMOS Analog Circuit Design © P.E. Allen - 2016

Deep Submicron Technology

Ultra Deep Submicron Technology (Nanotechnology)

• Categories of CMOS technology:

Why CMOS Technology?

CMOS Analog Circuit Design © P.E. Allen - 2016

FUNDAMENTAL IC PROCESS STEPS