RF and mm-Wave PA Fundamentals

Fundamentals of RF and Mm-Wave
Power Amplifier Designs
Hua Wang
School of Electrical and Computer Engineering
Georgia Institute of Technology, USA
hua.wang@ece.gatech.edu
Live Q&A Session: Feb. 13, 2021, 7:00-7:20 am, PST
Hua Wang Fundamentals of RF and Mm-Wave 1 of 98

Self Introduction
 BS from Tsinghua University, Beijing, China, in 2003
 MS and PhD from California Institute of Technology, Pasadena, CA,
in 2007 and 2009, respectively
 Was with Intel Corporation, Hillsboro, OR, in 2010-2011 and
Skyworks Solutions, San Jose, CA, in 2011
 Associate Professor at School of Electrical and Computer Engineering
of Georgia Institute of Technology, Atlanta, GA
 Director of Georgia Tech Center of Circuits and Systems (CCS)
 DARPA Director’s Fellowship in 2020, DARPA Young Faculty Award in
2018, and NSF CAREER Award in 2015
 My research interests are in integrated circuits and hybrid systems
for wireless communication, sensing, and bioelectronics applications

Outline
 Background and Motivations
 PA Operation Principles and PA Classes

 Linear Power Amplifiers
 Switching Power Amplifiers
 Power Amplifier Design Considerations

 Active Device Designs
 Passive Network Designs
 Advanced Power Amplifier Architectures
 RF and Mm-Wave PA Design Examples
 Summary and Conclusions

Background and Motivation
 Power amplifier (PA) is the last
active circuit stage of a transmitter.
 Ubiquitous in wireless systems
 Mobile devices, access points, base
stations, backhaul
 Automotive radar and imaging
 Satellite communication

Fundamental Questions
 What is a power amplifier (PA)? When an amplifier should be called a PA?
 Generating watt-level output power?
 The designers should NOT follow conjugate matching?
 Operation exhibits or requires some (large) nonlinearity?
 An amplifier that can do damage to something?
• Device Gain/Efficiency/Linearity • Impedance Transformation

• Operation Modes/Classes • Power Combining
• Harmonics/Waveform Shaping • Harmonics/Waveform Shaping
• Stability and Reliability • Bandwidth and Filtering

Basic PA Performance Metrics (1 of 4)
 Basic performance metrics/values of a power amplifier (PA).
 PIn, PPA, POut (PL), PDC = PDC, PA + PDC, Driver
 PA Power Gain: GP = POut/PIn
 PA Drain Efficiency (DE or η): η = POut/PDC
 Power Added Efficiency (PAE): PAE = (POut-PIn)/PDC

 Basic performance metrics of a power amplifier (PA).
PIn, PPA, POut, GP,

PDC = PDC, PA + PDC, Driver
 PA Drain Efficiency: η = POut/PDC

• If η = 40% and POut = 1W = +30dBm  PDC = 2.5W with 1.5W as heat!
• If VDD = 2.5V  total IDC = 1A!
Thermal Management,
DC IR Drop and Battery Life, etc…
Reliability

PIn, PPA, POut, GP,


Low Loss Passive
 Considering the output network loss: η = L×PPA/PDC Networks
• If L = 1dB ~ 80%  Required PPA/PDC = 50%
• For POut=1W  RF power loss in the output network = 250mW

PIn, PPA, POut, GP,


 Considering the output network loss: η = L×PPA/PDC
• If L = 1dB ~ 80%  Required PPA/PDC = 50%
• For POut=1W  RF power loss in the output network = 250mW
 Power Gain: GP = POut/PIn Large Input
• If GP = 20dB  Input Power PIn = 10mW = +10dBm Driving Power

PA Efficiency Fundamental Limit
 Fundamental Limits on Power Amplifier Efficiency [Asbeck19].
𝑷𝑨 𝑷𝑨𝑬 𝜼𝑫𝒆𝒗𝒊𝒄𝒆 𝜼𝑷𝑨 𝑴𝒐𝒅𝒆 𝜼𝑷𝑨 𝑮𝒂𝒊𝒏 𝜼𝑶𝒖𝒕𝒑𝒖𝒕 𝑳𝒐𝒔𝒔 𝜼𝑻𝒉𝒆𝒓𝒎𝒂𝒍 𝑨𝒈𝒊𝒏𝒈
 Device Intrinsic η  PA Classes and  Device Gain with  PA Output Network

• Knee Voltage Harmonic Input/Output Loading • Loss = POut/PPA
~ (1-VKnee/VDD) Shaping/Termination = (1-1/GP) • Differential Load
• Large-Signal Output ― “Waveform Balancing
Impedance Engineering”
~ ZOut/(ZOut+ZL)

Typical RF and Mm-Wave PA Power Levels
𝑨𝑹 𝑨𝑻
 PA Output Power POut by Link Budget Friis Transmission Equation 𝑷𝑹 = 𝒅𝟐𝝀𝟐 𝑷𝑻
 RF-Frequency PAs  Mm-Wave PAs

 LTE: 23dBm/26dBm for Power  PA Pout vs. array size [Asbeck19]
Class-3/-2 high-power UE  Small/medium arrays  higher Pout
 WLAN: 20-26dBm  Large arrays  lower Pout, system size/cost
 NB IoT: 14dBm/20dBm/23dBm Base station-1 Base station-2
 Bluetooth: Class 1 (20 dBm),

Class 2 (4dBm), Class 3 (0 Avg. Pout per element PA
dBm), and Class 4 (-3 dBm)

PA SoA and Performance Trend
 Challenge: POut vs. Frequency ― State-of-the-Art (SoA) [Wang, GT PA Survey]
-20dB/dec
~ Johnson’s Limit
Need: High Power

at High Frequency

PA Output Power vs. Efficiency
20-50GHz PAs in Silicon (2000-Present)
 Challenge: POut vs. Efficiency [Wang, GT PA Survey]
 Limited device output power and Device

Limited
voltage swing (VDD-VKnee)
Combiner/
 POut = IRF×(VDD-VKnee)/2 Network Limited
= (VDD-VKnee)2/2RL
 Larger devices or more devices
 Lossy impedance transformation
Need: High-Power High-Efficiency

and Compact PAs

PA Spectrum, Linearity, and Efficiency (1 of 2)
 Challenge: Spectrum Efficiency vs. Linearity vs. Energy Efficiency
 High-order QAM, OFDM, and Carrier Aggregation (CA)
 Power amplifier linearity
16-QAM 64-QAM 256-QAM 3GPP 38.101-
4 bits per symbol 6 bits per symbol 8 bits per symbol requirements on EVM
Parameter Average EVM
π/2-BPSK 30%
QPSK 17.5%
16 QAM 12.5%
64 QAM 8%
256 QAM 3.5%
Need: High Linearity and
High Data Rate PAs

PA Spectrum, Linearity, and Efficiency (2 of 2)
 Challenge: Spectrum Efficiency vs. Linearity vs. Energy Efficiency
 High-order QAM, OFDM, and Carrier Aggregation (CA)
 High peak-to-average-power-ratio (PAPR)
Need: High Back-off
 PA Back-off and averaged efficiency Efficiency and Linearity PA

PA Carrier Frequency Coverage
 Challenge: Crowded spectrum at GHz and
Need: Wideband or
multiple non-contiguous bands at mm-Wave Frequency Reconfigurable PA
 Multi-band, multi-mode, international roaming
US Spectrum Allocation Mm-Wave 5G Bands

PA Design Hexagon
 PA Design Hexagon and Tradeoffs
Carrier Output
Frequency Power
Reliability Data Rate
Energy Spectrum
Efficiency Efficiency

The Scope of This Tutorial
 Scope of this tutorial: Designer perspectives on silicon-based PAs
 Basic PA principles, PA classes, and PA architectures
 PA design practices and guidelines
 RF and mm-Wave PA design examples
 What we will NOT cover (but are essential)…

 III-V devices and power amplifiers
 EM modeling and simulation techniques
 Packaging and thermal modeling
 Reliability
 Digital pre-distortion (DPD)
 Regulations and standards

Outline



Popular PA Classes and Modes
 Popular PA classes and their general properties.
Linear Mode PAs Switching Mode PAs
PA Classes A, B, AB, C, J …. F‡, F-1‡ D, D-1, E …
Transistor Operation RF Current Source RF Switch
Linearity Good Limited
Drain Efficiency Medium-Low High (100% Theoretically)
Modulations Varying Amplitude (QAM, etc.) Constant Amplitude
Harmonics Harmonic Suppression Waveform Shaping

Gain High Low
Operating Frequency High Low-Medium
‡ Class F and F-1 PAs can be viewed as overdriven linear PAs with harmonic terminations.
Simplified Power Device Model for Linear PAs
 Power device assumptions [Cripps06]: ID ID
 Device can be abrupted turned ON or OFF. Vds Vds

Vgs Vgs
No sub-threshold region.
 Once ON, the device is completely linear,
ID ID Limitation
ID = k×(Vgs-VTH).
 Device as ideal current source with r0  ∞ Immediate
Linear Response
Onset
and no triode region ID = k × (Vgs-VTH)
 Hard limits on device output voltage and 0 VTH

Vgs
current
ID Input or Device
Vgs
 For simplicity, Vknee ≈ 0 and no device Current
Limited
Limit ID = k × (Vgs-VTH)
parasitics
 Idealized and simplified model, but useful Supply/Breakdown
Limited
for basic linear PA analysis 0 Vds
Vknee ≈ 0 Voltage Limit

Conjugate Matching vs. Loadline Matching (1 of 3)
RF Current Source YS = 1/ZS IL Load
(IS as the RF Current
Amplitude) 0 < IS < Imax
IS VL = VS < Vmax YL = 1/ZL
 Conjugate Matching  Loadline Matching

 Goal: Maximizing PL if Is has no  Goal: Maximizing PL with IS ≤ Imax
output voltage limitation. and VS ≤ Vmax.
 Desired YL = YS* or ZL = ZS* ― aka  Desired Re(YL) ≈ Imax/Vmax if Re(YL)
maximum power transfer matching >> Re(YS)
 Max PL = (1/8)×(Imax)2/Re[YS]  Im(YL) = (-1)×Im(YS)
 Max PL = (1/2)×(Imax)×(Vmax)
YS = 1/ZS IL
 Example of a typical silicon power device
0 < IS < Imax
 Imax=1A, Rs=100 ohm, Vmax=2V
 Conjugate Matching
 Desired RL = Rs = 100ohm, PL = 12.5W @ Imax = 1A
 VL = Vs = 50V???  Device Breakdown
 Now considering Vmax = 2V
 IL = 20mA with IS = 40mA  PL = 20mW in reality! IL
IL = 500mA RL = R S =
@ Imax = 1A 100ohm
IL = 20mA
VL
Vmax = 2V 50V
20mW 12.5W
YS = 1/ZS IL
 Example of a typical silicon power device
0 < IS < Imax
 Imax=1A, Rs=100 ohm, Vmax=2V
 Conjugate Matching
 Desired RL = Rs = 100ohm, PL = 12.5W @ Imax = 1A
 VL = Vs = 50V???  Device Breakdown 1W (Loadline)
IL
 Now considering Vmax = 2V IL = Imax = 1A
RL = 2ohm = Vmax/Imax
 IL = 20mA with IS = 40mA  PL = 20mW in reality! << Rs = 100ohm
RL = Rs =
 Loadline Matching IL = 500mA 100ohm
 RL = Vmax/Imax = 2ohm << RS = 100ohm

IL = 20mA
 PL = 1W (Loadline) >> 20mW (Conjugate)
VL
Vmax = 2V 20mW 50V
 How to achieve RL = 2ohm?  Impedance Transformation
(Conjugate)
Class-A PA (1 of 2)
 Schematic and waveforms
Vin
 Device is linear when it is on
 VKnee = 0 Vin (DC)
 r0  ∞ and no triode region IL

VTH t
 No device parasitics 0 t
 Short terminations on output Id
harmonics Id (DC)
VL
VDD 0 t
RF 0 t
Choke IDC = Id (DC)
IL Vd
Vd
Id VL
Vin VDD
RL
f0 = 1/√(LC) 0 t

Class-A PA (2 of 2)
 Signal waveforms at max POut
Vin
 Max PL = (1/2)×VDD×Imax
 Class-A Ropt = VDD/Imax Vin (DC)
IL Amplitude IL (f0) = Imax
 Max PDC = VDD×Id(DC) = VDD×Imax Imax
VTH t
 Max η = PL/PDC = 50% Amplitude Id (f0) = Imax = Id, peak/2 0 t
Id
Id, peak
 Back-off η = PL/PDC ∝ PL ∝ Pin
Id (DC) VL Amplitude VL (f0) = VDD
Constant PDC vs. PL VDD
VDD
0 t
RF 0 t
Choke IDC = Id (DC) Vd Amplitude Vd (f0) = VDD
IL 2VDD
Vd
Id VL
Vin VDD
RL
f0 = 1/√(LC) 0 t

Class-B PA (1 of 2)
 Schematic and signal waveforms
 Device is linear when it is on Vin
 VKnee = 0 IL
VTH t
 r0  ∞ and no triode region
0 t
 No device parasitics
Id
 Output harmonics are all shorted.
 Linear fundamental input/output
0 t VL
VDD
RF
Choke IDC = Id (DC) Vd 0 t
IL
Vd
Id VL VDD
Vin
RL
0 t
f0 = 1/√(LC)

Class-B PA (2 of 2)
 Signal waveforms at max POut
Vin
 Max PL = (1/2)×VDD×Imax
 Class-B Ropt = VDD/Imax = Class-A Ropt VTH t IL Amplitude IL (f0) = Imax
Imax
 Max PDC = VDD×(2/π)×Imax
Amplitude Id (f0) = Imax = Id,peak/2
0 t
 Max η = π/4 = 78.5% > 50% Id
Id, peak
Id (DC) = Id,peak/pi = Imax×2/pi
Class-A
 Drain current “bifurcation” in reality VL Amplitude VL (f0) = VDD
VDD
VDD 0 t
RF 0 t
Choke IDC = Id (DC) Vd Amplitude Vd (f0) = VDD
IL 2VDD
Vd
Id VL
Vin VDD
RL
f0 = 1/√(LC) 0 t

Class-A and Class-B PA Back-Off Efficiency
Id Id (DC)max = Id,peak/pi = Imax×2/pi
 Class-B PA efficiency at power back-off (PBO) Id, peak
 Back-off ηA ∝ PL/Id(DC) ∝ PL/PL0 ∝ PL ∝ Pin ∝ Vin2
Id (DC)max
 Back-off ηB ∝ PL/Id(DC) ∝ PL/PL0.5 ∝ PL0.5 ∝ Pin0.5 ∝ Vin Id (DC)’
0 t
η/ηmax η/ηmax
 Normalized back-off 1 1
efficiency comparison Class-B
Class-B
1/2 Class-A 1/2
Class-A
1/4 1/4
Pin/Pmax Vin/Vmax
0 0.25 0.5 1 0 0.5 1
Power Power
6dB 3dB 0dB 6dB 0dB
Back-off Back-off
 Note that Class-A PA (50%) and Class-B PA (78.5%) have different max η values.
 At 6dB PBO: Class-A η = 0.25×50%=12.5%; Class-B η = 0.5×78.5% = 39.25%
 Advanced PA architectures like Doherty, Outphasing, Envelope-Tracking PAs, etc.
Class-AB and Class-C PA
 Class-AB and Class-C PA gate voltage and drain current waveforms
Class-AB PA Class-C PA
Vin ON OFF ON OFF Vin ON OFF ON OFF
Vin (DC)
VDD
VTH t
RF
IDC = Id (DC)
Vin (DC)
Choke
IL VTH t
Vd
Id VL T0/2 < Ton < T0 0 < Ton < T0/2
Vin
RL Id
Id ON OFF ON OFF ON OFF ON OFF
f0 = 1/√(LC)
Id (DC)
t
0
Id (DC)
0 t
T0/2 < Ton < T0 0 < Ton < T0/2
Linear PA Summary
 Conduction Angle θ = 2π×(Transistor’s On-Time)/T0
Class A AB B C
θ 2ϖ ϖ<θ<2ϖ ϖ 0<θ<ϖ
 Peak drain efficiency η vs. conduction angle θ
1 𝜃 − 𝑠𝑖𝑛𝜃
𝜂= ·
4 sin 𝜃 − 𝜃 cos 𝜃
2 2 2
 Current at f0: Class-A = Class-B < Class-AB

 If θ  0, η  100%, but PL  0

Linear PA with Harmonic Tuning: Class-J PA
 Motivation: Achieving linear PA efficiency with capacitive harmonic terminations
 Is “short termination” really necessary for the harmonics in linear PAs?
VDD  Assume (1) Id only contains cosine waveforms (half-wave

RF f0=1/√(LC) with high Q rectified). (2) Only DC, 1st-order, and 2nd-order signals.
choke
IDC
Id Ic VL
Vin IL (1) Let ω0t = θ. (2) Normalize
Vd = Vc I0 sin(ω0t+Φ) RL V and I to Class-B PA
Id Id, peak 1
𝑉 = 1 − 𝑐𝑜𝑠𝜃 − 𝑠𝑖𝑛𝜃+ 𝑠𝑖𝑛2𝜃 (1) Only for
Amplitude Id (f0) = Imax = Id, peak/2 2 waveform shaping
1
IDC = Id (DC) = Id, peak/pi 𝐼 = 1 𝑐𝑜𝑠𝜃 + 0 𝑐𝑜𝑠2𝜃 (2) No RF power
2
θ
0 π/2 3π/2 5π/2 Class-B PDC Class-B RF Pout [Wright09]
Class-J and Class-J* PA
 Generalization of Class-J PA and its continuum [Cripps09]
α = -1
𝟏 No RF power α = -0.5
Given 𝑰𝒅 = 𝟏 + 𝒄𝒐𝒔𝜽 + 𝟎 + 𝒄𝒐𝒔𝟐𝜽 α=0
𝟐 α = 0.5
α=1
𝟏
𝑽𝒅 = 𝟏 − 𝒄𝒐𝒔𝜽 − 𝜶𝒔𝒊𝒏𝜽 + 𝜶𝒔𝒊𝒏𝟐𝜽
𝟐
= 𝟏 − 𝒄𝒐𝒔𝜽 × 𝟏 − 𝜶𝒔𝒊𝒏𝜽 , −𝟏 < 𝜶 < 𝟏
 A collection of continuum PA modes with

“non-short” harmonic termination
 α = 1 for Class-J PA
Angular Phase (ωt) [Degrees]
 α = 0 for Class-B PA
 α = -1 for Class-J* PA
 Any -1< α <1 will deliver the same Pout and η = 78.5% as the Class-B PA.
The same drain voltage/current overlap, just different voltage waveforms.
Switching PAs
 Motivation: Revisiting Class-B PA
𝑻
Class-B PA Power wasted in 𝑷 𝟏
𝒅𝒆𝒗𝒊𝒄𝒆 = [𝑽𝒅 𝒕 𝑰𝒅 𝒕 ]𝒅𝒕
Vd Id the device: 𝑻
Id(t) 𝟎
Vd(t) Drain voltage and current overlap that

t limits linear PA efficiency
0
 Switching PAs
 PA devices operating as switches
“On” as ideal short: can conduct high current + zero voltage
“Off” as ideal open: can withstand high voltage + zero current
 Dedicated passive networks + device duty cycle  Harmonics tuning and waveform
shaping

Class-F PA (1 of 2)
 Class-F PA: A switching PA or an overdriven linear PA + harmonic terminations
VDD
RF
ZL
Frequency f0 2f0 3f0 4f0 5f0 …
Choke λ/4 T-line @ f0
IL
Vd
VL
RL//LC-tank RL short short short short …
Id Z0=RL
Vin
RL ZL RL short open short open …
f0=1/√(LC)
 ZL is short for all the even harmonics Vd

OFF ON OFF ON Id, peak
and open for all the odd harmonics. 2VDD Id
 The device output current Id(t) only
VDD
contains f0 + all the even harmonics.
 The device output voltage Vd(t) only 0 t 0 t
contains f0 + all the odd harmonics.

Class-F PA (2 of 2)
 Class-F PA output power PL, Ropt, and drain efficiency η.
Vd  Output power PL
OFF ON OFF ON
𝟏 𝟒 𝟏
Amplitude Vd (f0) Class-F 𝑷𝒐𝒖𝒕 = 𝑽 𝑰𝒎𝒂𝒙 > 𝑽𝑫𝑫 𝑰𝒎𝒂𝒙
VDD 𝟐 𝝅 𝑫𝑫 𝟐
= (4/pi)×VDD
0 t Max Pout by Class-A or Class-B PA

 Optimum load Ropt with the same device and VDD.
Id, peak
Id 𝟒
Class-F 𝑹𝒐𝒑𝒕 = 𝑽 /𝑰𝒎𝒂𝒙 > 𝑽𝑫𝑫 /𝑰𝒎𝒂𝒙
Amplitude Id (f0) 𝝅 𝑫𝑫
= Imax = Id, peak/2
Ropt for a Class-A or Class-B PA
0 t  Drain efficiency η
 Vd(t) and Id(t) waveforms have no overlap!
 Zero power wasted in the device  ηF=100%

Class-F-1 PA (1 of 2)
 Class-F-1 PA as the duality circuit of Class-F PA
VDD
RF
ZL
Choke λ/4 T-line @ f0 IL Frequency f0 2f0 3f0 4f0 5f0 …
Vd
VL
Vin
Id Z0=RL RL + LC-tank RL open open open open …
RL
f0=1/√(LC) ZL RL open short open short …
 ZL is open for all the even harmonics

Id Vd pi×VDD
and short for all the odd harmonics. Id, peak ON OFF ON OFF
 The device output current Id(t) only Id, peak
contains f0 + all the odd harmonics. VDD
 The device output voltage Vd(t) only 0 t 0 t
contains f0 + all the even harmonics.

Class-F-1 PA (2 of 2)
 Class-F-1 PA output power PL, Ropt, and drain efficiency η.
Id  Output power PL
Id, peak ON OFF ON OFF
𝟏 𝟒 𝝅
Amplitude Id (f0) Class-F-1 𝑷𝒐𝒖𝒕 = 𝑰 𝑽 = 𝑽𝑫𝑫 𝑰𝒎𝒂𝒙
𝟐 𝝅 𝒎𝒂𝒙 𝟐 𝑫𝑫
= (4/pi)×Id, peak/2 = (4/pi)×Imax
0 t  Optimum load Ropt
Vd pi×VDD
pi×VDD 𝝅 𝟒
Class-F-1 𝑹𝒐𝒑𝒕 = 𝑽 / 𝑰 > 𝑽𝑫𝑫 /𝑰𝒎𝒂𝒙
Amplitude Vd (f0) 𝟐 𝑫𝑫 𝝅 𝒎𝒂𝒙
VDD = pi×VDD/2
0 t  Drain efficiency η
 Vd(t) and Id(t) waveforms have no overlap!
 Zero power wasted in the device  ηF-1=100%

Class-E PA (1 of 2)
 Schematic and waveforms: To absorb the non-negligible device output capacitance
VDD
RF f0=1/√(LC) with high Q Ic(t)
choke
I(t) I(t)=IDC+I0 cos(ω0t)
I(t) IDC
Id = ISW I0
Ic VL
IL IDC
Vd = Vc I0 cos(ω0t) RL t t
Cd -T1 0 T1 T0 -T1 -T1 0 T* T0 -T1
Id(t) = ISW(t)
ON ON
OFF OFF
t
-T1 0 T* T0 -T1

Class-E PA (2 of 2)
 Schematic and waveforms
VDD
RF f0=1/√(LC) with high Q
choke
I(t) IDC Ic(t)
Id = ISW I(t) I(t)=IDC+I0 cos(ω0t)
Ic VL A1
IL
Vd = Vc
I0
Cd I0 cos(ω0t) RL
IDC A2
t t
-T1 0 T1 T0 -T1 -T1 0 T* T0 -T1
T1
Id(t) = ISW(t)
Vd(t) Vd(t) peak
ON ON
OFF OFF
Charging Discharging
t t
-T1 0 T* T0 -T1 -T1 0 T* T1 T0 -T1

Class-D PA (1 of 2)
 Schematic and waveforms: To support digital process and ease process scaling
VSWA IL(t) I(t) = I0 cos(ω0t)
OFF ON OFF ON
VDD
VDD I0
t
Vin SWA f0=1/√(LC) with high Q 0
VSWA
IA 0 t
IA(t)
VL I0
IB VSWB
VSWB IL = I0 cos(ω0t) ON OFF ON OFF t
Vin SWB RL VDD 0
IB(t)
I0
0 t t
0
Series LC resonance

Class-D PA (2 of 2)
 Schematic and waveforms: To support digital process and ease process scaling
VSWA IL(t) I(t) = I0 cos(ω0t)
OFF ON OFF ON
VDD
VDD I0
t
f0=1/√(LC) with high Q 0
Vin SWA
VSWA
IA 0 t
IA(t)
Amplitude VSWA(f0) = IA(DC) = I0/pi
VL VSWB(f0) = (2/pi)×VDD
IB I0
VSWB t
VSWB IL = I0 cos(ω0t) RL ON OFF ON OFF 0
Vin SWB VDD
IB(t)
IB(DC) = I0/pi
I0
0 t t
0
 Output power PL and PDC  Drain efficiency and Ropt
𝟏 𝟐 𝟏 𝑰𝟎 𝟐
𝑷𝑳 = 𝑷𝑶𝒖𝒕 = 𝑽𝑫𝑫 𝑰𝟎 = 𝑽𝑫𝑫𝑰𝟎 𝑷𝑫𝑪 = 𝑽𝑫𝑫 𝜼 = 𝟏𝟎𝟎% 𝑹𝒐𝒑𝒕 = 𝑽 /𝑰𝟎
𝟐 𝝅 𝝅 𝝅 𝝅 𝑫𝑫

Class-D-1 PA
 Limitations of Class-D PA at high frequency:
 Power switch output capacitances are not part of the matching network
 Charging and discharging losses  Cannot ensure ZVS
 Both NMOS and PMOS are needed
 Duality: Class-D-1 PA as a “current-mode” Class-D PA [Kobayashi01] [Chowdhury12]
IA VL(t) VL(t) = V0 cos(ω0t)
f0=1/√(LC) with high Q ON OFF ON OFF V0
VDD 2IDC
t
IDC IDC 0
0 t VA(t)
V0
VSWA VSWB IB LC parallel resonance
OFF ON OFF ON t
2IDC 0  VA or VB =0 before
SWA IA IB SWB
VB(t) SWA or SWB are on.
Vin Vin V0
 ZVS
0 t
t
0
Outline



Loadpull Contour (1 of 3)
 Loadpull contour: What happens for a complex load ZL ≠ Ropt?
 For Re(ZL) = RL < Ropt : “Current limited regime”  Max Id swing, but not Max Vd swing
1 𝑅 1 K = RL/Ropt < 1 is the power

𝑃 = 𝑅 𝐼 = · 𝑅 𝐼 = 𝐾 · 𝑚𝑎𝑥 𝑃
2 𝑅 2 degradation factor.
VDD
RF 𝑉 = 𝑍 𝐼 = 𝑅 +𝑋 ·𝐼 ≤𝑉 ZL = RL + j√1-K2 × Ropt
Choke IL = Imax jXL
Vd ZL = R L Ropt = 12.5Ω
for Max Pout
Id V (f ) ≤ V
Vin d 0 DD
RL 𝑋 ≤ 𝑅 −𝑅 = 1−𝐾 ·𝑅 K × Max Pout
ZL = RL - j√1-K2 × Ropt
Following a constant resistance

circle on the Smith Chart

 Loadpull contour: What happens for a complex load ZL ≠ Ropt?
 For Re(ZL) = RL > Ropt : “Voltage limited regime”  Max Vd swing, but not Max Id swing
1𝑉 𝑅 1𝑉 K = Ropt/RL < 1 is the power

𝑃 = = · = 𝐾 · 𝑚𝑎𝑥 𝑃
2 𝑅 𝑅 2𝑅 degradation factor.
VDD
RF
𝐼 = 𝑌 𝑉 = 𝐺 +𝐵 ·𝑉 ≤𝐼 YL = GL - j√1-K2 × Gopt
Choke IL (f0) ≤ Imax
Ropt = 12.5Ω
Vd for Max Pout
Id
Vin Vd = VDD
jBL GL=1/RL 𝐵 ≤ 𝐺 −𝐺 = 1−𝐾 ·𝐺 K × Max Pout YL = GL = 1/RL
YL = GL + j√1-K2 × Gopt
Following a constant conductance
circle on the Smith Chart

 Loadpull contours at different reference planes due to device output parasitics
Loadpull Contours (45nm

CMOS SOI at 28GHz)
Load Plane 1 Load Plane 2
VDD
RF Load Load
choke Plane 1 Plane 2
Max Pout @
Vd Ropt = 12.5Ω
Id Max Pout -1dB

Vin
CD Max Pout -2dB
PAE
Pout Contour
Contour

Power Amplifier Nonlinear Distortions
 PA nonlinear distortions: AM-AM and AM-PM Distortions [Golara17]
 LTI system, memoryless nonlinear system, and nonlinear system with memory
𝑽𝒊𝒏 = 𝑨 · 𝐜𝐨𝐬 𝝎𝟎 𝒕 LTI System H(s) 𝑽𝒐𝒖𝒕 = 𝑯 ( 𝝎𝟎 | · 𝑨 · 𝐜𝐨𝐬(𝝎𝟎 𝒕 + ∠𝑯 ( 𝝎𝟎 ))
𝑽𝒊𝒏 = 𝑨 · 𝐜𝐨𝐬 𝝎𝟎 𝒕 Nonlinear System 𝑽𝒐𝒖𝒕 = 𝑯 ( 𝝎𝟎 , 𝑨 | · 𝑨 · 𝐜𝐨𝐬(𝝎𝟎 𝒕 + ∠𝑯 ( 𝝎𝟎 , 𝑨))

with Memory
AM-AM distortion
rtion AM-PM distortion
AM PM distortion PAE PAE
30
AM-AM Distortion AM-PM Distortion
AM-AM/AM-PM distortion (dB/deg.)

0
𝑯 ( 𝝎𝟎 , 𝑨 | ∠(𝑯 ( 𝝎𝟎 , 𝑨) 25
Psat=18dBm
Q ∆r Q -10 20
OP1dB = Psat-2.8dB
PAE (%)
AM-PM = 6.3°
r ∆r
 AM-AM Δr/r = 0.1 ≈ 1dB -20
15
r 10
θ
 AM-PM θ = 0.1 rad ≈ 6° -30
5
I I
Gain Constellation -40 0
202 -10 -8 -6 -4 -2 0
Compression Rotation Power Backoff (dB)

Power Amplifier Nonlinear Distortions
 PA AM-AM and AM-PM Distortions: In-Band Distortion  EVM (Error Vector
Magnitude)
 PA Spectral Regrowth: Out-of-Band Distortion  ACLR (Adjacent Channel
Leakage Ratio)
EVMrms EVMrms
Lower = -28dB Higher = -24dB
average Pout average Pout
Higher ACLR due

to Out-of-Band
Distortions
-31dBc -26dBc
-32dBc -32dBc -32dBc

Nonlinearity in a Physical Power Device
 Almost all the device elements are nonlinear  AM-AM and AM-PM distortions
 Large-signal model or bias-dependent small-signal model
 Taylor series or Volterra series [Razavi11]
Rg Cgd Rd
G D
VL Cjd
Vgs Cgs gmVgs Rds Cds
Rsub
 AM-AM: gm, Rds, Cgs, Cgd, Cds
 AM-PM: Cgs, Cgd, gm, Cds
Rs

Gm Nonlinearity and MGTR Technique
 Gm nonlinearity is bias dependent. ID
 Sweet spot gm biasing Vin

ID
Vin
ID_1 ID_2 ID_3 ID_4
 Multi-gated transistors (MGTRs)

Vbias
Vbias_1 Vbias_2 Vbias_3 Vbias_4
Gm nonlinearity gm3 impulse

4 44
gm -10
Pout
gm (A/V), gm2 (A/V2), gm3 (A/V3)
)
22 Class-ABconv IMD3L w/o MGTR
2) 2
3 IMD3L_conventional_Doherty
(S/V
gm2 freq -15 IMD3H w/o MGTR
ggm3m3(S/V
IMD3H_conventional_Doherty
00 IMD3L w MGTR
IMD3L_MGTR_Doherty
2 gm3 -20
-2-2 IMD3H_MGTR_Doherty
IMD3H w MGTR
1 Conv -25
IMD3 (dBc)
-4-4
0 00 0.4
0.4 VVGS (V)
0.8
0.8 1.2
1.2 -30
GS (V)
gm3 impulse -35
-1
Sweet spot 44
Class-ABMGTR -40
Pout
-2
biasing 22
(S/V22))
freq -45
ggm3m3(S/V
-3 00
M1 M2
-50
0 0.3 0.6 0.9 1.2 -2-2 M3 M4
MGTR 6 8 10 12 14 16 18 20 22
VGS (V) -4-4 Output Power (dBm)
00 0.4
0.4
0.4 0.8
0.8
0.8 1.2
1.2
1.2
VVGS (V)
(V)
V GS (V)
GS

Nonlinear Capacitors Cgs
 Cgs nonlinearity can be linearized by NMOS/PMOS devices [Chowdhury09] [Vigilante18].
 Extra capacitance loading  input matching, matching loss, bandwidth
2 𝐶 2𝑊 𝐿 𝐶 _
𝐶 ≈ 𝑊𝐿 𝐶 _ 𝐶 ≈𝑊𝐿 𝐶 _ ≈
3 𝐶 3𝑊 𝐿 𝐶 _
2.6
L RL C
2.2
Capacitance (pF)
NMOS
C 1.8 PMOS
Cgd gd
NMOS+PMOS
1.4
Rs VG
Vin 1
Cgs
0.6
VPMOS 0 0.2 0.4 0.6 0.8 1 1.2
Vin (V)

2nd Harmonic Terminations
 2nd harmonic feedback remixing with the fundamental signal  IMD3 generation
 2nd harmonic termination for PA linearity improvement [Kang06] [Li18].
VDD
RF +Id -Id
choke
2f0
+Vout -Vout
f0
2f0 Vd CN CN
Id
Vin +Vin -Vin
IMD3(dBc)
IMD3
f0
+Id -Id +Id -Id

+Vout -Vout +Vout -Vout
CN CN CN CN
2nd harmonic short
+Vin -Vin +Vin -Vin
Pin(dBm)

Active Devices for Mm-Wave PA Design
 The fundamental challenges in mm-Wave PA Power Gain vs. Freq. for a Typical
Design ― Limited active device gain Scaled CMOS Device (45nm)
 A two-port active device power gain W/L=1µm×25×4/40nm
25
RF device (Class-A)
(1) Conditionally stable region (0<K<1): 20 RF device (Class-AB)
0<K<1 K>1
15
Gmax(dB)
Gain = 10dB Fmax=262(GHz)
10 Fmax=334(GHz)
(2) Unconditionally stable region (K>1):
5
Gain = 7.5dB
0
0 50 100 150 200 250 300 350 400
 Dependent on device configurations: Frequency(GHz)
size/layout, biasing, matching
 Limited fmax  Limited device gain  Gain @ 60GHz = 10dB  7.5dB

Mm-Wave PA Active Device Optimization
500
 Transistor speed metric 0.5um_finger
400 1um_finger
2um_finger
Fmax(GHz)
300 2.5um_finger
200
100
0
0.001 0.01 0.1 1
 Device Layout Optimization and Extraction IDS/W(mA/µm)
400
PDK
Wf ↓  Nf↑ and Rg↓ 300 RC exraction
Fmax(GHz)
EM extraction
But Nf↑  other parasitics↑ 200
Power combining multiple 100

smaller devices
0
 Combiner η and area, etc… 0.001 0.01 0.1 1
IDS/W(mA/µm)
Mm-Wave PA Active Device Gain and Neutralization
Device size (W/L) : 1µm×25×4/40nm
 Cross-coupled capacitors CN to null the 35 Unilateral
feedback: Broadband Neutralization [Lee04] 30 Power Gain (U)
25
 Gmax ~ Device Unilateral Gain (U)
Gmax(dB)
20
 Gmax vs. CN with a “volcano” shaped function 15
10 Fmax=334(GHz)
RF device (Class-A)
 High input impedance 5 RF device Neutralized (Class-A)
0
 Parasitics of CN are important at high mm-Wave 1 10 100 1000
Frequency(GHz)
20 2.5
Gmax
+Id -Id 2
Gmax (dB) 15 K-factor
K-Factor
+Vout -Vout 1.5
+Ifb 10
-Ifb 1
CN CN 5 0.5
+Vin -Vin
Cgd Cgd 0 0
0 10 20 30 40 50 60 70 80 90 100
CN (fF)

PA Output Passive Network Design Basics
 Load impedance and output power of silicon PAs
VDD
RF  Example: A PA with VDD=2.5V and Vknee=0.2V
choke
PA Output
Vd Passive For Pout = 30dBm = 1W = (1/2)×(VDD-Vknee)2/RL
Id Nework
Vin
Vknee RL=50Ω  RL ≈ 2.6Ω and×19 transformation from 50 Ω
PA Load
 Challenge in passive network designs for silicon PAs

 Limited voltage swing (CMOS 1V/2V, SiGe 2V/4V)  Needs small load RL
 Large impedance transformation and/or power combining
 Low loss, wideband, harmonic controls, compact …

Output Passive Network: L-Match
 Lumped LC passive impedance transformation network: L-match network
RL = RS = R0/(1+QP2) < R0
CS LS = (1+QP2)/QP2
RL RL = RS  Impedance Down
Transformation
CS ω0 = 1/√ (LsCs) Rs =
LP R0=50Ω R0/(1+QP2)
L-Match QP = R0/ω0LS LP
CS
R0 = 50Ω
LS CS = (1+QP2)/QP2
RL RL = RS
LS
RL = 12.5Ω
LS ω0 = 1/√ (LsCs)
CP Rs =
R0=50Ω R0/(1+QP2) CP
L-Match QP = R0ω0CP
 Distributed T-line based implementations [Pozar11]

Output Passive Network: High-Order L-Match
 One-Section L-Match
RL = R0/(1+Qnetwork2)
 Direct tradeoff of transformation
Passive Efficiency (PE) ~ [1+Qnetwork/Qunloaded]-1
ratio, Qnetwork, BW, and PE
RL
RL
Q=3 Q = 1.717 ... Q=3 Q = 1.07
CS
LP CS CS
R0=50Ω
LP LP R0=50Ω
L-Match
L-Match L-Match
R0 = 50Ω R0 = 50Ω
RL = 12.5Ω
RL = 5Ω
RL = 5Ω
 Multi-Section L-Match
 Lower Qnetwork and broader BW but with complexity, area, and loss
Output Passive Network: Transformer
 On-chip Transformers: Different compact lumped models [Long00].
P LP - M LS - M S P IP 1:n IS S
M IS•M12/LP LP LS IP•M21/LS
C0/n
Ideal Transformer Ideal Transformer
P Rp (1-km2)LP 1: (n/km) Rs S LS rs
P 1:n S
Cp km2LP CS Cp/n2 n2RS Cs+

RS
C0(n-1)/n

Advantages of Transformer Networks
 Transformers are particularly suitable for RF or low/medium mm-Wave PAs.
RL
(1) Differential to Single-

Ended Conversion + Power (2) VDD Supply Feed with
Combining + Impedance No Need for RF Chokes
Matching VDD
Even
Harmonic
Term. (4) Differential Operation
(3) Even-Order Harmonic for Broadband Capacitive
+Vout -Vout
Controls (Class-F, F-1, J, J*, Neutralization
CN CN
etc.) or Linearity
(6) Device Gate/Base

Even
Harmonic
Biasing with No Need for
Term. Large Biasing Resistors.
(5) Common-Mode Isolation VG  Small Time Constant and
for Stability + Input Low Memory Effect
Matching  GHz Dynamic Biasing for
+Vin -Vin Mm-Wave 5G PAs

Transformer Matching Network Design Example
 On-chip transformer matching design example
 Single-transformer footprint  compact chip area
 Differential to single-ended conversion
 Impedance down-transformation
Device Parasitics and Output Matching Network
On-Chip Transformer Model
(1-k2)L/2 K:n
k2L/2 Cs Cpad
Output
Stage Z0
Cdev
k2L/2
(1-k2)L/2
ZOptimum Z5 Z4 Z3 Z2 Z1
• k: magnetic coupling coefficient • CS: extra matching capacitor • L: primary self-inductance

• n: transformer turn ratio • Cpad: pad parasitic capacitor • Cdev: device output parasitic capacitor

Power Combining Networks
 Power combining networks to further boost PA output power
Direct Parallel Power Distributed Power Transformer Power
Combiners (Zero-Phase) Combiners Combiners
 Simple  Wilkinson, Gysel, quadrature combiners  Compact and broadband

 Compact  Good isolation and asymmetry  Impedance transformation
 No isolation  Bulky and bandwidth limitation  Many variations

Transformers as Power Combiners
 Transformers as power combiners
XFMR Series Power Combiners XFMR Parallel Power Combiners
 Adding voltages in the secondary  Adding currents in the secondary

 Constant secondary currents  Constant secondary voltages
 PA load impedance down-scaling  PA load impedance up-scaling

Transformer-Based Broadband Network
 Transformer for broadband PAs with high-order matching/filter networks
XFMR for Bandpass Ladder Filters [Wang10] XFMR for Coupled Resonator Filters [Bassi15]
L2 C2 L2
R0 C1 L1 C3 L3 R0 R0 C1 L1 L3 C3 R0
(1) Splitting L2 +
Norton Transformation L2a′ L2b C2 (1) Δ-Y transformation L1′ L2′
R 0′ C1′ L1′ C3 L3 R0 R0 C1 L 3′ C3 R0
(2) Splitting L2b (2) Splitting L2’

L2a′ L2b′ L2b" C2 L1′ L2b′ L2b"
R0′ C1′ L 1′ C3 L3 R0 R0′ C1′ L 3′ C3 R0
(3) Fitting as a Physical

Transformer L2b" C2 (3) Fitting as a Physical
Transformer L2b"
Physical Transformer Physical Transformer
R0" C 1" C3 L3 R0 R0" C 1" C3 R0

Coupler Baluns as High Mm-Wave “Transformers”
 Lumped transformers at high mm-Wave: small, sensitive to parasitics, and low coupling
 Distributed coupler baluns for high mm-Wave circuits  Magnetic & capacitive coupling
Even/Odd-Mode
Analysis [Ang03]
𝑺𝟏𝟏 = 𝟎 𝑺𝟐𝟐 = 𝑺𝟑𝟑 𝑺𝟐𝟏 = − 𝑺𝟑𝟏

0 0 5
4
Imbalance(dB/degree)
-1 Passive loss -5 3
S-Parameters(dB)
Amplitude/Phase
S-Parameters(dB)
Broad Passband 2 Amplitude imbalance
-2 90-180 GHz -10 1
0
-3 -15 -1
-2
-4 Load Impedance Mismatch -20 -3
-4 Phase imbalance
-5 -25 -5
70 90 110 130 150 170 190 70 90 110 130 150 170 190
Frequency(GHz) Frequency(GHz)

Coupler Balun Properties in Practice
 Properties of coupler baluns in practice
 Low loss and broad bandwidth
 Naturally absorbs PA device output capacitances  Compact size << λ/4
 Ensures high CMRR and Teven ~ 0  Balanced differential impedance and transmission
 Built-in impedance transformation and many more!
Coupler Baluns for Impedance Coupler Baluns for Series

Inverting or Scaling [Nguyen20] Power Combining [Nguyen19]
𝟐𝒊×𝑷𝒉𝒂𝒔𝒆 (𝑺𝟐𝟏)
𝜞 𝑺 = 𝜞 𝑳𝒆
ZL Inverting
Balun
ZL Scaling
Balun

Outline



RF Power DAC PAs: Architectures
 RF power DACs or Digital PAs: Using switching PA power cell arrays as direct digital-
to-RF transmitters.
 Advantages: efficiency, scalable with process, complete TX, reconfigurability
 Disadvantages: pre-processing, speed/loss, synchronization, quantization, sampling images
Polar PA Quadrature PA
Architecture Architecture
 High efficiency, In-phase combining  No CORDIC, No BW expansion

 CORDIC, BW expansion (AM: 3~5×;  I/Q pulling, 3dB Pout and η drop  Voltage-Mode, 25%
PM: 5~7×), AM-PM sync. Duty-Cycle, Multiphase DPAs [Yuan17].
Quantization Noise and Sampling Images
 RF Digital PAs: System performance vs. sampling [Alavi14].
 Power DAC ENOB = (SINAD-1.76)/6.02: Every extra bit improves dynamic range by 6dB.
 Sampling Rate: Sampling images at f0 ± N×fS scaled by sinc2(f-f0/fS) zeroth-order-hold (ZOH)
Black: Desired Output

Red: Digital PA Output (Finite ENOB + ZOH)
Blue: Digital PA Output (Infinite ENOB + ZOH)
Output Envelope

RF Power DAC PA: Class-D and Class-D-1 PAs
 Class-D PA Power Cells  Inverse Class-D PA Power Cells
 Output voltage swing ~ [0, VDD]  Output voltage swing ~ [0, 2VDD]
 Voltage-mode with low Zout, less coupling  Current-mode with high Zout

RF Power DAC PA: Switched Capacitor PAs
 Switched capacitor PA [Yoo11]  Advantages: (1) Voltage-mode with low
ON: n cells OFF: N-n cells LS
+(n/N)VDD Zout, (2) Better capacitor matching, (3) Back-
t
off efficiency enhancement.
C C C C -(n/N)VDD
N-bit
DAC
N×Ron N×Ron N×Ron N×Ron
RL = Ropt
 Disadvantages: Output voltage swing ~
••• •••
[0, VDD], large capacitor bank area
VDD VDD VDD
ON: n cells 𝟐𝒏
𝑽𝒐𝒖𝒕 = 𝑽
N×ron/n OFF: N-n cells LS
+(n/N)VDD
𝝅 𝑵 𝑫𝑫
N-bit DAC t
Equivalent nC (N-n)C
-(n/N)VDD 𝟏 𝑽𝒐𝒖𝒕 𝟐 𝟐 𝒏 𝟐 𝑽𝑫𝑫 𝟐
Circuit RL = Ropt 𝑷𝒐𝒖𝒕 = = 𝟐( )
Ideal N×ron/(N-n)
𝟐 𝑹𝒐𝒑𝒕 𝝅 𝑵 𝑹𝒐𝒑𝒕
VDD
𝒏 𝑵−𝒏 𝑪
ZTH=Ron+1/jωNC
𝑷𝑺𝑪 = 𝑽𝑫𝑫 𝟐 𝒇𝟎
ON: n cells
OFF: N-n cells Ron nC LS +(n/N)VDD 𝑵
Thevenin t
Equivalent + -(n/N)VDD 𝑳𝒐𝒔𝒔 · 𝜷𝟐 𝑷𝒐𝒖𝒕 𝑹𝒐𝒑𝒕
Circuit
(n/N)VDD
- Series
RL = Ropt 𝜼= 𝒂𝒏𝒅 𝜷 =
Resonance 𝜷𝑷𝒐𝒖𝒕 + 𝑷𝑺𝑪 + 𝑷𝑺𝑾 𝑹𝒐𝒑𝒕 + 𝑹𝑺𝑾

Back-Off Efficiency Enhancement Architecture
 SoA power back-off (PBO) efficiency or modulation efficiency [Wang, GT PA Survey].
New PA Architecture,
Linearization…
Linearization, Power
Combining, Reconfiguration …

PBO Efficiency Enhancement: Doherty PA (1/3)
 Doherty PA Architecture (W. H. Doherty, 1936) [Doherty36]
Impedance Aux. Impedance Aux.

Main Main
Inverter Tube Inverter Tube
Tube Tube
Series Doherty PA Parallel Doherty PA
 Key concepts and circuit elements

 Multiple tubes (amplifiers)
 Active load modulation
 Almost constant amplifier efficiency over power back-off (PBO)
 Can achieve linear operation

Main PA Only Main PA + Aux PA
 Parallel Doherty PA Architecture
Impedanceto Ropt
2 100
0º ZMain
RFin
Load Normalized
Impedance
Main 1.6 80
Main Aux. PA
Efficiency (%)
Inverter Tube Phase Z-Inverter
Tube 1.2 60
Compensation (λ/4 T-Line
Normalized
(λ/4 T-Line) with Z0 = Ropt)
ZMain′ 0.8 40
Zmain
-90º
IMain 0.4 Zaux 20
Main/Aux
Aux
PA Efficiency
IAux 0 0
Parallel Doherty PA Load ZL -20 -15 -10 -5 0
ZAux = Ropt/2 Output Power Back-off (dB)
Ropt is the PA optimum load at 0dB PBO.

 At Low Output Power (Pout <6dB PBO): Only Main PA is turned on.
 At High Output Power (Pout is 6dB~0dB PBO): Both Main and Auxiliary PAs are on.
 When Auxiliary PA is being turned on
Auxiliary PA output increases ZMain’ = (1+IAux/IMain)×Ropt/2 increases ZMain decreases

Main PA Only Main PA + Aux PA
 Series Doherty PA Architecture
Impedance to Ropt
ZMain 2 100
0º Zmain
RFin
Load Normalized
Impedance Main VMain 1.6 Zaux 80
Main Aux.
Inverter PA Efficiency
Efficiency (%)
Tube Tube Phase 1.2 60
Compensation
Normalized
(λ/4 T-Line) 0.8 40
-90º ZOut, Aux′ ZAux
Main/Aux
Aux VAux Load ZL 0.4 20
PA = 2×Ropt
0 0
Series Doherty PA Z-Inverter
ZOut, Aux (λ/4 T-Line -20 -15 -10 -5 0
with Z0 = Ropt) Output Power Back-Off (dB)
Ropt is the PA optimum load at 0dB PBO.
 At Low Output Power (Pout <6dB PBO): Auxiliary PA is off with high Zout, Aux. Impedance
inverter ensures low Zout, Aux’, behaving like a voltage-mode amplifier.
 At High Output Power (Pout is 6dB~0dB PBO): Both Main and Auxiliary PAs are turned on.
Auxiliary PA output increases ZMain = VMain×2Rload/(VMain + VAux)

PBO Efficiency Enhancement: Outphasing PA
 Outphasing PA Architecture (H. Chireix, 1935) [Chireix35]
RFin1 = A(t)
Acos(ωt+θ(t)+φ(t)) A
+φ(t)
PA1
Outphasing -φ(t)
Tube 1
Combiner
Tube 2 A
Outphasing θ(t)
Combiner
Network RFout =
RFin2 =
Acos(ωt+θ(t)-φ(t)) A(t)cos(ωt+θ(t))
PA2
Outphasing (Chireix) PA
*Outphasing efficiency based on ideal Class-
 Key concepts and circuit elements B PAs and 30-degree Chireix compensation
 High PA peak efficiency φ(t)=cos-1[A(t)/2A]
 Backend overhead/complexity to generate outphasing signals (5×~7× BW expansion)
 Often requiring extensive digital pre-distortion (DPD)
 Outphasing network loss and carrier BW limiting
PBO Efficiency Enhancement: Envelope-Tracking PA
 Envelope-Tracking (ET) PA (L. Kahn 1952, A. Saleh 1983) [Kahn52] [Saleh83]
Constant Vdd ET supply voltage
PWM Switching Vdd
Supply Modulator Reduced
Power Loss
RF Envelope Linear Supply Envelope

Detector Modulator Path
Path Output Envelope
0 t
A(t) RFout =
Envelope
RFin A(t)cos(ωt+θ(t))
Path
PA Efficiency
PA
RF Path Efficiency
EER/ET PA Enhancement
 Key concepts and circuit elements

PA Output Power (dBm)
 PA efficiency enhancement over a very large PBO range
 Switching-mode converter + linear amplifier (3×~5× BW expansion)
 Envelope modulator has practical trade-offs on efficiency, speed, accuracy, and power.
 Limiting the modulation rate (~100MHz modulation bandwidth)
Boosting PA Output Power: Transistor Stacking
 PA device stacking (series-connection) [Mandegaran07] [Dabag13].
 (1) Increasing VDD, (2) large load Zopt, (3) High Pout & η.
 Practical limit of stacking: (1) More stages with marginal Psat increase  Practical designs ≤
4 stages. (2) Drain breakdown  CMOS SOI with floating body or bulk CMOS with triple-well.
Unlike cascode
PAs, CK and VGK
are designed for
Vgate swings and Equal VDS
desired K×Ropt swings and
K×Ropt

Boosting PA Output Power: Transistor Stacking
 PA device stacking at mm-Wave frequencies [Dabag13].
 (1) Parasitic capacitors at intermediate nodes  RF current leaking. (2) Voltage/current
swings de-phasing across the stacked transistors.
 Additional passive tuning elements are required.
Drain-Source
Series Inductor Shunt Inductor
Shunt Capacitor
VG2 2VMax VG2 2VMax VG2 2VMax
C2 C2 C2
M2 M2 M2 Cshunt
Cgs2 Cgs2 Cgs2
Miller Effect:
(1-AV)× Cshunt
VG1 VG1 VG1
VMax VMax VMax
Vin C1 Vin C1 Vin C1
M1 M1 M1

Outline



RF Analog PA Example: DAT Power Combining
 A 2.4GHz 2-Watt 2V Distributed Active Transformer (DAT) Power Combining PA in
350nm Bulk CMOS [Aoki02]
 DAT power combiner using high-Q slab inductors for output matching and series combining.
 Achieving 2-Watt Pout with 41% PAE under 2V supply in standard 350nm bulk CMOS.

RF Analog PA Example: XFMR Power Combining
 A 5.8GHz 1V Transformer (XFMR) Power Combining PA in 90nm Bulk CMOS [Haldi08]
 XFMR-based “Figure 8” series power combining network for four differential PAs.
 Achieving 24.3dBm max Pout, 27% peak η, 20.5dBm OP1dB.

RF Digital PA Example: A Current-DAC RF TX/PA
 A 1.36–2.51GHz 1.3V 2×13-bit All-Digital I/Q RF-DAC in 65nm Bulk CMOS [Alavi14]
 I/Q combining of current-DACs with 25% duty-cycle I/Q clocks to avoid I/Q coupling and
class-E matching for high efficiency.
 Achieving >21dBm max Pout with 34% system efficiency and 42% modulator drain efficiency.
 Judicious floor plan, calibration, and digital pre-distortion ensure high linearity.

RF Digital PA Example: Switched-Capacitor RF PA
 A 2.2GHz 1.5V/3V Polar Switched-Capacitor PA (SCPA) in 90nm Bulk CMOS [Yoo11]
 SCPA as a voltage-mode digital PA for high PA linearity.
 Achieving CW 25.2dBm max Pout with 45% PAE and 802.11g 64-QAM OFDM 17.7dBm Pout
and 27% PAE.

Recent Digital PAs and Technology Trend
 Technology Trend: Hybrid Techniques, Multi-Mode, Deep PBO, Linearity, Signal Processing
Voltage-Mode SC Quadrature SC PA
ClassD-1 Digital PA Hybrid Digital Doherty Doherty PA [W. Yuan, RFIC15,
[D. Chowdhury, Digital Doherty PA JSSC16] Polar/Quadrature SC PA
Class-G PA [V. Vorapipat, RFIC16,
RFIC11, JSSC12] [S. Hu, RFIC14, [Y. Yin, ISSCC18,
[S. Hu, ISSCC15, JSSC16] JSSC17]
JSSC15] JSSC19]
A Multiphase SC Switched-XFMR Deep

A Hybrid SC/Class-D-1
PA/TX PBO SC PA Complex-Domain
Doherty PA A Multimode Multi-
[Z. Bai, ISSCC19] [L. Xiong, ISSCC19, Quadrature Deep PBO
[D. Jung, CICC19, Phase-Interleaved Multi- Efficiency-Peak
Y. Yin, JSSC20] SC PA
JSSC20] Subharmonic SC PA Deep PBO SC PA
[D. Zheng, ISSCC20]
[A. Zhang, ISSCC19, [S. Yoo, ISSCC20,
JSSC19] JSSC20]

Mm-Wave PA Example: A XFMR Broadband PA
 A 40-67GHz Broadband Power Amplifier in 28nm Bulk LP CMOS [Bassi15]
 Broadband transformer matching network as inductively coupled LC resonator filter.
 Norton transformation for impedance scaling.
 Achieving 13dBm Pout, 40–67 GHz bandwidth, and 16% PAE with 1V supply in 28nm CMOS.

Mm-Wave PA Example: A Stacked-Transistor PA
 A 38-47GHz Stacked-Transistor Power Amplifier in 45nm PD CMOS SOI [Dabag13]
 Stacked-Transistor allows high supply voltages and simplified output matching networks.
 PD CMOS SOI provides floating body for reliability. Inductive tuning improves PAE.
 A 4-stack PA uses 5V supply and achieves 21.6dBm Pout with 25.1% peak PAE at 41GHz.
Inductive
Tuning

Mm-Wave PA Example: A Wideband Doherty PA
 A 28-/37-/39-GHz Linear Doherty Power Amplifier in 130nm SiGe for 5G Applications
[Hu17]
 On-chip XFMR Doherty network and Main/Aux PA reconfiguration for broadband operation
 Achieving >16.8dBm Pout with >27.6%CE/20.3% PAE under 1.5V supply in 130nm SiGe.

Recent Mm-Wave PAs and Technology Trend (1 of 2)
 Technology Trend: Higher Output Power, Efficiency, Bandwidth, Antenna Integration,
and Frequency
41GHz Stacked-Device
A 60GHz Dual-Mode An E-band Parallel- Class-E SiGe PAs 90GHz Multi-Drive A 24-31GHz Class- A 28GHz Inductively
Class-AB PA Series Combiner PA [K. Datta, RFIC13, 45GHz Stacked-Device Stacked-Device PAs F/F-1 PA Degenerated PA
[D. Zhao, ESSCIRC12, [D. Zhao, ISSCC14, IMS13, JSSC14] Class-E CMOS PA [A. Agah, JSSC14] [S. Mortazavi, [S. Shakib,
JSSC13] T-MTT15] [A. Chakrabarti, ISSCC14] ISSCC16, JSSC16]
CICC12, T-MTT14]
A 28.5GHz Continuous-Mode Class- A 140GHz D-Band A 60GHz 1-Watt CMOS A 24-40GHz

Highly Linear PA A 29-57GHz AM-PM F/F-1 PAs in CMOS SOI PA in 40nm CMOS Coupler DAT PA
A 60GHz Multi-Feed Broadband Ultra-
[B. Park, IMS16, Compensation PA [T. Li, ISSCC18, RFIC18, [D. Simic, RFIC18] [H. Nguyen, ISSCC19]
Linear Radiator/TX Compact PA
T-MTT16] [M. Vigilante, RFIC17, T-MTT19]
[T. Chi, ISSCC17] [F. Wang, ISSCC20]
JSSC18]

Recent Mm-Wave PAs and Technology Trend (2 of 2)
 Technology Trend: Power Back Efficiency, Linearity, Reconfigurability, VSWR
A Reconfigurable 40- A 30GHz SiGe A 28GHz CMOS A 28GHz Single-Input

A 60GHz 65GHz Multi-Port PA A 30-55GHz A 70GHz Linear
Doherty PA with Doherty PA with Linear Chireix PA
Outphasing TX [C. Chappidi, ISSCC16, Reconfigurable Digital Doherty Radiator/PA
Network Synthesis Network Synthesis [B. Rabet, ISSCC18,
[D. Zhao, ISSCC12, JSSC17] Multi-Port PA [H. Nguyen, ISSCC18,
[M. Ozen, MWCL17] [N. Rostomyan, JSSC20]
JSSC12] [C. Chappidi, RFIC17, JSSC18]
MWCL18]
JSSC18]
A 28GHz Mixed- A 28GHz Outphasing A 26-42 GHz VSWR- A 24-30GHz Watt-

Signal Doherty PA Radiator/TX A 37GHz VSWR- A 28GHz Current-
Resilient Back-Off A 60GHz Coupler Level DAT Doherty PA
[F. Wang, [S. Li, RFIC18, Resilient Reconfigurable Mode Inverse-
Efficient Multi-Port PA mm-Wave Doherty PA [F. Wang, ISSCC20]
ISSCC19, JSSC19] JSSC19] Doherty PA Outphasing PA/TX
[C. Chappidi, VLSI19, [H. Nguyen, RFIC19,
[S. Mannem, ISSCC20, [S. Li, ISSCC20,
TMTT20] JSSC20]
JSSC20] JSSC21]

Papers to See (Videos to Watch) This Year
Suggested papers based on Advance Program
 Session 6
 Paper 6.2 is a 4-Way Doherty Digital TX with 10dB Power Back-Off in the 5GHz band.
 Session 26
 Paper 26.1 is a 26-to-60GHz Coupler-Doherty PA for Over-An-Octave Back-Off Enhancement
 Paper 26.2 is a Doherty-Like mm-Wave load-modulated balanced PA (LMBA) in 28nm CMOS
 Paper 26.3 is a 30GHz dual-drive mm-Wave 5G PA for high efficiency
 Paper 26.5 is a Watt-level quadrature switched/floated-capacitor digital PA with Back-Off
Enhancement
 Paper 26.6 is a 5-to-6GHz current-mode subharmonic switching digital PA for Back-Off
Enhancement

Summary
 Power amplifiers (PAs) have been the key building blocks for
wireless systems.
 PA operation principles and PA classes
 PA active device design, large-signal operation, and linearity
 PA passive network design
 Advanced PA architectures: Digital PAs, Back-Off Efficient PAs, and
Stacked PAs
 RF/mm-Wave PA design examples and technology trends

Key References (1 of 5)
1. S. C. Cripps, RF Power Amplifiers for Wireless Communication, 2nd ed. Norwood, MA: Artech
House, 2006.
2. P. M. Asbeck, N. Rostomyan, M. Özen, B. Rabet, and J. A. Jayamon, “Power Amplifiers for
mm-Wave 5G Applications: Technology Comparisons and CMOS-SOI Demonstration Circuits,”
IEEE Trans. Microw. Theory Techn., vol. 67, no. 7, pp. 3099-3109, Jul. 2019.
3. H. Wang et al., "Power Amplifiers Performance Survey 2000-Present," [Online]. Available:
https://gems.ece.gatech.edu/PA_survey.html.
4. P. Wright, J. Lees, J. Benedikt, P. J. Tasker, and S. C. Cripps, “A Methodology for Realizing
High Efficiency Class-J in a Linear and Broadband PA,” IEEE Trans. Microw. Theory Techn., vol.
57, no. 12, pp. 3196-3204, Dec. 2009.
5. S. C. Cripps, P. J. Tasker, A. L. Clarke, J. Lees, and J. Benedikt, “On the Continuity of High
Efficiency Modes in Linear RF Power Amplifiers,” IEEE Microw. Wireless Compon. Lett., vol. 19,
no. 10, pp. 665–667, Oct. 2009.
6. H. Kobayashi, J. M. Hinrichs, and P. M. Asbeck, “Current-Mode Class-D Power Amplifiers for
High-Efficiency RF Applications,” IEEE Trans. Microw. Theory Techn., vol. 49, no. 12, pp. 2480-
2485, Dec. 2001.

7. D. Chowdhury, S. V. Thyagarajan, L. Ye, E. Alon, and A. M. Niknejad, ”A Fully-Integrated Efficient
CMOS Inverse Class-D Power Amplifier for Digital Polar Transmitters,” IEEE J. Solid State Circuits,
vol. 47, no. 5, pp. 1113–1122, May 2012.
8. S. Golara, S. Moloudi, and A. A. Abidi et al., “Processes of AM-PM Distortion in Large-Signal Single-
FET Amplifiers,” IEEE TCAS-I, vol. 64, no. 2, pp. 245–260, Feb. 2017.
9. B. Razavi, RF Microelectronics, 2nd ed. Prentice Hall, 2011.
10. D. Chowdhury, C. D. Hull, O. B. Degani, Y. Wang, and A. M. Niknejad, ” A Fully Integrated Dual-
Mode Highly Linear 2.4 GHz CMOS Power Amplifier for 4G WiMax Applications,” IEEE J. Solid State
Circuits, vol. 44, no. 12, pp. 3393–3402, Dec. 2009.
11. J. Kang, J. Yoon, K. Min, D. Yu, J. Nam, Y. Yang, and B. Kim, ” A Highly Linear and Efficient
Differential CMOS Power Amplifier With Harmonic Control,” IEEE J. Solid State Circuits, vol. 41, no. 6,
pp. 1314–1322, Jun. 2006.
12. T. Li, M. Huang, H. Wang, “A Continuous-Mode Harmonically Tuned 19-to-29.5 GHz Ultra-Linear PA
Supporting 18Gb/s at 18.4% Modulation PAE and 43.5% Peak PAE,” in IEEE ISSCC, 2018, pp. 410-
412.
13. M. Vigilante, P. Reynaert, “A Wideband Class-AB Power Amplifier With 29–57-GHz AM–PM
Compensation in 0.9-V 28-nm Bulk CMOS,” IEEE J. Solid State Circuits, vol. 53, no. 5, pp. 1288–
1301, May 2018.
14. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed. Cambridge, 2004.
15. D. Pozar, Microwave Engineering, 4th ed. Wiley, 2011.
16. J. Long, “Monolithic Transformers for Silicon RF IC Design,” IEEE J. Solid State Circuits, vol. 35, no.
9, pp. 1368–1382, Sep. 2000.
17. H. Wang, C. Sideris, and A. Hajimiri, “A CMOS Broadband Power Amplifier With a Transformer-
Based High-Order Output Matching Network,” IEEE J. Solid State Circuits, vol. 45, no. 12, pp. 2709 –
2722, Dec. 2010.
18. M. Bassi, J. Zhao, A. Bevilacqua, A. Ghilioni, A. Mazzanti, F. Svelto, “A 40–67 GHz Power Amplifier
With 13 dBm Psat and 16% PAE in 28 nm CMOS LP,” IEEE J. Solid State Circuits, vol. 50, no. 7, pp.
1618 – 1628, Jul. 2015.
19. K. S. Ang, Y. C. Leong, and C. H. Lee, “Analysis and Design of Miniaturized Lumped-Distributed
Impedance-Transforming Baluns,” IEEE Trans. Microw. Theory Techn., vol. 51, no. 3, pp. 1009–
1017, Mar. 2003.
20. H. Nguyen and H. Wang, "A Coupler-Based Differential Mm-Wave Doherty Power Amplifier with
Impedance Inverting and Scaling Baluns," IEEE J. Solid State Circuits, vol. 55, no. 5, pp. 1212 –
1223, May 2020.

21. H. Nguyen, D. Jung, and H. Wang, "A 60GHz CMOS Power Amplifier with Cascaded Asymmetric
Distributed-Active-Transformer Achieving Watt-Level Peak Output Power with 20.8% PAE and
Supporting 2Gsym/s 64-QAM Modulation," in IEEE ISSCC, 2019, pp. 90-92.
22. W. Yuan and J. S. Walling, "A Multiphase Switched Capacitor Power Amplifier," IEEE J. Solid State
Circuits, vol. 52, no. 5, pp. 1320 – 1330, May 2017.
23. M. S. Alavi, R. Bogdan Staszewski, L. C. N. de Vreede, and J. R. Long “A Wideband 2×13-bit All-
Digital I/Q RF-DAC,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 4, pp. 732–752, Apr. 2014.
24. S.-M. Yoo, J. S. Walling, E. C. Woo, B. Jann, D. J. Allstot, “A Switched-Capacitor RF Power
Amplifier,” IEEE J. Solid State Circuits, vol. 46, no. 12, pp. 2977-2987, Dec. 2011.
25. W. H. Doherty, “A New High Efficiency Power Amplifier for Modulated Waves,” Proc. Institute of
Radio Engineers, vol. 24, no. 9, pp. 1163-1182, Sep. 1936.
26. H. Chireix, “High Power Outphasing Modulation,” Proc. Institute of Radio Engineers, vol. 23, no. 11,
pp. 1370-1392, Nov. 1935.
27. L. Kahn, “Single-Sideband Transmission by Envelope Elimination and Restoration,” Proc. Institute
of Radio Engineers, vol. 40, no. 7, pp. 803-806, Jul. 1952.
28. A. Saleh and D. C. Cox, “Improving the Power-Added Efficiency of FET Amplifiers Operating with Varying-
Envelope Signals,” IEEE Trans. Microw. Theory Techn., vol. 31, no. 1, pp. 51–56, Jan. 1983.

29. S. Mandegaran and A. Hajimiri, "A Breakdown Voltage Multiplier for High Voltage Swing Drivers,"
IEEE J. Solid State Circuits, vol. 42, no. 2, pp. 302 – 312, Feb. 2007.
30. H.-T. Dabag, B. Hanafi, F. Golcuk, A. Agah, J. F. Buckwalter, and P. M. Asbeck, “Analysis and
Design of Stacked-FET Millimeter-Wave Power Amplifiers,” IEEE Trans. Microw. Theory Techn., vol.
61, no. 4, pp. 1543–1556, Apr. 2013.
31. I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, "Fully Integrated CMOS Power Amplifier Design
Using the Distributed Active-Transformer Architecture," IEEE J. Solid State Circuits, vol. 37, no. 3,
pp. 371 – 383, Mar. 2002.
32. P. Haldi, D. Chowdhury, P. Reynaert, G. Liu, and A. M. Niknejad, "A 5.8 GHz 1 V Linear Power
Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS," IEEE J.
Solid State Circuits, vol. 43, no. 5, pp. 1054 – 1063, May 2008.
33. S. Hu, F. Wang, H. Wang, "A 28GHz/37GHz/39GHz Multiband Linear Doherty Power Amplifier for
5G Massive MIMO Applications," in IEEE ISSCC, 2017, pp. 32-33.


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Fundamentals of RF and Mm-Wave

Power Amplifier Designs

Live Q&A Session: Feb. 13, 2021, 7:00-7:20 am, PST

Hua Wang Fundamentals of RF and Mm-Wave 1 of 98

Hua Wang Fundamentals of RF and Mm-Wave 2 of 98

 PA Operation Principles and PA Classes

 Power Amplifier Design Considerations

 Advanced Power Amplifier Architectures

 RF and Mm-Wave PA Design Examples

 Summary and Conclusions

Hua Wang Fundamentals of RF and Mm-Wave 3 of 98

Hua Wang Fundamentals of RF and Mm-Wave 4 of 98

• Device Gain/Efficiency/Linearity • Impedance Transformation

Hua Wang Fundamentals of RF and Mm-Wave 5 of 98

 PIn, PPA, POut (PL), PDC = PDC, PA + PDC, Driver

 PA Power Gain: GP = POut/PIn

 PA Drain Efficiency (DE or η): η = POut/PDC

 Power Added Efficiency (PAE): PAE = (POut-PIn)/PDC

Hua Wang Fundamentals of RF and Mm-Wave 6 of 98

PIn, PPA, POut, GP,

 PA Drain Efficiency: η = POut/PDC

Hua Wang Fundamentals of RF and Mm-Wave 7 of 98

PIn, PPA, POut, GP,

 PA Drain Efficiency: η = POut/PDC

Hua Wang Fundamentals of RF and Mm-Wave 8 of 98

PIn, PPA, POut, GP,

 PA Drain Efficiency: η = POut/PDC

Hua Wang Fundamentals of RF and Mm-Wave 9 of 98

 Device Intrinsic η  PA Classes and  Device Gain with  PA Output Network

Hua Wang Fundamentals of RF and Mm-Wave 10 of 98

 RF-Frequency PAs  Mm-Wave PAs

 Bluetooth: Class 1 (20 dBm),

Hua Wang Fundamentals of RF and Mm-Wave 11 of 98

Need: High Power

Hua Wang Fundamentals of RF and Mm-Wave 12 of 98

 Limited device output power and Device

Need: High-Power High-Efficiency

Hua Wang Fundamentals of RF and Mm-Wave 13 of 98

Parameter Average EVM

Hua Wang Fundamentals of RF and Mm-Wave 14 of 98

Hua Wang Fundamentals of RF and Mm-Wave 15 of 98

US Spectrum Allocation Mm-Wave 5G Bands

Hua Wang Fundamentals of RF and Mm-Wave 16 of 98

Reliability Data Rate

Hua Wang Fundamentals of RF and Mm-Wave 17 of 98

 What we will NOT cover (but are essential)…

Hua Wang Fundamentals of RF and Mm-Wave 18 of 98

 PA Operation Principles and PA Classes

 Power Amplifier Design Considerations

 Advanced Power Amplifier Architectures

 RF and Mm-Wave PA Design Examples

 Summary and Conclusions

Hua Wang Fundamentals of RF and Mm-Wave 19 of 98

Drain Efficiency Medium-Low High (100% Theoretically)

Modulations Varying Amplitude (QAM, etc.) Constant Amplitude

Harmonics Harmonic Suppression Waveform Shaping

 Device can be abrupted turned ON or OFF. Vds Vds

 Hard limits on device output voltage and 0 VTH

Hua Wang Fundamentals of RF and Mm-Wave 21 of 98

 Conjugate Matching  Loadline Matching

 RL = Vmax/Imax = 2ohm << RS = 100ohm

 r0  ∞ and no triode region IL

Hua Wang Fundamentals of RF and Mm-Wave 25 of 98