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HT12A/HT12E 2 Series of Encoders: Features
HT12A/HT12E 2 Series of Encoders: Features
12
2 Series of Encoders
Features
· Operating voltage · Minimum transmission word
- 2.4V~5V for the HT12A - Four words for the HT12E
- 2.4V~12V for the HT12E - One word for the HT12A
· Low power and high noise immunity CMOS · Built-in oscillator needs only 5% resistor
technology · Data code has positive polarity
· Low standby current: 0.1mA (typ.) at · Minimal external components
VDD=5V · HT12A/E: 18-pin DIP/20-pin SOP package
· HT12A with a 38kHz carrier for infrared
transmission medium
Applications
· Burglar alarm system · Car alarm system
· Smoke and fire alarm system · Security system
· Garage door controllers · Cordless telephones
· Car door controllers · Other remote control systems
General Description
The 212 encoders are a series of CMOS LSIs for via an RF or an infrared transmission medium
remote control system applications. They are upon receipt of a trigger signal. The capability
capable of encoding information which consists to select a TE trigger on the HT12E or a DATA
of N address bits and 12-N data bits. Each ad- trigger on the HT12A further enhances the ap-
dress/data input can be set to one of the two plication flexibility of the 212 series of encoders.
logic states. The programmed addresses/data The HT12A additionally provides a 38kHz car-
are transmitted together with the header bits rier for infrared systems.
Selection Table
Function Address Address/ Data Carrier Negative
Oscillator Trigger Package
Part No. No. Data No. No. Output Polarity
455kHz 18 DIP
HT12A 8 0 4 D8~D11 38kHz No
resonator 20 SOP
RC 18 DIP
HT12E 8 4 0 TE No No
oscillator 20 SOP
Note: Address/Data represents pins that can be address or data according to the decoder require-
ment.
Block Diagram
TE trigger
HT12E
O S C 2 O S C 1
O s c illa to r ¸ 3 D iv id e r D a ta S e le c t D O U T
T E
& B u ffe r
¸ 1 2 C o u n te r & S y n c .
A 0
1 o f 1 2 D e c o d e r C ir c u it
1 2 T r a n s m is s io n
G a te C ir c u it
A 7 B in a r y D e te c to r
A D 8 A D 1 1 V D D V S S
DATA trigger
HT12A
X 2 X 1
O s c illa to r ¸ 5 7 6 D iv id e r D a ta S e le c t D O U T
& B u ffe r
L /M B
¸ 1 2 C o u n te r & S y n c .
A 0
1 o f 1 2 D e c o d e r C ir c u it
1 2 T r a n s m is s io n
G a te C ir c u it
A 7
B in a r y D e te c to r
D 8 D 1 1 V D D V S S
Note: The address data pins are available in various combinations (refer to the address/data table).
Pin Assignment
8 -A d d re s s 8 -A d d re s s 8 -A d d re s s 8 -A d d re s s
4 -D a ta 4 -D a ta 4 -A d d r e s s /D a ta 4 -A d d r e s s /D a ta
N C 1 2 0 N C N C 1 2 0 N C
A 0 1 1 8 V D D A 0 2 1 9 V D D A 0 1 1 8 V D D A 0 2 1 9 V D D
A 1 2 1 7 D O U T A 1 3 1 8 D O U T A 1 2 1 7 D O U T A 1 3 1 8 D O U T
A 2 3 1 6 X 1 A 2 4 1 7 X 1 A 2 3 1 6 O S C 1 A 2 4 1 7 O S C 1
A 3 4 1 5 X 2 A 3 5 1 6 X 2 A 3 4 1 5 O S C 2 A 3 5 1 6 O S C 2
A 4 5 1 4 L /M B A 4 6 1 5 L /M B A 4 5 1 4 T E A 4 6 1 5 T E
A 5 6 1 3 D 1 1 A 5 7 1 4 D 1 1 A 5 6 1 3 A D 1 1 A 5 7 1 4 A D 1 1
A 6 7 1 2 D 1 0 A 6 8 1 3 D 1 0 A 6 7 1 2 A D 1 0 A 6 8 1 3 A D 1 0
A 7 8 1 1 D 9 A 7 9 1 2 D 9 A 7 8 1 1 A D 9 A 7 9 1 2 A D 9
V S S 9 1 0 D 8 V S S 1 0 1 1 D 8 V S S 9 1 0 A D 8 V S S 1 0 1 1 A D 8
H T 1 2 A H T 1 2 A H T 1 2 E H T 1 2 E
1 8 D IP 2 0 S O P 1 8 D IP 2 0 S O P
Pin Description
Internal
Pin Name I/O Description
Connection
CMOS IN
Pull-high
(HT12A)
NMOS Input pins for address A0~A7 setting
A0~A7 I TRANSMISSION These pins can be externally set to VSS or left open
GATE
PROTECTION
DIODE
(HT12E)
NMOS
TRANSMISSION
GATE Input pins for address/data AD8~AD11 setting
AD8~AD11 I
PROTECTION These pins can be externally set to VSS or left open
DIODE
(HT12E)
Input pins for data D8~D11 setting and transmission en-
CMOS IN able, active low
D8~D11 I
Pull-high These pins should be externally set to VSS or left open
(see Note)
DOUT O CMOS OUT Encoder data serial transmission output
Latch/Momentary transmission format selection pin:
CMOS IN
L/MB I Latch: Floating or VDD
Pull-high
Momentary: VSS
Internal
Pin Name I/O Description
Connection
CMOS IN
TE I Transmission enable, active low (see Note)
Pull-high
OSC1 I OSCILLATOR 1 Oscillator input pin
OSC2 O OSCILLATOR 1 Oscillator output pin
X1 I OSCILLATOR 2 455kHz resonator oscillator input
X2 O OSCILLATOR 2 455kHz resonator oscillator output
VSS I ¾ Negative power supply, grounds
VDD I ¾ Positive power supply
Note: D8~D11 are all data input and transmission enable pins of the HT12A.
TE is a transmission enable pin of the HT12E.
N M O S C M O S IN
T R A N S M IS S IO N C M O S O U T O S C IL L A T O R 1
P u ll- h ig h
G A T E
E N O S C 2
O S C 1
O S C IL L A T O R 2 N M O S T R A N S M IS S IO N G A T E
P R O T E C T IO N D IO D E
X 1 X 2
V D D
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-
mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo-
sure to extreme conditions may affect device reliability.
Electrical Characteristics
HT12A Ta=25°C
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾ ¾ 2.4 3 5 V
3V ¾ 0.1 1 mA
ISTB Standby Current Oscillator stops
5V ¾ 0.1 1 mA
3V No load ¾ 200 400 mA
IDD Operating Current
5V fOSC=455kHz ¾ 400 800 mA
VOH=0.9VDD (Source) -1 -1.6 ¾ mA
IDOUT Output Drive Current 5V
VOL=0.1VDD (Sink) 2 3.2 ¾ mA
VIH ²H² Input Voltage ¾ ¾ 0.8VDD ¾ VDD V
VIL ²L² Input Voltage ¾ ¾ 0 ¾ 0.2VDD V
HT12E Ta=25°C
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾ ¾ 2.4 5 12 V
3V ¾ 0.1 1 mA
ISTB Standby Current Oscillator stops
12V ¾ 2 4 mA
3V No load ¾ 40 80 mA
IDD Operating Current
12V fOSC=3kHz ¾ 150 300 mA
VOH=0.9VDD (Source) -1 -1.6 ¾ mA
IDOUT Output Drive Current 5V
VOL=0.1VDD (Sink) 1 1.6 ¾ mA
VIH ²H² Input Voltage ¾ ¾ 0.8VDD ¾ VDD V
VIL ²L² Input Voltage ¾ ¾ 0 ¾ 0.2VDD V
fOSC Oscillator Frequency 5V ROSC=1.1MW ¾ 3 ¾ kHz
RTE TE Pull-high Resistance 5V VTE=0V ¾ 1.5 3 MW
Functional Description
Operation
The 212 series of encoders begin a 4-word transmission cycle upon receipt of a transmission enable
(TE for the HT12E or D8~D11 for the HT12A, active low). This cycle will repeat itself as long as the
transmission enable (TE or D8~D11) is held low. Once the transmission enable returns high the en-
coder output completes its final cycle and then stops as shown below.
T E
< 1 w o rd
E n c o d e r
D O U T
4 w o rd s T r a n s m itte d 4 w o rd s
C o n tin u o u s ly
D 8 ~ D 1 1
K e y - in
< 1 w o rd
E n c o d e r
D O U T w ith 3 8 k H z c a r r ie r
1 w o rd T r a n s m itte d 1 w o rd
C o n tin u o u s ly
D 8 ~ D 1 1
K e y - in ( a ll d a ta = 1 )
< 1 w o rd 7 w o rd s
E n c o d e r
D O U T
7 w o rd s T r a n s m itte d 1 w o rd
C o n tin u o u s ly
1 w o rd ( a ll d a ta = 1 )
Information word
If L/MB=1 the device is in the latch mode (for use with the latch type of data decoders). When the trans-
mission enable is removed during a transmission, the DOUT pin outputs a complete word and then
stops. On the other hand, if L/MB=0 the device is in the momentary mode (for use with the momentary
type of data decoders). When the transmission enable is removed during a transmission, the DOUT
outputs a complete word and then adds 7 words all with the ²1² data code.
An information word consists of 4 periods as illustrated below.
1 /3 b it s y n c . p e r io d
p ilo t p e r io d ( 1 2 b its ) a d d r e s s c o d e p e r io d d a ta c o d e
p e r io d
Composition of information
Address/data waveform
Each programmable address/data pin can be externally set to one of the following two logic states as
shown below.
fO S C
"O n e "
"Z e ro "
A d d re s s /
D a ta B it
fO S C
3 8 k H z
"O n e " c a r r ie r
D a ta B it
"Z e ro "
D a ta B it
"O n e "
A d d r e s s B it
"Z e ro "
A d d r e s s B it
The address/data bits of the HT12A are transmitted with a 38kHz carrier for infrared remote con-
troller flexibility.
O S C 1 O S C 2
T r a n s m is s io n
D O U T m e d iu m
V D D A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 V S S T E A D 8 A D 9 A D 1 0 A D 1 1
V D D
V S S
Address/Data sequence
The following provides the address/data sequence table for various models of the 212 series of
encoders. The correct device should be selected according to the individual address and data require-
ments.
Address/Data Bits
Part No.
0 1 2 3 4 5 6 7 8 9 10 11
HT12A A0 A1 A2 A3 A4 A5 A6 A7 D8 D9 D10 D11
HT12E A0 A1 A2 A3 A4 A5 A6 A7 AD8 AD9 AD10 AD11
Transmission enable
For the HT12E encoders, transmission is enabled by applying a low signal to the TE pin. For the
HT12A encoders, transmission is enabled by applying a low signal to one of the data pins D8~D11.
O S C 2 V D D
O S C 1 A D 1 1
T E A D 1 0
A D 9
V S S
A D 8
1 2 V
H T 1 2 E
O S C 2 V D D
O S C 1 A D 1 1
T E A D 1 0
A D 9
V S S
A D 8
H T 1 2 E
Flowchart
· HT12A · HT12E
P o w e r o n P o w e r o n
S ta n d b y m o d e S ta n d b y m o d e
N o D a ta e n a b le ? N o T r a n s m is s io n
e n a b le d ?
Y e s Y e s
D a ta w ith c a r r ie r 4 d a ta w o rd s
s e r ia l o u tp u t tr a n s m itte d
Y e s N o T r a n s m is s io n
D a ta s till e n a b le d ?
s till e n a b le d
N o Y e s
Y e s 4 d a ta w o rd s
L /M B = G N D ? tr a n s m itte d
c o n tin u o u s ly
N o
S e n d th e S e n d ² 1 ² 7 tim e s fo r
la s t c o d e a ll o f th e d a ta c o d e s
fO S C
(S c a le )
R O S C (W )
7 .0 0
4 7 0 k
5 1 0 k
6 .0 0
5 6 0 k
6 2 0 k
5 .0 0
6 8 0 k
7 5 0 k
4 .0 0 8 2 0 k
9 1 0 k
1 .0 M
(3 k H z )3 .0 0
1 .2 M
1 .5 M
2 .0 0
2 .0 M
1 .0 0
2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 V D D (V D C )
Application Circuits
V D D 1 0 0 W
T r a n s m itte r C ir c u it
V D D
1 A 0 V D D 1 8
8 0 5 0 1 A 0 V D D 1 8
2 1 7 1 0 k W
A 1 D O U T 2 1 7
A 1 D O U T
3 1 6 4 5 5 k W
A 2 X 1 1 0 0 p F 3 1 6
A 2 O S C 1
1 0 M W R O S C
4 1 5 4 A 3 O S C 2 1 5
A 3 X 2 1 0 0 p F
5 1 4 5 A 4 T E 1 4
A 4 L /M B
6 1 3 6 A 5 A D 1 1 1 3
A 5 D 1 1
7 1 2 7 A 6 A D 1 0 1 2
A 6 D 1 0
8 1 1 8 A 7 A D 9 1 1
A 7 D 9
9 1 0 9 1 0
V S S D 8 V S S A D 8
H T 1 2 A H T 1 2 E