2476
6, NOVEMBER 2007
FPGA-Based Speed Control IC for PMSM
Drive With Adaptive Fuzzy Control
Ying-Shieh Kung, Member, IEEE, and Ming-Hung Tsai
Abstract—The new generation of field programmable gate
array (FPGA) technologies enables an embedded processor intel-
lectual property (IP) and an application IP to be integrated into a
system-on-a-programmable-chip (SoPC) developing environment.
Therefore, this study presents a speed control integrated circuit
(IC) for permanent magnet synchronous motor (PMSM) drive
under this SoPC environment. First, the mathematic model of
PMSM is defined and the vector control used in the current loop
of PMSM drive is explained. Then, an adaptive fuzzy controller
adopted to cope with the dynamic uncertainty and external load
effect in the speed loop of PMSM drive is proposed. After that, an
FPGA-based speed control IC is designed to realize the controllers.
The proposed speed control IC has two IPs, a Nios II embedded
processor IP and an application IP. The Nios II processor is
used to develop the adaptive fuzzy controller in software due to
the complicated control algorithm and low sampling frequency
control (speed control: 2 kHz). The designed application IP is
utilized to implement the current vector controller in hardware
owing to the requirement for high sampling frequency control
(current loop: 16 kHz, pulsewidth modulation circuit: 4–8 MHz)
but simple computation. Finally, an experimental system is set up
and some experimental results are demonstrated.
Index Terms—Field programmable gate arrays (FPGAs), fuzzy
control, permanent magnet motors, synchronous motor drives,
system-on-a-programmable-chip (SoPC).
I. INTRODUCTION
O WING to the advantages of the superior power density,
high performance in motion control—fast response
and better accuracy, permanent magnet synchronous motors
(PMSM) have used in many automation control fields as an
actuators [1]. But in industrial applications, there are many un-
certainties, such as system parameter uncertainty, external load
disturbance, friction force, unmodeled uncertainty, etc. which
always diminish the performance quality of the pre-design of
the motor driving system. To cope with this problem, in recent
years, many intelligent control techniques [2]–[5], such as
fuzzy control, neural networks control, adaptive fuzzy control
and other control method, have been developed and applied to
the speed control of servo motor drives to obtain high operating
performance. A high-performance motor control system should
Manuscript received September 7, 2006; revised February 18, 2007. Recom-
mended for publication by Associate Editor A. Emadi.
Y.-S. Kung is with the Department of Electrical Engineering, Southern
Taiwan University, Tainan 710, Taiwan, R.O.C. (e-mail: kung@mail.stut.edu.
tw).
M.-H. Tsai is with the Institute of Mechatronic Science and Technology,
Southern Taiwan University, Tainan 710, Taiwan, R.O.C. (e-mail: z4r@mail.
stut.edu.tw).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2007.909185
0885-8993/$25.00 © 2007 IEEE
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO.
have a fast dynamic response to adjustments in its control
parameters, so that the motor outputs that influenced by the dis-
turbances can recover to their original status as soon as possible
[6]. However, the execution of a neural network or adaptive
fuzzy control requires many computations, so implementation
of these highly complex control algorithms depend on the PC
systems in most studies [3], [7]. In recent years, the fixed-point
digital signal processor (DSP) and field programmable gate
array (FPGA) also provide a possible solution in this issue
[8], [9]. Comparing with FPGA, although the aforementioned
intelligent control technique using DSP provides a flexible
skill, it suffers from a long period of development and exhausts
many resources of the CPU [9].
Nowadays, due to the progress of VLSI technology, the
FPGA has brought more attention before. The advantages of
the FPGA include their programmable hard-wired feature, fast
time-to-market, shorter design cycle, embedding processor,
low power consumption and higher density for the implemen-
tation of the digital system [10]. FPGA provides a compromise
between the special-purpose application specified integrated
circuit (ASIC) hardware and general-purpose processors [11].
Hence, many practical applications in inverter [12], [13] and
motor control [9], [14]–[17] have been studied. Tzou [12]
and Zhou [13], respectively, gave an FPGA realization of the
space-vector pulsewidth modulation (PWM) for three-phase
inverters. Zhou [9] proposed an FPGA-realization of a speed
servo controller of PMSM. A PI controller was adopted in speed
loop of PMSM drive. Takshashi [14] utilized an FPGA to im-
plement a complete ac servo controller. An application specific
standard product (ASSP) created to reduce the gate count was
considered in this study. Fang [16] adopted an FPGA-based
chip to design the conceptual core of sliding mode control
strategy for PMSM. Lin [17] presented a fuzzy sliding-mode
control for a linear induction motor drive based on FPGA. The
fuzzy sliding-mode controller with fuzzy inference mechanism
to adapt the system uncertainty in real-time is proposed in
this paper. However, the above researches studied the servo
control system of inverter or ac motor only by FPGA hardware
implementation with the simple computation algorithm.
Embedded processor IP and application IP can now
be developed and downloaded into FPGA to construct
a system-on-a-programmable-chip (SoPC) environment
[18]–[20], allowing the user to design a SoPC module by
mixing hardware and software in one FPGA chip. The circuits
required with fast processing but simple computation are
suitable to be implemented by hardware in FPGA, and the
highly complicated control algorithm with heavy computation
KUNG AND TSAI: FPGA-BASED SPEED CONTROL IC 2477

Fig. 1. Internal architecture of FPGA-based speed control IC for PMSM drive.

can be realized by software in FPGA. With the results of scheme for PMSM is implemented by hardware in FPGA. The
the software/hardware co-design function increase the pro- detailed theoretical description follows.
grammable, flexibility of the designed digital system, reduce
A. Mathematical Model of PMSM
the development time and enhance the system performance.
Our previous works [21]–[23] have successfully applied the The mathematical model of a typical PMSM is described, in
SoPC technology to the servo system of PMSM drive, robot two-axis - synchronous rotating reference frame, as follows
arm, and – table. [1]:
To exploit the advantages, this study presents a fully digital (1)
speed control integrated circuit (IC) for PMSM drive based on
the new-generation FPGA technology, as in Fig. 1. The pro-
(2)
posed motion control IC has two IPs, a Nios II embedded pro-
cessor IP and an application IP. The Nios embedded processor
where are the and axis voltages; are the and
IP is adopted to implement the adaptive fuzzy control functions
axis currents, is the phase winding resistance; are the
using software, and the application IP is used to realize the cur-
and axis inductance; is the electrical angular speed;
rent vector control with hardware. Besides, a finite state machine
is the permanent magnet flux linkage. The current control of a
(FSM) method is also considered to reduce the logic elements
PMSM drive is based on vector control approach, such that if
(LEs) usage of FPGA in this paper. Hence, all functionalities,
is controlled to 0 in Fig. 1, the PMSM is decoupled. Therefore,
which are based on software/hardware co-design, required to
the developed electromagnetic torque can be simplified to [1]
build a fully digital servo control for PMSM drive can be in-
tegrated in one FPGA chip. The FPGA chip employed herein
is an Altera Cyclone EP1C20 with 20 060 LEs, maximum 301 (3)
user I/O pins, 294 912 b of RAM, and a Nios II embedded pro-
cessor. The processor has a 32-b configurable CPU core, 16 M with
byte Flash memory, 1 M byte SRAM and 16 M byte SDRAM.
Finally, an experimental system included by an FPGA experi-
mental board, an inverter and a PMSM, is set up to verify the (4)
correctness and effectiveness of the FPGA-based speed control
IC. Considering the mechanical load, the dynamic equation of
PMSM can be written as follows [1]:
II. SYSTEM DESCRIPTION OF PMSM DRIVE
AND ITS DESIGN METHODOLOGY
(5)
The internal architecture of the proposed FPGA-based servo
system for the PMSM drive is shown in Fig. 1. The adaptive where and are the number of pole
fuzzy control in the speed loop is developed in software using pairs, the rotor speed, the motor toque, the torque constant, the
the Nios II embedded processor. The current vector control inertial value, the damping ratio and the load toque, respectively.
2478 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

Fig. 2. Block diagram of internal circuit of an FPGA-based speed control IC.

The dashed rectangular area of Fig. 1 shows the configuration

of the current loop of the PMSM drive, including two PI con-
trollers, coordinate transformations of Clark, Modified inverse
Clark, Park, inverse Park, SVPWM, pulse signal detection of the
encoder and other element. Vector control (with set to zero in
Fig. 1) in the current loop of the PMSM drive, decouples the
nonlinear and coupled characteristics of PMSM. Accordingly,
controlling the torque of PMSM is only need to control the cur-
rent in the direction of -axis. The formulations about the trans-
formations among the stationary frame, the stationary
- frame and the synchronously rotating frame in Fig. 1
refer to [5].
In Fig. 1, two digital PI controllers are presented in the current
Fig. 3. Main program and ISR for adaptive fuzzy control in Nios II processor.
loop of PMSM and the formulations are as follows:

(6) B. Adaptive Fuzzy Controller in Speed Control Loop

(7)
(8)
(9)
where represents axis or axis and is the error be-
tween current command and measured current. Those
are P controller gain and I controller gain, respectively. The
are the output of P controller only, I con-
troller only and the PI controller, respectively.
The solid rectangular area in Fig. 1 presents the structure of
an adaptive fuzzy controller for PMSM drive. It consists of a
fuzzy controller, a reference model and an adjusting mechanism.
Detailed description is as follows.
1) Fuzzy Controller: Generally speaking, P controller in
series connection with fuzzy system belongs to a PD type
fuzzy controller, but PI controller in series connection with
fuzzy system belongs to a PID type fuzzy controller which
is adopted in our proposed system in Fig. 1. The latter one
KUNG AND TSAI: FPGA-BASED SPEED CONTROL IC 2479

Fig. 4. Designed CCCT circuit in Fig. 2 by using parallel processing method.

has more flexible and less steady state error than the former 2) Select the initial fuzzy control rules by referring to the dy-
one. The fuzzy controller in this study uses singleton fuzzifier, namic response characteristics [4], such as
triangular membership function, product-inference rule and
central average defuzzifier method [24]. In Fig. 1, the tracking IF is and is THEN is
error and the error change are defined by (13)
There are seven fuzzy sets for each linguist value
(10) and 49 fuzzy control rules are designed
(11) for the two inputs and one output fuzzy system. Therefore,
is 49 in (13).
3) Construct the fuzzy system, , by using the sin-
and represents the output of the fuzzy controller. The is
gleton fuzzifier, product-inference rule, and central average
the output of the reference model. The design procedure of the
defuzzifier method. Therefore, (13) is replaced with the
fuzzy controller is as follows.
following expression: [25]
1) Take and as the input and output vari-
able of fuzzy controller, and define their linguist values as
based on the symmetrical triangular member-
ship function

(14)

The are adjustable parameters. In imple-

mentation, the adjustable ranges for each parameter is
limited between and .
2) Reference Model: Second order system is taken as the
when (12) reference model in adaptive fuzzy controller in Fig. 1, and it
can be expressed as

where is the input value; is the output value; (15)

are mean and width of the triangular function;
are the gains of error and error change. where is natural frequency and is damping ratio.
2480 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

Fig. 5. Designed CCCT circuit in Fig. 2 by using FSM method.

Applying the bilinear transformation, the continuous model
in (15) can be transformed to a discrete model by
(16)
where represents learning rate. The formulations for the ad-
justment of the parameters of the fuzzy controller are derived,
by initially, assume to be zero in (5), and taking Laplace
transformation of (3) and (5)

(20)
the is back shift operator and and are the
parameters of the discrete model. Furthermore, the difference
equation is written as Next, the bilinear transformation is used to derive the following
difference equation of PMSM drive system

(17)
(21)
3) Parameter Adjusting Mechanism: The gradient descent
method is used to derive the fuzzy control law in Fig. 1. The pri- where is a back-shift operator and is the sampling period.
mary purpose of adjusting the parameters of the fuzzy controller Additionally, in Fig. 1, the current command, is formulated
is to minimize the square error (instantaneous cost function) be- by the output of fuzzy controller,
tween the rotor speed and the output of the reference model. The
instantaneous cost function is defined by
(22)
(18)
and where are the PI controller gains, and is the
and the parameters of are adjusted according to output of the controller. From (21) and (22)

(19)
(23)
KUNG AND TSAI: FPGA-BASED SPEED CONTROL IC
with . The chain
rule is used to rewrite, the partial differential equation for
in (18) can be rewritten as
(24)
From (14) and (23), we can get
(25)
and
(26)
Therefore, (25) and (26) are substituted into (24) and (19), and
then the parameters of fuzzy controller described by (14) can
be adjusted using the following expression:
(27)
Because the motor parameter is not easily to determined, so
the is used in (27). It is unity because is positive. The
represents the sign operator.
C. Proposed FPGA-Based Control IC for PMSM Drive
Fig. 2 illustrates the internal architecture of the proposed
FPGA-based speed control IC for PMSM drive. The speed
control IC, which comprises a Nios II embedded processor IP
and an application IP, is designed based on a SoPC technology,
which is developed by Altera Cooperation. The FPGA chip
adopted herein is a Cyclone EP1C20, which has 20 060 LEs,
maximum 301 user I/O pins and total 294 912 b of RAM.
The Nios II embedded processor has a 32-b configurable CPU
core, 16 M byte Flash memory, 1 M byte SRAM and 16 M
byte SDRAM. A custom software development kit (SDK)
consists of a compiled library of software routines for the SoPC
design, a Make-file for rebuilding the library, and C header files
containing structures for each peripheral.
The Nios II processor IP depicted in Fig. 2 performs the func-
tion of an adaptive fuzzy control in speed loop of PMSM drive
in software. The clock frequency of the Nios II processor is
50 MHz. Fig. 3 illustrates the flow charts of the main program
and the interrupt service routine (ISR) for adaptive fuzzy con-
trol, where the interrupt interval is designed with 500 s. All
programs are coded in the C programming language in Fig. 3.
Then, through the complier and linker operation in the Nios II
Integrated Development Environment (IDE), the execution code
is produced and can be downloaded to the external Flash or
SDRAM via JTAG interface. Finally, this execution code can
be read by Nios II processor IP via bus interface in Fig. 2. The
computation time in Nios II processor for executing the adap-
tive fuzzy control algorithm in speed loop is 120 s. Using the
C language to develop the control algorithm not only has the
portable merit but also is easier to transfer the mature code,
2481
Fig. 6. (a) Circuit of SVPWM generation and (b) circuit of QEP detection and
transformation.
which has been well-developed in other devices such as DSP
device or PC-based system, to the Nios II processor.
The application IP implemented by hardware, as depicted in
Fig. 2, is adopted to realize the current vector control of PMSM
drive. In addition, its circuits include frequency divider, current
controllers and coordinate transformation (CCCT), SVPWM
generation, QEP detection and transformation, ADC read in
and transformation, etc. The sampling frequency of current
control is designed with 16 kHz. The operating clock rate of the
designed FPGA controller is 50 MHz and the frequency divider
generates 50 Mhz (Clk), 25 MHz (Clk-sp) and 16 kHz (Clk-ctr)
clock to supply all module circuits of application IP in Fig. 2.
The internal circuit of CCCT in Fig. 2 performs the function of
two PI controllers, table look-up for function and the
coordinate transformation for Clark, Park, inverse Park, modi-
fied inverse Clarke. However, these formulations have a heavy
computational load. Herein, two kinds of design method that
one is parallel processing method and the other is finite state
machine (FSM) method are introduced to realize the CCCT
circuit. In the former method, the designed CCCT circuit is
shown in Fig. 4, that the circuits of -axis PI controller, -axis
PI controller, Clarke, Park, inverse Park, modified inverse
Clarke, and table look-up for function, will operate
continuously and simultaneously. In Fig. 4, the data type is 12-b
length with Q11 format and 2’s complement operation. Each
circuit of PI controller includes three adders, two multipliers
and two D-type flip-flops. The circuit of Park or inverse Park
transformation also needs two adders and four multipliers.
Under this designed methodology, the resource usage of CCCT
circuit needs 3 659 Logic Elements (LEs) and 24 576 RAM bits
and it is shown in the gray-filled part of Table I(a). Although
the parallel processing method has fast computation ability, it
consumes much more FPGA resources. To reduce the resource
2482 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

TABLE I
UTILITY EVALUATION OF SPEED CONTROL IC FOR PMSM DRIVE IN FPGA FOR
THE DESIGNED CCCT CIRCUIT IN FIG. 2 BY USING (a) PARALLEL
PROCESSING METHOD and (b) FSM METHOD

usage in FPGA, the designed CCCT circuit adopted by using

Fig. 7. (a) Experimental system for SVPWM generation, (b) experiment result
the FSM method is proposed and shown in Fig. 5, which uses without load connection, and (c) experiment result with RC circuit connection.
one adder, one multiplier, an 1-b left shifter, a look-up-table
and manipulates 23 steps machine to carry out the overall
dead-band. Related design method of SVPWM circuit in FPGA
computation of CCCT in Fig. 2. The data type in Fig. 5 is 12-b
refers to [12].
length and Q11 format. In Fig. 5, steps s0–s1 is for the look-up
Finally, the FPGA utility of the speed control IC in Fig. 2
table; steps s2–s4 and s5–s7 are for the computation of
is evaluated and the result is listed in Table I. The resource
d-axis and q-axis PI controller, respectively; and steps s8–s12,
usage of the controller architecture, where the CCCT circuit is
s13–s16, s16–s18 and s19–s23 represent the transformation
adopted by the FSM method in Fig. 2, is presented in Table I(b),
of inverse Park, modified inverse Clarke, Clarke, and Park,
which shows that the overall circuits of the proposed speed con-
respectively. In Fig. 5, the operation of each step in FPGA
trol IC included a Nios II embedded processor IP (3 440 LEs
can be completed within 40 ns (25 MHz clock); therefore
and 49 920 RAM b) and an application IP (2 335 LEs and
total 23 steps need 0.92 s operation time. Although the FSM
24 576 RAM b), use 28.7% LEs resource and 25.3% RAM
method needs more operation time than the parallel processing
resource of Cyclone EP1C20. Compared with Table I(a), the
method in executing CCCT circuit, it doesn’t loss any control
proposed FSM method in Table I(b) economizes the use of
performance at overall system because the 0.92 s operation
2 795 LEs in the overall circuits.
time is much less than the designed sampling interval, 62.5 s
(16 kHz) of current control loop in Fig. 2. Furthermore, from
III. EXPERIMENTS AND RESULTS
the gray-filled part of Table I(b), it is shown that the resource
usage of CCCT circuit designed by the FSM method is 864 LEs The overall experimental system is depicted in Fig. 1, and it
and 24 576 RAM b; therefore, the FSM method, comparing includes an FPGA (Cyclone EP1C20), a voltage source insu-
with the parallel processing method, spends only 1/4 times lated gate bipolar transistor (IGBT) inverter and a PMSM. The
resource usages (LEs) in FPGA. With exception of the CCCT power of the PMSM is 2200 W, the rating speed is 2000 rpm, and
circuit in Fig. 2, others circuit design like SVPWM and QEP the torque magnitude of the brake is adjustable in the range of
are presented in Fig. 6(a) and (b), respectively. The SVPWM 0.2 to 3 N*m. The parameters of the motor as stator resistance
circuit herein is designed to be 16 kHz frequency and 1 s , stator inductance , torque constant and rated
KUNG AND TSAI: FPGA-BASED SPEED CONTROL IC 2483

Fig. 8. (a) Three phase waveforms (b) i ;i and i ;i response in current

control loop.

stator current are 0.63 , 2.77 mH, 1.1 Kg-m/A and 12 A, re-
spectively. An incremental optical encoder (2 500 ppr) attached
to PMSM is used as the rotor’s position sensor. The inverter has
six sets of IGBT type power transistors. The collector-emitter
voltage of the IGBT is rating 600 V, the gate-emitter voltage is
rating 20 V, and the collector current in dc is rating 25 A and
in short time (1 ms) is 50 A. The photo-IC, Toshiba TLP250,
is used for gate driving circuit of IGBT. Input signals of the in-
verter are PWM signals from FPGA device. For the implement,
the PWM switching frequency of inverter, dead-band and the
control sampling frequency of current and speed loop are de-
signed to 16 kHz, 1 s, 16 kHz, and 2 kHz, respectively. In the
proposed FPGA-based speed control IC, the current controller
is implemented by using PLD hardware and the adaptive fuzzy
speed controller is realized by using software in the Nios II em-
bedded processor. The fuzzy controller in this study uses sin-
gleton fuzzifier, triangular membership function, product-infer-
ence rule and central average defuzzifier method. The parameter Fig. 9. Step response of rotor speed and control effort operated at
1200–1500 rpm square wave command and 0.2 N*m load torque under
adjustment mechanism is based on the gradient descent method. case of: (a) without adaptation, (b) with adaptation by learning rate 0.05,
The transfer function of the reference model in Fig. 1 is chosen (c) with adaptation by learning rate 0.1.
by a second order system with the natural frequency of 50 rad/s
and the damping ratio of 1. After applying the bilinear transfor-
mation with sampling frequency by 2 kHz, the parameters of dif- without load connection, PWM1 and PWM2 signals are mea-
ference equation in (17) are obtained by 0.000152 sured and show the results of 16 kHz switching frequency and
0.000306 0.000152 1. 950617 0.951227. 1 s dead-band in Fig. 7(b). When the experimental system is
To verify the correctness of SVPWM generation function in serially connected to a RC circuit with 10 resistor and 47 f
Fig. 1, an experimental block diagram is constructed in Fig. 7(a). capacitor, the results show the measured PWM1 and PWM3 as a
The input signal is set to a constant voltage and the is set saddle waveform in Fig. 7(c). Furthermore, to validate the effec-
to zero in Fig. 7(a), then PWM1–PWM6 outputs can be gen- tiveness of the current vector control in Fig. 1, the input current
erated through the transformation of inverse Park, modified in- command, is set, and the measured currents
verse Clarke and SVPWM. When the experimental system is of and corresponding currents in - - axes are shown in
2484
Fig. 10. Step response of rotor speed and control effort operated at 0–300 rpm
square wave command and 1.2 N*m load torque under case of (a) without adap-
tation, (b) with adaptation by learning rate 0.05, and (c) with adaptation by
learning rate 0.1.
Fig. 8. The load torque of brake is set to 2 N*m. In Fig. 8, the re-
sults present that the measured current tracks current command
perfectly. The experimental results validate the success of cur-
rent vector control, and will make the PMSM decouple.
Having confirmed the effectiveness of the current vector
control, the dynamic performance of PMSM drive is evaluated
while the adaptive fuzzy controller is applied in speed control
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007
Fig. 11. Frequency response of a 2 Hz sinusoid input signal with 1.0 N*m load
torque under using the (a) fuzzy controller and (b) adaptive fuzzy controller.
loop of Fig. 1. The step response under two tested cases is first
evaluated. The first case is motor running at the light-load con-
dition that the amplitude of speed command is 1200–1500 rpm
square wave and the external load torque is 0.2 N*m. The
second case is motor running at the heavy-load condition that
the amplitude of speed command is 0–300 rpm square wave
and the external load torque is 1.2 N*m. In addition, the per-
formance of using different control laws by PI controller only,
PID type fuzzy controller and the proposed adaptive fuzzy
controller are compared. At the light-load condition, when the
PI controller (PI gains: 0.61 and 0.015) is only
used in the speed loop of Fig. 1, the step response is shown
in Fig. 9(a). It reveals a bad tracking result with overshoot
and oscillation. However, when the fuzzy controller is serially
connected to the PI controller (called PID type fuzzy controller)
in Fig. 1, the experiment is done again and the step response is
also shown in Fig. 9(a). It is obvious that although the dynamic
is improved in Fig. 9(a) by using the PID type fuzzy controller,
the rotor speed is still can’t follow the output of the reference
model. However, when the proposed adaptive fuzzy controller
is presented in Fig. 1, and the learning rate are chosen by 0.05
or 0.1, its tracking results are highly improved and presented in
Fig. 9(b) and (c). At initial, the rotor speed tracks the output of
KUNG AND TSAI: FPGA-BASED SPEED CONTROL IC
Fig. 12. Frequency response of a 2 Hz sinusoid input signal with 2.0 N*m load
torque under using the (a) fuzzy controller and (b) adaptive fuzzy controller.
reference model with oscillation; at the meanwhile, the param-
eters of fuzzy controller are tuned toward reducing the error,
which is the output of the reference model and the rotor speed,
at each control sampling interval. After one or two square
wave command tracking, the parameters of fuzzy controller
are tuned to an adequate value, and the actual rotor speed can
get a good following with the output of the reference model.
Similarity, the proposed adaptive fuzzy controller demonstrates
the same adaptation ability at heavy-load condition, and the
tracking results are shown in Fig. 10. Secondly, the frequency
response is considered to evaluate the performance of the
proposed controller. A tested input signal of the sinusoid wave
with 1,350 150 rpm amplitude and a frequency of 2 Hz under
different load torque by 1.0N*m and 2.0N*m are provided. In
this design, the frequency tracking response and the tracking
error of the PMSM without and with adaptation are shown in
Figs. 11 and 12. In the case of light-load torque with 1.0N*m,
it reveal that the 20 rpm amplitude tracking error obtained
by using the adaptive fuzzy controller (learning rate 0.1) is
better than the 34 rpm tracking error obtained by only using
the fuzzy controller in Fig. 11(a) and (b). Similarly, in the case
of heavy-load torque with 2.0 N*m, although the tracking error
2485
with 62 rpm in Fig. 12(a) is worsen than the case of light-load
torque by only using the fuzzy controller, the rotor speed can be
tuned to the same 20 rpm amplitude tracking error after using
the adaptive fuzzy controller (learning rate 0.1) in Fig. 12(b).
Therefore, the experimental results in Figs. 7–12 demonstrate
that the proposed FPGA-based speed control IC for PMSM
drive is correctness and effectiveness.
IV. CONCLUSION
A speed control IC for PMSM drive based on the novel FPGA
technology is successfully demonstrated in this paper. First, a
vector control in the current loop of the PMSM drive is used
to decouple the nonlinear and coupled characteristics of PMSM
and an adaptive fuzzy controller in the speed loop of the PMSM
drive is applied to cope with the dynamic uncertainty and ex-
ternal torque effect. Secondly, a speed control IC based on an
FPGA and a Nios II embedded processor is designed to realize
the aforementioned control algorithms for ensuring high perfor-
mance. The current vector control algorithm is implemented by
hardware in FPGA and the adaptive fuzzy controller algorithm
is implemented in software by using Nios II embedded pro-
cessor. Therefore, all functionalities, which are based on soft-
ware/hardware co-design, required to build a fully digital speed
control for PMSM drive have been integrated in one FPGA chip.
In addition, a finite state machine (FSM) method is also pre-
sented in this paper, and given the results that the total resource
usages save 2 795 LEs of FPGA in the overall circuits. Com-
pared with DSP, using FPGA in the proposed control architec-
ture has two benefits, which are described as follows.
1) Current controller implemented by hardware and speed
controller implemented by software can all be pro-
grammable design. Therefore, the flexibility of designing
a specified function of PMSM drive is greatly increased.
2) Parallel processing of current loop vector controller and
speed loop adaptive controller makes the dynamic perfor-
mance of the PMSM drive improvable.
Finally, the performance of the proposed controller is val-
idated by the experimental results of the step and frequency
command responses. In the test of the step command response,
the adaptive fuzzy controller used in the speed loop of the
PMSM drive, compared with the PI controller and fuzzy
controller, is demonstrated to be the best tracking result at the
prescribed dynamic response under the different external load
condition.
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Ying-Shieh Kung (M’03) was born in Taiwan,
R.O.C., in 1957. He received the B.S. degree in
aeronautical engineering from National Cheng
Kung University, Tainan, Taiwan, in 1980, the M.S.
degree in mechanical engineering from National
Taiwan University, Taipei, Taiwan, in 1982, and the
Ph.D. degree in power mechanical engineering from
National Tsing Hua University, Hsinchu, Taiwan, in
1993.
From 1983 to 1996, he was an Engineer and fo-
cused on the research in the field of automatic con-
trol of machine system at the Industrial Technology Research Institute, Hsinchu.
Since 1996, he has been an Associate Professor with the Department of Elec-
trical Engineering, Southern Taiwan University (STU), Tainan. He is currently
a Professor at STU. His areas of research interest are controller design for ac
motor drives and linear motor drives, robot control, intelligent control, and dig-
ital control using the DSP and FPGA implementations.
Ming-Hung Tsai was born in Taipei, Taiwan,
R.O.C., in 1978. He received the B.S. degree in
electrical engineering from Minghsin University of
Science and Technology, Hsinchu, Taiwan, in 2001
and the M.S. degree in electrical engineering from
Southern Taiwan University, Tainan, Taiwan, in 2004
where he is currently pursuing the Ph.D. degree.
His research interests are in the areas of ac motor
control, fuzzy control, FPGA controller realization,
and FPGA-based control ICs for motor drives.