Asynchronous vs.

Synchronous Timing

Muhammad Wasiur Rashid

Overview
„ Issues distinguishing synchronous and asynchronous
timing
„ Comparison of some real life circuits
„ Adder comparison

„ Microprocessor comparison

„ Globally asynchronous locally synchronous systems

„ Summary
Introduction

„ Synchronous: Circuits that use a clock to separate

consecutive system states from one another.

„ Asynchronous: Circuits that define states in terms

of input value and internal action.
„ Asynchronous timing is event driven
„ Completion logic and Handshaking signals are used to
identify separate events
Overview

„ Issues distinguishing synchronous and asynchronous

timing
„ Comparison of some real life circuits
„ Adder comparison

„ Microprocessor comparison

„ Globally asynchronous locally synchronous systems

„ Summary
Issues Distinguishing Synchronous and
Asynchronous Timing

„ Clock
„ Average vs. worst case delay
„ Power consumption
„ Noise and electromagnetic compatibility
„ Handshaking and completion detection overhead
„ Complexity of design
 Clock

„ Global clock synchrony becoming harder to attain [1, 4, 18]

„ high clock speed
„ large chip size
„ large systems
„ Asynchronous circuits avoid clock distribution problem
„ Clock skew and jitter impact performance, functionality of
sequential circuits
Clock Period, T ≥ tc-q + tlogic + tsk - δ + 2tjitter , δ is the clock skew
„ Clock design is a major time, power budget and chip area drain
[4]
Average vs. Worst Case Delay

„ Average length of carry-propagation chain log2N [4]

„ For synchronous, clock period at least equal to worst
case
„ Completion detection and handshaking overheads
 RAPPID [17]

„ Large data dependent variation in delay

„ RAPPID (Revolving Asynchronous Pentium
Processor Instruction Decoder)
„ Research by Intel
„ 3 times better performance then
the synchronous decoder in 400
MHz Pentium-II processor
 Power Consumption

„ 40% of the total power of modern Synchronous

Processor is consumed by the clock network [11]
„ ‘On demand’ power consumption [4]
„ Clock gating
„ Asynchronous more efficient
when (Clock Rate > Data Rate)
 Noise and EMC [4]

„ Significant current flow over very short period of time

„ Noise due to
„ Burst of current
„ package inductance
„ power supply grid resistance
 Handshaking and Completion Detection

„ Handshaking and completion detection logic comes at the

expense of area, speed and power dissipation

B B0 B1
In transition 0 0
0 0 1
1 1 0
illegal 1 1

Redundant signal representation to include transition state

Complexity of Design

„ Manual design of asynchronous circuit

„ Difficult
„ Error prone
„ Can result in
„ Race conditions
„ Hazards
„ Synchronous design
„ Better understood
„ Process is more mature
Resource Utilization [23]

„ Asynchronous microprocessors require less resources

(ALU, Reservation Station)

1-station and 6-station model 1-ALU and 2-ALU models

 Overview
„ Issues distinguishing synchronous and asynchronous
timing
„ Comparison of Some Real Life Circuits
„ Adder Comparison

„ Microprocessor Comparison

„ AMULET
„ ARM
„ MiniMIPS
„ ALPHA
„ TATIC-2
„ Globally asynchronous locally synchronous systems
„ Summary
Adder Circuit Comparison [14]

„ Comparisons are made between 32 bit

„ Synchronous static ripple carry adder (RCA)
„ Asynchronous dynamic adder (ADA)
„ Synchronous dynamic adder (SDA)
„ Synchronous static Manchester ALTAS adder (ATLAS)
Power Analysis of AMULET [8]

„ High performance asynchronous ARM processor

„ Developed by the 'Advanced Processor Technologies Group' at the University of
Manchester

Processor power breakdown

AMULET core power consumption

AMULET vs. ARM [8]

„ 26% power of ARM is used in clock

„ Handshaking circuit used 10.5% of the total power
consumed by the core of AMPLET
„ Other overheads of AMULET
„ Lack of synchronization at different stages of the pipeline
results in duplication of information
„ Fine grain control circuit leads to existence of extra states
„ AMULET 1100 MIPS/W
„ 0.35 µm ARM9 => 120 MHz, 800MIPS/W
 MiniMIPS [15, 16]

„ Developed at Caltech
„ E * t2 metric
R3000 1.2µ 25MHz

R3000A 1.2µ 33MHz

VR3600 1.2µ 40MHz

R3000 0.6µ 47MHz

MiniMIPS 0.6µ 177MHz

Performance of MiniMIPS compared to R3000

Comparing MiniMIPS [15]
The Alpha Processor [11]
 TATIC-2 [24]

„ Full-featured 32-bit architecture that uses delay

scaling
„ Developed jointly by group at Tokyo Institute of
Technology and Tokyo University
 Other Asynchronous Processors [6]
„ Phillips Asynchronous 80C51: Microcontroller that
exhibits 4 times less power and significant less EM
emission compared to its Synchronous counterpart
„ Sharp DDMP Signal Processor: Operates at 8600
operations per second with less than 1 watt power
consumption
„ The Fred Architecture: It is a self-timed,
decoupled, pipelined, out-of-order architecture
Power and Speed Comparison [15]
 Overview

„ Issues distinguishing synchronous and asynchronous

timing
„ Comparison of some real life circuits
„ Adder comparison

„ Microprocessor comparison

„ Globally asynchronous locally synchronous systems

„ Summary
 Globally Asynchronous Locally
Synchronous Systems [1]

GALS

„ Delay due to synchronizers vs. clock skew

GALS Timing Analysis [1]

„ Curve suggests the use of two levels of granularity for VLSI

systems
„ At a finer level synchronous scheme to exploit higher rate
„ At a coarser level asynchronous scheme
 Interconnection Network [20]

„ In a multiprocessor connection network, the

condition under which GALS data rate is greater than
synchronous data is given by
δ/d > 2( k-1 ) + dp/d
„ If δ is high GALS design is better, if dp is high
synchronous design is better
„ Ideal network has to be modular and expandable,
pointing to the use of GALS scheme
 Summary

„ Distributing a clock at high speed becoming

exceedingly difficult
„ Asynchronous timing circuits will gain popularity
„ No asynchronous revolution, but a steady evolution
„ Globally-asynchronous locally-synchronous approach
most promising
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