Krishna Institute of Management & Technology, Moradabad

2nd Sessional Examination (Odd Semester)2010-2009

Subject: Digital Logic Design Time Duration: 1.30 Hrs.

Subject Code: ECS-301 Max marks: 15
Branch / Section : CSE–IT / A-C

Note: Attempt any five Questions. (5X3)

Q1: Convert the RS flip flop to JK flip flop.

Q2: Derive the state table and state diagram for the sequential circuit shown in the figure below

Q3: A sequential circuit has one input and one output and its state diagram is shown in figure below
.Derive the sequential circuit using D flip flop.

Q4: Design Mod 4 counter using JK flip flop and implement it.
Q5: A Combinational circuit is define by the function s
F1= ∑m (1,5,7)
F2= ∑m(5,6,7)
Implement the circuit with a PLA.
Q6: Implement the following boolean expression using ROM.
F1(ABC) = ∑m(0,2,4,7) and F2(ABC)= ∑m(1,3,5,7).
Q7: Define a 4 bit shift register. Explain modes of operations of shift registers.

~~~~~~~~~~~(Best of Luck)~~~~~~~~~~~