ECOC 2010, 19-23 September, 2010, Torino, Italy
Integrated PAM2 Decision Feedback Equalizer for Gigabit
Ethernet over Standard SI-POF using red LED
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C. Zerna , J. Sundermeyer , A. Fiederer , N. Verwaal , B. Offenbeck , N. Weber
(1)
Fraunhofer Institute for Integrated Circuits, Erlangen, Germany, conrad.zerna@iis.fraunhofer.de
Abstract We present an integrated equalizer used for electronic dispersion compensation in the 1mm
SI-POF home-networking scenario applying 650nm RCLED and SI-PIN-PD. Real-time experimental
results demonstrate that the approach gives better BER performance then to date published with
competing architectures.
Introduction
The 1mm large core step-index Polymethyl
methacrylate (PMMA) plastic optical fiber (SI-
POF) has been a popular data communication
medium for several years (e.g. since 2000 in the
automotive MOST [4]). Its popularity stems from
its many usability advantages: As an optical
medium, it is immune to electro-magnetic
interference. Its large diameter allows for
impureness and misalignment of the boundary
surface and the rugged plastic material also
contributes to an overall ease of installation. In
the home networking environment, two
additional advantages contribute to the appeal
of the SI-POF: Firstly, the fiber can be
terminated by use of a razorblade cutter and
used in a connector-less fashion (Firecomms
Optolock). And secondly, the PMMA SI-POF
has its attenuation minima in the visible
spectrum and hence the link can be debugged
by visual inspection.
The SI-POF is being commercially used in the
MOST system at speeds up to 150Mbit/s and in
industry and home networking at speeds up to
100Mbit/s with LEDs. There are also commercial
links for Gigabit Ethernet, which are using laser
diodes and are constrained to shorter fiber
reaches. Those current speed/distance
limitations stem from the drawbacks of the SI-
Fig. 1: Typical impulse response of a SI-POF link
shorter than 50m. Characteristic is the shorter pre-
cursor ISI compared to the longer post-cursor ISI.
978-1-4244-8535-2/10/$26.00 ©2010 IEEE
We.6.B.
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POF, namely its attenuation and multi-mode
propagation, which lead to lower SNR and
distortion at the receiver. The EU-Project POF-
PLUS ([1]) is dedicated to the development of
an engineering solution for Gigabit Ethernet over
50m using practical low-cost components. Such
desirable low-cost components are RCLEDs
(resonant cavity light emitting diodes) and PIN
photo diodes. Because of the multi-mode
propagation and the need for simplicity of
hardware, only intensity modulation, direct
detection systems (IM-DD) are being considered
as an option. To overcome the drawbacks of the
plastic optical fiber, more sophisticated signal
processing approaches in the electrical domain
are being explored. An investigation of more
complex modulation formats in conjunction with
equalizing has already been conducted within
the forum of the project. It concluded that PAM2
(pulse amplitude modulation) and PAM4
delivered comparable performance on the SI-
POF channel. Modulation formats with a higher
number of levels showed no benefit. Similar
investigations have been conducted previously
for the scenario of sophisticated modulation
formats without equalization (see [5]).
This paper presents an integrated equalizer
solution. We chose the PAM2 modulation format
for the advantage of ease of implementation and
the higher immunity to nonlinearities in the
channel and electronics. The presented results
were obtained with the first test chips for a more
sophisticated equalizing architecture. We will
show that PAM2 in conjunction with equalization
outperforms the DMT (discrete multi-tone)
approach on the SI-POF link.
POF Channel Characteristics
The large diameter PMMA SI-POF as a
communication medium has the disadvantage of
optical attenuation and multi-mode propagation.
The optical attenuation leads to less signal at
the receiver and hence a degradation of the
SNR. The multi-mode propagation furthermore
reduces the signal power and introduces

frequency selective attenuation or spreading of
the signal in the time domain. This causes inter-
symbol-interference (ISI) and has to be
compensated for. A typical SI-POF channel for
the length of interest (up to 50m) and the net
target data rate of 1.25 Gbit/s introduces a
smaller portion of pre-cursor ISI and a larger
portion of post-cursor ISI (see Fig. 1).
Architecture of Equalizer
The work on the presented architecture was
preceded by the implementation of a fully
analogue solution (see [2]). The experiments on
this solution pointed out its shortcomings: Firstly,
the limited control over the transfer function only
allowed equalizing a limited subset of channels.
And secondly, the enhancement of the noise on
the signal through the equalizing filter also
limited the achievable performance.
To overcome these shortcomings, we decided to
move to a mixed-signal architecture for the
equalizer as depicted in Fig. 2 (Box “Equalizer”).
It consists of an analogue filter (HP) in the
forward path as it was used in the previous
approach. However, the equalizer has been
extended by a discrete-time filter in the feedback
path. This filter receives the decided symbol as
input and is hence called a decision-feedback-
equalizer (DFE). A variable gain amplifier (VGA)
acts as the preamplifier (or forward tap) for the
DFE. It is placed in front of the HP for best
signal quality.
The advantages of the DFE are the following:
Firstly, its finite-impulse response (FIR) filter
2

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structure allows for a much more refined control
of the transfer function than an analogue filter
does. Secondly, a filter in the feedback path is
known to amplify noise on the signal much less
then a filter in the forward path. However the
forward filter is still necessary, because a DFE
can only compensate for post-cursor ISI (see
Fig. 1). The pre-cursor ISI has to be mitigated by
the analogue peaking filter/high pass. With the
new mixed-signal architecture, we address both
shortcomings of the fully analogue architecture
while still maintaining relatively low power
consumption.
Implementation
The chosen architecture has been allocated to
three separate chips: a variable gain amplifier
(VGA), an analogue tuneable high-pass filter
(HP), and the DFE. It is thus possible to test
each chip on its own or combine them into the
mixed-signal equalizer architecture. The VGA
acts as the only forward tap of DFE portion; this
tap is necessary to maintain a constant
amplitude level for the equalized signal. The
VGA is controlled via an analogue voltage. The
HP is set via a 5-bit digital control word and can
deliver a boost of 20dB electrical amplitude at
higher frequencies. The transfer function is
controlled by the size of a source degeneration
capacitor of a differential amplifier. In first
approximation, it is a one-zero, two-pole transfer
function. The DFE features five feedback taps
with continuously settable coefficients. It
samples the symbol and the sign of the error at

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Fig. 2: Architecture of the equalizer broken down to the level of implemented chips and shown in the laboratory
setup. The HP is controlled by hand, the VGA and DFE is controlled by the automatic coefficient adaption loop
consisting of real-time oscilloscope, PC and a programmable voltage source.

the internal summing node and outputs them.
The implementation has been done in the
180nm CMOS technology of UMC.
Lab Setup and Experimental Results
Our laboratory setup is depicted in Fig. 2. We
used the following components: a Fraunhofer IIS
developed LED driver (see [3]) with a
Firecomms red (650nm) RCLED, 25m or 50m of
the Asahi TC-1000 1mm SI-POF and an optical
lab receiver (Hamamatsu S5052 800um PIN
photo diode with 3mm lens and 28V reverse
bias, Maxim 3266 TIA). The output of the optical
receiver was fed to the chain of equalizer chips.
The HP control word, which sets the peaking,
was set by hand. The combination of VGA and
DFE was controlled via the combination of a
real-time oscilloscope (for recording symbol and
error signal), a PC (for running the adaption
algorithm) and a programmable voltage source
(for feeding back the coefficient values). The
adaption loop of the VGA and DFE is fully
automated. Only the phase of the sampling
clock in the DFE had to be adjusted by hand.
This is due to the momentary nonexistence of a
CDR (clock and data recovery) circuit.
We were able to achieve a BER of less than
-13
10 for 25m of POF and a BER of less than
-6
10 for 50m of POF (both at room temperature).
The accumulated BER result for transmission
over 50 m can be seen in Fig. 3. The adaption
loop runs on a much slower speed than the bit
rate, because it is limited by the laboratory
hardware.
Further Development
The current mixed-signal architecture has
recently been integrated monolithically on one
chip. We refined parts of the circuitry and
optimized the interaction between the single
stages of the equalizer. A CDR was also added
to the DFE. We expect to achieve error-free
-12
(BER < 10 ) 1.25Gbit/s transmission over 50m
of SI-POF with RCLED for an extended
temperature range.
Although the addition of the DFE improved the
performance of the equalizer considerably, the
shortcoming of the limited control over the
forward filter transfer function is still standing.
This lack of precise control, especially the
existing correlation between high frequency
peaking and overall bandwidth, proved to be a
performance-limiting factor during our laboratory
experiments. For this reason, we decided to
move to an even more sophisticated
architecture and replace the analogue forward
filter with an FFE (feed-forward-equalizer). The
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Fig. 3: Accumulated BER results for the 50m SI-POF
link. The upper left corner shows the current BER. The
accumulated BER is shown in the text window at the
bottom in the line ‘Error Ratio’.
design work on this architecture is in progress
and results are to be expected in the second
half of 2010.
Conclusion
We presented the architecture of an integrated
mixed-signal equalizer for SI-POF home
networking links developed inside the EU project
POF-PLUS ([1]). Experiments were conducted
using the first test chips for this equalizer
solution. We showed successful transmission of
1.25Gbit/s net data rate on a link of red (650nm)
RCLED and 50m of SI-POF. In the case of FEC
(forward error correction) usage, the
transmission is to be considered error-free. This
is the best published result to date (to the best
knowledge of the authors) for 50m SI-POF using
RCLED in a real-time experiment (see [6], see
[7] for offline results).
The integration of the current architecture will
most probably yield a natively (without FEC)
error-free transmission for the 50m over a wider
temperature range. The migration to the
FFE+DFE architecture will make even longer
lengths possible.
References
1 POF-PLUS (http://www.ict-pof-plus.eu)
2 J. Sundermeyer et al, Proc. LEOS '09. IEEE
TuI2 (2009)
3 B. Offenbeck et al, Proc. ICPOF’09 PS104
(2009)
4 MOST – media oriented systems transport
(http://www.mostcooperation.com)
5 S. Randel et al, Proc. OFC’08 OWR2 (2008)
6 F. Breyer et al, Proc. ECOC’08 We2A3 (2008)
7 F. Breyer et al, Proc. ECOC’07 paper 9.9.6
(2007)