Lecture Contents

Lecture 01 1. Introduction to Digital Systems

2. Review of Basic Concepts
 

Lecture 02 1. Introduction to Verilog HDL

1. Gate Level Modeling
2. Test bench

Lecture 03  Introduction to ModelSim

 Simulations of Gate Level designs
 Timing diagrams
 

Lecture 04  Data flow modeling

 Continuous Assignment,
 Port Assignments,
 Operators (Logical, Bitwise, Reduction, Shift,
Concatenation, Relational, Equality, Conditional, Arithmetic)
 

Lecture 05  Behavioral Modeling,

 Procedural Blocks (initial, always)
 Blocking & Non-Blocking Assignments,
 Clock & Async / Sync Reset in Digital System Events,
 Combinatorial Statements, Timing Analysis ,Delays
 
Lecture 06  Simulations of Data Flow and Behavioral Models in ModelSim
 Examples

Lecture 07  Synthesis of Combinational Logic

Lecture 08  Synthesis of Sequential Logic

Lecture 09  Digital Systems, State Machine Concept,

 Moore & Mealy State Machines based Design
 State machine based Traffic Controller

Lecture 10  Xilinx ISE Tools

 FPGA Implementation
 Real world applications
 State machine based systems
 A simple RISC processor implementation using Verilog HDL