Digital System Design

Homework #1
(Due on 03/17 PM 8:00)
Note: Please hand in the hardcopy of this experiment including
a. Verilog Codes (50%)
b. Test bench (20%)
c. Input/Output waveforms.(30%)
In the following experiments, we will find a more efficient way to hand in the
experimental report.

1. For those even-numbered students,

Fig. 1 J-K flip-flop

a. Please use Verilog to describe the digital circuits in Fig. 1.

b. Write a test bench to test your design.
c. The input waveforms are given as the following patterns. For students with
lab. time on Tuesday, the initial state of Q is 1. For students with lab. time on
Thursday, the initial state of Q is 0.

Fig. 2 J-K flip-flop test pattern

2. For those odd-numbered students,

D Q Q
N

CLK

Reset

Fig. 3 P-N flip-flop

a. Please use Verilog to describe the digital circuits in Fig. 3.

b. Write a test bench to test your design.
c. The input waveforms are given as the following patterns. For students with
lab. time on Tuesday, the initial state of Q is 1. For students with lab. time on
Thursday, the initial state of Q is 0.

Fig. 4 P-N flip-flop test pattern

Hint: Flip-flop code example

reg Q; 
always@(posedge CLK or negedge Reset ) 
begin 
if (!Reset) Q<=1’b0; 
else Q<=D ; 
end