System on Chip Laboratory, NCTU

VLSI Lab5
I. Design a 4-bit Wallace Tree Multiplier
A. Figure 1a is a structure of Wallace tree and figure 1b is the reference schematic. You can
simplify the circuit. Make sure inputs and outputs are added buffers as loading.

Figure 1a. Structure of Wallace tree

Figure 1b. 4-bit Wallace Tree Multiplier

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a0_b a0 b0_b b0 P0 P0_b P4 P4_b

a1_b a1 b1_b b1 P1 P1_b P5 P5_b

a2_b a2 b2_b b2 P2 P2_b P6 P6_b

a3_b a3 b3_b b3 P3 P3_b P7 P7_b

B. Show a waveform to verify your design. (set the input as below)

➢ Measure 𝒕𝒅𝒆𝒍𝒂𝒚,𝒂𝟑→𝑷𝟕 at the time which Pattern 1 changes to Pattern 2.

➢ tdelay = 0ns and tperiod (Change to next Pattern) = 50ns

➢ Rise time = 1ns, Fall time = 1ns

Pattern a3_b a2_b a1_b a0_b b3_b b2_b b1_b b0_b Repeat 1 times.
1 0 0 1 1 1 1 1 1
2 1 0 1 1 1 1 1 1
3 0 1 0 0 0 0 0 0
4 1 1 0 0 0 0 0 0

II. Design a 4-bit Array Structure Multiplier, using carry ripple adder
A. Figure 2 is reference schematic. You can simplify the circuit. Make sure inputs and
outputs are added buffers as loading.

Figure 2. 4-bit array structure multiplier

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a0_b a0 b0_b b0 P0 P0_b P4 P4_b

a1_b a1 b1_b b1 P1 P1_b P5 P5_b

a2_b a2 b2_b b2 P2 P2_b P6 P6_b

a3_b a3 b3_b b3 P3 P3_b P7 P7_b

B. Show a waveform to verify your design. (set the input as below)

➢ Measure 𝒕𝒅𝒆𝒍𝒂𝒚,𝒂𝟑→𝑷𝟕 at the time which Pattern 1 changes to Pattern 2.

➢ tdelay = 0ns and tperiod (Change to next Pattern) = 50ns

➢ Rise time = 1ns, Fall time = 1ns

Pattern a3_b a2_b a1_b a0_b b3_b b2_b b1_b b0_b Repeat 1 times.

1 0 0 1 1 1 1 1 1
2 1 0 1 1 1 1 1 1
3 0 1 0 0 0 0 0 0
4 1 1 0 0 0 0 0 0

III. Questions of this lab

Compare two types of multiplier, show their advantages and disadvantages.

IV. Grading Policy

➢ You can decide the transistor size of your design.
➢ Metal 3 ~ Metal 6 are forbidden to use in this lab.
A. 4-bit Wallace Tree Multiplier: 85%
1. Pre-sim waveform: 20%
2. DRC & LVS: 20%
3. Post-sim waveform: 20%
4. Performance: 25%
⚫ 𝑡𝑑𝑒𝑙𝑎𝑦,𝑎3→𝑃7 take for maximum
𝐹𝑖𝑔𝑢𝑟𝑒 𝑜𝑓 𝑀𝑒𝑟𝑖𝑡 (𝐹𝑜𝑀) = 𝑡𝑑𝑒𝑙𝑎𝑦,𝑎3→𝑃7 × 𝐴𝑟𝑒𝑎 × 𝑃𝑜𝑤𝑒𝑟
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B. [BONUS] 4-bit Array Structure Multiplier: 20%
1. Pre-sim waveform: 6%
2. DRC & LVS: 4%
3. Post-sim waveform: 6%
4. Performance: 4%
⚫ 𝑡𝑑𝑒𝑙𝑎𝑦,𝑎3→𝑃7 take for maximum
𝐹𝑖𝑔𝑢𝑟𝑒 𝑜𝑓 𝑀𝑒𝑟𝑖𝑡 (𝐹𝑜𝑀) = 𝑡𝑑𝑒𝑙𝑎𝑦,𝑎3→𝑃7 × 𝐴𝑟𝑒𝑎 × 𝑃𝑜𝑤𝑒𝑟
C. Report: 15% + [BONUS] 5%
1. Question: 5%
2. Wallace tree multiplier: 10%
➢ Layout screenshot with ruler: 4%
➢ Post-sim waveform & measure delay: 6%
3. [BONUS] Array structure multiplier: 5%
➢ Layout screenshot with ruler: 2%
➢ Post-sim waveform & measure delay: 3%

V. Demo time: 12/21 (Wed.) 15:30 ~ 18:20

You have only “one” chance to demo!
After deadline, any requests for demo are denied.

VI. Report hand-in deadline: ~12/26 (Mon.) 23:59 on New E3

After deadline, any requests for handing in report are denied.

VII. Appendix
Power measurement by Hspice
.tran 0.1n 400n
.meas tran total_cur integ par('-i(vvdd)')
.meas tran total_pwr param='1.8*total_cur'
where “vvdd” is element name of power supply.

How to use inv.sp after PEX in Lab1

※ Notice circuit pins’ order in Lab1
.include 'inv.pex.netlist.sp'
x1 Y Y1 VDD VSS inv
x2 Y1 Y2 VDD VSS inv

Y Y1 Y2