IMPLEMENTATION OF CYCLIC REDUNDANCY CHECK

(CRC4) USING VHDL ON FPGA

The below is the code for CRC4 using VHDL. This was also
implemented on FPGA (Spartan 3). Here the data taken is 4bits.
The code can be modified for any number of data bits.
Correspondingly the length of the array should also be varied.

CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity crc1 is
port(data_in:in std_logic_vector(3 downto 0);
poly:in std_logic_vector(4 downto 0):="10011";
crc:out std_logic_vector(3 downto 0));
end crc1;

architecture Behavioral of crc1 is

signal data_in1:std_logic_vector(7 downto 0):="00000000";
begin
process(data_in1)
variable r1:std_logic_vector(4 downto 0):="00000";
begin
data_in1 <= data_in & "0000";
if(data_in1(7)='0') then
r1:=data_in1(7 downto 3) xor "00000";
else
r1:=data_in1(7 downto 3) xor poly;
end if;

for i in 2 downto 0 loop

r1:=r1(3 downto 0) & data_in1(i);
if(r1(4)='0') then
r1:= r1 xor "00000";
else
r1:= r1(4 downto 0) xor poly;
end if;
end loop;
crc<= r1(3 downto 0);

end process;

end Behavioral;