Procesorul Z80 Manual - Eng

Z80 Family
CPU User Manual
User Manual
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This publication is subject to replacement by a later edition. To determine whether a later

edition exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters

910 E. Hamilton Avenue
Campbell, CA 95008
Telephone: 408.558.8500
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ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products
and/or service names mentioned herein may be trademarks of the companies with which they are associated.
©2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
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information, devices, or technology as critical components of life support systems is not authorized. No
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Table of Contents
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This user manual describes the architecture and instruction set of the Z80
CPU.
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ZiLOG recommends that the user read and understand everything in this
manual before setting up and using the product. However, we recognize
that users have different styles of learning: some will want to set up and
use their new evaluation kit while they read about it; others will open
these pages only to check on a particular specification. Therefore, we
have designed this manual to be used either as a how to procedural
manual or a reference guide to important data.
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This document is written for ZiLOG customers who are experienced at
working with microprocessors or in writing assembly code or compilers.
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The Z80 CPU User’s Manual is divided into four chapters.
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Presents an overview of the User’s Manual Architecture, Pin descriptions,
timing and Interrupt Response.
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Presents examples of the User’s Manual hardware and software.
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Presents the User’s Manual instruction types, addressing modes and
instruction Op Codes.
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Presents an overview of the User’s Manual assenbly language, status
indicator flags and the Z80 instructions.
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The following assumptions and conventions are adopted to provide clarity
and ease of use:
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The words set and clear imply that a register bit or a condition contains
the values logical 1 and logical 0, respectively. When either of these
terms is followed by a number, the word logical may not be included, but
it is implied.
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A field of bits within a register is designated as: Register (n–n). For
example: PWM_CR (31–20). A field of bits within a bus is designated as:
Busn–n. For example: PCntl7–4. A range of similar (whole) registers is
designated as: Registern–Registern. For example: OPBCS5–OPBCS0.
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In this document, the terms LSB and MSB, when appearing in upper case,
mean least significant byte and most significant byte, respectively. The
lowercase forms, msb and lsb, mean least significant bit and most
significant bit, respectively.
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Commands, code lines and fragments, register (and other) mnemonics,
values, equations, and various executable items are distinguished from
general text by the use of the Courier font. This convention is not used
within tables. For example: The STP bit in the CNTR register must be 1.
Where the use of the font is not possible, as in the Index, the name of the
entity is presented in upper case.
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Hexadecimal values are designated by a uppercase H and appear in the
Courier typeface. For example: STAT is set to F8H.
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The use of all uppercase letters designates the names of states and
commands. For example: The receiver can force the SCL line to Low to
force the transmitter into a WAIT state. The bus is considered BUSY after
the Start condition. A START command triggers the processing of the
initialization sequence.
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Initial uppercase letters designate settings, modes, and conditions in
general text. For example: The Slave receiver leaves the data line High. In
Transmit mode, the byte is sent most significant bit first. The Master can
generate a Stop condition to abort the transfer.
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Register access is designated by the following abbreviations:
Designation Description
R Read Only
R/W Read/Write
W Write Only
– Unspecified or indeterminate
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The ZiLOG Z80 CPU family of components are fourth-generation
enhanced microprocessors with exceptional computational power. They
offer higher system throughput and more efficient memory utilization
than comparable second- and third-generation microprocessors. The
speed offerings from 6–20 MHz suit a wide range of applications which
migrate software. The internal registers contain 208 bits of read/write
memory that are accessible to the programmer. These registers include
two sets of six general purpose registers which may be used individually
as either 8-bit registers or as 16-bit register pairs. In addition, there are
two sets of accumulator and flag registers.
The Z80 CPU also contains a Stack Pointer, Program Counter, two index
registers, a REFRESH register, and an INTERRUPT register. The CPU is
easy to incorporate into a system since it requires only a single +5V
power source. All output signals are fully decoded and timed to control
standard memory or peripheral circuits; the Z80 CPU is supported by an
extensive family of peripheral controllers.
Figure 1 illustrates the internal architecture and major elements of the
Z80 CPU.
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The Z80 CPU contains 208 bits of R/W memory that are available to the
programmer. Figure 2 illustrates how this memory is configured to
eighteen 8-bit registers and four 16-bit registers. All Z80 registers are
implemented using static RAM. The registers include two sets of six
general-purpose registers that may be used individually as 8-bit registers
or in pairs as 16-bit registers. There are also two sets of accumulator and
flag registers and six special-purpose registers.
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The program counter holds the 16-bit address of the current instruction
being fetched from memory. The PC is automatically incremented after its
contents have been transferred to the address lines. When a program jump
occurs, the new value is automatically placed in the PC, overriding the
incrementer.
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The stack pointer holds the 16-bit address of the current top of a stack
located anywhere in external system RAM memory. The external stack
memory is organized as a last-in first-out (LIFO) file. Data can be pushed
onto the stack from specific CPU registers or popped off of the stack to
specific CPU registers through the execution of PUSH and POP instructions.
The data popped from the stack is always the last data pushed onto it. The
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stack allows simple implementation of multiple level interrupts, unlimited

subroutine nesting and simplification of many types of data manipulation.
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The two independent index registers hold a 16-bit base address that is
used in indexed addressing modes. In this mode, an index register is used
as a base to point to a region in memory from which data is to be stored or
retrieved. An additional byte is included in indexed instructions to specify
a displacement from this base. This displacement is specified as a two’s
complement signed integer. This mode of addressing greatly simplifies
many types of programs, especially where tables of data are used.
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The Z80 CPU can be operated in a mode where an indirect call to any
memory location can be achieved in response to an interrupt. The I
register is used for this purpose and stores the high order eight bits of the
indirect address while the interrupting device provides the lower eight bits
of the address. This feature allows interrupt routines to be dynamically
located anywhere in memory with minimal access time to the routine.
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The Z80 CPU contains a memory refresh counter, enabling dynamic
memories to be used with the same ease as static memories. Seven bits of
this 8-bit register are automatically incremented after each instruction
fetch. The eighth bit remains as programmed, resulting from an LD R, A
instruction. The data in the refresh counter is sent out on the lower portion
of the address bus along with a refresh control signal while the CPU is
decoding and executing the fetched instruction. This mode of refresh is
transparent to the programmer and does not slow the CPU operation. The
programmer can load the R register for testing purposes, but this register
is normally not used by the programmer. During refresh, the contents of
the I register are placed on the upper eight bits of the address bus.
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The CPU includes two independent 8-bit accumulators and associated 8-
bit flag registers. The accumulator holds the results of 8-bit arithmetic or
logical operations while the FLAG register indicates specific conditions
for 8-bit or 1 16-bit operations, such as indicating whether or not the
result of an operation is equal to zero. The programmer selects the
accumulator and flag pair with a single exchange instruction so that it is
possible to work with either pair.
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Two matched sets of general-purpose registers, each set containing six 8-bit
registers, may be used individually as 8-bit registers or as 16-bit register
pairs. One set is called BC, DE, and HL while the complementary set is
called BC’, DE’, and HL’. At any one time, the programmer can select either
set of registers to work through a single exchange command for the entire
set. In systems that require fast interrupt response, one set of general-purpose
registers and an ACCUMULATOR/FLAG register may be reserved for handling
this fast routine. One exchange command is executed to switch routines.
This greatly reduces interrupt service time by eliminating the requirement
for saving and retrieving register contents in the external stack during
interrupt or subroutine processing. These general-purpose registers are used
for a wide range of applications. They also simplify programing, specifically
in ROM-based systems where little external read/write memory is available.
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The 8-bit arithmetic and logical instructions of the CPU are executed in
the ALU. Internally, the ALU communicates with the registers and the
external data bus by using the internal data bus. Functions performed by
the ALU include:
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• Add
• Subtract
• Logical AND
• Logical OR
• Logical Exclusive OR
• Compare
• Left or Right Shifts or Rotates (Arithmetic and Logical)
• Increment
• Decrement
• Set Bit
• Reset Bit
• Test bit
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As each instruction is fetched from memory, it is placed in the
INSTRUCTION register and decoded. The control sections performs this
function and then generates and supplies the control signals necessary to
read or write data from or to the registers, control the ALU, and provide
required external control signals.
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The Z80 CPU I/O pins are illustrated in Figure 3 and the function of each
is described in the following paragraphs.
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27 30
M1 A0
31
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19 32
MREQ A2
20 33
System IORQ A3
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Control RD A4
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WR
36 A6
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RFSH A7 Address
38 A8 Bus
HALT 18 39 A9
40 A10
24 1
WAIT A11
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CPU Z80 CPU
Control 16 3 A13
INT
17 4 A14
NMI
5 A15
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RESET
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Bus 23
Control BUSACK
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Address Bus (output, active High, tristate). A15-A0 form a 16-bit address
bus. The Address Bus provides the address for memory data bus
exchanges (up to 64 Kbytes) and for I/O device exchanges.
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Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the
requesting device that the CPU address bus, data bus, and control signals
MREQ, IORQ RD, and WR have entered their high-impedance states.
The external circuitry can now control these lines.
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Bus Request (input, active Low). Bus Request has a higher priority than
NMI and is always recognized at the end of the current machine cycle.
BUSREQ forces the CPU address bus, data bus, and control signals
MREQ IORQ, RD, and WR to go to a high-impedance state so that other
devices can control these lines. BUSREQ is normally wired-OR and
requires an external pull-up for these applications. Extended BUSREQ
periods due to extensive DMA operations can prevent the CPU from
properly refreshing dynamic RAMS.
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Data Bus (input/output, active High, tristate). D7–D0 constitute an
8-bit bidirectional data bus, used for data exchanges with memory and I/O.
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HALT State (output, active Low). HALT indicates that the CPU has
executed a HALT instruction and is waiting for either a non-maskable or a
maskable interrupt (with the mask enabled) before operation can resume.
During HALT, the CPU executes NOPs to maintain memory refresh.
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Interrupt Request (input, active Low). Interrupt Request is generated by
I/O devices. The CPU honors a request at the end of the current
instruction if the internal software-controlled interrupt enable flip-flop
(IFF) is enabled. INT is normally wired-OR and requires an external
pull-up for these applications.
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Input/Output Request (output, active Low, tristate). IORQ indicates that
the lower half of the address bus holds a valid I/O address for an I/O read
or write operation. IORQ is also generated concurrently with M1 during
an interrupt acknowledge cycle to indicate that an interrupt response
vector can be placed on the data bus.
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Machine Cycle One (output, active Low). M1, together with MREQ,
indicates that the current machine cycle is the opcode fetch cycle of an
instruction execution. M1 together with IORQ, indicates an interrupt
acknowledge cycle.
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Memory Request (output, active Low, tristate). MREQ indicates that the
address bus holds a valid address for a memory read of memory write
operation.
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Non-Maskable Interrupt (input, negative edge-triggered). NMI has a
higher priority than INT. NMI is always recognized at the end of the
current instruction, independent of the status of the interrupt enable flip-
flop, and automatically forces the CPU to restart at location 0066H.
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Read (output, active Low, tristate). RD indicates that the CPU wants to
read data from memory or an I/O device. The addressed I/O device or
memory should use this signal to gate data onto the CPU data bus.
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Reset (input, active Low). RESET initializes the CPU as follows: it resets
the interrupt enable flip-flop, clears the PC and registers I and R, and sets
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the interrupt status to Mode 0. During reset time, the address and data bus
go to a high-impedance state, and all control output signals go to the
inactive state. Notice that RESET must be active for a minimum of three
full clock cycles before the reset operation is complete.
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Refresh (output, active Low). RFSH, together with MREQ indicates that
the lower seven bits of the system’s address bus can be used as a refresh
address to the system’s dynamic memories.
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WAIT (input, active Low). WAIT communicates to the CPU that the
addressed memory or I/O devices are not ready for a data transfer. The
CPU continues to enter a WAIT state as long as this signal is active.
Extended WAIT periods can prevent the CPU from properly refreshing
dynamic memory.
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Write (output, active Low, tristate). WR indicates that the CPU data bus
holds valid data to be stored at the addressed memory or I/O location.
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Clock (input). Single-phase MOS-level clock.
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17 ; e second element in comparison
18 ; h flag to indicate exchange
19 ; l unused
20 ; ix pointer into data array
21 ; iy unused
22 ;
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0003 cb84 24 loop: res flag, h ; initialize exchange flag
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0006 05 26 dec b ; adjust for testing
0007 dd2a2600 27 ld ix, (data) ; initialize array pointer
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000e 57 29 ld d, a ; temporary storage for element
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0013 3008 32 jr pc, noex-$ ; if first > second, no jump
0015 dd7300 33 ld (ix), e ; exchange array elements
0018 dd7201 34 ld (ix+i), d
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0010 dd23 36 noex: inc ix ; point to next data element
001f 10ea 37 djnz next-$ ; count number of comparisons
38 ; repeat if more data pairs
0021 cb44 39 bit flag, h ; determine if exchange occurred
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2 ; on entrance: multiplier in de.
3 ; multiplicand in hl.
4 ;
5 ; on exit result in hl.
6 ;
7 ; register uses:
8 ;
9 ;
10 ; h high order partial result
11 ; l low order partial result
12 ; d high order multiplicand
13 ; e low order multiplicand
14 ; b counter for number of shifts
15 ; c high order bits of multiplier
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16 ; a low order bits of multiplier
17 ;
0000 0610 18 ld b, 16; number of bits-initialize
0002 4a 19 ld c, d; move multiplier
0003 7b 20 ld a, e;
0004 eb 21 ex de, hl; move multiplicand
0005 210000 22 ld hl, 0; clear partial result
0008 cb39 23 mloop: srl c; shift multiplier right
000a if 24 rra least significant bit is
25 ; in carry.
000b 3001 26 jr nc, noadd-$; if no carry, skip the add.
good 19 27 add hl, de; else add multiplicand to
28 ; partial result.
000e eb 29 noadd: ex de, h l; shift multiplicand left
goof 29 30 add hl, hl; by multiplying it by two.
0010 eb 31 ex de, hl;
0011 10f5 32 djnz mloop-$; repeat until no more bits.
0013 c9 33 ret;
34 end;
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LD A, n Notify peripheral that service
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Enable Interrupt
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11OUT - output ED
dec HL and B AB
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Port
Destination
Address
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NOP 00
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IM0 46
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IM1 56
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Part Number Title DC number

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stack allows simple implementation of multiple level interrupts, unlimited

A15 — A0 PC Refresh Address

Memory Read Cycle Memory Write Cycle

A15 — A0 Port Address

*Automatically inserted WAIT state

Last M Cycle of Instruction M1

Last T State T1 T2 TW* TW* T3

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A7–A0 A7–A0 A7–A0

D7–D0 D3–D0 D7–D4

;B IS NOT ZERO, OTHERWISE FALL

DAA ;ADJUST RESULT TO DECIMAL CODED

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Op Code One or Two Bytes

Op Code One or Two Bytes

Op Code Low Order

Op Code High Order

Op Code One Byte

Op Code Jump Relative (One Byte Op Code)

High Order Address to Low Order Operand

Displacement Operand added to index register

Op Code One or Two Bytes

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Destination I 5 $ % & ' ( ) / +/ %& '( ,;G O<G ,QQ Q

Register A ED (' )   $ % & ' ( $ $ )' '' )' )'

B         '' )' ''

C )   $ % & ' ( '' )' ''

D         '' )' ''

E )   $ % & ' ( '' )' ''

H         '' )' ''

L )   $ % & ' ( '' )' ''

Reg (HL)        ''

(IY+d) )' )' )' )' )' )' )' )'

A+1 32 Low Order Address

A+2 6F High Order Address

A+2 F1 One or Two Bytes

(SP) F Top of stack

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Register AF BC DE HL SP IX IY nn (nn) (SP)

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5HJLVWHU$GGUHVVLQJ 5HJ,QGLU ,QGH[HG ,PPHG

A B C D E F L (HL) (IX+d) (lY+d) n

5HJLVWHU$GGUHVVLQJ 5HJ,QGLU ,QGH[HG ,PPHG

Decimal Adjust Acc, DAA 27

Type A B C D E F L (HL) (IX+d) (lY+d) A Rotate

A+1 32 Low Order Address

A+2 3E High Order Address

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Destination I 5 $ % & ' ( ) / +/ %& '( ,;G O<G ,QQ Q

Register A ED (' ) $ % & ' ( $ $ )' '' )' )'

B '' )' ''

C ) $ % & ' ( '' )' ''

D '' )' ''

E ) $ % & ' ( '' )' ''

H '' )' ''

L ) $ % & ' ( '' )' ''

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