Design problem

First, we will choose common emitter with voltage divider bias at two stage
because

1- Voltage divider more stable at Q point

2- Common emitter has a high voltage gain

3- Common emitter has a phase shift 180 so, the output of two stages will
be without phase shift

Let we use a transistor with the following parameters

Beta=200 vce=0.25v

Let we use again=60 let first stage gain =-10 and the second =-5

1-Design of first stage

To achieve the condition ZIN>10RS

ZIN = RB||Bre
So Bre at minimum equal 10k and with large value of RB hence
ZIN=Bre=10k>=10 RS

Bre =10 k and B=200 so re=50 ohm

IE=26mv/re=26mv/50=0.52 mA

Let VE=6.8 SO RE=6.8/0.52 =13076 ohm =13 k

VB= VE + 0.7 =7.5

AS VB=7.5=0.5VCC SO (R1=R2)

BUT R1 && R2 SHOULD ACHEVIE TWO CONDITIONS

1- BRE>10R2 (TO USE APPROXIMATE ANALYSIS)

2- R1||R2 =RB , LARGE ENOUGH TO MAKE RB||Bre

So we select R1=R2=260K

G1= -(RC||ro)/re …….. ro=ZIN2

SO RC1=530 OHM

2-DESIGN OF SECOND STAGE

As in first stage but gain2=-6

G2=-RC2||ro/re………….ro=Rl=6k

RC1=320 ohm

R1=R2=260k

LET R1=R2=60K

Q RE RC R1 R2 ICQ VCEQ
Q1 13k 530 O 260K 260K 0.52mA 7.5V
Q2 13k 320 O 260K 260K 0.52mA 7.5V

AND WITH SELECT APPROPRATE VALUES OF CAPACITORS WE GET

TO CHECK WE MADE ANALYSIS WITH PSPICE
1-WE NOTICE THAT WHEN V(13) =VI =3.33mA … Vo=200 m A

ie gain =60

2-And we notice also there is no phase shift between vin and vo

WHICH REQUIRED

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