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RF/MICROWAVE DESIGN

Managing The Challenges


in RF/MICROWAVE DESIGNS
Because of the growth in mixed-technology products, designers often
can’t use traditional PCB layout tools for RF, and RF tools won’t work
with non-RF circuits. So what’s the solution? by PER VIKLUND

Not long ago, a cell phone was a cell phone and a car sound ■ Design rule check (DRC).
system was just a car sound system. Today, the sound system To facilitate effective RF design, layout tool functionality
and the cell phone are integrated via a Bluetooth RF link to is extended with drafting, snapping and align features more
provide built in hands-free functionality. More traditionally commonly found in mechanical design systems. Without
“pure” RF or analog/digital products are integrated system them, RF design becomes a painfully slow task.
designs, with RF systems embedded as “system on board,” For many types of designs, a strictly schematic-driven
and all technologies sharing a rapidly shrinking board space. flow is optimal. But since RF design is a very iterative
This is true not only for consumer products, but for defense process, with the circuit often being designed as it’s being laid
and aerospace applications and all varieties of designs. out on the board, a schematic-driven flow is not always best.
Anyone who has placed a cell phone close to an office On top of that, purely layout-driven design is not feasible
phone or a sound system is aware of how easily unwanted RF either, because we have large non-RF sections in the same
energy can be coupled into other systems. If a cell phone design. The solution often used is a mixed schematic/layout-
three feet away from another system can ruin that system’s driven design flow where non-RF circuits are driven from the
performance, how can RF circuits be placed on the same schematic and selected parts of the RF circuitry are designed
board as other circuits? For one thing, it leads to a com- bottom-up, directly in the layout tool.
pletely new set of design requirements. And managing RF
system design – which very much includes managing RF interference
EMI/EMC – has become a critical focus area. With the basic design foundation in place, managing electro-
But performing RF design in a traditional CAD environ- magnetic interference (EMI) becomes the next major complex-
ment causes severe pain. And at the same time, specialized ity to manage. EMI is all unwanted coupling of signal energy
RF design tools cannot be used as the sole solution, because within a design or between the design and other systems.
most RF circuits must coexist with substantial sections of After years of high-speed challenges, many designers
digital/analog technology. Moreover, the interdependent have become experienced at controlling crosstalk and achiev-
challenges involved have made the design of RF system ing signal integrity. A key to their success is a good under-
boards a slow and highly iterative process. This is unaccept- standing of how signal currents flow on a board. With a sig-
able, and there is a strong focus on streamlining the process nal propagating down a trace, there has to be a return
with tools that understand the characteristics of RF and that current to form a closed circuit. What we have learned is that
supply automation in critical areas. the return path tries to find the way back that has the least
There are a number of separate tasks to manage, each impedance. In a low-speed design this was the same as the
with its own issues. These include: path of least resistance or typically a straight line, but a high-
■ Design the RF circuitry and layout. speed signal will have the path of least inductance, which
■ Instantiate the RF circuitry in schematic and layout. typically is right under the trace in the ground plane.
■ Isolate/separate RF from non-RF circuitry. Managing return paths allows designers to control
■ Manage power and grounds. unwanted coupling and radiation/susceptibility as the
■ Analyze couplings and parasitics. amount of radiation is proportional to the loop area formed

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RF/MICROWAVE DESIGN

c
fc =
(s - d)2 εr

FIGURE 1. Formula for calculating pass band center frequency


of a via fence.
FIGURE 2. Random variance via peppering and contour stitch-
ing can prevent parallel plate excitation.
by the conductor and its return path. Furthermore, if two
signals share the return path, energy from one signal may be put stages share a return path, as we otherwise risk causing
coupled into the other in the form of common impedance enough feedback coupling (from the higher power output
coupling. So knowing where the return path is, making sure stage to the sensitive input stages) to cause oscillation.
the loop area is minimized and making sure that two critical
signals don’t share the return path – at the same time – is Ground Via Fences
always at the back of the high-speed designer’s mind. Having created ground shields and ground planes, it is com-
With RF circuitry, the signal typically returns by way of mon to generate arrays (peppering with vias) or fences of vias
the path of least capacitance. This is a complicating factor, as (contour stitching) connecting the planes together. Why do
it actually may include any conductive surface in reasonable we do this? Often we hear vague explanations like “It will
proximity, such as a neighboring shield box or a metal cabi- make the ground better/tighter” or “It will stop RF leaks.”
net. For this reason, RF function blocks are kept compact, The real reason for these techniques may not be well
with different blocks separated by grounded compartments, understood. There is little research available, but the includ-
and RF specialists use small capacitors to control RF ground- ed references provide some good information.
ing and return paths. Avoid having a circuit’s input and out- For all of you RF designers who just pepper with vias
without really knowing why, read on. Because we almost
never have a single ground layer, designers pepper the ground
areas with vias and stitch the edges of ground areas with vias
to avoid coupling. This coupling is due to the parallel ground
planes’ being excited into the so-called parallel plate mode,
letting signals propagate between the two planes. The vias are
shorting the planes together, preventing this propagation
mode in the ground plane.1 Via fences at very high frequen-
cies behave as band pass filters and the via-to-via spacing con-
trols the pass band poles and thereby the cut of frequency of
the filter.2 Hence the via-to-via spacing is very important.
The center frequency of the band pass filter is shown in
FIGURE 1: a function of via diameter, via spacing and dielec-
tric material.1 (εr is the relative permittivity of the dielectric
material; c is the speed of light.)
The center frequency is not the same as the usable upper
limit. The space enclosed by four via holes is cavity that res-
onates at about 0.65 times the center frequency, and we have
to keep our RF frequencies out of that region.1 In other
words, how we insert the vias, their pitch and diameter have
a great impact on their effectiveness at preventing unwanted
coupling in our design.
This leads to how the ground vias are to be inserted in the
layout. Manually inserting many thousands of ground vias,
only to move them when the design is to be changed, is not a
feasible solution. On the other hand, this is precisely what
EDA tools are for: providing design automation. With rou-
tines that can trace objects and automatically insert multiple
row via fences, understanding the boundaries of a ground fill
and peppering its surface with ground-assigned vias saves

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RF/MICROWAVE DESIGN

tremendous time. By recognizing the frequency lines in the design. We can safely say that signals
resonance effects from ground vias, With the RF section designed on a behave very differently in the RF world
one can let the tool apply a random mixed technology board, it becomes than they do in the not-so-high-fre-
variance to the via pattern to avoid important to be able to analyze whether quency world: With RF, the signal
having all via-formed cavities resonat- non-RF structures in the design have a wavelength in relation to the length of
ing at the same frequency. negative impact on the RF structures the conductors on the circuit board is
FIGURE 2 shows a contour stitching and vice versa. The RF circuit may or such that resonance and standing waves
and a surface via pepper with random may not originate from an RF design can occur. This fact is used to generate
variance applied. Although these vias and simulation tool. But no matter passive RF components as metal pat-
also form cavities, the cavity sizes are what, there is now a need to define terns on the board. These metal pat-
randomly different, giving different regions around the RF circuits, includ- terns connect to each other, and often
resonance frequencies for every little ing surrounding non-RF circuitry, and to the ground, to form an RF circuit. To
section of the planes. send the entire region into the RF a classic analog digital design system,
At this point we have the circuit analysis tools for a detailed analysis. this would all look like a massive short-
under control but are still missing a Because of this, the integration circuit. To make matters even worse,
critical part: power supply. In the old requirements between layout tools and with a large number of nets shorted to
days, RF compartments were closed analysis tools have increased dramati- ground, it’s common that the remaining
metal cabinets connected to ground. cally. With an analysis tool link that nets cannot be properly DRCed either,
Every signal and power source entering preserves model and parameter data leaving us with a complex design that
or leaving such a compartment was through a tool round-trip and still cannot be checked.
passed through a feed-through capaci- allows inclusion of non-RF board fea- On the other hand, we cannot just
tor, basically a conductor with a coaxi- tures, the RF engineer can verify the pretend that the RF elements are non-
al capacitance grounded to trap any RF design without using the very slow conductive, because we need DRC to
that tried to escape. RF chokes, typical- manual modeling process. verify that the RF components also are
ly one quarter wavelength of wire properly connected to each other. The
wound as a coil, were connected in seri- DRC For RF solution is to use a design system that can
al to further limit RF leaks. Needless to Why is DRC a naughty word in RF differentiate between RF structures and
say, this was a very expensive way to design? In many aspects, this is where non-RF structures and provide DRCs
build; today’s integrated board com- using traditional PCB layout tools for RF that makes sense in each discipline.
partments are much more practical. design becomes painful. If the design only Following the paradigm that every
However, now we can’t use feed- contained a bit of RF, a skilled RF design- time you succeed in doing a design, the
through capacitors, which theoretically er would scrutinize the layout manually next one will be much worse, we can
provide an almost perfect decoupling and make sure all is well. But today’s RF count on more integrated RF, more
with low inductance, and we need to designs have not only very complex and complex RF modules and with much
decouple interconnects more carefully large RF sections but also large sections of higher frequencies making it even hard-
to prevent RF leaks via power and low- analog and digital circuits. er to control return paths and coupling.
The future of RF/microwave design
will no doubt be harsh, but exciting. PCD&M

PER VIKLUND is a product marketing


manager at Mentor Graphics. He is
responsible for RF, embedded compo-
nents and advanced packaging solu-
tions. Viklund can be reached at
per_viklund@mentor.com.

REFERENCES
1. Takeshi Yuasa, Tamotsu Nishino, and
Hideyuki Oh-hashi, ”Simple Design Formu-
la for Parallel Plate Mode Suppression by
Ground Via-Holes in Multi-Layered Pack-
ages,” Mitsubishi Electric Corp., May 2001,
Ofuna, Kamakura, Kanagawa, Japan.
2. Thorsten Tischler, Matthias Rudolph,
Andreas Kilk, and Wolfgang Heinrich, ”Via
Arrays for Grounding in Multilayer Packag-
ing – Frequency Limits and Design Rules,”
Ferdinand-Braun-Institut für Höchstfre-
quenztechnik, Berlin, Germany.

30 PRINTED CIRCUIT DESIGN & MANUFACTURE NOVEMBER 2005

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