Each cell which can store a single bit requires six transistors. 3. Does not need to be refreshed periodically as flips flops retain the data. 4. Faster access time compared to DRAM, therefore used as caches mostly. 5. Low density / less memory per chip due to more circuitry capacitor leaks. 6. Less costly than SRAM because of high chip density and because of simple required for a single cell.
Each cell which can store a single bit requires six transistors. 3. Does not need to be refreshed periodically as flips flops retain the data. 4. Faster access time compared to DRAM, therefore used as caches mostly. 5. Low density / less memory per chip due to more circuitry capacitor leaks. 6. Less costly than SRAM because of high chip density and because of simple required for a single cell.
Each cell which can store a single bit requires six transistors. 3. Does not need to be refreshed periodically as flips flops retain the data. 4. Faster access time compared to DRAM, therefore used as caches mostly. 5. Low density / less memory per chip due to more circuitry capacitor leaks. 6. Less costly than SRAM because of high chip density and because of simple required for a single cell.