FPGA System Design with

Verilog
A Workshop Prepared for
Rose-Hulman Ventures
Ed Doering
Workshop Goals
 Gain familiarity with FPGA devices
 Gain familiarity with HDL design methods
 Implement basic designs in hardware

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Agenda
FPGA Overview 8:30 - 9:15
Verilog Overview 9:15 - 10:00
Combinational Circuits 10:15 - 11:00
Lab Projects I 11:00 - 12:00
Sequential Circuits 1:15 - 2:00
Lab Projects II 2:00 - 3:00
Lab Projects III 3:15 - 4:00
Aug 9, 2001 FPGA System Design with Verilo 3
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 FPGA Overview

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What is an FPGA?
 Field Programmable Gate Array
 Blank slate for your digital hardware system

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FPGA in Context
 Microprocessor/microcontroller
 Executes a program

 Fixed hardware and interconnections

 Full-custom IC
 Design at the transistor level

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FPGA in Context
 Semicustom IC
 Standard cell (CBIC, ASIC)

 Masked gate array (MGA)

 Programmable logic device (PLD)

 PLD
 Complex PLD (CPLD)

 FPGA

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When to Use an FPGA
 Design economics
 Shortest time to market

 Lowest NRE cost

 Highest unit cost

 Make quick grab for market share, then do

cost reduction with ASICs

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FPGA Pictures
 Board
 Packages
 Wafer
 Die photos
 FPGA

 Pentium II microprocessor

Sources: http://www.xilinx.com/company/press/products/pictures2.htm,
http://micro.magnet.fsu.edu/chipshots/pentium/

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Internal Architecture
 Array of Configurable Logic Blocks (CLBs)
 User-defined (SRAM-based) interconnect
between CLBs
 Dedicated resources
 Power distribution

 Clock distribution

 Programmable I/O blocks (IOBs)

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Configurable Logic Block

Source: Smith, M.J.S., Application-Specific Integrated Circuits,Addison-Wesley, 1997.

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Programmable I/O Block

Source: Smith, M.J.S., Application-Specific Integrated Circuits, ddison-Wesley, 1997.

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PLD Vendors
Total 1999 PLD Market = $2.6B

Other
9%
Actel
7% Xilinx
35%
Lattice
16%

Altera
33%
Source: Xilinx University Program Workshop Notes

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Xilinx FPGA Product Families
 Virtex-II (“Platform FPGA, ” 10M gates)
 Virtex (1M gates), Virtex-E (3M gates)
 Spartan (low cost ASIC replacement)
 XC4000 (first FPGA family, now with
enhancements)

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Altera FPGA Product Families
 APEX-II (up to 7M gates)
 APEX20K (up to 1.5M gates)
 Mercury (ASIC replacement, “ASSP”)
 FLEX 10K

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Hybrid FPGA / Microcontroller
 Triscend E5 CSoC (configurable system-
on-chip)
 8-bit 8051-based microcontroller

 40K system gates

 Triscend A7 CSoC
 32-bit ARM7TDMI processor

 40K system gates

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Hybrid FPGA / Microcontroller
 Atmel FPSLIC (Field Programmable
System-Level Integrated Circuit)
 5K to 40K system FPGA gates

 8-bit AVR RISC microprocessor core

 Microcontroller peripherals

 36K program and data RAM

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Choosing CPLD or FPGA
 CPLD
 Nonvolatile (ROM- or EEPROM-based)

 Predictable delays (no routing)

 “Register poor” (relatively few FFs)

 Low-to-medium density

 For simple, fast logic with many inputs

 Specialized decoders, combinational circuits,

counters
Aug 9, 2001 FPGA System Design with Verilo 18
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Choosing CPLD or FPGA
 FPGA
 Volatile (SRAM-based)

 Configuration must be stored externally (serial

EEPROM)
 Permits field upgrades, reconfigurable computing

 Variable routing delays

 “Register rich” (relatively many FFs)

 For arbitrary digital systems, system-on-chip (SoC),

medium-to-high density

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Verilog Overview

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Hardware Description Languages
 Verilog  VHDL
 Gateway Design  Origins in DoD
Automation (1983; VHSIC program
proprietary) (1980’s)
 Acquired by
 IEEE standard in
Cadence 1989
 IEEE standard in
1987
 Similar to ADA
1995
 Similar to C

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Verilog vs. VHDL
 Verilog is less “wordy”
 Industry is about 50%-50%
 VHDL more common in adademe
 I think Verilog is easier to learn

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What is “HDL”?
 HDL = Hardware Description Language
 A text-based method for describing
hardware to a synthesis tool

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HDL Advantages Over
Schematic Entry
 Produce correct designs in less time
 Produce larger and more complex systems
per unit time
 Shifts focus to specifying functionality
 Synthesis tools automate details of
connecting gates and devices

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Design Flow Comparison
Schematic Text

Netlist HDL Sim

Gate-Level Hardware
Simulation Synthesis

Implement Netlist

Implement
Aug 9, 2001 FPGA System Design with Verilo 25
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Key Advantages of HDL-Based
Design Methodology
 Operate at higher level of abstraction
 Can debug earlier (behavioral simulator)
 Parameterized design, easy to make
wholesale modifications to a design (e.g.,
bus width)

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Key Advantages of HDL-Based
Design Methodology
 Can quickly specify desired behavior
 Example: Up-counter with reset

if (reset == 1)
count <= 0;
else
count <= count + 1;

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Key Advantages of HDL-Based
Design Methodology
 Can easily target multiple devices (eases
product migration)

HDL

FPGA ASIC

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Key Advantages of HDL-Based
Design Methodology
 HDL is more universal than schematic tools
 Promotes design reuse
 Promotes integration of third party designs,
or IP (intellectual property)

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What HDL is NOT
 HDL is not a programming language
(HDL is a description language)

 HDL is not highly abstract, e.g., implement

the DSP algorithm y(n) = 0.75y(n-1) +
0.3x(n)
(HDL is at the RTL level (register transfer))

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Synthesizable Subset
 Verilog (and VHDL) began life as
simulation and modeling tools
 Hardware synthesis developed during the
1990’s
 Need to use a subset of Verilog and specific
coding styles to allow synthesis tool to infer
correct (and realizable) hardware

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Synthesizable Subset
Use this to write
testbenches for
behavioral simulation

Verilog

Synthesizable
Verilog

Use this to
make hardware
in FPGA
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Most Likely Learning Hurdle
 May try to write HDL code as if it will
eventually be “executed” by some
mysterious processor device in the FPGA
 Code is written sequentially (like a
program), but you are simply writing
descriptions of the various hardware entities
in your system

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 Verilog:
Combinational
Circuits
Aug 9, 2001 FPGA System Design with Verilo 34
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A Gradual Introduction
 New concepts in boldface
 Verilog keywords in italic
 Refer to your handout...

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“Do Nothing” Circuit
module Gadget;
endmodule

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“Do Nothing” with I/O
module Gadget (a,b,c);
// Port modes
input a,b;
output c;
endmodule

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NAND Gate: Continuous
Assignment
module Gadget (a,b,c);

/* Port modes */
input a,b;
output c;

// Functionality
assign c = ~(a & b);
endmodule
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Bitwise Operators
~ NOT
& AND
| OR
^ EXOR

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NAND Gate: Procedural
Assignment
module Gadget (a,b,c);

// Port modes
input a,b;
output c;

// Registered identifiers
reg c;

// Functionality
always @ (a or b)
c <= ~(a & b);
endmodule

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Two Gates
module Gadget (a,b,c,d);

// Port modes
input a,b;
output c;
output d;

// Registered identifiers
reg c,d;

// Functionality
always @ (a or b) begin
c <= ~(a & b);
d <= a ^ b;
end
endmodule

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Two-Input MUX
module Mux2 (
A, // A input
B, // B input
Sel, // Selector
Y // Output
);

// Port modes
input A,B,Sel;
output Y;

// Registered identifiers
reg Y;

// Functionality
always @ (A or B or Sel)
if (Sel==0)
Y <= A;
else
Y <= B;
endmodule

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Relational Operators

== Equal to
!= Not equal
< Less than
> Greater than
<= Less than or equal
>= Greater than or equal
&& AND
|| OR
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More Operators

>> Shift right

<< Shift left
+ Add
- Subtract
* Multiply
/ Divide Not likely to synthesize!

% Modulus
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MUX Again...
// Functionality
always @ (A or B or Sel)
if (Sel)
Y <= B;
else
Y <= A;

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... and Again!
// Functionality
always @ (A or B or Sel)
Y <= (Sel) ? B : A;

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4-Input MUX
module Mux4 (
Data, // Data input
Sel, // Selector
Y // Output
);

// Port modes
input [3:0] Data;
input [1:0] Sel;
output Y;

// Registered identifiers
reg Y;

// Functionality
always @ (Data or Sel)
if (Sel == 0)
Y <= Data[0];
else if (Sel == 1)
Y <= Data[1];
else if (Sel == 2)
Y <= Data[2];
else Y <= Data[3];

endmodule

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4-Input MUX Using ‘case’
// Functionality
always @ (Data or Sel)
case (Sel)
0: Y <= Data[0];
1: Y <= Data[1];
2: Y <= Data[2];
3: Y <= Data[3];
default: Y <= Data[0];
endcase
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Custom MUX
module Mux16 (
Data, // Data input
Sel, // Selector
Y // Output
);

// Port modes
input [15:0] Data;
input [3:0] Sel;
output Y;

// Registered identifiers
reg Y;

// Functionality
always @ (Data or Sel)
casez (Sel)
4’b0000: Y <= Data[0];
4’b0001: Y <= Data[1];
4’b01??: Y <= Data[2];
default: Y <= Data[3];
endcase

endmodule

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Code Translator (Truth Table)
module Code_Translator (
Code_In,
Code_Out,
);

// Port modes
input [2:0] Code_In;
output [2:0] Code_Out;

// Registered identifiers
reg [2:0] Code_Out;

// Functionality
always @ (Code_In)
case (Code_In)
3’b000: Code_Out <= 3’b101;
3’b001: Code_Out <= 3’b111;
3’b010: Code_Out <= 3’b001;
3’b011: Code_Out <= 3’b000;
3’b100: Code_Out <= 3’b100;
3’b101: Code_Out <= 3’b010;
3’b110: Code_Out <= 3’b110;
3’b111: Code_Out <= 3’b011;
endcase

endmodule

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Miscellaneous Techniques
{a,b}

{Data[13:12],a,b,Data[11:0]}

{16{a}}

assign Y = (en) ? X : 1’bz;

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4-Bit Magnitude Comparator
module Compare4 (
A, // Data input A
B, // Data input B
AltB, // A is less than B
AeqB, // A is equal to B
AgtB // A is > than B
);

// Port modes
input [3:0] A,B;
output AltB,AeqB,AgtB;

// Registered identifiers
reg AltB,AeqB,AgtB;

// Functionality
always @ (A or B) begin
AltB <= (A < B);
AeqB <= (A == B);
AgtB <= (A > B);
end
endmodule

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Parameterized Design
module Compare4 (
A, // Data input A
B, // Data input B
AltB, // A is less than B
AeqB, // A is equal to B
AgtB // A is > than B
);

// Define bus width

parameter BusWidth = 8;

// Port modes
input [BusWidth-1:0] A,B;
...
...

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Parameterized Design (Using
Compiler Directive)
`define BusWidth = 8;

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 Lab Projects I

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Simulating Your Design
 See beginning of From Concept to Working
FPGA Chip: Step-by-Step Instructions
 Demo:
 Verilog Boilerplate Generator

 Silos 2001 Behavioral Simulator

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Combinational Design Projects
 Pick several of the following designs:
 3-to-8 decoder with output enable

 8-to-3 priority encoder

 16-bit three-input adder

 10-bit barrel shifter

 Enter your design and verify in Silos

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 Verilog:
Sequential
Circuits
Aug 9, 2001 FPGA System Design with Verilo 58
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A Gradual Introduction
 New concepts in boldface
 Verilog keywords in italics
 Refer to your handout...

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D Flip-Flop
module D_FF (D,Clock,Q);

/* Port modes */
input D,Clock;
output Q;

// Registered identifiers
reg Q;

// Functionality
always @ (posedge Clock)
Q <= D;

endmodule

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T Flip-Flop, Falling Edge
module T_FF (T,Clock,Q);

/* Port modes */
input T,Clock;
output Q,;

// Registered identifiers
reg Q;

// Functionality
always @ (negedge Clock)
if (T == 1)
Q <= ~Q;

endmodule

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T Flip-Flop, Dual Outputs
module T_FF (T,Clock,Q,_Q);

/* Port modes */
input T,Clock;
output Q,_Q;

// Registered identifiers
reg Q;

// Functionality
always @ (negedge Clock)
if (T == 1)
Q <= ~Q;

assign _Q = ~Q;

endmodule

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Flip-Flop with Async. Reset
module D_FF (D,Clock,Q,_Q,Reset);

/* Port modes */
input D,Clock,Reset;
output Q,_Q;

// Registered identifiers
reg Q;

// Functionality
always @ (negedge Clock or
posedge Reset)
if (Reset == 1)
Q <= 0;
else
Q <= D;

assign _Q = ~Q;

endmodule

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Flip-Flop with Async. Preset
module D_FF (D,Clock,Q,_Preset);

/* Port modes */
input D,Clock,_Preset;
output Q;

// Registered identifiers
reg Q;

// Functionality
always @ (posedge Clock or
negedge _Preset)
if (_Preset == 0)
Q <= 1;
else
Q <= D;

endmodule

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Flip-Flop, Synchronous Reset
module D_FF (D,Clock,Q,Reset);

/* Port modes */
input D,Clock,Reset;
output Q;

// Registered identifiers
reg Q;

// Functionality
always @ (posedge Clock)
Q <= (Reset)? 0 : D;

endmodule

Aug 9, 2001 FPGA System Design with Verilo 65

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A Brief Sermon...
NOTE: Avoid the temptation to design arbitrary flip-flop
behavior, e.g., ability to trigger on both edges of the
clock, ability to trigger on multiple clock signals, etc.
The hardware synthesis tool does not “magically”
create new hardware from thin air! You have to write
circuit descriptions that are realizable, that is, can be
mapped onto existing (known) hardware elements
such as standard D flip-flops.
Bottom line: Use the constructs listed above exactly as
shown... don’t invent your own!!

Aug 9, 2001 FPGA System Design with Verilo 66

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Data Register
module Reg16 (D,Clock,Q,Reset);

/* Port modes */
input [15:0] D;
input Clock,Reset;
output [15:0] Q;

// Registered identifiers
reg [15:0] Q;

// Functionality
always @ (posedge Clock or
posedge Reset)
if (Reset == 1)
Q <= 0;
else
Q <= D;

endmodule

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Up Counter with Async. Reset
module CountUp (Clock,Reset,Q);

// Port modes
input Clock,Reset;
output [7:0] Q;

// Registered identifiers
reg [7:0] Q;

// Functionality
always @ (posedge Clock or
posedge Reset)
if (Reset == 1)
Q <= 0;
else
Q <= Q + 1;

endmodule

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Up Counter with Enable
// Functionality
always @ (posedge Clock or
posedge Reset)
if (Reset == 1)
Q <= 0;
else
Q <= (Enable) ? Q + 1 : Q;

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Down Counter
module CountDown (Clock,Reset,Enable,Init,Q);

// Port modes
input Clock,Reset,Enable,Init;
output [7:0] Q;

// Registered identifiers
reg [7:0] Q;

// Functionality
always @ (posedge Clock or
posedge Reset)
if (Reset == 1)
Q <= 0;
else
if (Init)
Q <= 8’hFF;
else if (Enable)
Q <= Q – 1;

endmodule

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Loadable Shift Register
module Shifter (Clock,Reset,Load,D,Q);

// Port modes
input Clock,Reset,Load;
input [7:0] D;
output [7:0] Q;

// Registered identifiers
reg [7:0] Q;

// Functionality
always @ (posedge Clock or
posedge Reset)
if (Reset == 1)
Q <= 0;
else
Q <= (Load) ? D :
{1’b0,Q[7:1]};

endmodule

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Clock Divider
parameter MaxCount = 12;
 
always @ (posedge Clock or posedge Reset)
if (Reset) begin
ClockDiv <= 0;
SlowClock <= 0;
end
else if (ClockDiv == MaxCount)
begin
SlowClock <= 1;
ClockDiv <= 0;
end
else begin
SlowClock <= 0;
ClockDiv <= ClockDiv+1;
end

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Design Rules
 Generally speaking, follow good design
practice for digital systems, e.g., avoid
gated clocks
 In particular, strive to write descriptions
that make all flip-flop clocks connect to the
master clock
 Use asynchronous reset on all flip-flops

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Design Rules (cont’d)
 Use a systematic naming convention for
identifiers:
 i$Identifier Module input
 o$Identifier Module output
 r$Identifier Registered
 p$Identifier Parameter
 w$Identifier Wire
Aug 9, 2001 FPGA System Design with Verilo 74
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Topics for Future Exploration
 Finite State Machines
 One-hot encoding

 ‘casez’ (efficient next-state decoder)

 Data path / controller architecture

 Detailed design rules for FPGAs
 Timing and performance tuning
 Instantiation, multi-module systems
 Testbench design
Aug 9, 2001 FPGA System Design with Verilo 75
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References
 http://www.rose-
hulman.edu/~doering/fpga_workshop/refere
nces.htm

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 Lab Projects II

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Development Procedure
 Introduction to the XS-40 board
 Review the step-by-step development
procedure

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First Design Project
 Implement the following system:

A B (use Pin 19)

(use Pin 44) SimpleSystem

C (use Pin 25)

B = A, C = ~A

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 Lab Projects III

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10-Second Count Down Timer
 Design and implement a 10 second counter
(9 down to 0) with pause and reset inputs
 Display the count value on the 7-segment
display
 Use the 100 MHz on-board clock
 Use the lower two bits of the PC parallel
port for the pause and reset input signals

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FPGA System Design with
Verilog
A Workshop Prepared for
Rose-Hulman Ventures
Ed Doering