Code No: RR310201

Set No. 1

III B.Tech I Semester Supplementary Examinations, February 2007 COMPUTER ORGANIZATION ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering, Electronics & Telematics and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Discuss about PCI bus arbitration (b) List the merits and demerits of centralized and distributed bus arbitrations. [8+8] 2. Write an algorithm to nd all allowable weights for a weighted BCD code. Assume that all weights are positive numbers [16] 3. (a) Dene the elements of a machine instruction (b) How various instruction are categorized (c) Explain about simple instruction format. [4+6+6]

4. (a) List and describe various co-processor and special instructions of MIPS Rseries processors. (b) Dierentiate between theoretical R3000 and actual R4000 super pipelines. [10+6] 5. (a) What is demand paging. Explain its advantages and disadvantages. (b) Explain the page table structure. Discuss its purpose. [8+8]

6. Discuss three possible techniques for I/O operations with merits and demerits of each. [16] 7. (a) Discuss about microinstruction sequencing containing the single address eld. (b) Dierentiate between explicit and implicit microinstruction address generation techniques. (c) Give dierent classications of micro instructions. 8. (a) Dierentiate between miltiprocessors and multicomputers. (b) Discuss about instruction pipeline. [7+9] [6+5+5]

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Code No: RR310201

Set No. 2

III B.Tech I Semester Supplementary Examinations, February 2007 COMPUTER ORGANIZATION ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering, Electronics & Telematics and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Dierentiate between dedicated and multiplexed bus lines. (b) Discuss various methods of bus arbitration. (c) What do you mean by bus width? 2. Convert the following decimal numbers to base three and to base ve. (a) 73 (b) 10.333 (c) 21.25

[5+7+4]

[4+6+6]

3. Write programs to execute Y= (A-B) / (C+D*E) using one-address, two-address and three-address instructions. [16] 4. (a) List the characteristics of superscalar processors and contrast it with CISC processors. (b) Explain the instruction execution characteristics of RISC processors. (c) What is semantic gap problem? [6+6+4] 5. Write short notes on the following approaches with suitable examples. What are merits and demerits of each. (a) First - t (b) Best - t (c) Worst - t 6. (a) Explain about magnetic disk layout (b) Elaborate on Winchester disk track format.

[5+6+5] [8+8]

7. (a) Dierentiate between micro programmed and hard wired control units with merits and demerits of each. (b) Discuss about the design considerations of micro instruction sequencing technique. [8+8] 8. (a) Explain about directory protocols. (b) Draw and explain the state diagram for MESI protocol. 1 of 1 [6+10]

Code No: RR310201

Set No. 3

III B.Tech I Semester Supplementary Examinations, February 2007 COMPUTER ORGANIZATION ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering, Electronics & Telematics and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Explain about VonNeumann architecture design in detail. 2. (a) Explain how oating point division is done? (b) Explain the addition of binary numbers in ones complement notation. [10+6] 3. Explain various characteristics of machine instructions in detail 4. (a) Give weighted relative dynamic frequency of HLL operations (b) What do you mean by dynamic percentage of operands? (c) Discuss about overlapping register windows [6+5+5] [16] [16]

5. (a) Explain the cache execution of a read operation with a neat diagram (b) Explain look-aside system organization for caches. 6. (a) What is data striping ? (b) Discuss about the recent disk system developments. (c) Explain the control command operations enabled by magnetic tape drive controller. Also explain about cartridge tape system. [4+4+8] 7. (a) Explain about microinstruction format of TI 8800 (b) Explain about ALU control elds of IBM 3033 microinstruction. [8+8] 8. (a) Dierentiate between short and long pipeline. Which is more advantageous? (b) Elaborate on depending constraints of pipelining. Give an example for pipeline stalled by data dependency. (c) Give an example for idle cycle caused by a branch instruction. [5+6+5] [8+8]

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Code No: RR310201

Set No. 4

III B.Tech I Semester Supplementary Examinations, February 2007 COMPUTER ORGANIZATION ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering, Electronics & Telematics and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Draw and explain the instruction cycle state diagram that includes interrupt cycle processing. (b) Discuss about transfer of control with multiple interrupts. Demonstrate with a neat diagram [8+8] 2. Explain about error detecting and correcting codes. What is their relevance [16] 3. Discuss various key design issues of an instruction format. 4. (a) Dierentiate between large register le versus cache. (b) Discuss how compiler based register optimization is done. (c) Explain various characteristics of reduced instruction set architectures. [6+6+4] 5. (a) Explain major dierences between cache-main and main-secondary memory hierarchies (b) Discuss main features and basic structure of caches. [8+8] [16]

6. (a) Dierentiate between I/O techniques with and without the use of interrupts. (b) Explain dierent types of I/O commands. (c) What is isolated I/O. Dierentiate between memory-mapped and isolated I/O with examples. [5+6+5] 7. (a) List sequencing and branching control elds of IBM 3033 microinstruction. (b) Discuss the functioning of micro sequencer with example 8. (a) Dierentiate between high-level and low-level parallelism (b) Discuss about Flynns classication of parallel processor systems. (c) Explain dierent MIMD interconnection topologies. [5+6+5] [8+8]

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