ASIC Design Flow

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Agenda
ASIC definition and History Typical ASIC Design steps ASIC specification phase ASIC Frontend phase ASIC Backend phase

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ASIC definition
What is an ASIC
ASIC is a combination of digital and analog circuits packed into an IC to achieve the desired control/computation function ASIC typically contains
CPU cores for computation and control Peripherals to control timing critical functions Memories to store data and program Analog circuits to provide clocks and interface to the real world which is analog in nature I/Os to connect to external components like LEDs, memories, monitors etc.

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ASIC history(1/2)
Initial target of an IC is to have programmable devices to adapt to various functions (e.g.. Microprocessor systems like 8051, 8086 etc.) As the technology grew in different areas, performance and requirements grew differently for different areas
This led to the advent of application specific ICs to achieve performance in required areas with reasonable cost

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ASIC history(2/2)
As application technology improves (eg.2G to 3G, High definition TVs etc.), ASIC has become more and more complex over the years To keep up the speed, various tools and methods were introduced in ASIC design to automate the flow and produce quicker and better results IC design moved from putting transistors by hand through designing the logic using standard gates with schematic entry to describing the logic at a higher level of abstraction
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Typical ASIC lifecycle

Requirements Architecture definition Micro architecture definition Design Entry
Implementation Definition and Exploration Phase

Design Verification Physical design IC Fabrication IC Testing and characterization Production and Monitoring
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Phase

Manufacturing and Production

ASIC Flow : Requirements

First step in defining the ASIC is to define the market and requirements
What function we want to achieve? What should be the cost of the product to make it viable? Etc.

This step is primarily driven by the markets with technical inputs from technology experts The seed for the ASIC development is sown here

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ASIC Flow : Architecture and System definition(1/2)

Architecture definition involves
Requirements

Memory1

Memory

External interfaces

Define the SW interface for HWSW interaction to achieve the HWSW partition targets Define the contents of the ASIC and if it can be done with a single ASIC taking into account manufacturing technology
For e.g.., the process to manufacture RF chip and digital chip can be very different.

CPU Cores
Peripheral 1 Peripheral n Clocks and reset

Clock generators

Reset generators

Power Pins

Define the interfaces needed to communicate with external components

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ASIC Flow : Architecture and System definition(2/2)

Architecture definition involves (Contd.)

Model the HW/SW system at higher level and run simulations to see if the performance requirements are met. Define the SW interface for HW-SW interaction to achieve the HWSW partition targets Define the contents of the ASIC and if it can be done with a single ASIC taking into account manufacturing technology
For e.g.., the process to manufacture RF chip and digital chip can be very different.

Define the interfaces needed to communicate with external components Model the HW/SW system at higher level and run simulations to see if the performance requirements are met.
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ASIC Flow :Micro Architecture definition

Peripheral 1

The implementation specific details are defined in this phase Typically it includes
Module partitioning Reset strategy

Bus Interface

Register Block

Clocking strategy Verification strategy Testing strategy

Interrupt/ DMA Interface FIFO FSM

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Design Flow
ASIC design categories
Frontend Design
Technology independent design entry Design verification In most cases, the effort can be re-used over various technology nodes or fabs

Backend design
Technology related implementation Requires additional effort for implementation in different technology node or fab => limited re-usability

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FE Design flow

Design Entry

Semantic checks

Verification

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Design Entry
S1 S4 S3 S2

Design entry is a stage where the micro architecture is implemented in a Hardware Description language like VHDL, Verilog, System Verilog etc.
In early days , a schematic editor was used for design entry where designers instantiated gates. Increased complexity in the current designs require the use of HDLs to gain productivity Another advantage is that HDLs are independent of process technology and hence can be re-used over time

p_fsm : process(ck,ResetX) begin If (ResetX = 0) then Cur_state <= S1; Elsif (ckevent and ck = 1) then Case Cur_state is when S1 => when S2 => .. end case; End if; End process p_fsm;

Tools
Text Editors (Vi, emacs, nedit etc.) Visual design entry tools like Visual HDL

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Semantic checks
Design entry need to checked for language correctness This phase can also be used to check the synthesizability of code
Synthesizability is important to check as the RTL should be mapped to standard cells using synthesis tools later in the flow

Some structural checks can also be undertaken at this stage

Open/Short ports Unused signals Using both edges of clock Usage of correct clock domain crossing mechanisms

Tools
Modelsim, NCsim, VCS Spyglass for structural checks

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Design Verification (1/2)

Verification is the process where the design is tested against the specification The verification methods are classified broadly as
Static methods Dynamic methods

Static methods use the Boolean equations to match the design with specifications
Specification is converted into properties
Example : A rising transition on input pin A will make the output pin X fall within 5 clock cycles

Static verification tools like IFV are capable to read properties described in PSL (Property Specification Language) and the design in VHDL/Verilog The tool is then able to explore the design by converting it to complex Boolean equations and compare the equations written in PSL
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Design Verification (2/2)

Dynamic verification uses stimuli generators to apply to the inputs and simulates the design in a simulator to obtain the results Dynamic verification uses following methods
Directed test cases : A test case is written with a pre-defined set of stimuli and the outputs are checked against the specification Constrained random verification (CRV) : In this method, properties (a.k.a constraints) are written and fed into a tool which generates the stimuli as per the constraints. It also allows property to be written for expected behavior of the design.

Tools used
Languages : PSL ,Verilog, VHDL, C, System Verilog EDA tools : Incisive IFV ,Questa (Mentor Graphics), VCS (Synopsys), NCSim (Cadence)
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ASIC BE Steps
Synthesis/Scan Insertion Floorplan

Placement

CTS

Routing

Glossary :
STA

CTS : Clock Tree Synthesis STA : Static timing analysis DRC : Design Rule Check LVS : Layout versus schematic

Formal Equivalence

DRC/LVS
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Floor plan
Floor plan consists of defining the following :
Aspect ratio of the chip
Logic Area

Partitioning digital and analog cells placement Power ring for core logic I/O Pad Placement Power ring for I/O Pad

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Sample Floor plan

Logic Area

Memories

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Sample Power Plan

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p_fsm : process(ck,ResetX)

Synthesis
The HDL will be mapped to standard cells at this stage The mapping will be done as per the following constraints given by the designer
Technology library to be used (45nm/32nm etc., Max capacitance, Max Transition) Performance constraints ( Clock frequency, I/O timings) Operating conditions (Voltage/temperature range) Area constraints Placement information from floor plan

begin If (ResetX = 0) then Cur_state <= S1; Elsif (ckevent and ck = 1) then Case Cur_state is when S1 => when S2 => .. end case; End if; End process p_fsm;

Tech Library Placement Info

Constraints

Synthesis Tool

Tools Used
Synopsys Design compiler Magma Talus
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Verilog Netlist

Scan Insertion
Comb Logic Comb Logic

The synchronous circuits are tested using Scan based method The objective is to test for manufacturing defects rather than functional defects Fault Models used
Stuck-at At-speed

Scan based method uses each flipflop in the design as control/Observe point
All flipflops are connected in a shift register fashion so that they can be initialized Once initialized, the functional logic is restored by selecting the other input of the multiplexor On the next clock edge, the data is captured into the flop which can then be shifted out
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Placement

The hard macros (like Memories, I/O Pads) are placed during the Floorplan phase
Verilog Netlist

Floor Plan

User constraints

The Logic is placed in the logic area defined in the floorplan phase by using automatic placement tools Placement of standard cells can be driven using the following constraints
Wire length optimization (Default) Timing driven based on performance requirements

Placement tool

Placed Database

Tools Used
ICCompiler
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Nano Encounter

Clock Tree Synthesis (CTS)

Synchronous designs require clocks to arrive at the flip flops at almost the same time Since the flip flops are spread out in the design after placement, the clock arrival time will be different for different flops To make the clocks arrive at around the same time, a clock tree needs to be built and this phase is called clock tree synthesis (CTS) In this phase, tool builds the clock tree by adding buffers in the clock path and delaying the fast arriving clock to match the slow arriving clock Tools Used
Talus ICCompiler

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Routing
The instances which were placed, now need to be connected through wires Automatic tools take the connectivity information from the verilog netlist and connect the pins of the instances Automatic routing is done only for logic signals and not for power supply/ Analog signals The tools normally does a global route where it estimates the congestion and connects the pins. However, spacing violations may remain in this phase The detailed route actually places the metal wires and connects the pins by using routing channels Tools used
ICCompiler Talus

Placed and CTS DB

Verilog Netlist

Technology Rules

Routing tool

Routed Database

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Static timing analysis

The performance requirements in terms of clock frequencies and I/O delays should be evaluated and confirmed to be matching with the requirements The flow for STA would be as follows
Generation of delay numbers ( RC Extraction) Post Layout Netlist Timing Constraints (Clock frequency and I/O delay constraints, Timing Exceptions such as False path/Multicycle Path and Case Analysis)

Using the above data perform the following checks using STA tool (like PrimeTime)
Setup, Hold, Recovery and Removal violations Clock Gating setup/hold violations Design Rule Violations (max transition time, max capacitance, max fan-out)
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Equivalence Check
During the BE phase, new components may have been added or removed (E.g.. Clock tree buffers) There is a need to verify that RTL and Gate netlist are equivalent Equivalence check is a method which compares the boolean equation from RTL and Gate netlist To speed up the process, it uses certain invariants in the design
Primary functional ports are the same in RTL and gate level Registers/Flipflops are kept the same in RTL and gate level
Here there can be some exceptions as Flipflops with constant values may be removed during synthesis

Tools used :
Formality LEC
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Physical verification (1/2)

What is a layout?
Layout is set of patterns which uses different layers to describe the transistors and their connections using different layers Layout is the exact description of patterns present in the silicon The patterns present in the layout will be processed and will be etched in the silicon during the manufacturing process

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Physical verification(2/2)
Layout versus schematic (LVS) checks
The functional verification is done on verilog netlist (schematic), whereas the final handoff for manufacturing is a Layout This makes the LVS checks mandatory The schematic can either be a verilog netlist or a spice netlist incase of analog blocks The tool converts the layout into sets of transistors and checks with the supplied reference schematic

Design Rule checks

These are the rules imposed by the manufacturing technology Verifies that the layout satisfies the design rules of the technology like minimum layer width, spacing between layers etc.

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Questions & Answers Can also be posted at : discussion.forum.nokia.com/vtuedusat

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Thank You

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