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08dt4
08dt4
08dt4

1. B Muxer 32-1:
- B chn knh, chn 1 bit u ra t 32 bit u vo.
+ Code:
// Multiplexor select 1bit from 32bits
module Muxer (f, data, sel);
output f;
input [0:31] data;
input [0:31] sel;
wire
wire
wire

[0:31] f1;
[0:7] f2;
f3,f4;

genvar i;
generate
for (i=0; i<32; i=i+1) begin: and_gates
and (f1[i], data[i], sel[i]);
end
for (i=0; i<8; i=i+1) begin: or_gates
or (f2[i], f1[4*i], f1[4*i+1], f1[4*i+2], f1[4*i+3]);
end
or (f3, f2[0], f2[1], f2[2], f2[3]);
or (f4, f2[4], f2[5], f2[6], f2[7]);
or (f, f3, f4);
endgenerate
endmodule
+ Kt qu m phng trong Quartus:

2. B gii m 5 32:
- Gii m 5 bit la chn thanh ghi thnh bus select 32 bit
+ Code:
// Decoder 5 to 32
module Decoder (UnCoded, Coded);
input [4:0] Coded;
output [31:0] UnCoded;
wire
wire
wire

[4:0] nCoded;
[4:0] dCoded;
f1, f2, f3, f4;

not

#50

(nCoded[3], Coded[3]),
(nCoded[4], Coded[4]);

buf

#50

(dCoded[3], Coded[3]),
(dCoded[4], Coded[4]);

and

#50

(f1, nCoded[3], nCoded[4]),

(f2, dCoded[3], nCoded[4]),
(f3, nCoded[3], dCoded[4]),
(f4, dCoded[3], dCoded[4]);

not

#100

(nCoded[0], Coded[0]),
(nCoded[1], Coded[1]),
(nCoded[2], Coded[2]);

buf

#100

(dCoded[0], Coded[0]),
(dCoded[1], Coded[1]),
(dCoded[2], Coded[2]);

and #50

(UnCoded[1], dCoded[0], nCoded[1], nCoded[2], f1),

(UnCoded[2], nCoded[0], dCoded[1], nCoded[2], f1),
(UnCoded[3], dCoded[0], dCoded[1], nCoded[2], f1),
(UnCoded[4], nCoded[0], nCoded[1], dCoded[2], f1),
(UnCoded[5], dCoded[0], nCoded[1], dCoded[2], f1),
(UnCoded[6], nCoded[0], dCoded[1], dCoded[2], f1),
(UnCoded[7], dCoded[0], dCoded[1], dCoded[2], f1);

and #50

(UnCoded[8], nCoded[0], nCoded[1], nCoded[2], f2),

(UnCoded[9], dCoded[0], nCoded[1], nCoded[2], f2),
(UnCoded[10], nCoded[0], dCoded[1], nCoded[2], f2),
(UnCoded[11], dCoded[0], dCoded[1], nCoded[2], f2),
(UnCoded[12], nCoded[0], nCoded[1], dCoded[2], f2),
(UnCoded[13], dCoded[0], nCoded[1], dCoded[2], f2),

(UnCoded[14], nCoded[0], dCoded[1], dCoded[2], f2),

(UnCoded[15], dCoded[0], dCoded[1], dCoded[2], f2);
and #50

(UnCoded[16], nCoded[0], nCoded[1], nCoded[2], f3),

(UnCoded[17], dCoded[0], nCoded[1], nCoded[2], f3),
(UnCoded[18], nCoded[0], dCoded[1], nCoded[2], f3),
(UnCoded[19], dCoded[0], dCoded[1], nCoded[2], f3),
(UnCoded[20], nCoded[0], nCoded[1], dCoded[2], f3),
(UnCoded[21], dCoded[0], nCoded[1], dCoded[2], f3),
(UnCoded[22], nCoded[0], dCoded[1], dCoded[2], f3),
(UnCoded[23], dCoded[0], dCoded[1], dCoded[2], f3);

and #50

(UnCoded[24], nCoded[0], nCoded[1], nCoded[2], f4),

(UnCoded[25], dCoded[0], nCoded[1], nCoded[2], f4),
(UnCoded[26], nCoded[0], dCoded[1], nCoded[2], f4),
(UnCoded[27], dCoded[0], dCoded[1], nCoded[2], f4),
(UnCoded[28], nCoded[0], nCoded[1], dCoded[2], f4),
(UnCoded[29], dCoded[0], nCoded[1], dCoded[2], f4),
(UnCoded[30], nCoded[0], dCoded[1], dCoded[2], f4),
(UnCoded[31], dCoded[0], dCoded[1], dCoded[2], f4);

assign UnCoded[0] = 0;
endmodule
+ Kt qu m phng trn Quartus:

3. Thit k 32 thanh ghi:

3.1 Thit k 1 DFF:
- Gm 1 u vo d liu d, 1 u ra d liu q v 2 u vo iu khin clk, reset.
- Mi khi c sn ln ca xung clk, bit u vo d s c cht sang u ra q.
- Xung reset s xa u ra q thnh 0.
+ Code:
// Single DFF
module D_FF (q, d, reset, clk);
output q;
input d, reset, clk;
reg
q; // Indicate that q is stateholding
always @(posedge clk or posedge reset) begin
if (reset)
q = 0; // On reset, set to 0
else
q = d; // Otherwise out = d
end
endmodule
+ Kt qu m phng trn Quartus:

3.2 Thit k 1 thanh ghi 32 bit:

- Gm 1 bus d liu u vo v 1 bus d liu u ra 32bit
- C 3 u vo iu khin l clk, reset v cho php ghi wri_en.
- Khi bit wri_en = 1, mi ln c sn ln ca xung clk, d liu u vo s c cht ti u ra.
- Sn ln ca xung reset s xa u ra v 0.

+ Code:
// Single register from 32 DFF
module SinReg (data_out, data_in, reset, clk, wri_en);
output [31:0] data_out;
input [31:0] data_in;
input reset, clk, wri_en;
wire

f;

and

(f, wri_en, clk);

genvar i;
generate
for (i=0; i<32; i=i+1) begin: DFF
D_FF DFF(data_out[i], data_in[i], reset, f);
end
endgenerate
endmodule

3.3. Thit k 32 thanh ghi:

- Gm 1 bus u vo d liu data_in v 2 bus d liu ra data_out1, data_out2.
- 3 bus select 32 bit la chn thanh ghi cho hot ng c hoc ghi.
- 2 u vo iu khin clk, reset.
- 32 b Muxer s dng bus select read_sel1 la chn u ra data_out1 t 32 u ra ca 32
thanh ghi.
- 32 b Muxer s dng bus select read_sel2 la chn u ra data_out2 t 32 u ra ca 32
thanh ghi.
+ Code:
// 32 registers from Single register
module MulReg (data_out1, data_out2, data_in, reset, clk, wri_sel, read_sel1, read_sel2);
output [31:0] data_out1;
output [31:0] data_out2;
input [31:0] data_in;
input [31:0] wri_sel;
input [31:0] read_sel1;
input [31:0] read_sel2;
input reset, clk;
wire
wire

[31:0] f1 [31:0];
[31:0] f2 [31:0];

genvar i,j;
generate
for (i=0; i<32; i=i+1) begin: register
SinRegregister(f1[i], data_in, reset, clk, wri_sel[i]);
end
for (i=0; i<32; i=i+1) begin: Mux1
for (j=0; j<32; j=j+1) begin: Mux2
assign f2[j][i] = f1[i][j];
end
end
for (i=0; i<32; i=i+1) begin: Mux3
Muxer Muxers1(data_out1[i], f2[i], read_sel1);
Muxer Muxers2(data_out2[i], f2[i], read_sel2);
end
endgenerate
endmodule
4. Module chnh regfile:
- Gm 1 bus d liu u vo v 2 bus d liu u ra.
- 3 bus 5bit la chn thanh ghi
- 3 u vo iu khin clk, reset v cho php ghi RegWrite
+ Code:
// register file
module regfile (ReadData1, ReadData2, WriteData, ReadRegister1, ReadRegister2, WriteRegister,
RegWrite, clk, reset);
output [31:0] ReadData1;
output [31:0] ReadData2;
input [31:0] WriteData;
input [4:0] WriteRegister;
input [4:0] ReadRegister1;
input [4:0] ReadRegister2;
input clk, reset, RegWrite;
wire
wire
wire
wire

[31:0] wri_sel;
[31:0] read_sel1;
[31:0] read_sel2;
[31:0] f;

genvar i;
generate
Decoder Decoder1(f, WriteRegister);

Decoder Decoder2(read_sel1, ReadRegister1);

Decoder Decoder3(read_sel2, ReadRegister2);
for (i=0; i<32; i=i+1) begin: WriteEnable
and (wri_sel[i], f[i], RegWrite);
end
MulReg
read_sel1, read_sel2);

Registers(ReadData1, ReadData2, WriteData, reset, clk, wri_sel,

endgenerate
endmodule
+ Kt qu m phng trn Quartus: