EXPERIMENT-10

AIM : To Verify The 2-bit Comparator using VHDL.

TOOLS AND VERSION USED
Tool Used : XLNX
Version : 8.1


CIRCUIT DIAGRAM / RTL






TRUTH TABLE

,0 ,1 b0 b1 g
(,b)
e
(,b)
I
(,b)

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

VHDL CODE
library EEE;
use EEE.STD_LOGC_1164.ALL;
use EEE.STD_LOGC_ARTH.ALL;
use EEE.STD_LOGC_UNSGNED.ALL;

entity s is
Port ( a0 : in STD_LOGC;
a1 : in STD_LOGC;
b0 : in STD_LOGC;
b1 : in STD_LOGC;
g : out STD_LOGC;
l : out STD_LOGC;
e : out STD_LOGC);
end s;

architecture Behavioral of s is
begin
g<=(a0 and (not b0))or((a0 xnor b0) and(a1 and (not b1)));
l<=((not a0) and b0) or ((a0 xnor b0) and ((not a1) and b1));
e<=(a0 xnor b0) and (a1 xnor b1);
end Behavioral;

SIMULATION REPORT