Introduction to CMOS VLSI Design

Lecture 1: Circuits & Layout

David Harris

Harvey Mudd College Spring 2004

Outline
q q q q q q A Brief History CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams

1: Circuits & Layout

CMOS VLSI Design

Slide 2

A Brief History
q 1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instruments q 2003 Intel Pentium 4 processor (55 million transistors) 512 Mbit DRAM (> 0.5 billion transistors) q 53% compound annual growth rate over 45 years No other technology has grown so fast so long q Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society
1: Circuits & Layout CMOS VLSI Design Slide 3

Annual Sales
q 1018 transistors manufactured in 2003 100 million for every human on the planet
Global Semiconductor Billings (Billions of US$)
200

150

100

50

0 1982

1984

1986

1988

1990

1992

1994

1996

1998

2000

2002

Year
1: Circuits & Layout CMOS VLSI Design Slide 4

Invention of the Transistor

q Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable q 1947: first point contact transistor John Bardeen and Walter Brattain at Bell Labs Read Crystal Fire By Riordan, Hoddeson

1: Circuits & Layout

CMOS VLSI Design

Slide 5

Transistor Types
q Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density q Metal Oxide Semiconductor Field Effect Transistors nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration
1: Circuits & Layout CMOS VLSI Design Slide 6

MOS Integrated Circuits

q 1970s processes usually had only nMOS transistors Inexpensive, but consume power while idle

Intel 1101 256-bit SRAM Intel 4004 4-bit Proc q 1980s-present: CMOS processes for low idle power
1: Circuits & Layout CMOS VLSI Design Slide 7

Moores Law
q 1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 months
1,000,000,000 100,000,000 Pentium 4 Pentium III Pentium II Pentium Pro Pentium

Integration Levels SSI: 10 gates

Intel486 Intel386

10,000,000

Transistors

1,000,000 80286 8086 10,000 8008 4004 1,000 8080

100,000

MSI: 1000 gates LSI: 10,000 gates

1970

1975

1980

1985

1990

1995

2000

VLSI: > 10k gates

Slide 8

Year

1: Circuits & Layout

CMOS VLSI Design

Corollaries
q Many other factors grow exponentially Ex: clock frequency, processor performance
10,000 1,000 4004 8008 8080 100 8086 80286 Intel386 10 Intel486 Pentium Pentium Pro/II/III 1 Pentium 4

1: Circuits & Layout

Clock Speed (MHz)

1970

1975

1980

1985

1990

1995

2000

2005

Year

CMOS VLSI Design

Slide 9

CMOS Gate Design

q Activity: Sketch a 4-input CMOS NAND gate

1: Circuits & Layout

CMOS VLSI Design

Slide 10

CMOS Gate Design

q Activity: Sketch a 4-input CMOS NOR gate

A B C D Y

1: Circuits & Layout

CMOS VLSI Design

Slide 11

Complementary CMOS
q Complementary CMOS logic gates nMOS pull-down network pMOS pull-up network inputs a.k.a. static CMOS
pMOS pull-up network

output
nMOS pull-down network

Pull-up OFF Pull-down OFF Z (float) Pull-down ON 0

Pull-up ON 1 X (crowbar)

1: Circuits & Layout

CMOS VLSI Design

Slide 12

Series and Parallel

q q q q nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON
a g1 g2 b (a) 0 0 b OFF a 0 0 b (b) b ON 0 1 b OFF a 0 1 b OFF a 1 0 b OFF a 1 0 b OFF a 1 1 b OFF a 1 1 b ON a a

a g1 g2

a g1 b (c) g2 0

a 0 b OFF 0

a 1 b ON 1

a 0 b ON 1

a 1 b ON

a g1 b (d) g2 0

a 0 b ON 0

a 1 b ON 1

a 0 b ON 1

a 1 b OFF

1: Circuits & Layout

CMOS VLSI Design

Slide 13

Conduction Complement
q Complementary CMOS gates always produce 0 or 1 q Ex: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Y Requires parallel pMOS
A

q Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel

1: Circuits & Layout

CMOS VLSI Design

Slide 14

Compound Gates
q Compound gates can do any inverting function q Ex: Y = Ag B + C g D (AND-AND-OR-INVERT, AOI22)
A B (a) C D A B (b) C A (d) D B Y A B (e) C D (f) A B C D Y D B C D

A (c) C A

B C

1: Circuits & Layout

CMOS VLSI Design

Slide 15

Example: O3AI
q Y = ( A + B + C )g D

1: Circuits & Layout

CMOS VLSI Design

Slide 16

Example: O3AI
q Y = ( A + B + C )g D

A B C D Y D A B C

1: Circuits & Layout

CMOS VLSI Design

Slide 17

Signal Strength
q Strength of signal How close it approximates ideal voltage source q VDD and GND rails are strongest 1 and 0 q nMOS pass strong 0 But degraded or weak 1 q pMOS pass strong 1 But degraded or weak 0 q Thus nMOS are best for pull-down network

1: Circuits & Layout

CMOS VLSI Design

Slide 18

Pass Transistors
q Transistors can be used as switches
g s d

g s d

1: Circuits & Layout

CMOS VLSI Design

Slide 19

Pass Transistors
q Transistors can be used as switches
g s d s g=1 s g s s d g=1 s d g=0 d d 1 Input 0 g=0 strong 1 g=0 g=0 d Input g = 1 Output 0 strong 0 g=1 degraded 1 Output degraded 0

1: Circuits & Layout

CMOS VLSI Design

Slide 20

Transmission Gates
q Pass transistors produce degraded outputs q Transmission gates pass both 0 and 1 well

1: Circuits & Layout

CMOS VLSI Design

Slide 21

Transmission Gates
q Pass transistors produce degraded outputs q Transmission gates pass both 0 and 1 well
Input g a gb g a gb b a gb g b a gb b g = 0, gb = 1 a b g = 1, gb = 0 a b Output

g = 1, gb = 0 0 strong 0 g = 1, gb = 0 strong 1 1

g b

1: Circuits & Layout

CMOS VLSI Design

Slide 22

Tristates
q Tristate buffer produces Z when not enabled
EN 0 0 1 1 A 0 1 0 1 Y

EN A Y

EN A EN Y

1: Circuits & Layout

CMOS VLSI Design

Slide 23

Tristates
q Tristate buffer produces Z when not enabled
EN 0 0 1 1 A 0 1 0 1 Y Z Z 0 1

EN A Y

EN A EN Y

1: Circuits & Layout

CMOS VLSI Design

Slide 24

Nonrestoring Tristate
q Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y

EN A EN
1: Circuits & Layout CMOS VLSI Design Slide 25

Tristate Inverter
q Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output
A EN Y EN

1: Circuits & Layout

CMOS VLSI Design

Slide 26

Tristate Inverter
q Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output
A A EN Y EN Y Y A

EN = 0 Y = 'Z'
1: Circuits & Layout

EN = 1 Y=A
Slide 27

CMOS VLSI Design

Multiplexers
q 2:1 multiplexer chooses between two inputs
S
S 0 0 1 1 D1 X X 0 1 D0 0 1 X X Y

D0 D1

0 Y 1

1: Circuits & Layout

CMOS VLSI Design

Slide 28

Multiplexers
q 2:1 multiplexer chooses between two inputs
S
S 0 0 1 1 D1 X X 0 1 D0 0 1 X X Y 0 1 0 1

D0 D1

0 Y 1

1: Circuits & Layout

CMOS VLSI Design

Slide 29

Gate-Level Mux Design

q Y = SD1 + SD0 (too many transistors) q How many transistors are needed?

1: Circuits & Layout

CMOS VLSI Design

Slide 30

Gate-Level Mux Design

q Y = SD1 + SD0 (too many transistors) q How many transistors are needed? 20

D1 S D0

D1 S D0
1: Circuits & Layout

4 2 4

2 4 2 2

CMOS VLSI Design

Slide 31

Transmission Gate Mux

q Nonrestoring mux uses two transmission gates

1: Circuits & Layout

CMOS VLSI Design

Slide 32

Transmission Gate Mux

q Nonrestoring mux uses two transmission gates Only 4 transistors

S D0 S D1 S
1: Circuits & Layout CMOS VLSI Design Slide 33

Inverting Mux
q Inverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thing q Noninverting multiplexer adds an inverter
D0 S S S D1 Y S S S D1 D0 S D1 S Y D0 0 Y 1 S

1: Circuits & Layout

CMOS VLSI Design

Slide 34

4:1 Multiplexer
q 4:1 mux chooses one of 4 inputs using two selects

1: Circuits & Layout

CMOS VLSI Design

Slide 35

4:1 Multiplexer
q 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates S1S0 S1S0 S1S0 S1S0
D0 S0 D0 D1 D2 D3 0 D1 1 0 Y 0 1 D3 1 D2 Y S1

1: Circuits & Layout

CMOS VLSI Design

Slide 36

D Latch
q When CLK = 1, latch is transparent D flows through to Q like a buffer q When CLK = 0, the latch is opaque Q holds its old value independent of D q a.k.a. transparent latch or level-sensitive latch

CLK D Latch Q

CLK D Q

1: Circuits & Layout

CMOS VLSI Design

Slide 37

D Latch Design
q Multiplexer chooses D or old Q
CLK D 1 0 CLK CLK Q Q D CLK Q Q

CLK

1: Circuits & Layout

CMOS VLSI Design

Slide 38

D Latch Operation
Q D Q D Q Q

CLK = 1

CLK = 0

CLK D Q
1: Circuits & Layout CMOS VLSI Design Slide 39

D Flip-flop
q When CLK rises, D is copied to Q q At all other times, Q holds its value q a.k.a. positive edge-triggered flip-flop, master-slave flip-flop

CLK

CLK
D

Flop

Q
Q

1: Circuits & Layout

CMOS VLSI Design

Slide 40

D Flip-flop Design
q Built from master and slave D latches
CLK CLK D CLK Latch QM Latch CLK Q CLK CLK CLK QM CLK CLK CLK Q

1: Circuits & Layout

CMOS VLSI Design

Slide 41

D Flip-flop Operation
D QM Q CLK = 0

QM

CLK = 1

CLK D Q

1: Circuits & Layout

CMOS VLSI Design

Slide 42

Race Condition
q Back-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition
CLK1 CLK1 Flop D Q1 CLK2 Flop Q2 CLK2 Q1 Q2
1: Circuits & Layout CMOS VLSI Design Slide 43

Nonoverlapping Clocks
q Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew q We will use them in this class for safe design Industry manages skew more carefully instead
2 D 2 2 QM 1 1 1 Q

2 1 2

1: Circuits & Layout

CMOS VLSI Design

Slide 44

Gate Layout
q Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells q Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts

1: Circuits & Layout

CMOS VLSI Design

Slide 45

Example: Inverter

1: Circuits & Layout

CMOS VLSI Design

Slide 46

Example: NAND3
q q q q q Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 by 40

1: Circuits & Layout

CMOS VLSI Design

Slide 47

Stick Diagrams
q Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers

1: Circuits & Layout

CMOS VLSI Design

Slide 48

Wiring Tracks
q A wiring track is the space required for a wire 4 width, 4 spacing from neighbor = 8 pitch q Transistors also consume one wiring track

1: Circuits & Layout

CMOS VLSI Design

Slide 49

Well spacing
q Wells must surround transistors by 6 Implies 12 between opposite transistor flavors Leaves room for one wire track

1: Circuits & Layout

CMOS VLSI Design

Slide 50

Area Estimation
q Estimate area by counting wiring tracks Multiply by 8 to express in

1: Circuits & Layout

CMOS VLSI Design

Slide 51

Example: O3AI
q Sketch a stick diagram for O3AI and estimate area Y = ( A + B + C )g D

1: Circuits & Layout

CMOS VLSI Design

Slide 52

Example: O3AI
q Sketch a stick diagram for O3AI and estimate area Y = ( A + B + C )g D

1: Circuits & Layout

CMOS VLSI Design

Slide 53

Example: O3AI
q Sketch a stick diagram for O3AI and estimate area Y = ( A + B + C )g D

1: Circuits & Layout

CMOS VLSI Design

Slide 54