Field Effect Transistor (FET)

• The bipolar junction transistor (BJT) relies on two types of charge carriers: free electrons and holes.

• In case of field effect transistor we use only one type of charge carrier, either free electrons or holes.
So these type of devices are unipolar.

• In other words, an FET has majority carriers but not minority carriers.

• Although BJT is the preferred device in most of the applications, there are some applications in which
the FET is better suited because of its high input impedance and other properties.

• FET is the preferred device for most switching applications. As a result, it can switch off faster since no
stored charge has to be removed from the junction area.

• There are two kinds of unipolar transistors: junction (JFET) and metal-oxide semiconductor FET
(MOSFET).
Junction Field-Effect Transistor (JFET):
• The JFET is a type of FET that operates with a reverse biased junction to control current in the channel.

N-channel FET P-channel FET

• The control of current flowing in this channel is achieved by varying the voltage applied to the Gate.

• It has no PN-junctions like a BJT, instead has a narrow piece of semiconductor material forming a
“Channel” of either N-type or P-type silicon for the majority carriers to flow through with two
ohmic electrical connections, called the Drain and the Source.
• N-channel JFET’s are mostly used in electronic circuit in comparison to the P-channel types, since
electrons have a higher mobility compared to holes.
Biasing of JFET:

The supply voltage VDD To produce a JFET, two areas of The normal biasing voltages for
forces free electrons to flow p-type material are diffused a JFET
from the source to the drain. into the n-type material.

• In the present case the drain supply voltage is positive, and the gate supply voltage is negative.
• The term field effect is related to the formation of depletion layers around each p region.

• We always reverse-bias the gate-source diode. Because of reverse bias, the gate current IG is approximately zero,
which is equivalent to saying that the JFET has an almost infinite input resistance.
• Here basically the gate voltage controls the drain current. So JFET is a voltage-controlled device because an input
voltage controls an output current.
• The gate-to-source voltage VGS determines how much current flows between the source and the drain. When VGS is
zero, maximum drain current flows through the JFET. If VGS is negative enough, the depletion layers touch and the
drain and the current is cut off.
• The depletion region is wider toward the drain end of the channel because the reverse-biased voltage between the
gate and the drain is greater than that between the gate and the source.
JFET Symbols

p-channel n-channel, offset-gate

n-channel

• In many low-frequency applications, the source and the drain are interchangeable because you can
use either end as the source and the other end as the drain.

• The source and drain terminals are not interchangeable at high frequencies due to the capacitance
involved.
Drain Curves:

• The gate-source voltage VGS equals the gate supply voltage VGG , and
the drain-source voltage VDS equals the drain supply voltage VDD .

• If we short the gate to the source, we will get maximum drain current
because VGS = 0.

• The drain current increases rapidly and then becomes almost horizontal when VDS is
greater than VP.
• When VDS increases, the depletion layers expand. At VDS = VP, the depletion layers
are almost touching. The narrow conducting channel pinches off or prevents a
further increase in current. This is why the current has an upper limit of IDSS.
• The active region of a JFET is between VP and VDS(max).
• The minimum voltage VP is called the pinchoff voltage, and the maximum voltage
VDS(max) is the breakdown voltage.

• Between pinchoff and breakdown, the JFET acts like a current source of approximately IDSS when VGS = 0.
• IDSS is one of the most important JFET quantities, and you should always look for it first because it is the upper limit
on the JFET current.
 • The pinchoff voltage separates two major operating regions of the
JFET. The almost-horizontal region is the active region. The almost-
vertical part of the drain curve below pinchoff is called the ohmic
region.

• When operated in the ohmic region, a JFET is equivalent to a resistor with a value of approximately,

RDS is called the ohmic resistance of the JFET.

• The drain current of maximum 10 mA for VGS = 0, where the pinchoff voltage is 4 V and the breakdown voltage is 30 V.

• The more negative the gate-source voltage, the smaller the drain current.

• At VGS of -4 V, the drain current reduces to almost zero. This voltage is called the gate-source cutoff voltage and is
symbolized by VGS(off) . At this cutoff voltage, the depletion layers touch. In effect, the conducting channel
disappears and the drain current is approximately zero.
Transconductance curve:
• The transconductance curve of a JFET is a graph of ID versus VGS

By plotting the values of ID and VGS of each drain

curve for a particular VDS, we can plot the
transconductance curve.

The half-cutoff point, This produces a normalized current of

 When the gate voltage is half the cutoff voltage, the drain current is one quarter of maximum.
Transconductance:

 In a FET, the gate voltage controls the drain current. An important FET parameter is the
transconductance, gm, which is defined as

 Transconductance tells us how effective the gate-source voltage is in controlling the drain current.

 The higher the transconductance, the more control the gate voltage has over the drain current.

 The gate-source cutoff voltage can be expressed using trnasconductance as

• gm0 is the value of transconductance when VGS = 0 and the maximum value of gm for a JFET.
Self-biased JFET:

Since IS=ID and VG =0, then VS=IDRS.

VDD-IDRD-VDS-IDRS=0

Find VD, VS,VDS and VGS for ID = 5 mA?

 Voltage-Divider Bias

• The voltage divider produces a gate voltage that is a fraction of

the supply voltage.

Voltage applied to the gate is

IDRS=VG-VGS

• When the VG is large, it can swamp out the variations in VGS. So the drain current equals the gate
voltage divided by the source resistance. As a result, the drain current is almost constant for any JFET.

• As we know, the Q point has to be in the active region.

This means that VDS must be greater than IDRDS and
less than VDD (cutoff).

• When a large supply voltage is available, voltage-

divider bias can set up a stable Q point.
Draw the dc load line and the Q point for using ideal methods.
Two-Supply Source Bias
• The idea is to swamp out the variations in VGS by making VSS
much larger than VGS.

• Ideally, the drain current equals the source supply voltage

divided by the source resistance.

• In this case, the drain current is almost constant in spite of JFET

replacement and temperature change.
The Metal-Oxide Semiconductor FET (MOSFET):
• In case of MOSFET the gate is insulated from the channel. Because of this, the gate current is
even smaller than it is in a JFET.

• A silicon dioxide (SiO2) layer is used as the insulating layer.

• Two basic types of MOSFETs used are depletion (D) mode type and enhancement (E) mode type.

• In general the enhancement-mode MOSFET is widely used in both discrete and integrated circuits
in comparison to the depletion mode MOSFETs.

Depletion MOSFET (D-MOSFET):

• The drain and source are diffused into the substrate material and then connected by a narrow
channel adjacent to the insulated gate.
• The D-MOSFET can be operated in either of two modes—the depletion mode or the enhancement
mode—and is sometimes called a depletion/enhancement MOSFET.

• Since the gate is insulated from the channel, either a positive or a negative gate voltage can be
applied.

• The n-channel MOSFET operates in the depletion mode when a negative gate voltage is applied and
in the enhancement mode when a positive gate voltage is applied.

Depletion mode: VGS negative Enhancement mode: VGS positive

 • Imagine the gate as one plate of a parallel plate capacitor and
the channel as the other plate; insulating layer is the dielectric.

• With a negative gate voltage, the negative charges on the gate

repel conduction electrons from the channel, leaving positive
ions in their place.

• The n-channel is depleted of some of its electrons, so the

channel conductivity is decreased.

• The greater the negative voltage on the gate, the greater the
depletion of n-channel electrons.

• At a sufficiently negative gate-to-source voltage, VGS(off), the channel is totally depleted and the drain
current is zero. VGS(off) is called the gate-source cutoff voltage.

• In the enhancement mode, a positive gate voltage attract more conduction electrons into the
channel, thus increasing (enhancing) the channel conductivity.

n channel p channel
Enhancement MOSFET (E-MOSFET):

• This type of MOSFET operates only in the enhancement mode and has no depletion mode.

• It differs in construction from the D-MOSFET in that it has no structural channel.

• For an n-channel device, a positive gate voltage above a threshold value, VGS(th), induces a channel by
creating a thin layer of negative charges in the substrate region adjacent to the SiO2 layer.
• The conductivity of the channel is enhanced by increasing the gate-to-source voltage, thus pulling
more electrons into the channel. For any gate voltage below the threshold value, there is no channel.
• When the gate voltage is zero, the current between source and drain is zero. For this reason, an E-
MOSFET is normally off when the gate voltage is zero.
 n channel p channel

• Because the gate of a MOSFET is insulated from the channel, the input resistance is extremely high
and the gate leakage current, IGSS for a typical MOSFET is in the pA range.

• Due to the input capacitance in MOSFETs an excess static charge can accumulate and can result in
damage to the device as a result of electrostatic discharge. Therefore, the MOSFETS should be handled
very carefully.
D-MOSFET Biasing:
• Depletion/enhancement MOSFETs can be operated with either positive or negative values of VGS

• A simple bias method, called zero bias, is to set VGS = 0 V so that an ac signal at the gate varies the gate-
to-source voltage above and below this bias point.

Since VGS = 0 V, ID = IDSS.

E-MOSFET Biasing:
• In case of enhancement-only MOSFETs the VGS greater than the threshold value, VGS(th).

• There are two ways to bias an E-MOSFET, Drain-feedback bias and Voltage-divider bias.

• In the drain-feedback bias circuit there is

negligible gate current, so no voltage drop
across RG. As a result, VGS = VDS.

• For voltage divider bias,

Drain-feedback
Voltage-divider bias
Determine the amount of drain current?
JFET Amplifiers:
Self-biased-Common-Source (CS) Amplifiers:

Voltage Gain: Av= vout/vin

Input impedance:

• The input resistance is extremely high and is produced by the reverse-biased pn junction in a JFET and
by the insulated gate structure in a MOSFET.

• In the present circuit the actual input resistance seen by the signal source is the gate-to-ground
resistor RG in parallel with the FET’s input resistance, VGS/IGSS.

• JFET small-signal amplifier, the input signal that drives the gate should never reach a point at which
the gate-source junction is forward biased.
What is the total output voltage (dc + ac) of the amplifier?
If gm is 1800 S, ID is 2 mA, VGS(off) is -3.5 V, and IGSS is 15 nA, what is the input resistance seen by the
signal source?
Voltage divider-biased for E-MOSFET Common-Source (CS) Amplifiers:

• Because the drain current is zero when VGS = 0, the standard transconductance formula will not
work with the E-MOSFET.
• The drain current can be found by:
where k is a constant value for the E-MOSFET.
For the above circuit, find VGS, ID, gm, and Vout. The MOSFET specifications
are k= 104 x 10-3 A/V2, ID(on) =600 mA, and VGS(th) = 2.1 V.
Common-Drain (CD) Amplifier (Source Follower):

• The input signal is applied to the gate through a coupling capacitor, and the output is at the source
terminal. There is no drain resistor. This circuit is analogous to the bipolar emitter-follower and is
sometimes called a source-follower.

Voltage Gain:

Vout=IdRS Vin=Vgs+ IdRS