Finding the Pull-up network of CMOS Circuits

INEL 4207 - ECE Dept. - UPRM - M. Toledo February 9, 2011

The implementation of logic circuits require two networks, known as pull-up and pull-down, that force the output signal to reach the voltage levels that correspond to logic-1 and -0. CMOS circuits use complementary structures in which the pull-up and pull-down networks are implemented using P-MOSFETs and N-MOSFETs, respectively. The graph method allows us to, given the pull-down circuit, deduce the pull-up circuit. In the graph, connection points are represented by nodes and transistors are represented by arcs. To use the method, follow the following steps: 1. Draw the NMOS networks graph. 2. Place a new node inside every enclosed path of the graph. 3. Add new arcs to connect the new nodes, such that the new arcs intercept one and only one of the original arcs. 4. The new graph represent the PMOS circuit topology. Intercepting arcs identify the input logic signal for each transistor. The following example illustrates the method.
Diagram of pull-down circuit 3 Y A 1 B 0
4

Pull-down graph and derived pull-up graph 3 A C

C 2 D B 0 D 4 1 5 2 3

VDD 4

B 5 D

A B 5 C D 5 C Y A

3 Pull-up graph (rotated)

Diagram of pull-up circuit

Figure 1: Y = [AB + CD] Other examples follow. For simplicity, the node numbers have been excluded. 1

Y A C A C E B

VDD

A B B D D F E E F C Y

Figure 2: Y = ((A + C) ((B + D) E + F ))

VDD

Y A D C A D B E E C F

A D

E F F

C Y

Figure 3: Y = (F [A (B + DE) + C (E + BD)])

Y A F

A F D C

VDD B A

G I

B G

I E D

H C

E E

I Y

Figure 4: Y = (E (A (BC + DH) + F G (H + DBC) + I))