Differential Amplifiers (Chapter 8 in Horenstein)

Differential amplifiers are pervasive in analog electronics

Low frequency amplifiers
High frequency amplifiers
Operational amplifiers the first stage is a differential amplifier
Analog modulators
Logic gates
Advantages
Large input resistance
High gain
Differential input
Good bias stability
Excellent device parameter tracking in IC implementation
Examples
Bipolar 741 op-amp (mature, well-practiced, cheap)
CMOS or BiCMOS op-amp designs (more recent, popular)
R. W. Knepper
SC412, slide 8-1
Amplifier With Bias Stabilizing Neg Feedback Resistor
Single transistor common-emitter or common-source amplifiers often use a bias
stabilizing resistor in the common node leg (to ground) as shown below
Such a resistor provides negative feedback to stabilize dc bias
But, the negative feedback also reduces gain accordingly
We can shunt the common node bias resistor with a capacitor to reduce the negative
impact on gain
Has no effect on gain reduction at low frequencies, however
Large bypass capacitors are difficult to implement in IC design due to large area
Conclusion: try to avoid using feedback resistor R2 in biasing network
R. W. Knepper
SC412, slide 8-2
Differential Amplifier Topology
In contrast to the single device common-
emitter (common-source) amplifier with
negative feedback bias resistor of the
previous slide, the differential ckt shown at
left provides a better bypass scheme.
Device 2 provides bypass for active device 1
Bias provided by dc current source
Device 2 can also be used for input, allowing
a differential input
Load devices might be resistors or they
might be current sources (current mirrors)
The basic differential amplifier topology can
be used for bipolar diff amp design or for
CMOS diff amp design, or for other active
devices, such as JFETs
R. W. Knepper
SC412, slide 8-3
Differential Amplifier with Two Simultaneous Inputs
The differential amplifier topology shown at
the left contains two inputs, two active
devices, and two loads, along with a dc
current source
We will define the
differential mode of the input v
i,dm
= v
1
v
2

common mode of the input as v
i,cm
= (v
1
+v
2
)
Using these definitions, the inputs v
1
and v
2

can be written as linear combinations of the
differential and common modes
v
1
= v
i,cm
+ v
i,dm

v
2
= v
i,cm
v
i,dm

These definitions can also be applied to the
output voltages
Differential mode v
o,dm
= v
o1
v
o2
Common mode v
o,cm
= (v
o1
+ v
o2
)
Alternately, these can be written as
v
o1
= v
o,cm
+ v
o,dm


v
o2
= v
o,cm
v
o,dm

R. W. Knepper
SC412, slide 8-4
Bipolar Transistor Differential Amplifier
Q1 & Q2 are matched (identical) NPN
transistors
Rc is the load resistor
Placed on both sides for symmetry, but could be
used to obtain differential outputs
I
o
is the bias current
Usually built out of NPN transistor and current
mirror network
r
n
is the equivalent Norton output resistance of
the current source transistor
Input signal is switching around ground
V
ref
= 0 for this particular design
Both sides are DC-biased at ground on the base
of Q1 and Q2
v
BE
is the forward base-emitter voltage across
the junctions of the active devices
Since Q1 and Q2 are assumed matched, Io
splits evenly to both sides
I
C1
= I
C2
= I
o
/2
R. W. Knepper
SC412, slide 8-5
NPN Bipolar Transistor Physical Structure
Dual-Polysilicon Bipolar Transistor Features:
Two polysilicon layers
P+ for extrinsic base, N+ for emitter
Self-aligned with emitter window opening
Trench Isolation
Oxide lined, polysilicon filled
Shallow Trench Isolation (STI)
Isolate base/emitter active region from
collector reach-thru
N-type Pedestal Implant for high f
T
device
Self-aligned with emitter opening
Limits base push-out (Kirk Effect)
Highly doped extrinsic base lower R
b
Emitter (arsenic) diffused from N+ poly
SiGe Heterojunction BJT:
Typically 10-15% mole fraction of Ge
graded into intrinsic base region (as shown),
bandgap is narrowed in base, adding drift
component to electron velocity
R. W. Knepper
SC412, slide 8-6
Yaun Taur, Tak Ning
Modern VLSI Devicees
Bipolar Transistor Operation (1D Device)
BJT operation:
An external voltage (0.75-0.85 V) is applied
to forward-bias the emitter-base junction
Electrons are injected from the emitter into
the base comprising the majority of the
emitter current
Holes are injected from the base into the
emitter, as well, but their numbers are much
smaller, since N
D,e
>> N
A,b
Since X
B
<< L
n
in the base, most of the
injected electrons get to the collector
without recombining with holes. Any holes
that do recombine with electrons in the base
are supplied as base current.
Electrons reaching the collector are collected
across the base-collector depletion region.
Since most of the injected electrons reach
the collector and only a few holes are
injected into the emitter, or recombine with
electrons in the base, I
B
<< I
C
, implying that
the device has a large current gain.
R. W. Knepper
SC412, slide 8-7
Shown at left are the effects of
different NPN bias conditions
on the energy bands and the
electron concentrations:
(a) No bias (thermal equilibrium)
Fermi levels are flat
Electron concentration is N
D
in
emitter and collector and
n
i
2
/N
A
in the base
(b) both junctions reverse biased
Increased E-B & B-C barriers
Increase in depletion regions
Electron density in base = ~0
(c) both junctions forward biased
Reduced barrier heights
Electrons injected into base
from both emitter and collector
(d) forward-biased emitter, reverse-
biased collector
Small E-B/large C-B barriers
Electrons injected from emitter
Electron density = ~ 0 at C-B
junction and appears linear in
base region (small W
B
)
R. W. Knepper, SC412, slide 8-8
BJT Regions of Operation: Ebers-Moll DC Model
Jim Ebers and John Moll developed a
dc model for the bipolar transistor
which describes the four regions of
operation on the Vbe vs Vbc voltage
plot shown at the left
Forward active region:
Emitter-base forward biased,
collector-base reverse biased
Normal useful region for BJT
Current Gain | = ~ 100 typically
Reverse active region:
Collector-base forward biased,
emitter-base reverse biased
Transistor is being operated in the
inverse mode
Inverse | is usually small ~ 1 or < 1
Saturation region:
Both E-B and C-B forward biased
Base region is flooded with electrons
Cut-off region:
Both junction reverse biased
No current flow
R. W. Knepper
SC412, slide 8-9
(a) Both junctions are forward-biased the same amount.
No current flows even though the base is loaded with
charge (electrons).
(b) Saturation condition: both junctions forward
biased. Net electron flow from emitter to collector.
Ebers-Moll BJT DC Model Current Equations
The Ebers-Moll model may be used under all junction bias conditions (i.e., forward-
active, inverse, saturation, and cut-off) to estimate the terminal currents.
R. W. Knepper
SC412, slide 8-10
Bipolar Transistor Collector Characteristics
Shown below is a set of BJT (bipolar junction transistor) collector characteristics
I
C
versus V
CE
with I
B
as the parameter
The curves have several regions of operation
At low V
CE
both the emitter-base junction and the collector-base junction are forward-biased,
resulting in what is called saturation in the bipolar transistor
The base volume is flooded with mobile carriers injected from both E-B and C-B junctions
At higher (normal) V
CE
only the emitter-base junction is forward-biased, while the collector-
base junction is reverse-biased, resulting in the normal active (forward mode) region
The carrier concentration is pinned at zero (i.e. very small) at the collector junction, resulting in a
linear (triangular) distribution of charge in the base
Non-zero slope in normal active region is caused by base width narrowing due to increase in V
CB

reverse bias and corresponding increase in C-B depletion region (Early Effect named after Jim Early)
At even higher V
CE
the transistor enters the onset of avalanche breakdown at the CB junction
R. W. Knepper
SC412, slide 8-11
The non-zero slope in the forward mode
region is modeled, as shown below, with
a linear term V
CE
/V
A
, where V
A
is the
Early Voltage.
NPN DC Characteristics
Top left figure shows a set of collector
characteristics (common emitter) for base
current stepped from 0 to 30 uA for a SiGe
HBT with emitter area of 0.5 x 2.5 um
Very flat curves indicate Early voltage
greater than 70 volts.


Gummel plots showing log Ic and log Ib
versus V
BE
indicate excellent SiGe NPN
behavior and extremely low recombination
current at low V
BE
Beta remains constant at about 200 to V
BE
=
0.9 volt or higher
R. W. Knepper
SC412, slide 8-12
Harame, et al., IEEE Trans ED,
Vol. 48, No. 11, Nov. 2001
Definitions of f
T
and f
max
Cuttoff frequency f
T
can be defined as a series of time constants including base storage
time t
b
, emitter storage time t
e
, collector storage time t
c
, and several RC time constants
due to emitter and collector depletion capacitances and collector-to-substrate capacitance
R. W. Knepper
SC412, slide 8-13
IBM SiGe Design Kit Training: Technology, IBM
Microelectronics, Burlington, VT, July 2002
Normally the dominant
terms in order of
significance are the
base storage time t
b
,
emitter storage time t
e
,
and the depletion
charge terms
(kT/qIc)(Cje + Cjc)
For IBM SiGe NPN
technology the last
several terms are
usually negligible since
Re, Rc, and R
ns
are
small
SiGe NPN Bipolar | and f
T
versus Current
Plotted at left are the current gain | and f
T

versus collector current for two different
emitter width NPN transistors
Both | and f
T
drop off at high current density
due to base push-out (called the Kirk Effect)
When the number of injected electrons exceeds
the N type doping of the collector region, the
base-collector space charge region pushes all
the way to the heavily-doped N+ subcollector.
The use of a self-aligned collector pedestal N
implant raises the doping in the intrinsic
portion of the collector N epi and prevents base
push-out until very high current (<1 mA/um2)
Use of a self-aligned pedestal implant limits
the increase in C
cb
due to the higher collector
doping (which is only in the intrinsic portion of
the device)
The two curves in the plots are shifted by the
area of the emitter.
Using minimum width for the emitter improves
base resistance and therefore improves device
performance.
R. W. Knepper
SC412, slide 8-14
Harame, et al., IEEE Trans ED,
Vol. 48, No. 11, Nov. 2001
Bipolar Transistor Large-Signal & Small-Signal Models
Shown at the left is a simplified dc large-signal
BJT model for normal forward-mode only
The base-emitter junction is modeled as a diode
with base current I
B
as an exponential function of
base-emitter bias V
BE
The collector current I
C
is given simply as |
F
times
I
B
The emitter current I
E
is given by I
C
+ I
B
A small-signal ac bipolar model is
shown at the left:
The base-emitter junction is modeled as
a parallel RC combination C
be
(stored
charge in the base + B-E junction
capacitance) with r
t
(= kT/qI
B
= |
o
/g
m
)

The collector current is determined by
the transconductance term g
m
V
be
in
parallel with the output resistance r
o

The base resistance is modeled as r
b
Collector-to-base and collector-to-substrate
capacitances are shown
A simplified expression for f
T
(shown) can be
derived by setting ac current gain to unity
R. W. Knepper
SC412, slide 8-15
BJT SPICE Model Parameters
Typical SPICE circuit model parameters for a vintage 1 um silicon bipolar technology are
given below (from Johns and Martin, Analog Integrated Circuit Design, 1997, p. 65)
The f
T
would be about 13 GHz, based on the forward base transit time t
F
of 12 ps
Reverse current gain-bandwidth product would be about 40 MHz based on t
R
of 4 ns
R
b
of 500 ohms and C
cb
of 18 fF suggest a relatively low f
max
of about 7-8 GHz
f
max
= [f
T
/ 8tR
b
C
cb
]

R. W. Knepper
SC412, slide 8-16
Small-Signal Model Analysis for Single Input Diff Amp
Consider transistor Q2 with grounded base
dc small-signal model shown in top-left figure
Use the test voltage approach to calculate Q2s
input impedance looking into emitter
Using KCL equations, we can write
i
test
= v
test
/r
t
|
o
i
b2
where i
b2
= - v
test
/r
t

Rearranging and solving for v
test
/i
test
, we have
r
th2
= v
test
/i
test
= r
t
/(|
o
+ 1) = ~ r
t
/|
o
= 1/g
m2
Generally g
m2
is large, causing r
th2
to act like an
ac short
Consider transistor Q1 with Q2 replaced by r
th2
Since r
th2
is much smaller than r
n
(output
impedance of Io), we will neglect r
n
Writing KCL, we have
v
in
= i
b1
r
t1
+ i
b1
(|
o
+ 1) r
th2
= i
b1
2 r
t1

where we assumed r
t1
= r
t2

We can now find vout as a function of vin
v
out
= - i
c1
R
c
= - |
o
i
b
Rc = - |
o
v
in
Rc/2r
t1
= - g
m
R
c
v
in
where we have used g
m
= |
o
/r
t1

Small signal gain A
v
= v
out
/v
in
= - g
m
R
c

R. W. Knepper, SC412, slide 8-17
Bipolar Diff Amp with Differential Inputs
At left is a bipolar differential amplifier schematic
having two inputs that are differential in nature, i.e.
equal in magnitude but opposite in phase
The differential input v
1
v
2
= v
a
(t) (-v
a
(t)) = 2v
a
(t)
The common mode input = [v
a
+ (-v
a
)]/2 = 0
A small-signal model for the diff amp is shown
below, where the Tx output collector resistance r
o
is
assumed to be >> R
C
(in parallel) and is neglected
We can derive the small-signal gain due to the
differential input by applying KVL to loop A
v
a
(t) (-v
a
(t)) = 2v
a
(t) = i
b1
r
t1
i
b2
r
t2
= 2i
b1
r
t

since i
b1
= -i
b2
and r
t1
= r
t2

Or, i
b1
= v
a
(t)/r
t
and i
b2
= - v
a
(t)/r
t

R. W. Knepper
SC412, slide 8-18
Bipolar Diff Amp with Differential Inputs (continued)
Solving for the output voltages we can obtain
v
o1
= -i
c1
R
C
= - |
o
i
b1
R
C
= - (|
o
/r
t
)v
a
(t)R
C
and v
02
= + (|
o
/r
t
)v
a
(t)R
C

We can now find the gain with differential-mode input and single-ended output or with
differential-mode input and differential output
A
dm-se1
= v
01
/v
idm
= -g
m
R
C
/2 and A
dm-se2
= + g
m
R
C
/2
A
dm-diff
= (v
01
v
02
)/ v
idm
= - g
m
R
C
Since corresponding currents on the left and right side of the differential small-signal
model are always equal and opposite, implying that no current ever flows throw r
n
Node E acts as a virtual ground
If the output resistances of Q1 and Q2 are low enough to require keeping them in the
analysis, we simply replace R
C
with the parallel combination of R
C
||r
o
for transistor Q1
and Q2
R. W. Knepper
SC412, slide 8-19
Small-Signal Model of BJT Diff Amp with CM Inputs
The figure below is the small-signal model for the diff amp with common-mode inputs
v1 = v2 = v
b
(t) and v
icm
= (v1 + v2) = v
b
(t)
The common-mode currents from both inputs flow through rn as shown by the two loops
i
n
= 2(|
o
+ 1) i
b1
= 2 (|
o
+ 1) i
b2
and therefore, v
b
= i
b
r
t
+ 2(|
o
+ 1)i
b
r
n
or i
b
= v
b
/[r
t
+ 2(|
o
+ 1)r
n
]
The collector voltages can be found as
v
01
= v
02
= - |
o
R
C
v
b
/[r
t
+ 2(|
o
+ 1)r
n
] = ~ - g
m
R
C
v
b
/ [1 + 2g
m
r
n
]
The common-mode gain with single-ended output is given by
A
cm-se1
= A
cm-se2
= v
o1
/v
icm
= v
o2
/v
icm
= - g
m
R
C
/[1 + 2g
m
r
n
] = ~ -R
C
/2r
n
The common-mode gain with differential output is A
cm-diff
= (v
o1
v
o2
)/v
icm
= 0
Do Example 8.1, p. 488
R. W. Knepper
SC412, slide 8-20
BJT Diff Amp Circuit with Both Diff & CM Inputs
The example below illustrates the principle of superposition in dealing with both
differential mode and common mode inputs to a diff amp
v
1
= v
x
cos e
1
t + v
y
sin e
2
t and v
2
= v
x
cos e
1
t v
y
sin e
2
t
Using the definitions of differential mode and common mode inputs, respectively,
v
idm
= v1 v2 = 2v
y
sin e
2
t and v
icm
= (v1 + v2)/2 = v
x
cos e
1
t ,
we can obtain
v
o1
= A
dm-se1
v
idm
+ A
cm-se1
v
icm
= - |
o
R
C
[(v
y
/ r
t
) sin e
2
t + (v
x
/{r
t
+ 2 (|
o
+ 1) r
n
}) cos e
1
t]
The expression for v
02
is similar except that the first term (differential mode) has a minus sign
Note that the common mode output is reduced by the factor (|
o
+ 1) in the denominator
R. W. Knepper
SC412, slide 8-21
Common-Mode Rejection Ratio
In a differential amplifier we typically want to amplify the differential input while, at
the same time, rejecting the common-mode input signal
A figure of merit Common Mode Rejection Ratio is defined as
CMRR = |A
dm
|/|A
cm
|
where A
dm
is the differential mode gain and A
cm
is the common mode gain
For a bipolar diff amp with differential output, the CMRR is found to be
CMRR = |A
dm-diff
|/|A
cm-diff
| = |- g
m
R
C
| / 0 = infinity
In the case of the bipolar diff amp with single-ended output, CMRR is given by
CMRR = |A
dm-se
|/|A
cm-se
| = | g
m
R
C
| / | |
o
R
C
/[r
t
+ 2(|
o
+ 1)r
n
]|
= [r
t
+ 2(|
o
+ 1)r
n
]/2r
t
= ~ |
o
r
n
/r
t
= g
m
r
n
= I
C
r
n
/qV
T

= I
o
r
n
/2qV
T

since |
o
= g
m
r
t
and V
T
is defined as kT/q
CMRR is often expressed in decibels, in which case the definition becomes
CMRR = 20 log (|A
dm
|/|A
cm
|)

R. W. Knepper
SC412, slide 8-22
BJT Diff Amp Input and Output Resistance
Input Resistance:
For differential-mode inputs, the input resistance can be found as
r
in-dm
= (v1 v2)/i
b1
= (v
a
(-v
a
)) / (v
a
/r
t
) = 2v
a
r
t
/v
a
= 2r
t

For common-mode inputs, the input resistance is quite different
r
in-cm
= (v1 + v2)/i
b1
= v
b
/ [v
b
/(r
t
+ 2(|
o
+ 1)r
n
)] = r
t
+ 2(|
o
+ 1)r
n

Output Resistance:
For differential outputs, we can use the test voltage method (below) for deriving the output
resistance where all inputs are set to zero
Since i
b1
and i
b2
are both zero, we have i
test
= v
test
/(R
C
+ R
C
) = v
test
/2R
C
or r
out-diff
= 2R
C
For single-ended outputs, r
out-se
= R
C
|| r
o
= ~ R
C
R. W. Knepper
SC412, slide 8-23
Bipolar Diff Amp Biasing Considerations
A bipolar differential amplifier with ideal
current source and resistor loads is shown
It is assumed that components are matched
sufficiently such that bias current Io is split
evenly between the left and right-hand legs
Node E will take a voltage value such that
I
C1
= I
C2
= Io/2 when v1 = v2 = 0
By using the Ebers-Moll dc model for the
NPN transistors, we can determine the voltage
at node E
I
E
= I
EO
[exp (qV
BE
/qkT) 1]
= I
EO
exp (qV
BE
/qkT)
= Io/2
or, V
BE
= (qkT/q) ln (I
E
/I
EO
)
Typically, V
BE
= 0.75-0.85 V in modern NPN
transistors
It is important to design R
C
such that v
out

never drops so low so as to force Q1 or Q2
into saturation.
R. W. Knepper
SC412, slide 8-24
BJT Diff Amp with Simple Resistor Current Source
The simplest approach to building a current
source is with a resistor
Given that node E is one V
BE
drop below
GND, we can choose R
E
to provide the
desired bias current I
o
R
E
= (0 V
BE
V
EE
) / Io
Preventing saturation in Q1 and Q2
provides an upper bound for R
C
R
C
~ < (V
CC
0)/(Io/2) = 2 V
CC
/ Io
Look at Example 8.3 in text.
Do problem 8.31 in class.
R. W. Knepper
SC412, slide 8-25
Example 8.3: Diff Amp with Complete Bias Design
Design Conditions
Differential-mode, single-ended gain > = 50
Common-mode, single-ended gain < = 0.2
Completed design is shown above
In class Exercise: 8.4, 8.5, & 8.6
R. W. Knepper
SC412, slide 8-26
BJT Diff Amp with BJT Current Source
The expression for common-mode gain on slide
8-20 (-R
C
/2r
n
) shows that in order to reduce A
cm
,
we want to make the effective impedance of the
current source very high
Using a resistor to generate the current source
limits our design options in making r
n
(R
E
in this
case) high
An alternate method of generating Io is to use an
NPN transistor current source similar to that
shown at the left
Q3 is an NPN biased in the forward active region
so that r
n
(given by the inverse slope of the
collector characteristics) is very high
RA and RB form a voltage divider establishing
V
B
= V
EE
x RA/(RA + RB) where V
EE
is <0
The voltage across RE can be used to find Io
V
RE
= V
B
V
f
V
EE
Io = (V
B
V
f
V
EE
)/RE is the bias current
provided to the diff amp
R. W. Knepper
SC412, slide 8-27
Small Signal Model of BJT Current Source Transistor
Find the small-signal resistance looking into
the collector of Q3 on slide 8-27 diff amp
If R
E
were = 0, then the solution becomes
simply r
o
, since the incremental base current i
b3

would, in fact, be 0
With a finite feedback resistor R
E
, we need to
use KVL and KCL to derive an expression for
r
n
(See Example 8.4 in text)
Apply a test current i
test
and find v
test
Obtain v
t3
by applying KVL to the 3 left-most
resistors to obtain i
b3
and multiply by r
t3

v
t3
= -i
test
R
E
r
t3
/[R
E
+ r
t3
+ R
P
]
If we multiply this result by g
m3
and substract
from i
test
, we obtain i
o3
which can be used to
find v
o3
by multiplying by r
03
v
o3
= i
test
{1 + g
m3
R
E
r
t3
/[R
E
+ r
t3
+ R
P
]}r
o3
v
e
can be found as (i
test
+ i
b3
) x R
E
v
e
= i
test
(r
t3
+ R
P
) R
E
/(R
E
+ r
t3
+ R
P
)
Adding v
o3
+ v
e
= v
test
, we obtain r
n
= v
test
/i
test

r
n
= R
E
|| (r
t3
+ R
P
) + r
03
[1 + |
o
R
E
/(R
E
+ r
t3
+R
P
)]
Do Exercise 8.8 and 8.9 in class.
R. W. Knepper
SC412, slide 8-28
Bipolar Current Mirror Circuit
A method used pervasively in analog IC design to generate a current source is the current
mirror circuit
In the bipolar design arena, the method is as follows:
A reference current is forced through an NPN transistor connected as a base-emitter diode (base
shorted to collector), thus setting up a V
BE
in the reference transistor
This V
BE
voltage is then applied to one or more other identical NPN transistors which sets up
the same current I
ref
in each one of the bias transistors
As long as the bias transistor(s) is (are) identical to the reference transistor, and as long as the
bias transistor(s) is maintained in its normal active region (where collector current is
independent of the collector-emitter voltage), then the current in the bias transistor(s) will be
identical to the current in the reference transistor.
Variations on the basic current mirror circuit can be used to generate 2X or 3X or maybe
10X the original reference current by using several bias NPN transistors in parallel
Or alternately, by using an emitter that has 2X or 3X or 10X emitter stripes and is otherwise
identical to the reference transistor
Advantages
One reference current generator can be used to provide bias to several stages
Very high incremental output impedance can be obtained from the current mirror
The technique can be used in both bipolar and in CMOS/BiCMOS technologies
R. W. Knepper
SC412, slide 8-29
Bipolar Current Mirror Bias Circuit Design
Design procedure:
Given R
A
and the I
C
vs V
BE

characteristics of the NPN
reference device, we can
determine I
A
, or
Given the desired I
A
and the
I
C
vs V
BE
characteristics of
the NPN reference device,
we can choose R
A
R. W. Knepper
SC412, slide 8-30
We can find I
A
by dividing the voltage drop across R
A
by the resistance value
I
A
= (V
CC
V
BE1
V
EE
) / R
A
Assuming that the two base currents are small, we can say I
A
= I
ref
Because of the current mirror action, the V
BE1
set up in Q1 to sustain current I
ref
will be equal
to V
BE2
, the base-emitter voltage in Q2
Therefore, Io = I
ref
= I
A
Note: corrections for I
B1
and I
B2
can easily be made is needed
Note 2: Q2 must be maintained in its forward active region

BJT Diff Amp with Current Mirror Bias (Ex. 8.5)
Design Objectives:
Diff amp with 1.5 mA in each leg
5V drop across load resistors
VCC = +10V, VEE = -10V
Design Procedure:
Set Io = I
A
= 3 mA
R
A
= (0 V
BE
= V
EE
)/3mA = 3.1K
where we used V
BE
= 0.7 volt
RC1 & RC2 can be found as follows:
RC1 = RC2 = 5V/1.5 mA = 3.3K
Check V
CE
of Q2, Q3, and Q4 to see if
they are in normal active region
V
C
= VCC 1.5 mA x 3.3K = 5V
V
E
= 0 V
BE
= -0.7V
V
CE
= 5 (-0.7) = 5.7V for Q2 and Q3
For Q2 VCE = -0.7V (-10) = -9.3V
Calculate power in each device
P
Q3
= P
Q4
= 1.5mA x 5.7V = 8.6 mW
P
Q2
= 3 mA x 9.3V = 28 mW
P
Q1
= 3 mA x 0.7V = 2.1 mW
R. W. Knepper
SC412, slide 8-31
BJT Current Mirror Feeding 2-stage Diff Amp
The example below shows a 2-stage bipolar diff amp fed from two current sources with a
single current mirror
Reference current 0.93mA is determined by placing (0 V
BE
V
EE
) across a 10K bias resistor
The reference current is used for the first differential stage with 0.47 mA on each leg
The second differential stage is to have double the bias current of the first stage
This is accomplished by using two bias NPN transistors in parallel giving 1.86 mA bias current with 0.93
mA flowing on each leg (Q7 and Q8)
Check the VCE of each device to check for normal active region and calculate power in circuit.
R. W. Knepper
SC412, slide 8-32
The total circuit power is found
by computing the sum of the
three current source currents
multiplied by the source-sink
voltage differential for each.
Q1: 0.93mA x 10V = 9.3mW
Q2: 0.93mA x 20V = 18.6mW
Q3/Q4: 1.86mA x 20V = 37.2
mW
Total circuit power = 65.1 mW
Bipolar Widlar Current Source
A special use of the current mirror is the Widlar
Current Source (shown at left)
A resistor in the emitter of Q2 is used to reduce the
current Io in Q2 to a value less than that in Q1
Io can be set to a very small value by increasing the
R2 value
Design procedure:
As in the standard current mirror, we can find I
ref
as
follows:
I
ref
= (V
CC
V
EE
V
BE1
)/R
A
But, in contrast to the standard current mirror, V
BE2

will not be equal to V
BE1
V
BE1
= V
BE2
+ I
E2
R
2
Using the Ebers-Moll model for emitter current
I
E
= I
EO
(exp[V
BE
/qV
T
] 1) = ~ I
EO
exp[V
BE
/qV
T
]
We can invert this expression and insert it into the
above equation for V
BE1
to obtain
I
E2
= (qV
T
/R
2
) ln(I
E1
/I
E2
) = Io = (qV
T
/R
2
) ln(I
ref
/I
o
)
Since this is not a closed form solution, an iterative
approach can be used to solve for Io by starting with
a best guess.

R. W. Knepper
SC412, slide 8-33
Example iteration procedure:
Assume that Iref = 1 mA and R2 = 500 ohms.
Guess Io inside ln term. Find LHS Io.
1. Initial guess = 0.5 mA, then Io = 0.036mA
2. Try a guess of 0.2 mA, then Io = 0.083mA
3. Try a guess of 0.1mA, then Io = 0.119mA
4. Try a guess of 0.11mA, then Io =
0.114mA Close enough!!
Small-Signal Model for Widlar Current Source Q1
The incremental output impedance (looking into Q2 collector) of Widlar Current Source is
similar to the expression derived for the BJT current source (slide 8-28) except that RP
must be replaced by the incremental resistance at the base of Q1
From the model below, the incremental resistance at the base of Q1 is given by
r
t1
|| 1/g
m1
|| r
o1
|| R
A
= ~ [r
t1
/(|
o1
+ 1)] || R
A
Thus, the output impedance seen looking into the collector of the Widlar Current Source is given
by
r
n
= R
2
|| (r
t2
+ R
P
) + r
02
[1 + |
o2
R
2
/(R
2
+ r
t2
+R
P
)]
where the above expression is to be used in place of R
P
However, with a number of approximations and using the relation I
o
R
2
/qV
T
= ln (I
ref
/I
o
),
the expression may usually be simplified to
r
n
= r
02
[1 + ln (I
ref
/I
o
)]
Look over Example 8.9 in text.
R. W. Knepper
SC412, slide 8-34
NMOS Differential Amplifier Circuit
Shown below is a differential amplifier circuit built with NMOS technology
Q1 and Q2 comprise the diff amp active gain transistors
fed by a current mirror Q7 and Q5
Q3 and Q4 are NMOS enhancement mode saturated loads
Q6 and Qref are used for biasing the NMOS current mirror
Current Io is presumed to split equally on the left and right legs of the diff amp
The voltage rails are now called VDD and VSS
Before going into the biasing and small signal models, we will take a look at MOSFET
devices and models
R. W. Knepper
SC412, slide 8-35
MOSFET Transistor DC Current Modes
DC Current Modes:
Cut-off: V
gs
V
T
I
ds
= 0 (interface is depleted)
Linear Region: V
gs
> V
T
, V
gs
V
T
> V
ds
I
ds
= |
N
V
ds
(V
gs
V
T
V
ds
/2)
interface is inverted and not pinched off at
drain (Fig. a)
Pinch-off Point: V
gs
> V
T
, V
ds
= Vdsat
channel pinches off at the drain junction
simple theory: Vdsat = V
gs
V
T
(Fig. b)

Saturated Region: V
gs
> V
T
, V
gs
V
T
< V
ds
I
ds
= |
N
(V
gs
V
T
)
2

interface is inverted and pinched off at drain
further increase in Vds occurs across pinch-
off depletion region (Fig. c)
|
N
=
N
C
ox
(W/L)
N
where
N
is the mobility of
electrons in the channel, C
ox
is the gate
capacitance per unit area, W is the device width
and L is the device effective channel length
R. W. Knepper
SC412, page 8-36
MOSFET DC Characteristics: linear vs saturation

If the linear Ids expression from the previous chart is plotted with increasing Vds, one
observes a maximum at Vds = Vgs Vt after the current reduces in a parabolic fashion.
In fact, the charge in the channel Q
n
(y) goes to zero at Vds = Vgs Vt
The voltage V
ds
= V
gs
V
t
= V
dssat
is the pinch-off voltage where the channel pinches
off at the drain junction.
Further increase in Vds simply increases the voltage between the drain and the channel pinch-
off point, and does not increase the voltage V(y) along the channel.
Therefore, I
DS
remains constant for further increases in Vds and we say the device is in
the saturation region (or active region) with
I
DS
= n C
ox
(W/L) (Vgs Vt)
2

R. W. Knepper
SC412, slide 8-37
The transconductance in saturation
can be found by differentiating the
expression for I
DS
with Vgs, giving
g
m
=
n
C
ox
(W/L) (Vgs Vt)
= [2
n
C
ox
(W/L) I
DS
]

I
DS
versus V
DS
for A Real Device
Channel length modulation:
As V
DS
increases, in fact, there is some non-zero slope on the I
DS
vs V
DS
characteristic
The increase in I
DS
with V
DS
is caused by a shortening of the effective channel length
L
eff
with increasing V
DS
due to an increase in the depletion region thickness from the
channel tip to the drain junction
Substituting for L, from the expression for the thickness of an abrupt junction (with a square
root dependence on reverse biased voltage), one can obtain a modified expression for the
current I
DS
in saturation (active region) as shown below.
From this new expression one can derive an expression for the output drain-source
resistance of the NMOS transistor in the saturation region as
r
ds
= 1/(dI
DS
/dV
DS
) = 1/(I
DS
)

where is defined below and k
ds
= [2c
SI
c
o
/qN
A
]

R. W. Knepper
SC412, slide 8-38
MOSFET Capacitance Model
The MOSFET capacitances (gate-to-
source, gate-to-drain, gate-to-substrate,
source-to-substrate, and drain-to-
substrate) are illustrated in the drawing at
left and summarized in the table below
C
ov
is an overlap capacitance due
primarily to lateral diffusion of the source
and drain junctions, but also includes
fringing capacitance
C
ov
=~ 2/3 C
ox
W x
j
where x
j
is the junction depth
The gate-to-channel capacitance is evenly
divided between source and drain in the
linear (triode) region, but is effectively
connected only to the source at pinchoff
Integration of the channel charge shows
that only 2/3 of Cgc becomes part of Cgs
in the saturation (active) region
A similar reasoning is used to partition
Ccx (C
CB
in picture) between Csx and Cdx
Cgx (gate-to-substrate) is zero when Vgs
> Vt, but increases to C
ox
W(L - 2AL) in
the accumulation region.
R. W. Knepper
SC412, slide 8-39
MOSFET High Frequency Figures of Merit
Unity gain bandwidth product f
T
(frequency where current gain falls to 1):
Assume that a small signal sinusoidal source v
GS
= V
p
sin(et) is applied to the gate
Input current is given by i
G
= C
G
(dv
GS
/dt) = C
G
e V
p
cos(et) = (Cgs + Cgd) e V
p
cos(et)
Output current is given by i
DS
= g
m
v
GS
from the definition of g
m

If we write the magnitude of the ac current gain, we have
|i
DS
/i
G
| = |g
m
v
GS
/ (Cgs + Cgd)eV
p
cos(et)| = g
m
/e(Cgs + Cgd)
Where we have replaced V
p
cos(et) with v
GS
since we are using only the magnitudes
Setting the magnitude of the current gain to unity, we obtain
f
T
= g
m
/2t(Cgs + Cgd)
Because of the manner in which it is derived, f
T
neglects series gate resistance r
g
and
capacitance on the output, such as Cgd.
Unity power gain bandwidth product f
max
(frequency where power gain falls to 1):
A useful expression for the unity power gain point f
max
is given by
f
max
= [f
T
/ 8tr
g
C
gd
]

These figure of merits are useful for technology comparisons and are also often used
in high frequency amplifier design
R. W. Knepper
SC412, slide 8-40
Long-Channel versus Short-Channel Considerations
Consider the current gain bandwidth product f
T
as a function of device parameters:
f
T
= g
m
/ 2tC
gs
=
n
C
ox
(W/L)(Vgs Vt) / (2/3)WLC
ox
= 1.5
n
(Vgs Vt) / L
2
where we have assumed the gate capacitance is predominantly the Cgs portion
Note that f
T
increases with small L (inverse with L
2
) and with increasing Vgs
This is a result based only on a long-channel assumption.
As the channel shortens, the electric field increases beyond the point where mobility is
constant any longer (typical of todays advanced CMOS technology)
Scattering of electrons by optical phonons causes the drift velocity to saturate at about 1E7
cm/sec, occurring at an electric field E
sat
= ~ 1E4 V/cm.
Beyond this point further increases in E field result in diminishing increases in carrier velocity
This effect represents itself in the I
DS
current equation by a reduction in Vds
sat
below Vgs Vt
thus reducing I
DSsat
to less than
n
C
ox
(W/L)(Vgs Vt)
2
If we redefine Vdsat to be determined by the minimum of (Vgs Vt) and LE
sat
(i.e. sort of
having (Vgs Vt) and LE
sat
in parallel), we can write
Vdsat = [(Vgs Vt)(LE
sat
)] / [(Vgs Vt) + (LE
sat
)]
We can then rewrite the current equation as
I
DS
=
n
C
ox
(W/L)(Vgs Vt)(Vdsat) = WC
ox
(Vgs Vt) v
sat
[1 + LE
sat
/(Vgs Vt)]
1

where v
sat
is the saturation velocity given by
n
E
sat
and
n
is the low field mobility
At short L, the equation becomes I
DS
=
n
C
ox
W(Vgs Vt)E
sat
which is independent of L

R. W. Knepper
SC412, slide 8-41
Small Signal Model for a MOSFET
The main contribution to the output current is the source g
m
v
gs
and is given by the
expression below
The current source g
s
v
sx
is due to the possibility that the source and substrate (bulk)
voltages may not be the same.
g
s
= I
DS
/V
SX
= g
m
/ [2(V
sx
+ |2|
F
|)

]
where = [{2qcN
A
}]/C
ox
and 2|
F
is the band bending at strong inversion (from Vt equation)
In essence g
s
is a back-gate transconductance which contributes current due to bulk-charge
voltage change
r
ds
accounts for the finite output impedance and is given by
r
ds
= 1 / I
DS

where is the output impedance constant (defined on slide 8-38)
R. W. Knepper
SC412, slide 8-42
MOSFET SPICE Model
Level 3 SPICE model parameters are
shown in the table at the left.
The following parameters are given in
text for a 0.5 um technology:
(PMOS in parentheses if different than NMOS)
PHI=0.7, TOX=9.5E-9, XJ=0.2U
TPG=1 (-1), VTO=0.7 (-0.95)
DELTA=0.88(0.25), LD=5E-8 (7E-8)
KP=1.56E-4 (4.8E-5), UO=420 (130)
THETA=0.23 (0.20), RSH=2.0 (2.5)
GAMMA=0.62 (0.52)
NSUB=1.4E17 (1.0E17)
NFS=7.2E11 (6.5E11)
VMAX=1.8E5 (3E5)
ETA=0.02125 (0.025)
KAPPA=0.1 (8)
CGDO=CGSO=3.0E-10 (3.5E-10)
CGBO=4.5E-10, CJ=5.5E-4 (9.5E-4)
MJ=0.6 (0.5), CJSW=3E-10 (2E-10)
MJSW=0.35 (0.25), PB=1.1 (1.0)
R. W. Knepper
SC412, slide 8-43
MOSFET Transistor at Threshold (N-FET)
MOSFET with Vgs > V
T
causes formation of a channel (inversion layer)
connecting source to drain
With Vds > 0, a positive current I
ds
flows from drain to source (N-FET)
Depletion layer exists from source, drain, & channel N region to P substrate
At Vgs = V
T
, bands are bent by |2|
F
| at oxide-silicon interface
Threshold definition (by summation of charges in gate, oxide, channel, and bulk:
V
TN
= - Q
fc
/C
ox
+ \{2qcN
A
(2|
F
+ V
sx
)}/C
ox
+ |
MS
+ 2|
F
for N-FETs
V
TP
= - Q
fc
/C
ox
- \{2qcN
A
(|2|
F
+ V
sw
|)}/C
ox
+ |
MS
+ |2|
F
| for P-FETs
R. W. Knepper
SC412, page 8-44
Kang & Leblebici, CMOS Digital
Integrated Circuits, 1999
CMOS NFET and PFET Transistors
V
TN
= - Q
fc
/C
ox
+ {2qcN
A
(2|
F
+ V
sx
)}/C
ox
+ |
MS
+ 2|
F
for N-FETs
V
TP
= - Q
fc
/C
ox
- {2qcN
A
(|2|
F
+ V
sw
|)}/C
ox
+ |
MS
+ |2|
F
|

for P-FETs
gate
N+
N +
oxide
source drain
N
P substrate
N channel device
gate
P+ P+
P channel device
N well
oxide
drain
source
R. W. Knepper
SC412, page 8-45
Threshold Voltage is a square root function of source-
to-substrate per chart at left. Applies to both N and P
devices using |V
sx
+2|
F
|
Implications for circuit applications where the source
voltage rises significantly above ground potential.
DC Bias Considerations for NMOS Diff Amp
It is desired to design the NMOS diff amp (below) with device symmetries in such a way
that V
DS3
= V
DS4
= V
DSref
Since I
o
/2 = I
ref
/2 flows through Q3 and Q4, and since Q
ref
, Q3, and Q4 are all biased in their
saturation (active) regions where I
DS
=
n
C
ox
(W/L)(V
GS
V
T
)
2
= K(V
GS
V
T
)
2
, we can
obtain V
GS3
= V
GS4
= V
GSref
if W
3
= W
4
= W
ref
This condition will be met independent of other device parameter values as long as their ratios remain
fixed, i.e. good tracking between devices exists
Assuming that the W of Q6 and Q7 are identical to that of Qref, then we can see that the above
current equation will require that V
GS6
= V
GS7
= V
GSref
= 1/3 (V
DD
V
SS
), where we have
neglected any dependence of V
T
on Vsx.
R. W. Knepper
SC412, slide 8-46
If we set the current in Q3 to that in Qref,
we can obtain the following expression
V
DS3
= o(V
DD
V
SS
)/3 + [1 - o]V
T
where o = (K
ref
/2K
pu
)

Thus, setting Kref = 2Kpu leads to
V
DS3
= 1/3 (V
DD
V
SS
)
or V
out1
= V
DD
V
DS3
= 2/3 V
DD
+ 1/3 V
SS
Modified MOSFET Current Mirror Reference Ckt
At left is a modified current mirror reference
circuit in which four saturated NMOS transistors
split the voltage between VDD and VSS
Assuming that each transistor is designed with the
same W/L ratio, the reference device V
DS
will be
of V
DD
V
SS

Assuming we design transistor Q3 with the W of
Q
ref
(as on the previous chart), then we will have
V
DS3
= (V
DD
V
SS
) and Vout1 = (3V
DD
+ V
SS
)/4
For n reference devices in series, we can generalize
the above to
Vout1 = [(n-1)/n]VDD + VSS/n
Exercises 8.15 and 8.16
R. W. Knepper
SC412, slide 8-47
Small-Signal Model for the NMOS Diff Amp Ckt
The small signal model below is the starting point for deriving the gain expressions for the
NMOS differential amplifier
Each transistor is modeled by the gate transconductance current source, the back-gate
transconductance current source, and the incremental ac impedance of the device in saturation
Note the opposite direction of the back-gate (body effect) term is due to the use of bulk-to-source voltage
rather than source-to-bulk voltage
The current mirror current source is modeled simply by its output impedance (in saturation)
Each transistor is presumed to be in its saturation (constant current) region
R. W. Knepper
SC412, slide 8-48
Small-Signal Model for NMOS Diff Amp Load Imp
We can simplify the equivalent circuit of
the previous chart by replacing the load
transistors by their Thevenin equivalent
resistance looking into their source nodes.
Using the test voltage method (shown at
left), we can obtain
r
th
= 1/[g
m
+ g
mb
+ (1/r
o
)]
= [1/g
m
(1 + X)] || r
o
where g
mb
= Xg
m

and X = {(2c/qN
A
)/(Vsx + 2|
F
)}

Generally we can assume X = 0.2, I.e. the
back-gate (body) effect adds about 20% to
the gate transconductance (if we define the
voltage as bulk-to-source) or reduces the
gate transconductance about 20% (using the
voltage as source-to-substrate).
With the above approximation for the load
device, we can simplify the NMOS diff
amp incremental model to that shown on
the following slide
R. W. Knepper
SC412, slide 8-49
Simplified Small-Signal Circuit Model of NMOS Diff Amp
Differential mode gain can be found from the small signal circuit below
A
dm-se1
= -A
dm-se2
= - g
m1
[(1/g
m3
(1 + X3)) || r
o3
|| r
o1
]
A
dm-diff
= - g
m1
[(1/g
m3
(1 + X3)) || r
o3
|| r
o1
] and g
m
= [2
n
C
ox
(W/L) I
DS
]

where we have assumed matched pairs Q1 & Q2 and Q3 & Q4
Resistances r
01
and r
03
are often large enough to be neglected relative to 1/gm
Common mode gain can also be found from the small signal circuit below
A
cm-se1
= A
cm-se2
= -g
m1
r
th3
/[1 + 2r
o5
g
m1
(1 + X
1
)]
= ~ r
th3
/2r
o5
(1 + X
1
)
Input impedance is assume to be infinite
Output impedance is given by
r
out-se
= r
th3
= 1/g
m3
(1 + X
3
) and r
out-diff
= 2/g
m3
(1 + X
3
)
R. W. Knepper
SC412, slide 8-50
Generic CMOS Differential Amplifier
A simple version of a CMOS differential
amplifier is shown at the left
The load devices Q3 and Q4 are built with
PMOS transistors
Q3 and Q4 operate as a form of current
mirror, in that the small signal current in Q4
will be identical to the current in Q3
Q3 has an effective impedance looking into
its drain of 1/g
m
|| r
o3
since its current will be
a function of the voltage on node vd1
Q4 has an effective impedance looking into
its drain of r
o4
only, since its current will be
constant and not a function of v
out
The gain of the right hand (inverting) leg
will be higher than the gain of the left side
Since all transistors have grounded source
operation, there is no body effect to worry
about with this CMOS diff amp circuit
R. W. Knepper
SC412, slide 8-51
CMOS Diff Amp Equivalent Circuit Model

R. W. Knepper
SC412, slide 8-52
CMOS Diff Amp with Current Mirror Sources

R. W. Knepper
SC412, slide 8-53
BiCMOS Differential Amplifier

R. W. Knepper
SC412, slide 8-41
Small Signal Model of BiCMOS Diff Amp

R. W. Knepper
SC412, slide 8-41
BiCMOS Diff Amp with Cascode BJT EF Devices

R. W. Knepper
SC412, slide 8-41
JFET Differential Amplifier Circuit

R. W. Knepper
SC412, slide 8-41
Large Signal Analysis of Bipolar Diff Amp

R. W. Knepper
SC412, slide 8-41
Large Signal Analysis of MOSFET Diff Amp

R. W. Knepper
SC412, slide 8-41
Large Signal Analysis of CMOS Diff Amp

R. W. Knepper
SC412, slide 8-41
Bipolar Diff Amp DC Design Analysis

R. W. Knepper
SC412, slide 8-41
Bipolar Diff Amp DC Design Example 8.11

R. W. Knepper
SC412, slide 8-41
NMOS Diff Amp SPICE Simulation Example

R. W. Knepper
SC412, slide 8-41

R. W. Knepper
SC412, slide 8-41