Decoder

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Decoder
3 - 8 Binary Decoder
Decoders are used to decode data that has been previously encoded using a binary, or possibly other, type of coded format. The models of a 3 - 8 binary decoder conform to the truth table below:

inputs outputs A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Models can use if, case and for statements. The case statement is commonly used because of its clarity, and the fact that it is not a continuous assignment and so may simulate faster. As input and output bit widths increase, it is more code efficient to use for loop statement. Only for model is shown here. Other models are left to reader as exercise.

module DECODER (A,Y); input [2:0] A; output [7:0] Y; reg [7:0] Y; integer N; always @(A) begin for (N=0; N<=7; N=N+1) if (A==N)
Y[N]=1;

else
Y[N]=0;

end endmodule

Four Bit Address Decoder

This example is a four bit address decoder. It provides enable signals for segments of memory, the address map of which is shown below:

fourth quadrant third quadrant second quadrant first quadrant

12-16 8-11 7 6 5 4 0-3 The decoder's inputs could be the upper bour bits of a larger address bus which case the decoded outputs would enable larger segments of memory. Seven eable outputs are provided, one for each memory segment. The address map is divided into quarters, and the second quarter is further subdivided into four. There are four outputs from the second quarter corresponding to four consecutive binary input values.

module ADDRESS_DECODER (Address, AD0_3, AD4_7, AD8_11, AD12_15); input [3:0] Address; output AD0_4, AD8_11, AD12_15; output [3:0] AD4_7; integer N; reg AD0_3, AD8_11, AD12_15; reg AD4_7; always @(Address) begin
//first quarter if (Address>=0 && Address<=3) AD0_3=1;
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Decoder

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else
AD0_3=0; //third quarter if (Address>=8 && Address<=11) AD8_11=1;

else
AD8_11=0; //fourth quarter if (Address>=12 && Address<=15) AD12_15=1;

else
AD12_15=0; //second quarter for (N=0; N<=3; N=N+1) if (Address==N+4) AD4_7[N]=1;

else
AD4_7[N]=0;

end endmodule
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