Experiment no.

AIM: Write a VHDL program to implement 3:8 decoder

APPRATUS:
Hardware Requirement: Computer
Software Requirement: ISE 14 Software
THEORY:
A binary decoder is a combinational logic circuit that converts a binary integer
value to an associated pattern of output bits. They are used in a wide variety of
applications, including data de- multiplexing, seven segment display, and
memory address decoding. Decoder is with multiple data inputs and multiple
outputs that converts every unique combination of data input states into a
specific combination of output states.
For Example :- A security phone system with 3 dialing buttons and 8 speakers
will require as 3:8 decoder to be able to connect all speakers with control room
in just 3 lines.
Application: The Decoders were used in analog to digital conversion in analog
decoders, used in electronic circuits to convert instructions into CPU control
signals, also used in logical circuits, data transfer and in microprocessors for
memory mapping etc.
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8
line decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6,
and Y7 and three outputs, i.e., A0, A1, and A2. This circuit has an enable input
'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of these four
outputs will be 1.
The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as
follows:
Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
AIM: Write a VHDL program to implement 3:8 decoder

Fig 1.1 : Truth Table of 3:8 decoder

Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

VHDL Code :
Behavioral Modelling
entity decoder is
Port ( a : in STD_LOGIC_VECTOR(2 DOWNTO 0);
a1 : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end decoder;
architecture Behavioral of decoder is
begin
process(a)
begin
case a is
when "000"=>a1<="10000000";
when "001"=>a1<="01000000";
when "010"=>a1<="00100000";
when "011"=>a1<="00010000";
when "100"=>a1<="00001000";
when "101"=>a1<="00000100";
when "110"=>a1<="00000010";
when "111"=>a1<="00000001";
when others=>null;
end case;
end process;
end Behavioral;
Observations:

Result:
The 3:8 decoder was implemented using schematics and VHDL and
successfully simulated and verified.
AIM: Write a VHDL program to implement 3:8 decoder

RTL Schematic: