Cell Broadband Engine

Microprocessor
By Gabriel Goliath
 Cell broadband Engine
• RISC instruction architecture
• Most important objective of the Cell
microprocessor was to obtain high
performance.
• Style of architecture is Load/Store
• Includes the Power Processing Element
and Synergistic Processing Element
 Power Processing Element
• Main processor of the Cell Broadband
Element
• 64 bit Power Architecture
• 96 registers to store data
• Contains L2 and L1 Cache
• Uses a Pipeline datapath with 3
instructions and 10 stages.
 Synergistic Processing Elements
• Made up of 8 coprocessors
• Uses single-instruction multiple data
architecture (SIMD).
• Contains 128 registers that are each 128
bits wide. This helps mask the latency of
the pipeline.
• The performance is 25.6 Giga floating
point instructions per second for single
precision.
 Performance
• Performance is 205 Giga Floating-point
operations per second on a computer
running @ 3.2 GHz (Single Precision).
• Performance is 410 Giga operations per
second on a computer running @ 3.2 GHz
(Double Precision).
• Synergistic Processing Element is 3 times
faster than the fastest Pentium core
 Applications
• Used in the Playstation 3 video game
console. The clock frequency of the chip is
3.2 GHz.
• Toshiba is producing HDTV’s that use
Cell.
• IBM is developing a super computer called
IBM Roadrunner which is a hybrid of the
complex instruction set computer
architecture and the Cell processor.