LCD HD44780 - Giao Tip V Lp Trnh iu Khin

Trietnguyen, SPKT, 30/6/2007 Bi vit ny c th c in ra dng vi mc ch c nhn v phi thng mi, nu bn mun pht hnh trong trang WEB ca bn, lm n lin lc vi ti (minhtrietk2003@yahoo.com) hoc t nht phi trch dn li ngun l http://vagam.dieukhien.net
* Gii thiu : Ngy nay, thit b hin th LCD (Liquid Crystal Display) c s dng trong rt nhiu cc ng dng ca VK. LCD c rt nhiu u im so vi cc dng hin th khc: N c kh nng hin th k t a dng, trc quan (ch, s v k t ha), d dng a vo mch ng dng theo nhiu giao thc giao tip khc nhau, tn rt t ti nguyn h thng v gi thnh r Bi vit ny ch yu da vo datasheet HD44780 ca Hitachi, mt loi chp iu khin LCD rt thng dng nc ta. Phn u l phn gii thiu v c tnh ca HD44780 c tnh cht tham kho, phn sau l mt KIT ng dng c th cc bn c th t lm th nghim.

Phn 1 :

Tng Qut V LCD HD44780

1> Hnh dng v kch thc:

C rt nhiu loi LCD vi nhiu hnh dng v kch thc khc nhau, trn hnh 1 l hai loi LCD thng dng.

Hnh 1 : Hnh dng ca hai loi LCD thng dng Khi sn xut LCD, nh sn xut tch hp chp iu khin (HD44780) bn trong lp v v ch a cc chn giao tip cn thit. Cc chn ny c nh s th t v t tn nh hnh 2 :

Hnh 2 : S chn ca LCD

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2> Chc nng cc chn :

Chn s Tn 1 2 3 VSS VDD Vee Chc nng Chn ni t cho LCD, khi thit k mch ta ni chn ny vi GND ca mch iu khin Chn cp ngun cho LCD, khi thit k mch ta ni chn ny vi VCC=5V ca mch iu khin Chn ny dng iu chnh tng phn ca LCD. Chn chn thanh ghi (Register select). Ni chn RS vi logic 0 (GND) hoc logic 1 (VCC) chn thanh ghi. 4 RS + Logic 0: Bus DB0-DB7 s ni vi thanh ghi lnh IR ca LCD ( ch ghi write) hoc ni vi b m a ch ca LCD ( ch c - read) + Logic 1: Bus DB0-DB7 s ni vi thanh ghi d liu DR bn trong LCD. 5 R/W Chn chn ch c/ghi (Read/Write). Ni chn R/W vi logic 0 LCD hot ng ch ghi, hoc ni vi logic 1 LCD ch c. Chn cho php (Enable). Sau khi cc tn hiu c t ln bus DB0-DB7, cc lnh ch c chp nhn khi c 1 xung cho php ca chn E. 6 E + ch ghi: D liu bus s c LCD chuyn vo(chp nhn) thanh ghi bn trong n khi pht hin mt xung (high-to-low transition) ca tn hiu chn E. + ch c: D liu s c LCD xut ra DB0-DB7 khi pht hin cnh ln (lowto-high transition) chn E v c LCD gi bus n khi no chn E xung mc thp. Tm ng ca bus d liu dng trao i thng tin vi MPU. C 2 ch s dng 8 ng bus ny : 7-14 DB0DB7 + Ch 8 bit : D liu c truyn trn c 8 ng, vi bit MSB l bit DB7. + Ch 4 bit : D liu c truyn trn 4 ng t DB4 ti DB7, bit MSB l DB7 Chi tit s dng 2 giao thc ny c cp phn sau. Bng 1 : Chc nng cc chn ca LCD * Ghi ch : ch c, ngha l MPU s c thng tin t LCD thng qua cc chn DBx. Cn khi ch ghi, ngha l MPU xut thng tin iu khin cho LCD thng qua cc chn DBx.

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3> S khi ca HD44780:

hiu r hn chc nng cc chn v hot ng ca chng, ta tm hiu s qua chp HD44780 thng qua cc khi c bn ca n.

Hnh 3 : S khi ca HD44780 a> Cc thanh ghi : Chp HD44780 c 2 thanh ghi 8 bit quan trng : Thanh ghi lnh IR (Instructor Register) v thanh ghi d liu DR (Data Register) - Thanh ghi IR : iu khin LCD, ngi dng phi ra lnh thng qua tm ng bus DB0-DB7. Mi lnh c nh sn xut LCD nh a ch r rng. Ngi dng ch vic cung cp a ch lnh bng cch np vo thanh ghi IR. Ngha l, khi ta np vo thanh ghi IR mt chui 8 bit, chp HD44780 s tra bng m lnh ti a ch m IR cung cp v thc hin lnh . VD : Lnh hin th mn hnh c a ch lnh l 00001100 (DB7DB0) Trang 3

Lnh hin th mn hnh v con tr c m lnh l 00001110 - Thanh ghi DR : Thanh ghi DR dng cha d liu 8 bit ghi vo vng RAM DDRAM hoc CGRAM ( ch ghi) hoc dng cha d liu t 2 vng RAM ny gi ra cho MPU ( ch c). Ngha l, khi MPU ghi thng tin vo DR, mch ni bn trong chp s t ng ghi thng tin ny vo DDRAM hoc CGRAM. Hoc khi thng tin v a ch c ghi vo IR, d liu a ch ny trong vng RAM ni ca HD44780 s c chuyn ra DR truyn cho MPU. Bng cch iu khin chn RS v R/W chng ta c th chuyn qua li gi 2 thanh ghi ny khi giao tip vi MPU. Bng sau y tm tt li cc thit lp i vi hai chn RS v R/W theo mc ch giao tip. RS R/W Khi cn 0 0 1 1 0 1 0 1 Ghi vo thanh ghi IR ra lnh cho LCD (VD: cn display clear,) c c bn DB7 v gi tr ca b m a ch DB0-DB6 Ghi vo thanh ghi DR c d liu t DR Bng 2 : Chc nng chn RS v R/W theo mc ch s dng b> C bo bn BF: (Busy Flag) Khi thc hin cc hot ng bn trong chp, mch ni bn trong cn mt khong thi gian hon tt. Khi ang thc thi cc hot ng bn trong chip nh th, LCD b qua mi giao tip vi bn ngoi v bt c BF (thng qua chn DB7 khi c thit lp RS=0, R/W=1) ln bo cho MPU bit n ang bn. D nhin, khi xong vic, n s t c BF li mc 0. c> B m a ch AC : (Address Counter) Nh trong s khi, thanh ghi IR khng trc tip kt ni vi vng RAM (DDRAM v CGRAM) m thng qua b m a ch AC. B m ny li ni vi 2 vng RAM theo kiu r nhnh. Khi mt a ch lnh c np vo thanh ghi IR, thng tin c ni trc tip cho 2 vng RAM nhng vic chn la vng RAM tng tc c bao hm trong m lnh. Sau khi ghi vo (c t) RAM, b m AC t ng tng ln (gim i) 1 n v v ni dung ca AC c xut ra cho MPU thng qua DB0-DB6 khi c thit lp RS=0 v R/W=1 (xem bng tm tt RS - R/W). Lu : Thi gian cp nht AC khng c tnh vo thi gian thc thi lnh m c cp nht sau khi c BF ln mc cao (not busy), cho nn khi lp trnh hin th, bn phi delay mt khong tADD khong 4uS5uS (ngay sau khi BF=1) trc khi np d liu mi. Xem thm hnh bn di.

Hnh 4 : Gin xung cp nht AC

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d> Vng RAM hin th DDRAM : (Display Data RAM) y l vng RAM dng hin th, ngha l ng vi mt a ch ca RAM l mt k t trn mn hnh v khi bn ghi vo vng RAM ny mt m 8 bit, LCD s hin th ti v tr tng ng trn mn hnh mt k t c m 8 bit m bn cung cp. Hnh sau y s trnh by r hn mi lin h ny :

Hnh 4 : Mi lin h gia a ch ca DDRAM v v tr hin th ca LCD Vng RAM ny c 80x8 bit nh, ngha l cha c 80 k t m 8 bit. Nhng vng RAM cn li khng dng cho hin th c th dng nh vng RAM a mc ch. Lu l truy cp vo DDRAM, ta phi cung cp a ch cho AC theo m HEX e> Vng ROM cha k t CGROM: Character Generator ROM Vng ROM ny dng cha cc mu k t loi 5x8 hoc 5x10 im nh/k t, v nh a ch bng 8 bit. Tuy nhin, n ch c 208 mu k t 5x8 v 32 mu k t kiu 5x10 (tng cng l 240 thay v 28 = 256 mu k t). Ngi dng khng th thay i vng ROM ny.

Hnh 5 : Mi lin h gia a ch ca ROM v d liu to mu k t. Trang 5

Nh vy, c th ghi vo v tr th x trn mn hnh mt k t y no , ngi dng phi ghi vo vng DDRAM ti a ch x (xem bng mi lin h gia DDRAM v v tr hin th) mt chui m k t 8 bit trn CGROM. Ch l trong bng m k t trong CGROM hnh bn di c m ROM A00. V d : Ghi vo DDRAM ti a ch 01 mt chui 8 bit 01100010 th trn LCD ti th 2 t tri sang (dng trn) s hin th k t b.

Bng 3 : Bng m k t (ROM code A00)

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f> Vng RAM cha k t ha CGRAM : (Character Generator RAM) Nh trn bng m k t, nh sn xut dnh vng c a ch byte cao l 0000 ngi dng c th to cc mu k t ha ring. Tuy nhin dung lng vng ny rt hn ch: Ta ch c th to 8 k t loi 5x8 im nh, hoc 4 k t loi 5x10 im nh. ghi vo CGRAM, hy xem hnh 6 bn di.

Hnh 6 : Mi lin h gia a ch ca CGRAM, d liu ca CGRAM, v m k t.

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4> Tp lnh ca LCD :

Trc khi tm hiu tp lnh ca LCD, sau y l mt vi ch khi giao tip vi LCD : * Tuy trong s khi ca LCD c nhiu khi khc nhau, nhng khi lp trnh iu khin LCD ta ch c th tc ng trc tip c vo 2 thanh ghi DR v IR thng qua cc chn DBx, v ta phi thit lp chn RS, R/W ph hp chuyn qua li gi 2 thanh ghi ny. (xem bng 2) * Vi mi lnh, LCD cn mt khong thi gian hon tt, thi gian ny c th kh lu i vi tc ca MPU, nn ta cn kim tra c BF hoc i (delay) cho LCD thc thi xong lnh hin hnh mi c th ra lnh tip theo. * a ch ca RAM (AC) s t ng tng (gim) 1 n v, mi khi c lnh ghi vo RAM. (iu ny gip chng trnh gn hn) * Cc lnh ca LCD c th chia thnh 4 nhm nh sau : Cc lnh v kiu hin th. VD : Kiu hin th (1 hng / 2 hng), chiu di d liu (8 bit / 4 bit), Ch nh a ch RAM ni. Nhm lnh truyn d liu trong RAM ni.

Cc lnh cn li . (!!!) Bng 4 : Tp lnh ca LCD

Tn lnh Hot ng M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = 0 0 0 0 0 0 0 1 Lnh Clear Display (xa hin th) s ghi mt khong trng-blank (m hin k t 20H) vo tt c nh trong DDRAM, sau tr b m a AC=0, tr li kiu hin th gc nu n b thay i. Ngha l : Tt hin th, con tr di v gc tri (hng u tin), ch tng AC. M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1.52 DBx = 0 0 0 0 0 0 1 * Lnh Return home tr b m a ch AC v 0, tr li kiu hin th gc nu n b thay ms i. Ni dung ca DDRAM khng thay i. M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = 0 0 0 0 0 1 [I/D] [S] I/D : Tng (I/D=1) hoc gim (I/D=0) b m a ch hin th AC 1 n v mi khi c hnh ng ghi hoc c vng DDRAM. V tr con tr cng di chuyn theo s tng 37 gim ny. uS S : Khi S=1 ton b ni dung hin th b dch sang phi (I/D=0) hoc sang tri (I/D=1) mi khi c hnh ng ghi vng DDRAM. Khi S=0: khng dch ni dung hin th. Ni dung hin th khng dch khi c DDRAM hoc c/ghi vng CGRAM.

texe (max)

Clear Display

Return home

Entry mode set

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Hnh 7 : Hot ng dch tri v dch phi ni dung hin th M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = 0 0 0 0 1 [D] [C] [B] D: Hin th mn hnh khi D=1 v ngc li. Khi tt hin th, ni dung DDRAM khng thay i. C: Hin th con tr khi C=1 v ngc li. V tr v hnh dng con tr, xem hnh 8 B: Nhp nhy k t ti v tr con tr khi B=1 v ngc li. Xem thm hnh 8 v kiu nhp nhy. Chu k nhp nhy khong 409,6ms khi mch dao ng ni LCD l 250kHz. Display on/off control

37uS

Hnh 8: Kiu con tr, kiu k t v nhp nhy k t M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 * DBx = 0 0 0 1 [S/C] [R/L] * Lnh Cursor or display shift dch chuyn con tr hay d liu hin th sang tri m khng cn hnh ng ghi/c d liu. Khi hin th kiu 2 dng, con tr s nhy xung dng di khi dch qua v tr th 40 ca hng u tin. D liu hng u v hng 2 dch cng mt lc. Chi tit s dng xem bng bn di: S/C 0 0 1 1 R/L Hot ng 0 1 0 1 Dch v tr con tr sang tri (Ngha l gim AC mt n v). Dch v tr con tr sang phi (Tng AC ln 1 n v). Dch ton b ni dung hin th sang tri, con tr cng dch theo. Dch ton b ni dung hin th sang phi, con tr cng dch theo. Trang 9 37uS

Cursor or display shift

Bng 5: Hot ng lnh Cursor or display shift M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 * DBx = 0 0 1 [DL] [N] [F] * DL: Khi DL=1, LCD giao tip vi MPU bng giao thc 8 bit (t bit DB7 n DB0). Ngc li, giao thc giao tip l 4 bit (t bit DB7 n bit DB0). Khi chn giao thc 4 bit, d liu c truyn/nhn 2 ln lin tip. vi 4 bit cao gi/nhn trc, 4 bit thp gi/nhn sau. Function N : Thit lp s hng hin th. Khi N=0 : hin th 1 hng, N=1: hin th 2 hng. 37uS set F : Thit lp kiu k t. Khi F=0: kiu k t 5x8 im nh, F=1: kiu k t 5x10 im nh. * Ch : Ch thc hin thay i Function set u chng trnh. V sau khi c thc thi 1 ln, lnh thay i Function set khng c LCD chp nhn na ngoi tr thit lp chuyn i giao thc giao tip. Khng th hin th kiu k t 5x10 im nh kiu hin th 2 hng

M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Set DBx = 0 1 [ACG][ACG][ACG][ACG][ACG][ACG] CGRAM Lnh ny ghi vo AC a ch ca CGRAM. K hiu [ACG] ch 1 bit ca chui d liu 37uS address 6 bit. Ngay sau lnh ny l lnh c/ghi d liu t CGRAM ti a ch c ch nh. M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = 1 [AD] [AD] [AD] [AD] [AD] [AD] [AD] Lnh ny ghi vo AC a ch ca DDRAM, dng khi cn thit lp ta hin th Set mong mun. Ngay sau lnh ny l lnh c/ghi d liu t DDRAM ti a ch 37uS DDRAM c ch nh. address Khi ch hin th 1 hng: a ch c th t 00H n 4FH. Khi ch hin th 2 hng, a ch t 00h n 27H cho hng th nht, v t 40h n 67h cho hng th 2. Xem chi tit hnh 4. M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (RS=0, R/W=1) DBx = [BF] [AC] [AC] [AC] [AC] [AC] [AC] [AC] Read BF Nh cp trc y, khi c BF bt, LCD ang lm vic v lnh tip theo (nu and c) s b b qua nu c BF cha v mc thp. Cho nn, khi lp trnh iu khin, bn 0uS address phi kim tra c BF trc khi ghi d liu vo LCD. Khi c c BF, gi tr ca AC cng c xut ra cc bit [AC]. N l a ch ca CG hay DDRAM l ty thuc vo lnh trc M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = [Write data] (RS=1, R/W=0) Khi thit lp RS=1, R/W=0, d liu cn ghi c a vo cc chn DBx t mch 37uS Write ngoi s c LCD chuyn vo trong LCD ti a ch c xc nh t lnh ghi a data to tADD ch trc (lnh ghi a ch cng xc nh lun vng RAM cn ghi) CG or 4uS DDRAM Sau khi ghi, b m a ch AC t ng tng/gim 1 ty theo thit lp Entry mode. Lu l thi gian cp nht AC khng tnh vo thi gian thc thi lnh. Chi tit v giao thc Ghi d liu, xin xem hnh 10. Read M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 data DBx = [Read data] (RS=1, R/W=1) from CG 37uS tADD Trang 10

Khi thit lp RS=1, R/W=1,d liu t CG/DDRAM c chuyn ra MPU thng qua 4uS or DDRAM cc chn DBx (a ch v vng RAM c xc nh bng lnh ghi a ch trc ). Sau khi c, AC t ng tng/gim 1 ty theo thit lp Entry mode, tuy nhin ni dung hin th khng b dch bt chp ch Entry mode. Chi tit hn v giao thc c d liu, xin xem hnh 11.

5> Giao tip gia LCD v MPU :

a> c tnh in ca cc chn giao tip : LCD s b hng nghim trng, hoc hot ng sai lch nu bn vi phm khong c tnh in sau y: Chn cp ngun (Vcc-GND) Nhit hot ng Nhit bo qun Min:-0.3V , Max+7V Min:-30C , Max:+75C Min:-55C , Max:+125C

Cc chn ng vo (DBx,E,) Min:-0.3V , Max:(Vcc+0.3V)

Bng 6 : Maximun Rating c tnh in lm vic in hnh: (o trong iu kin hot ng Vcc = 4.5V n 5.5V, T = -30 n +75C) Chn cp ngun Vcc-GND in p vo mc cao VIH in p vo mc thp VIL in p ra mc cao (DB0-DB7) in p ra mc thp (DB0-DB7) Dng in cp ngun ICC Tn s dao ng ni fOSC 2.7V n 5.5V 2.2V n Vcc -0.3V n 0.6V Min 2.4V (khi IOH = -0.205mA) (khi VIN = 0 n Vcc) Max 0.4V (khi IOL = 1.2mA) 350uA(typ.) n 600uA 190kHz n 350kHz (in hnh l 270kHz) Bng 7: Min lm vic bnh thng b> S ni mch in hnh: - S mch kt ni gia m un LCD v VK 89S52 (8 bit). - S mch kt ni gia mun LCD v VK (4 bit). c> Bus Timing:

Dng in ng vo (input leakage current) ILI -1uA n 1uA

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6> Khi to LCD:

Khi to l vic thit lp cc thng s lm vic ban u. i vi LCD, khi to gip ta thit lp cc giao thc lm vic gia LCD v MPU. Vic khi to ch c thc hin 1 ln duy nht u chng trnh iu khin LCD v bao gm cc thit lp sau : Display clear : Xa/khng xa ton b ni dung hin th trc . Function set : Kiu giao tip 8bit/4bit, s hng hin th 1hng/2hng, kiu k t 5x8/5x10. Display on/off control: Hin th/tt mn hnh, hin th/tt con tr, nhp nhy/khng nhp nhy. Entry mode set : cc thit lp kiu nhp k t nh: Dch/khng dch, t tng/gim (Increment).

a> Mch khi to bn trong chp HD44780: Mi khi c cp ngun, mch khi to bn trong LCD s t ng khi to cho n. V trong thi gian khi to ny c BF bt ln 1, n khi vic khi to hon tt c BF cn gi trong khong 10ms sau khi Vcc t n 4.5V (v 2.7V th LCD hot ng). Mch khi to ni s thit lp cc thng s lm vic ca LCD nh sau: Display clear : Xa ton b ni dung hin th trc . Function set: DL=1 : 8bit; N=0 : 1 hng; F=0 : 5x8 Display on/off control: D=0 : Display off; C=0 : Cursor off; B=0 : Blinking off. Entry mode set: I/D =1 : Tng; S=0 : Khng dch.

Nh vy sau khi m ngun, bn s thy mn hnh LCD ging nh cha m ngun do ton b hin th tt. Do , ta phi khi to LCD bng lnh. b> Khi to bng lnh: (chui lnh) Vic khi to bng lnh phi tun theo lu sau ca nh sn xut :

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Nh cp trn, ch giao tip mc nh ca LCD l 8bit (t khi to lc mi bt in ln). V khi kt ni mch theo giao thc 4bit, 4 bit thp t DB0-DB3 khng c kt ni n LCD, nn lnh khi to ban u (lnh chn giao thc giao tip function set 0010****) phi giao tip theo ch 8 bit (ch gi 4 bit cao mt ln, b qua 4 bit thp). T lnh sau tr i, phi gi/nhn lnh theo 2 nibble. Lu l sau khi thit lp function set, bn khng th thay i function set ngoi tr thay i giao thc giao tip (4bit/8bit).

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Phn 2 :

KIT TH NGHIM LCD HD44780

Gii thiu: Trong phn trc, cc bn tm hiu cc c tnh ca LCD, by gi chng ta cng thi cng mt KIT th nghim LCD HD44780 vn dng kin thc trn vo thc t. 1> S mch :
Mch nguyn l (schema):

S b tr linh kin:

Mch in : (ko ly ci ny em in nh

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Hnh nh hon tt :

2> Chng trnh iu khin: V code hi di, xin download code din n VAGAM Chng ta s tho lun chi tit cch lp trnh cho LCD din n VAGAM 3> Li kt: Cheer!!!

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Phn 3:

LCD tutorial

Phn ny l qu trnh trin khai ng dng vi LCD, ch yu l copy bi vit ca ti din n VAGAM Bi 1: Khi to LCD ch 8 bit
Khi to LCD l hnh ng thit lp cc thng s lm vic ban u cho n. Khi to c thc hin mt ln vo u chng trnh v bao gm: + Thit lp ch giao tip (function set): Bi ny s gip bn khi to LCD ch 8 bit. + Thit lp ch nhp (Entry mode set): Cc thit lp v k t + Thit lp ch hin th (Display control): Kiu con tr, kiu k t ... + Xa mn hnh. Tt c cng c cn cho bi hc ny l: + Phn mm son tho v dch file ASM no (khuyn dng MIDE51) + Phn mm m phng: Proteus (C kh khn v phn mm th lin h cc thnh vin VAGAM) Kin thc: Bn khng nht thit phi bit s dng proteus, nhng bn phi bit c bn v vi iu khin cng nh lp trnh cho vi iu khin. OK, here we go ...

Bi 1: (tt) Ra 1 lnh cho LCD

khi to, bn phi "ra lnh" cho LCD. LCD "hiu" c "lnh ca bn", bn phi tun theo "qui c ni chuyn" ca n (giao thc), c "m lng" (phn cng) v "ngn ng" (phn mm). - Nhp gia ty tc m, bn nh!? a. Giao thc phn cng: (xem chi tit trong bi vit hoc datasheet) + LCD giao tip theo chun logic TTL thng thng (5V cho logic 1 v 0V cho logic 0) cho nn c th kt ni trc tip vi 8051. + Chn d liu (nhng chn dng "ra lnh") ca LCD t chn 7 n chn 14 (c nh sn xut t tn l DB0-DB7) + Chn tn hiu l cc chn 4(RS), 5(RW), 6(E) Nh vy l bn c th thit k mch ng dng cho LCD ri y d qu phi ko no! Di y l mt hnh kt ni LCD trong file m phng ca mnh:

- Hnh 1: Kt ni phn cng cho LCD b. Giao thc phn mm: - LCD hiu c lnh, chng ta cn theo ng giao thc ca nh sn xut. Hnh bn di l giao thc ghi mt lnh vo LCD:

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T s gii thch lu ny mt cht: + u tin l ng RS, ta thy n v 2 ng trn (mc logic 1) v i (mc logic 0), tc l chng ta c th cp cho chn ny mc 0 hay mc 1 u c. Mc 0 th LCD hiu d liu chn DBx l d liu hin th, mc 1 th LCD hiu d liu chn DBx l l lnh. + Chn RW phi c cp mc logic 0 + Chn E: D liu s c np vo LCD thi im chn E t cao xung thp (high-to-low). Nhng d liu cn t DBx trc thi im mt khong tDSW=80ns v gi tH=10ns (trong ti liu ti c tnh vit sai thnh l low-tohigh transition, mong rng bn no quan tm c s pht hin ra, nhng hnh nh ai cng "chp nhn" hoc l "ko ai c", nn chng ai c kin, hic hic)

Vi hai lu ny, theo bn ci no tt hn? (cu hi tho lun nh ;)

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T hai lu , ta c on chng trnh ra mt lnh cho LCD nh sau:

MOV lcd_port,#00111000B ; DL=1, N=1, F=1,(8bit mode, 2 line, 5x8) CLR RS ;RS = 0 CLR RW ;RW = 0 CLR E SETB E

v:
MOV lcd_port,#00111000B ; N=1, F=1 CLR RS ;RS = 0 CLR RW ;RW = 0 SETB E CLR E

vi #00111000B l m lnh Function Set cho N=1, F=1 on video clip sau m t qu trnh ti th nghim vi LCD Vi on code 1, ta thy thi gian nhn lnh LCD l 0.100007758s, cn on code 2 l 0.100008258s => on 1 ngn hn on 2 : 0.5uS y l 1 chu k my 0.5us (thch anh 24MHz), chnh l thi im LCD nhn c tn hiu "CLR E".
Attachment(s)

LCD-protues.rar (17.8 KB, 1 ln ti) LCD-codehoc1.rar (0.5 KB, 1 ln ti) LCDdebugavi1.rar (716.8 KB, 1 ln ti)

Bi 1: (tt) c d liu t LCD

Nh cp trong bi vit, LCD v 8051 hot ng khng ng b vi nhau. 8051 "chy" nhanh hn LCD, do sau khi "ra mt lnh" cho LCD, n phi i LCD "lm xong" lnh mi c ra lnh tip theo. Xut pht t y, ta c 2 cch: + i "m": tc l sau khi ra mt lnh, 8051 i mt khong thi gian c nh. Thi gian ny phi di hn thi gian lm vic ca LCD, v do nh sn xut qui nh( t 37uS n 1,52ms - xem thm trong bi vit) + i c bo bn BF t LCD: LCD c chn DB7 lm 2 nhim v, khi "ra lnh" th n ng vai tr chn d liu, cn khi "c d liu (*)" th n ng vai tr c bo bn BF. Hot ng ca c BF xin xem thm trong bi vit. (*) : khi ni "ra lnh" hoc "c d liu" th ta ngm hiu l hnh ng ca 8051. (LCD ch l i tng iu khin) Vi cch 1, on m khi to ca chng ta th ny:
MOV ms_num,#100 ; delay 40ms after Vcc rise to 2.7V call delayms MOV lcd_port,#00111000B ;N=1, F=1 CLR RS ;RS = 0 CLR RW ;RW = 0 CLR E SETB E MOV ms_num,#1 ; delay 1ms call delayms MOV lcd_port,#00001111B ; display on, display cursor + blink CLR RS ;RS = 0 CLR RW ;RW = 0 CLR E SETB E jmp $

Lu , cho gn, ti lt bt phn hm delayms v cc th linh tinh khc --> nu bn ch copy, paste y chang th ko chy nh!!! Mun th nghim th download code cui bi vit ny. Sau on chng trnh trn, con tr trn LCD s chp, LCD khi to thnh cng ri y. u im theo cch ny l n gin v d hiu, tuy nhin ko ti u cho lm.(t thy c rt nhiu bn chn cch ny cho gn :-D) Vi cch 2, ta phi c d liu (c c BF thng qua chn DB7) t LCD. on chng trnh c d liu cng phi tun theo giao thc ca nh sn xut:

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Ti cng xin gii thch s qua gin xung ny, nhn ging gin write nhng cch l gii ko ging u bn : + Th nht, chn RW phi treo ln mc cao. + Hai, chn E tch cc bng cnh ln ch ko phi cnh xung! Sau tDDR=160ns khi c tn hiu t mc thp ln mc cao chn E, d liu c LCD xut ra qua chn DBx, d liu ny c gi ti khi no chn E xung thp tr li (ko di thm tDHR=5ns) + Thi gian gia hai ln c cnh ln chn E ti thiu l 0.5uS + Thi gian gi mc cao chn E ti thiu l 230ns T gin xung, ta c lu hm kim tra c BF nh sau:

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v on chng trnh bng ASM nh sau:

check_BF: CLR RS SETB RW SETB BF recheck: CLR E SETB E JB BF,recheck ret ;RS=0 ;RW=1 ;latch for read

Kt hp cc th li, ta c on chng trnh khi to cho LCD theo cch 2 nh sau:

MOV lcd_port,#00111000B ;N=1, F=1 CLR RS ;RS = 0 CLR RW ;RW = 0 CLR E SETB E call check_BF MOV lcd_port,#00001111B ; display on, display cursor + blink CLR RS ;RS = 0 CLR RW ;RW = 0 CLR E SETB E jmp $

im khc bit duy nht gia 2 chng trnh l dng

call check_BF ; trong chng trnh 2

v
MOV ms_num,#1 call delayms ; trong chng trnh 1

Ta hy xem s ti u ca chng trnh 2 qua video m phng sau: chng trnh 2, thi gian gia 2 ln nhn lnh l 0.100052259s-0.100007758s=44.501us (trong datasheet cho thi gian thc thi lnh ny l 37us). => Ti u hn nhiu so vi 1ms ca chng trnh 1 bn nh!!!
Attachment(s)

LCD-chuongtrinh1.rar (0.5 KB, 0 ln ti) Trang 22

LCD-chuongtrinh2.rar (0.6 KB, 0 ln ti) LCDdebugavi2.rar (179.5 KB, 0 ln ti)

Bi 1: (tt) Xut dng ch

Nh vy bn "ra lnh" v "c d liu" t LCD. By gi hy th xut mt dng ch trn LCD xem sao? Vic xut ch ln LCD thc cht cng l "ra lnh", khc ch ta thit lp chn RS=[1] DBx ni vi vng ram d liu DDR
RS bit P1.0 RW bit P1.1 E bit P1.2 BF bit P2.7 ms_num equ 2fh lcd_port equ P2 lcd_mask equ 0FFh ORG 000h jmp main ORG 030h ; main program begin here main: MOV ms_num,#100 ; delay 40ms after Vcc rise to 2.7V call delayms MOV lcd_port,#00111000B ;N=1, F=1 CLR RS ;RS = 0 CLR RW ;RW = 0 CLR E SETB E call check_BF MOV lcd_port,#00001111B ; display on, display cursor + blink CLR RS ;RS = 0 CLR RW ;RW = 0 CLR E SETB E call check_BF MOV lcd_port,#'V' SETB RS CLR RW CLR E SETB E call check_BF MOV lcd_port,#'A' SETB RS CLR RW CLR E SETB E call check_BF MOV lcd_port,#'G' SETB RS CLR RW CLR E SETB E call check_BF MOV lcd_port,#'A' SETB RS CLR RW CLR E SETB E call check_BF MOV lcd_port,#'M' SETB RS CLR RW CLR E SETB E jmp $ check_BF: CLR RS ;RS=0 SETB RW ;RW=1 SETB BF ; latch for read LR E recheck SETB E JB BF,recheck ret

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delayms: ; Xtal = 24MHZ, Tm=0.5us PUSH 7 PUSH 6 MOV R7,#51 de_rep: MOV R6,#18 DJNZ R6,$ DJNZ R7,de_rep POP 6 POP 7 DJNZ ms_num,delayms ret END

Khi debug trong proteus, mc d LCD vn hin ch "VAGAM", nhng n bo li to tng:

Logic contention(s) detected on net P2.0,P2.1,P2.2 !!!

Tm dch l: "C ni tt Vcc vi GND cc chn logic!" S d ti mun ni n ci ny v thy nhiu bn vit m ko ch lm gim tui th LCD v 8051 m ko r nguyn nhn (c tha "LCD hng china") Sai l ch: + Sau cu lnh "call check_BF" l lnh "MOV lcd_port,#data": trong khi LCD xut d liu ra sau lnh check_BF th ta li cp d liu mi vo DBx => xung khc + Trong hm check_BF, ta ch cht 1 chn BF c, cc chn cn li khng kim sot => Nguy c xung t khi LCD xut d liu ra DBx T nhc im trn, chng ta ci tin li chng trnh: + Chuyn cu lnh "MOV lcd_port,#data" ra sau hai cu lnh "SETB RS" v "CLR RW" LCD trng thi "c lnh t MPU" v treo DBx ln tng tr cao. + i "SETB BF" thnh "MOV lcd_port,#0FFh" Nh vy, chng trnh thnh (download code bn di) Chng ta cng kt thc bi 1 y! (Ph, khe qu )
Attachment(s)

LCD-codehoc4.rar (0.6 KB, 0 ln ti)

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Bi 2: Ti u code
T chng trnh cui, chng ta ci tin mt cht cho code ngn gn li:
dta: call check_BF SETB RS ;RS = 1, DR selected CLR RW ;RW = 0, write to LCD exec: MOV lcd_port,A SETB E CLR E ret

By gi hnh ng ghi d liu n gin l li gi hm dta:

MOV A,#d_liu Call dta

Vi hnh ng xut lnh, ta bin i hm dta mt t thnh hm cmd:

cmd: call check_BF CLR RS ;RS = 0, IR selected CLR RW ;RW = 0, write to LCD exec: MOV lcd_port,A SETB E CLR E ret

Lc ny, hnh ng ra mt lnh cho LCD nh sau:

MOV A,#m_lnh Call cmd

Do ging nhau phn exec, ta c th vit li:

cmd: call check_BF CLR RS ;RS = 0, IR selected CLR RW ;RW = 0, write to LCD jmp exec dta: call check_BF SETB RS ;RS = 1, DR selected CLR RW ;RW = 0, write to LCD exec: MOV lcd_port,A SETB E CLR E Ret

Cui cng, sau khi ci tin ln 1, ta c on chng trnh hin ch VAGAM nh sau (*):
MOV A,#mode8bit call cmd MOV A,#cursor_on call cmd MOV A,#'V' call dta MOV A,#'A' call dta MOV A,#'G' call dta MOV A,#'A' call dta MOV A,#'M' call dta jmp $ cmd: call check_BF CLR RS ;RS = 0, IR selected

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CLR RW ;RW = 0, write to LCD jmp exec dta: call check_BF SETB RS ;RS = 1, DR selected CLR RW ;RW = 0, write to LCD exec: MOV lcd_port,A SETB E CLR E return: ret

* Cc chi tit ph c b bt, chng trnh y c th ti y

codetoiuu1.asm
Vic xut dng ch VAGAM xem ra cn c tnh lp li. Ta ti u mt ln na bng cch s dng con tr DPTR v kiu nh a ch gin tip to vng lp
putcmd: MOV A,#00h MOVC A,@A+dptr CJNE A,#endcmd,next_pc jmp return next_pc: CALL cmd inc dptr jmp putcmd

Ta xut ra mt chui lnh bng cch np a ch ca d liu:

MOV dptr,#initcmd ; Ln lt ra cc lnh trong dy initcmd call putcmd

Vi nhn initcmd nm cui chng trnh:

initcmd: DB mode8bit,cursor_on,clr_disp,endcmd

Tng t nh vy, ta lm hm xut chui d liu:

putstr: MOV A,#00h MOVC A,@A+dptr CJNE A,#endstr,next_ps jmp return next_ps: CALL dta PUSH ms_num call delayms POP ms_num inc dptr jmp putstr

V vic xut chui d liu ra n gin l lnh np nhn d liu cho dptr v li gi hm putstr:
MOV ms_num,#200 ; Mi k t xut ra delay 200ms MOV dptr,#messa1 ; Ln lt xut tng k t trong dy messa1 call putstr

Vi nhn messa1 nm cui chng trnh

messa1: DB 'VAGAM',endstr

Kt hp li ta c on chng trnh sau:

MOV dptr,#initcmd ; initial call putcmd MOV ms_num,#200 MOV dptr,#messa1 ; call putstr jmp $ putstr: MOV A,#00h MOVC A,@A+dptr CJNE A,#endstr,next_ps jmp return next_ps: CALL dta

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PUSH ms_num call delayms POP ms_num inc dptr jmp putstr putcmd: MOV A,#00h MOVC A,@A+dptr CJNE A,#endcmd,next_pc jmp return next_pc: CALL cmd inc dptr jmp putcmd cmd: call check_BF CLR RS ;RS = 0, IR selected CLR RW ;RW = 0, write to LCD jmp exec dta: call check_BF SETB RS ;RS = 1, DR selected CLR RW ;RW = 0, write to LCD exec: MOV lcd_port,A SETB E CLR E Ret initcmd: DB mode8bit,cursor_on,clr_disp,endcmd messa1: DB 'VAGAM',endstr END

* Cc chi tit ph c b bt, chng trnh y c th ti y codetoiuu2.asm

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Vic ti u code c th cn ngn v ti u hn na, cng nh thm cc hm to hiu ng ng cho k t. Tuy nhin do tnh cht tutorial l gii thiu, chng ta kt thc bi ti u code y.

Bi 3: Lp trnh hin th k t ha
cc bi trc chng ta bit cch xut ra mt k t ln a ch hin th trong LCD. V d hin th ch b ln LCD ti a ch hin thi ta ra mt lnh xut d liu (hm dta) vi m lnh l 01100010 (y chnh l v tr ch 'b' trong bng m k t LCD trang 6 ca bi vit). V do trng vi bng m ASCII, nn thay v vit #01100010B ta c th vit #'b' trong ASM.

By gi nu ta xut mt m d liu #00000000B th LCD hin th ci g? Cu tr li nm vng RAM ha CGRAM (xin xem thm v CGRAM ti trang 7 ca ti liu). T bng 5 bn di v lnh Write data to CG or DDRAM, ta c lu ghi mt k t ha "" vo CGRAM ti a ch #00000000B. Trang 28

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T lu , ta ci tin hm putstr c c hm put_cg: put_cg: MOV R0,#40h putcg: MOV A,R0 CALL cmd INC R0 MOV A,#00h MOVC A,@A+dptr CJNE A,#endcmd,next_cg JMP return next_cg: CALL dta INC dptr JMP putcg V sau y l chng trnh hin ch C in T trn mn hnh LCD.

Chng ta kt thc bi 3 y, cng kt thc lun phn lp trnh LCD theo giao thc 8 bit bng ASM. Nu nm vng kin thc ny, cc bn c th lp trnh cho LCD bng ngn ng g cng c (C chng hn) v bng vi iu khin g cng c nt ... Cc bi tip theo chng ta s lp trnh LCD theo ch 4 bit, y l ch c a chung trong thc t ... Attachment(s) LCDCGRAM-code.rar (1.2 KB, 11 ln ti) LCDCGRAM-code.rar (1.2 KB, 11 ln ti)

Bi 4: Giao tip LCD HD44780 theo ch 4 bit bi hc ny chng ta s s dng LCD theo ch 4 bit, tc l ch dng 4 chn DB4-DB7 truyn d liu. V giao thc giao tip, ch 4 bit khng c cp chi tit trong bi vit v n c bn ging nh giao thc 8 bit, ch khc mt im l ta gi/nhn mi ln 4 bit, vi 4 bit cao gi/nhn trc. Hnh bn di minh ha cho giao thc gi mt lnh n LCD theo ch 4 bit. Gia hai nibble (4-bit) ta cn thm mt xung enable.

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T y l c lu xut mt lnh hoc d liu theo giao thc 4 bit nh sau:

Vi mt cht kinh nghim lp trnh ASM, ta c th vit chng trnh cho lu trn vi mt cht ci tin (bng cch dng chng trnh con). Mt chng trnh mu c cho bn di: dta: call check_BF ; Kim tra c BF CLR RW ; Thit lp ch nhn d liu SETB RS ; // jmp exec cmd: call check_BF
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CLR RW ; Thit lp ch nhn lnh CLR RS ; // exec: PUSH ACC call nibble ; 4 bit cao gi i trc POP ACC SWAP A ; i 4 bit thp ln v tr 4 bit cao call nibble ; 4 bit thp gi sau return: ret nibble: ; chng trnh con gi i 4 bit ORL lcd_port,#lcd_mask ; Che 4 chn khng dng ORL A,#data_mask ; lcd_mask=0F0h, data_mask=0Fh ANL lcd_port,A ; 4 chn port khng dng khng i SETB E ; Xung enable CLR E ret Vic c c bn BF cng tng t nh ch 8 bit, 4 bit cao c trc, 4 bit thp c sau (b qua 4 bit sau). C BF nm bit u tin (MSB) ca 4 bit cao.

on chng trnh mu: check_BF: CLR SETB ORL jmp recheckBF: clr setb next_BF:

RS ; Thit lp ch xut d liu RW ; lcd_port,#lcd_mask ; Cht c vo next_BF E E ; Xung enable

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clr E setb E JB BF,recheckBF clr E setb E ret l tt c nhng g c bn v ch 4 bit (ch c th :D). Nhng xin lu cc bn mt iu v khi to LCD: (trch li trong bi vit trang 15) Nh cp trn, ch giao tip mc nh ca LCD l 8bit (t khi to lc mi bt in ln). V khi kt ni mch theo giao thc 4bit, 4 bit thp t DB0-DB3 khng c kt ni n LCD, nn lnh khi to ban u (lnh chn giao thc giao tip function set 0010****) phi giao tip theo ch 8 bit (ch gi 4 bit cao mt ln, b qua 4 bit thp). T lnh sau tr i, phi gi/nhn lnh theo 2 nibble. Qu trnh tin ha code c ni ti cc bi trc, bi ny ch nu ra on code cui cng, on code hin ch C in T trn LCD (c th down load din n VAGAM)

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