Digital Systems Design

Digital Systems Design and Test

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-1

Introduction
Traditional digital design
Manual process of designing and capturing circuits
Schematic entry

System-level design
Top-down design
Required due to design complexity Rapid time-to-market requirements

Hardware Description Language (HDL) use

Synthesis Use a hardware compiler to implement a design Applicable to different digital product types
ASIC, CPLD, FPGA, etc.

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-2

Top-down HDL Design Methodology

Increased productivity
Shorter development cycle More product features Reduced time-to-market

Reduced non-recurring engineering (NRE) costs Design reuse facilitated Flexibility in design changes Rapidly explore alternatives
Architectures Implementation technologies

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-3

Other Design Methodology Considerations

Bottom-up design
Design simple components Test desired functionality Integrate into larger designs Questions/Concerns?

How are software versus hardware distinctions made?

Hardware and software designed concurrently
Hardware/software codesign

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-4

ASIC and FPGA Devices

Standard off-the-shelf integrated circuits have fixed functionality defined by the chip manufacturer ASIC and FPGA
Functionality fixed by the designer for a particular application ASIC requires a manufacturing process step to layout the design FPGA is field programmable by the designer

Structured ASICs
Some lower levels of the device are prefabricated Upper levels are based on a given (user) design
Mix between ASIC and FPGA

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-5

ASIC Types
Types of ASIC devices
Gate Arrays
Transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization in other words, unconnected The physical design process then defines the interconnections of the final device.

Standard Cell
No concept of a basic cell No components prefabricated on the IC Silicon used more efficiently ASIC manufacturer would create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance, that could also be represented in third-party tools

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-6

FPGA
The field-programmable gate array (FPGA) is completely manufactured by the IC vendor
The device is design independent

Each manufacturer has their own proprietary architecture for their devices that includes
Programmable blocks connected to Programmable switch matrices

A device is configured to implement a particular design by programming the switch matrices to route signals between programmable logic blocks
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-7

ASIC versus FPGA

ASIC devices have an initial NRE cost
After the initial cost, the per unit cost can be low

FPGA devices typically have a higher unit cost than ASIC devices If production volume is low then FPGA is probably the implementation choice For high volume devices, ASICs may be more cost effective For the same design, ASICs will generally hold a performance advantage over FPGAs Alternately FPGA may be used in prototyping and ASIC used in high volume production

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-8

Top-down Design Methodology

System Algorithm

Increasing behavioral abstraction

Architecture RTL Gate Transistor

Increasing detail and complexity

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-9

Example Design Flow

Quartus II Development Software Handbook v 5.0

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-10

Design Domains

Behavioral level of abstraction System Algorithm RTL Logic Gate

Design Model Domain Abstract Architectural Design Structural Design

verification verification verification

Structural
Architecture synthesis

Physical

RTL synthesis Logic synthesis

Logic Design Layout Design

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-11

Electronic Design Automation Tools

An EDA system usually includes the following tools
Design entry Synthesis and optimization Simulation Physical design

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-12

Design entry
The process of entering into the CAD system a description of a circuit being designed is called design entry Three common design entry methods
Using truth tables
User enters a truth table in plain text format or draws a waveform that represents the desired functional behavior

Schematic capture
User graphically enters a desired logic circuit

Hardware description languages

User enters a programming language-like description of a desired logic circuit
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-13

Design entry with truth tables

Commonly use a waveform editor to enter a timing diagram that describes a desired functionality for a logic circuit
CAD system transforms this into equivalent logic gates Not appropriate for large circuits, but can be used for a small logic function that is to be part of a larger circuit

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-14

Schematic capture
Schematic: refers to a diagram of a circuit in which circuit elements (logic gates) are shown as graphical symbols and connections between them are drawn as lines Tool provides a collection of symbols that represent gates of various types with different inputs and outputs. A library. Previously designed circuits can be represented with a graphical symbol and used in larger circuits.
Known as hierarchical design and provides a way of dealing with complexities of large circuits
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 1-15

Hierarchical Design

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-16

Hardware description languages

A hardware description language (HDL) is similar to a computer program except that it is used to describe hardware Common HDLs
VHDL (VHSIC Hardware Description Language) Verilog Many others (vendor specific)

VHDL and Verilog are standards

Offer the option for portability across different CAD tools and different types of programmable chips

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-17

Synthesis
Synthesis CAD tools perform the process of generating a logic circuit from some stated functional behavior Translating (compiling) VHDL code into a network of logic gates is a part of synthesis Not only will the CAD tool produce a logic circuit, but it can also optimize that circuit
In terms of speed and/or size (logic optimization) Called logic synthesis or logic optimization

Finally, technology mapping and layout synthesis (physical design) complete the synthesis process

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-18

Simulation
Once designed, it is necessary to verify that the design circuit functions as expected In a functional simulation the user specifies valuations of the circuits inputs and the CAD tool generates the outputs (commonly in the form of a timing diagram)
User verifies generated outputs against expected outputs

Functional simulators assume the time needed for signals to propagate through the logic gates is negligible
Sometimes called zero-delay simulators For a real implementation this is not sufficient Use a timing simulator to obtain accurate (complete) simulation

Electrical & Computer Engineering

Dr. D. J. Jackson Lecture 1-19

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