Chapter 3
Instruction Set Summary
(I. Scott Mackenzie)
By: Masud-ul-Hasan
8051 Addressing Modes
There are basically 5 ways of specifying source/destination operand addresses: 1. Particular On-chip Resources: This includes the Accumulator (A), the Stack Pointer (SP), the Data Pointer (DP), the Program Counter (PC), and the Carry (C). Other On-chip Registers are Memory-mapped while these have special Op-codes. 2. Immediate operands: The # sign is the designator. These are 8-bits except for DPTR contents (16-bits). 3. Register operands: Designated as Rn, where n is 0..7. One of the four Register Banks is used (selected by RS0 and RS1 in PSW). 4. Direct Operands: From 00 to FF Hex, specifies one of the internal data addresses. 5. Indirect Address: Designated as @Ri, where i is 0 or 1, uses the contents of R0 or R1 in the selected Register Bank to specify the address. Other form is @A, using Accumulator contents.
By: Masud-ul-Hasan 2
8051 Addressing Modes
Addressing modes are an integral part of each computers instruction set. They allow different ways of specifying source/destination operand addresses depending on the programming situation. There are 8 modes of addressing:
1. 2. 3. 4. 5. 6. 7. 8. Immediate Register Direct Indirect Relative Absolute Long Indexed
General Format of Instruction: Label: OpCode Destination, source ; Comments
By: Masud-ul-Hasan 3
Instruction Set : Arithmetic
Mnemonics ADD ADDC SUBB Operands Bytes/Cycles 1/1 2/1 1/1 2/1 1/1 1/1 2/1 1/1 1/2 1/4 1/4 1/1 A, Rn A, direct A, @Ri A, #data INC DEC A Rn direct @Ri INC MUL DIV DA DPTR AB AB A
In Rn, n is 0..7. One of the four Register Banks is used (selected by RS0 and RS1 in PSW)
MOV PSW, #00011000B ADD A, R7 ; Select Register Bank 3 ; Add the contents of Register 7 to the Acc.
In Ri, i is 0 or 1.
By: Masud-ul-Hasan 4
Instruction Set : Logical
Mnemonic ANL ORL XRL Operands A, Rn A, direct A, @Ri A, #data direct, A direct, #data C, bit CLR CPL A C bit Bytes/Cycles 1/1 2/1 1/1 2/1 2/1 3/2 2/2 1/1 1/1 2/1
By: Masud-ul-Hasan
Instruction Set : Logical (cont'd)
Mnemonic RL RLC RR RRC SWAP SETB CLR CPL Operands A A A A A C bit Bytes/Cycles 1/1 1/1 1/1 1/1 1/1 1/1 2/1
By: Masud-ul-Hasan
Instruction Set : Logical (cont'd)
RL RLC RR A A A
7 C C 7 Acc 0 Acc 7 Acc 7 Acc 0 0 0
RRC A
4 3
SWAP A
Acc
By: Masud-ul-Hasan
Instruction Set : Data Transfer
Mnemonic MOV Operands A, Rn A, direct A, @Ri A, #data Rn, A Rn , direct Rn, #data direct, A direct, Rn direct, direct direct, @Ri direct, #data Bytes/Cycles 1/1 2/1 1/1 2/1 1/1 2/2 2/1 2/1 2/2 3/2 2/2 3/2
By: Masud-ul-Hasan
Instruction Set : Data Transfer (cont'd)
Mnemonic MOV Operands @Ri, A @Ri, direct @Ri, #data DPTR, #data16 C, bit bit, C MOVX A,@DPTR @DPTR,A A,@Ri @Ri,A Bytes/Cycles 1/1 2/2 2/1 3/2 2/1 2/2 1/2 1/2 1/2 1/2
By: Masud-ul-Hasan
Instruction Set: Data Transfer (cont'd)
Mnemonic MOVC Operands A, @A+DPTR A, @A+PC PUSH POP XCH direct direct A, Rn A, direct A, @Ri XCHD A, @Ri Bytes/Cycles 1/2 1/2 2/2 2/2 1/1 2/1 1/1 1/1
By: Masud-ul-Hasan
10
Instruction Set : Branching
Mnemonic LCALL ACALL RET RETI LJMP AJMP SJMP JMP JZ JNZ Operands addr16 addr11 addr16 addr11 rel @A+DPTR rel rel Bytes/Cycles 3/2 2/2 1/2 1/2 3/2 2/2 2/2 1/2 2/2 2/2
By: Masud-ul-Hasan
11
Instruction Set : Branching (cont'd)
Mnemonic CJNE Operands A, direct, rel A, #data, rel Rn, #data, rel @Ri,#data,rel DJNZ Rn, rel direct, rel NOP JC JNC JB JNB JBC rel rel bit, rel bit, rel bit, rel Bytes/Cycles 3/2 3/2 3/2 3/2 2/2 3/2 1/1 2/2 2/2 3/2 3/2 3/2
By: Masud-ul-Hasan
12
