Time-Division Multiplexing of Digital Signals

Siemens

Time-Division Multiplexing of Digital Signals

Contents
1 2 2.1 2.2 3 4 5 6 6.1 6.2 6.3 Basic Methods of Multiplexing Synchronization between Transmitting End and Receiving End Recovery of Frame Alignment Loss of Frame Alignment Definition of Plesiochronous Digital Signals Clock Alignment of Plesiochronous Signals Basic Pulse Frame Structure Realization of the Positive Justification Method The Elastic Store (Multiplex-Side) The Elastic Store (Demultiplex-Side) Jitter caused by Multiplexers 3 9 12 12 13 21 25 29 30 34 36

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Basic Methods of Multiplexing

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For the generation of the sum signal out of the individual separate signals the following two methods may be used: Code word interleaving With this method code words of the individual separate signals (i.e. bit combinations having some kind of relation between each other) are arranged one after the other in a time sequence. Such is the case for the generation of a 2-Mbit/s-signal, where the 8 bit binary words of the coded PCM-voice channels are transmitted sequentially in a 125 ms cycle. This figure shows the code word interleaving of two separate signals with a word length of four bits.

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Code word interleaving

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Fig. 1

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Bit-by-bit interleaving This method is used for all systems beyond the 2 Mbit/s hierarchy. Here a cyclic transmission sequence is applied, where only one bit of each separate signal is transmitted. This means that the signal of a certain multiplexer input appears only in every fourth bit of the sum signal. The figure shows the bit-by-bit interleaving of two separate signals.

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Bit-by-bit interleaving

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Fig. 2

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Two basic cases can be distinguished with multiplexing: 1. the original signals are synchronous, i.e. their clocks are exactly the same. This is valid for a PCM30 system, where the clocks of the individual 64-kbit/s-signals and the 2 Mbit/s-clock are derived from a central system clock. In this case the multiplexing process is restricted to a simple parallel-to-serial conversion of the 8 bit code words. 2. the original signals are not synchronous, i.e. their clocks come from different sources. This is valid for the multiplexing of output signals, originating from various PCM30 systems their clocks being generated in each system in an autonomous way. Here it is necessary to take appropriate measures in order to compensate the occurring clock differences. This case will be dealt with in the following chapters.

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Synchronization between Transmitting End and Receiving End

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Time-Division Multiplexing of Digital Signals

For each type of multiplexing it has to be ensured that the sum signal can be resolved into the individual original signals (demultiplexing process). The receiver of the sum signal thus has to know which bits are assigned to the individual subsystems. To allow for this, a fixed bit combination, the so-called frame alignment word (FAW) is inserted by the transmitting system in periodically recurring intervals into the sum signal. If the receiver detects the frame alignment word in the received signal it is possible to perform the assignment of the following bits to the subsystems by means of the regenerated receiving clock (see also chapter 6). The time intervals between the beginning of a FAW and the beginning of the following FAW are called pulse frames.

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F A W

F A W

F A W

F A W

frame N

frame N+1

frame N+2

a) b) FAW X Y

continous searching of the FAS position periodical check of the FAW position Frame alignment word Bit combination pretending the FAW any bit combination one frame length after X

a) b) FAW X Y
Fig. 3

continuous searching of the FAS position periodical check of the FAW position Frame alignment word Bit combination pretending the FAW any bit combination one frame length after X

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Time-Division Multiplexing of Digital Signals

2.1

Recovery of Frame Alignment

During recovery of frame alignment (e.g. during initial commissioning of a system) the receiver continuously examines the incoming signal upon occurrence of the FAW. If this FAW is detected for the first time, the receiver expects a renewed occurrence only after the specified pulse frame period has elapsed (counting of the receiving signal clocks). In this case the process will be repeated; the synchronization is established. Otherwise, the system takes the continuous searching up again. This procedure ensures that a synchronization to a bit combination, which accidentally has the same content as the FAW, is excluded.

2.2

Loss of Frame Alignment

Only if the FAW does not appear in the expected positions for several consecutive times (e.g. four) the frame alignment is supposed to be lost. This guarantees that in case of transmission errors the system does not perform an immediate desynchronization. For each faulty frame alignment word a pulse is produced, which can be used for the estimation of the bit error rate (see also chapter 6, in-service measurement of bit error rates).

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Definition of Plesiochronous Digital Signals

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Time-Division Multiplexing of Digital Signals

Supposed a data source (S) transmits a digital signal with a bitrate fS to a data drain (D). The data drain decides with the aid of an internally generated clock frequency fR whether the incoming signal is zero or one in the moment of the clock pulse. The two clock signals fS and fR are thus generated in different places and although they do have the same nominal frequency, they will always differ from each other to a certain extent. Definition: Data signals are termed plesiochronous if their clock rates have the same nominal value, but may differ from each other within certain tolerance ranges.

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data signal with bitrate fS read in data with clock rate fR

Fig. 4

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The effects of these clock deviations are represented in the two figures below: Sampling clock fR > transmission clock fS Two sampling instants are within one bit interval of the transmitting signal. The data drain (D) interprets this situation as double transmission of bit a5.

double bit transmission

fS a1 a2 a3 a4 a5 a6 a7

fR

D a1 a2 a3 a4 a5 a5 a6 a7

Fig. 5

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Sampling clock fR < transmission clock fS One transmitted bit is between two sampling instants. Bit b5 not detected by the data drain (D).

no bit transmission

fS b1 b2 b3 b4 b5 b6 b7

fR

D b1 b2 b3 b4 b6 b7

Fig. 6

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Plesiochronism during Multiplexing Process The multiplexing process may be represented with the aid of the following figure. A rotating pointer samples the feeder links (tributaries) for the separate signals with a frequency which is four times higher than the nominal bitrate fS (fR = 4 X fS), i.e. each digital signal is sampled with a nominal fS. As both, the digital signal sources (S1...S4) as well as the sampling frequency (fR) are generated by different clock sources, the result is a plesichronous state of operation for every feeder link. Example: The signal sources (S1...S4) are PCM30 devices transmitting with their individual transmission clock a 2 Mbit/s-signal with clock tolerances to the inputs of a 2/8 multiplexer.

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fS Df1 S1

fS Df2 S2 fR Df D fS Df3 S3 fR = 4x fS fS Df4

S4

Fig. 7

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Clock Alignment of Plesiochronous Signals

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During multiplexing of plesiochronous digital signals the so-called positive justification method is applied, which is based on the following principles:
l

a bitrate for each subsystem is provided in the multiplex signal, which is somewhat higher than the subsystems nominal bitrate. This means that the transmission capacity is systematically higher than actually needed. the difference between the bitrate of the subsystem and the multiplex bitrate per system is compensated for each channel by the justification bitrate, which does not contain any information and serves only for the compensation mentioned above. the justification bitrate is thus always adjusted to the difference between the bitrate of the subsystem and the multiplex system and thereby compensates for each channel the tolerance between the tributary signal bitrates and multiplex signal bitrates.

Example:

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fR - fS1 fS1 S1 + fR fR - fS2 fS2 S2 + fR fR - fS3 fS3 S3 + fR fR - fS4 S4 fS4 + fR 4 x fR D

Fig. 8

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l l

The signal sources S1..S4 emit signals with a nominal value of 2048 kbit/s The sampling pointer rotates with a frequency of fR = 2052 kHz, i.e. the transmission capacity per channel is 4 kbit/s higher than the nominal bitrate of the subsystem. Supposed the signal sources transmit the following actual bitrates: S1 S2 S3 S4 : : : : fS1 = 2048.1 kbit/s fS2 = 2048.05 kbit/s fS3 = 2048.0 kbit/s fS4 = 2047.9 kbit/s

This results in the following justification bitrates: for channel 1 : 2052 kbit/s - 2048.10 kbit/s = 3.90 kbit/s channel 2 : 2052 kbit/s - 2048.05 kbit/s = 3.95 kbit/s channel 3 : 2052 kbit/s - 2048.00 kbit/s = 4.00 kbit/s channel 4 : 2052 kbit/s - 2047.90 kbit/s = 4.10 kbit/s Thus, the resulting signals at the rotating pointers sampling points are synchronous. The multiplexing procedure can be performed without the former discussed problems of omission or double sampling of individual bits.

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Basic Pulse Frame Structure

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How is a variable justification bitrate realized The signals of higher hierarchy levels are transmitted within a predetermined frame structure, the same as for the 2 Mbit/s signal of the first hierarchy level. This frame begins with a frame alignment word of fixed length and content in order to allow on the demultiplex side of the system an allocation of the following bit-interleaved tributary bits to the appropriate channels. In addition, the frames of the plesiochronous hierarchy contain one bit position per individual signal, which is either used for the transmission of a tributary bit, or not used at all. This bit position is called justification bit. By alternate use/non-use of this bit position, the transmission capacity for the individual signals may be varied to some extent. This process is called positive pulse justification; thus, the non-use of the justification bit position corresponds to an increase in the justification bitrate (= decrease in the transmission capacity), whereas the use of the justification bit position has the opposite effect.

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Siemens

FAW

TB 1...4

JS JS JS JS 1 2 3 4

TB 1...4

JB JB JB JB 1 2 3 4

TB 1...4

FAW JS1..4 JB1..4 TB1..4

Fig. 9

Frame alignment word Justification service bit position for channels 1..4 Justification bit position for channels 1..4 Tributary bits for channels 1..4; here the tributary signals are transmitted bit-by-bit interleaved

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The receiving end of such signals requires an information on how the justification bit position has been used (non-information bit or tributary bit). To allow for this, there are justification service bits arranged before the justification bits in the time sequence. The content of the justification service bits indicates how the following justification bit position has to be interpreted. If, for example, the content of the justification service bit for channel 3 is a binary one, the receiver ignores the following justification bit positions of channel 3. The other way round (JS3 = 0), the position JB3 is interpreted as tributary bit. Example: The frame structure in a 8 Mbit/s pulse frame: frame duration: 100.38 ms overall number of bits in blocks TB1:200 bit, TB2:208 bit, TB3:208 bit, TB4:204 bit or 208 bit. This results is an actual bitrate/channel of: BRT = 820bit = 2,04224Mbit / s 100.38 ms 4

This is the bitrate /channel if the justification bit position is always unused. If every justification bit position is used for a tributary bit of the separate signal the following actual bitrate/channel is calculated: BRT = 824bit =2,05220Mbit / s 100.38 ms 4

By alternate use/non-use of the justification bit position in the frames the transmission capacity for the individual channels in this examples may be varied within a range of 9.962 kbit/s.

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Realization of the Positive Justification Method

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6.1

The Elastic Store (Multiplex-Side)

How can the justification process be realized? An elastic store consists of a number of 1 bit memory cells (typ. 12) which can be written in and read out independently of each other (i.e. at the same time it is possible to write in one cell, while another is read out). The incoming separate signal with its own clock is written in the cells 1...8, 1...8 etc. in a cyclic way. The store is read out with a clock, generated in the multiplexer; a clock which is systematically higher than the bitrate of the separate signal. The difference between write address and read address is monitored by an address comparator. It goes without saying that the write address always has to be ahead of the read address. Due to the greater read out velocity the read address continually approaches the write address. If the difference between the two becomes < 3 memory cells, the comparator releases a signal. Then the following procedures are started: If the justification service bit position in the frame is reached, the bit is set to one. On reaching the justification bit position, the read address is maintained for one clock period and the actual memory cell is read out once more. This is the justification bit which is ignored at the receiving end. By maintaining the read address during one clock cycle the difference between the addresses increases and the whole procedure is repeated in the same way. Thus, the plesiochronous clock rate of the channel is matched to the multiplex bitrate. Between the initiation of the justification process (comparison of addresses) and its execution there may be an interval of max. 1 frame period, within which the read address approaches the write address more and more. That is why the justification process is initiated already when the address spacing is smaller than 3, in order to ensure a reserve against memory overflow, e.g. an empty memory. Each channel is assigned an elastic store. As the read out clock for all channels come from the same clock supply (in the multiplexer), the output bitrates of the elastic stores are synchronous. The actual multiplexing procedure is thereby continued to a simple parallel-to-serial conversion of the output signals of the elastic stores for the four separate signals.

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Siemens

T2

TG ch 2 . . 4

TR

T1

GAP

D1

JS

D2

ch 2..4

P/S

AC

LOGIC

TR AC TG GAP JS LOGIC P/S D1 D2 T1 T2

: : : : : : : : : : :

Timing regenerator input signal (= write in timing) Address comparator Timing generation of read out timing channels 1..4 Timing gap for justification procedure Insertion of justification service bit Control of the justification service bit and of the timing gap Parallel-to-serial converter Tributary input data with independent of the system clock Stuffed output data, synchronous to the system clock Retrieved clock from tributary input data for write in Read out clock from central clock supply

Fig. 10 Principle of an elastic store

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D1

ES

JS

D2

AC LOG TR T1 CTR CTR T2

ch 2 ... 4 TG

P/S

ch 2 ... 4

TR CTR ES AC JS LOG TG D1 D2 T1 T2

: : : : : : : : : : :

Timing regenerator input signal Counter for the generation of write in/read out address Elastic store Address comparator Insertion of justification service bit Logic circuit - controls the insertion of the justification service bits, removes one clock period depending on the output signal of the AC Generation of timing signals for the complete multiplexer side Plesiochronous tributary Stuffed tributary, synchronized to system clock Recovered clock from tributary input for write in Read out clock, derived from central clock supply

Fig. 11 Block diagram of an elastic store

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Realization of the positive justification method positive justification method : f2 > f1

f1

Input signal

f2

Output of the elastic store

Multiplex signal

Justification bit (non-information bit)

Fig. 12

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Example (see also fig.12):

l l l

the bitrate of the input signal shall be f1 = 2048 kbit/s. the pulse frame of the multiplex signal shall be 100,38 ms and contains 1 justification bit per channel the read out timing rate shall be 2052 kbit/s. The reading pointer would overpass the writing pointer (2052 kHz-2048 kHz = 4 kHz) 4000 times per second. That is why on average one justification bit is inserted every 250 ms (1/4 kHz = 250 ms). For a pulse frame of 100,38 ms, this means that one justification is effected on average in every 2,5th frame (250 ms/ 100,38 ms) (2 in 5 frames).

the bitrate of the input signal shall now be T1 = 2047,90 kbit/s. Now the justification must be effected every 243,90 ms, i.e. in every 2,4 pulse frame.

the bitrate of the incoming signal shall be T1 = 2048,10 kbit/s. A justification is required every 256,40 ms, i.e. in every 2,56 frame.

6.2

The Elastic Store (Demultiplex-Side)

The task of the demultiplexer is to distribute the sum signal in the right sequence to the output of the separate signals. Therefore, the incoming multiplex signal is divided into 4 separate signals by means of parallel-to-serial conversion. By control of the frame alignment signal the 4 separate signals can be assigned to the right channels. Besides, the justification service bits and justification bits can be identified (by counting the bits transmitted since the beginning of the frame). By means of this information the justification process is canceled, i.e. all bits which do not come from the original signal are removed from the separate signals. Thus, a signal with timing gaps instead of the removed bit positions is generated. In order to guarantee a continuous signal at the outputs, elastic stores are used on the demux-side to smooth the signal. For this, the incoming datas signal is written into the store with the gap timing and read out of the store with a continuous timing which corresponds to the average value of the gap timing; thus the signal is forwarded in a smoothed condition to the outgoing subsystem interface.

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Siemens

data signal with gaps ES

data signal continuous

CTR gap timing

CTR continuous timing

phi

CTR

ES CTR VCO phi/U

Elastic store Counter Voltage controlled oscillator Phase comparator

Fig. 13 Principle of an elastic store (demultiplex-side)

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A continuous timing is generated from the gap timing by means of a phase-locked loop (PLL). For this, a voltage-controlled oscillator is synchronized to the gap timing frequency. If the critical frequency of the control loop is selected sufficiently low (lowpass filter) it is ensured that the voltage-controlled oscillator adjusts itself to the average value of the gap timing frequency.

6.3

Jitter caused by Multiplexers

The gap in the write clock of the elastic store result in phase shifts on the input-side of the PLLs phase comparator, which are converted to voltage shifts. These voltage shifts are smoothed by the low pass filter of the PLL, but they can never be smoothed perfectly. That is why the smoothed clock of the control voltage will vary accordingly also at the output of the PLL circuit, i.e. jitter is generated. The jitter in the output signal depends on the system. The highest jitter frequency is determined by the limit frequency value of the PLL low-pass filter.

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