National Chip Implementation Center

SystemC

7.
SystemC C++ long int short char
unsigned longunsigned intunsigned shortunsigned charfloat
doublelong doubleboolSystemC
2
2 SystemC

sc_bit

01

sc_logic

0(false)1(true)X()Z()

sc_int

164(signed)

sc_uint

164(unsigned)

sc_bigint

sc_biguint

sc_bv

sc_lv

sc_fixed

(templated)
(compile time)

sc_ufixed

sc_fix

(untemplated)

sc_ufix

sc_fixed_fast

(double precision)

sc_ufixed_fast

(Mantissa)53

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National Chip Implementation Center
8.

sc_main
6module.h
module.cpp7
[2]

// adder.h
// adder.cpp

#include systemc.h

#include adder.h

SC_MODULE(adder) {

void adder::adder_proc() {

//

while(true) {//

sc_port<sc_fifo_in_if<int> > in1;

out->write(in1->read()+in2->read() );

sc_port<sc_fifo_in_if<int> > in2;

out->write(in1->read()+in2->read()

//

+2);
sc_port<sc_fifo_out_if<int> > out;
}
//
}
void adder_proc();
SC_CTOR(adder){
SC_THREAD(adder_proc);
}
}

6 [2]

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National Chip Implementation Center

7 -[2]

// stimgen.h
// stimgen.cpp

#include "systemc.h"

#include "stimgen.h"

SC_MODULE(stimgen) {

void stimgen::stim_proc()

//

{
sc_port<sc_fifo_out_if<int> > a1;
int tmp;
sc_port<sc_fifo_out_if<int> > a2;
for (int i = 0; i <= 20; i++) {
//
tmp = seed + 1;
int seed;

a1->write(tmp);

//thread

a2->write(tmp + 5);

void stim_proc ();

seed = (seed + 19) % 123;

SC_CTOR(stimgen) {

seed = 12;

sc_stop();

SC_THREAD(stim_proc);

}
};

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National Chip Implementation Center

// monitor.h
// monitor.cpp

#include "systemc.h"

#include "monitor.h"

SC_MODULE(monitor) {

void monitor :: monitor_proc()

//

{
sc_port<sc_fifo_in_if<int> > re;
while (true) {
//sc_fifo_in<int> re;
cout << "The result of the computation
void monitor_proc ();

is = " << re->read() << endl;

SC_CTOR(monitor) {

SC_THREAD(monitor_proc);

}
};

main.cpp
// main.cpp

//

#include systemc.h

stimgen stim(stim);

#include adder.h

stim(s1,s2);

#include stimgen.h
#include monitor.h

adder add(add);

int sc_main(int argc, char *argv[ ] )

add(s1, s2, s3);

{
// 10 fifo

monitor mon(mon);

sc_fifo<int> s1(10);

mon.re(s3);

sc_fifo<int> s2(10);
//

sc_fifo<int> s3(10);

sc_start();
return 0;
}

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National Chip Implementation Center
9.
SystemC

(protocol)
()()
SoCIPIP

SystemC
YX8
UTF(UnTimed Functional)
(zero time)
TF(Timed Functional)
(latency)BCA(Bus Cycle Accurate)
transactionPCA(Pin Cycle Accurate)
clockRT(Register Transfer)
clock
FSMRTL
RTL
(System Architectural ModelSAM)

(System Performance ModelSPM)

SAMSPM(Functional ModelFM)
Transaction(TLM)transaction
transactionclock
TLM
RTL(System Level Model
SLM)(Behavioral Level ModelBLM)

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National Chip Implementation Center
(Behavioral Synthesis ModelBSM)
PCATF
(Bus Functional ModelBFM)ARM
AMBABFMtransaction

8 [3]

RTL

UTF

UTF

TLM

RTL

RTL

Adaptor

UTF
DSP

TLM

MEM

Testbench
9 [2]

-6-

RTL

DUT


National Chip Implementation Center

RTL

UTF

UTF

TLM

RTL

RTL

RTL

Adaptor

UTF
MEM

TLM

Testbench
#include
main() {

DSP
development
environment

10 [2]

9
RTL(VerilogSystemCVHDL)
(Design Under TestDUT)UTFTLM(executable
specification)(adaptoradapter)
UTF TLM SC_METHOD
SC_THREADTLM

sc_fifoI/O
(Application Program InterfaceAPI)TLMRTL
sc_signal
10RTLDSP

(communication
refinement)SystemC 2.011
TLMmy_master
my_procTLM
RTLTLM

TLMRTLTLMRTL
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National Chip Implementation Center
12

SystemC

11 TLM

-8-


National Chip Implementation Center

12

10. SystemC
(ESL)
SystemC

transaction IP Synopsys Behavioral

Compiler SystemC Compiler SystemC
RTL SystemC 2003 Synopsys
SystemC RTL SystemVerilog
Synopsys SystemC CoCentric System
Studio SystemC
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National Chip Implementation Center
Synopsys ARM SystemC Virtio
System Studio [4] 7.2 VCS Verilog
SystemC SystemCVerilogVHDLVera
SystemVerilog Synopsys ESL
Cadence 2003 Signal Processing Worksystem (SPW)
CoWare CoWare SystemC
ConvergenSC SystemC
(design aggregation & exploration)
SoC
ESL Cadence Cadence Incisive
SystemC 90 VCC
transaction Cadence Palladium
Cadence Get2Chip
Architectural Compiler Cadence Berkeley
[4]
Mentor Graphics ESL C 2004 6
2 C/C++ Catapult Forte
Cynthesizer Cadence Seamless

C ModelSim 5.8 SystemC

Platform Express IP
Mentor Graphics
SystemC TLM
[4]
SynopsysCadence Mentor Graphics ESL
ESL
EDA CoWareForteSummit DesignCeloxicaAccelChip Verisity
SystemC IC SystemC
SystemC OSCI 2003 SystemC 2.1 IEEE
2004 11 IEEE IEEE
(DASC) IEEE P16666 SystemC
SystemC
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National Chip Implementation Center
(LRM) LRM
SystemC 3.0 scheduler RTOS
SoC

1
IP ESL
SystemC ESL EDA

HDL

3C IC Top-down
SystemC IC
SystemC SoC
SoC

[1] S. Swan, An Introduction to System Level Modeling in SystemC 2.0, white paper,
www.systemc.org, May 2001.
[2] Getting Started with CoCentric System Studio Architectural Modeling Student Guide,
Synopsys Inc., USA. January 2003.
[3] Modeling with SystemC & CoCentric System Studio, Version 4.6a, Willamette HDL, Inc.
2002.
[4] , (ESL)EDA, EE Times Taiwan(

), Nov. 2004.

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