Lovely Professional University, Punjab

Course Code ECE440 Course Category Course Title HDL PROGRAMMING LABORATORY Practical Course Course Planner 15929::Abhinav Vishnoi Lectures 0.0 Tutorials Practicals Credits 0.0 2.0 1.0

TextBooks Sr No T-1 Title Digital System Design Reference Books Sr No R-1 Title Verilog HDL Author Samir Palnitkar Edition 2nd Year 2006 Publisher Name Pearson Author Charles Roth Edition 3rd Year 2010 Publisher Name 2. Prentice Hall

Relevant Websites Sr No RW-1 (Web address) (only if relevant to the course) http://nptel.iitm.ac.in/courses/IITMADRAS/ CAD_for_VLSI_Design_II/magma_tutorial/magma_tutorial.html (AV aids) (only if relevant to the course) http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/index.php Salient Features ASIC tutorials

Audio Visual Aids Sr No AV-1 Salient Features lectures delivered by IIT professors on digital system design

Software/Equipments/Databases Sr No SW-1 Virtual Labs Sr No VL-1 (VL) (only if relevant to the course) Salient Features http://deploy.virtual-labs.ac.in/labs/cse13/index.php?section=List%20of %20experimentsOnline Simulators Developed by MHRD (S/E/D) (only if relevant to the course) cadence NC sim / virtuoso Salient Features Simulation of Digital Circuits

*Each experiment of the lab will be evaluated using following relative scheme:
Component J/E WR VIVA % of Marks 20 50 30

Detailed Plan For Practicals

Practical No Practical 1 Practical 2 Practical 3 Broad topic (Subtopic) Implementation of SSI(Design and implementation of different gates) Practical Description Implementing Logic Gates Learning Outcomes Equipment Used Students know to simulate Basic Gates Cadence Tools in NCLaunch Students know to simulate 1-bit Adders Cadence Tools in NCLaunch Students know to simulate Multiplexer Cadence Tools in NCLaunch Students know to simulate Parity Generator in NCLaunch Cadence Tools

Implementation of SSI(Design a half and Design and Implementation of 1-bit full adder) Adders Implementation of Applications of SSI(Design of MUX with different modelling styles) Implementation of Applications of SSI(Design of Parity generator) Design and Implementation of MSI Devices Design and Implementation of Parity Generator in NCLaunch

Practical 4 Practical 5

Transition from Combinational to Design and Implementation of CLA Students know to simulate CLA and/or Cadence Tools sequential circuits(Design of Ripple carry and/or Ripple Carry Adder in NCLaunch Ripple Carry Adder in NCLaunch adder/carry look ahead adder) Transition from Combinational to sequential circuits(Design and implementation of different flip flops) Design and Implementation of Basic Flip- Students know to simulate Flip-Flops Flops in NCLaunch in NCLaunch Students know to simulate Ripple Counter in NCLaunch Cadence Tools

Practical 6

Practical 7 Practical 8 Practical 9 Practical 10

Applications of Flip-Flops(Design a ripple Design and Implementation of Ripple counter) Counter in NCLaunch Applications of Flip-Flops(Design a sequence generator)

Cadence Tools Cadence Tools

Design and Implementation of Sequence Students know to simulate Sequence Generator in NCLaunch Generator in NCLaunch

ALU and Shift Registers(Design of an 4 Design and Implementation of 4-bit ALU Students know to simulate 4-bit ALU in Cadence Tools bit ALU for 4/5 different functions) in NCLaunch NCLaunch ALU and Shift Registers(Design of SISO/PIPO shift registers) Design and Implementation of Shift Registers in NCLaunch Students know to simulate Shift Registers in NCLaunch Cadence Tools

SPILL OVER
Practical 11 Practical 12 Revision Revision Doubts will be Cleared Doubts will be Cleared Cadence Tools Cadence Tools