SYNOPSIS

CARRER INSTITUTE OF TECHNOLOGY & MANAGEMENT. BRANCH ELECTRONICS AND COMMUNICATION PROJECT NAME FUTURE GENERATION VOTING MACHINE

WITH NEW SMART RF CARD. Submitted by, Nishant Yadav Gaurav Goyal Mentor, Ms-Prerna Department of ECE.

Himanshu Gurumaita

Introduction With the help of this technique we provide a smart and new concept in the voting machine. With the help of this technique we provide a smart dual security in the voting machine. Machine automatic recognize the person detail and demanding a password. If the smart card is not verified then machine never respond and if the password is wrong then again machine refuse for voting.

For this purpose we provide a advance smart card to each voter. This smart card TH NEW SMART RF CARD is actually a U.I.D code of the

person. Person use this card as a pan number or as a citizen id number. Each card equipped with a password. When person enter a password then only machine accept the card. We use the same card as a ATM CARD ALSO. When any voter receive this card then it is possible for the voter to cast the vote by showing its RF based smart card to the machine.

Basic concept on project,

This specail code is in the form of bits characters.

This receiving module is of 125khtz receiver and provide a data in the form of ascii code or in the form of wiegand 26 bit. We receive this code and process inside the microcontroller. If the microcontroller compare this code then only name is to be display on the lcd. Every name has a special variable with password. Now person enter a

password and if the password is ok then person enter a vote in the voting machine

This project aimed to develop a wireless system to detect and allow only the authorized persons. The system was based on Radio Frequency Identification (RFID) technology and consists of a passive RFID tag. The passive micro transponder tag collects power from the 125 KHz magnetic field generated by the base station, gathers information about the Tag ID and sends this information to the base station. The base station receives, decodes and checks the information available in its Database and Manchester code was used to send those information. The system performed as desired with a 10cm diameter antenna attached to the transponder. The Base Station is built by using the Popular 8051 family Microcontroller. It gets the tag ID and if the tag ID is stored in its memory then the microcontroller will allow the person inside.

RFID Reader Module, are also called as interrogators. They convert radio waves returned from the RFID tag into a form that can be passed on to Controllers, which can make use of it. RFID

tags and readers have to be tuned to the same frequency in order to communicate. RFID systems use many different frequencies, but the most common and widely used Reader frequency is 125 KHz.

Circuit diagram and description VOTIN Voting is a method for a group such as a meeting or an electorate to make a decision or to express an opinion often following discussions or debates. 1.1.1 Voting Techniques In India all earlier elections be it state elections or centre elections a voter used to cast his/her vote to his/her favorite candidate by putting the stamp against his/her name and then folding the ballot paper as per a prescribed method before putting it in the Ballot box. This is a long, time-consuming process and very much prone to errors. This method wanted voters to be skilled voters to know how to put a stamp, and methodical folding of ballot paper. Millions of paper would be printed and heavy ballot boxes would be loaded and unloaded to and from ballot office to polling station. All this continued till election scene was completely changed by electronic voting machine

No more ballot paper, ballot boxes, stamping, etc. all this condensed into a simple box called ballot unit of the electronic voting machine.

.2 Project componet detail, Power Requirement _ 5V@44mA nominal Frequency _ 125 KHz Card Format _ EM4001 or compatible Encoding _ Manchester 64bit_modulus 64 I/O Output Current _ 25mA sink/source Antenna Volt _ 150Volt PKPK Output Format-ASCII 02 10ASCII Data Characters Checksum 03 The checksum is the result of the exclusive or of the 5 Binary Data bytes the 10 ASCII data

ADVANTAGES OF E-VOTING

The EVMs have following advantages: Elimination of CHECKING DATA. Can be interfaced with PC to generate back-ups The saving of considerable printing stationery and transport of large volumes of electoral material, Easy transportation, storage, and maintenance, No invalid votes, Reduction in polling time. Easy and accurate counting without any mischief at the counting centre Eco-friendly.

1.3 COMPARE A ND CONTRAST: PAPER VOTING, EVM and TVM We have so far discussed three different voting systems. These systems are being used or considered obsolete because of certain positive and negative points. These are summarized as follows:

Device type Ballot paper EVM RF EVM : Papers and boxes : Embedded system with Assembly code : Embedded system with Assembly code+ RF IDENTIFICATION

Visual Output Ballot paper EVM RF EVM : Stamp on paper : Single LED against each candidate's name : LCD screen and one LED

Security Issues Ballot paper : No security provided by the system, neither during polling nor during voting. EVM : During polling, a facility is provided to seal the machine in case of booth capturing. No further voting can be done afterwards. RF EVM : machine Is ok when you show your card with unique id code.

Power Supply Ballot paper : No power supply required.

EVM RFVM

: 6V alkaline batteries or electricity. : battery operated.

Capacity Ballot paper EVM RF- evm : As much a ballot box can hold. : 3840 Votes. Depends on the size of flash memory attached.

CHAPTER 2 POWER SUPPLY

2.1 INTRODUCTION These days almost all the electronic equipments include a circuit that converts AC supply into DC supply. The part of equipment that converts AC into DC is known as AC to DC converter. In general, at the input of the power supply is a transformer. It is followed by a rectifier, a smoothing filter and then by a voltage regulator circuit. 2.2 COMPONENTS OF POWER SUPPLY Power supply consists of four components:(i) Step-Down Transformer (ii) Rectifier (iii) Filter (iv) Voltage Regulator

Block diagram of such a supply is shown below:TRANSFORMER RECTIFIER FILTER VOLTAGE REGULATOR

Fig. 2.1 Block diagram 2.2.1 Step down Transformer A transformer in which the output (secondary) voltage is less than the input (primary) voltage is called step down transformer. Alternating current is passed through the primary coil which creates the changing magnetic field in iron core. The changing magnetic field then induces alternating current of the same frequency in the secondary coil (the output). A step down transformer has more turns of wire on the primary coil than in secondary coil which makes a smaller induced voltage in the secondary coil. The transformer equation relates the number of turns of wire to the difference in voltage between the primary and secondary coils.
Vp

/Vs = Np/Ns

...(2.1)

Vp is the voltage in the primary coil. Vs are the voltage in the secondary coil. Np is the number of turns of wire on the primary coil.

Ns is the number of turns of wire on the secondary coil.

2.2.2 Rectifier

Rectifier is defined as an electronic device used for converting A.C voltage into unidirectional voltage. A rectifier utilizes unidirectional conduction device like P-N junction diode. There are three types of rectifier:a. Half wave rectifier. b. Full wave center tap rectifier. c. Full wave bridge rectifier.

2.2.3 Filter The output from any of the rectifier circuits is not purely D.C but also has some A.C components, called ripples, along it. Therefore such supply is not useful for driving sophisticated electronic devices/circuits. Hence, it becomes essential to reduce the ripples from the pulsating D.C supply available from rectifier circuits to the minimum. This is achieved by using a filter or smoothing circuit which removes the A.C components and allows only the D.C component to reach the load. A filter circuit should be placed between the rectifier and the load.

2.2.4 Voltage Regulator Voltage Regulator (regulator), usually having three legs, converts varying input voltage and produces a constant regulated output voltage. 7805 voltage regulator has three pins:a. Input:- For 7805 the rectified and filtered voltage coming at this pin must be between 8 to 18V in order to get stable 5V DC output at the output pin.

7805

INPUT

OUTPUT GND

Fig. 2.2 Pin configuration b. Ground:- This pin is connected to the ground of the circuit to which this 5V DC supply is provided. c. Output:- If the input voltage at input pin is between 8-18V then at the output pin a stable 5V DC voltage will be available. 7805 can give +5V output at about 150 mA current, but it can be increased to 1A when good cooling is added to 7805 regulator chip.

2.3 5V DC POWER SUPPLY USING FULL WAVE CENTER TAP RECTIFIER The transformer supplies the source voltage for two diode rectifiers, D1 and D2. This transformer has a center-tapped, low-voltage secondary winding that is divided into two equal parts (W1 and W2). W1 provides the source voltage for D1, and W2 provides the source voltage for D2. The connections to the diodes are arranged so that the diodes conduct on alternate half cycles. When the center tap is grounded, the voltages at the opposite ends of the secondary windings are 180 degrees out of phase with each other. Thus, when the voltage at point A is positive with respect to ground, the voltage at point B is negative with respect to ground. Let's examine the operation of the circuit during one complete cycle.

During the first half cycle (indicated by the solid arrows), the anode of D1 is positive with respect to ground and the anode of D2 is negative. As shown, current flows from ground (center tap) to point A, through diode D1 to point B and to point D. When D1 conducts, it acts like a closed switch so that the positive half cycle is felt across the load (RL). During the second half cycle (indicated by the dotted lines), the polarity of the applied voltage has reversed. Now the anode of D2 is positive with respect to ground and the anode of D1 is negative. Now only D2 can conduct. Current now flows, as shown, from point C to point B through diode D2 then to point F and back to point D. Now during both the cycles the capacitor C1 quickly charges to the peak voltage but when the input voltage becomes less than peak voltage the capacitor discharges through load resistance and loses charge. But because of large load resistance the discharging time is large and hence capacitor does not have sufficient time to discharge appreciably. Due to this the capacitor maintains a sufficiently large voltage across the load.

Fig. 2.3 Centre-tap full-wave rectifier The voltage across the capacitor is applied to 7805 voltage regulator which provides a constant 5V D.C. voltage at its output.

Fig. 2.4 Output waveforms of centre-tap full-wave rectifier

Fig. 2.5 Output waveform of voltage regulator.

MICROCONTROLLER 89S52

7.1 INTRODUCTION The AT89S52 is a low-power, high-performance CMOS 8-bit

microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry- standard 80C51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer. By combining a

versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and Interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

7.2 FEATURES

Compatible with MCS-51 Products 8K Bytes of In-System Programmable (ISP) Flash Memory Endurance: 1000 Write/Erase Cycles 4.0V to 5.5V Operating Range Fully Static Operation: 0 Hz to 33 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters

 Eight Interrupt Sources Full Duplex UART Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Watchdog Timer Dual Data Pointer Power-off Flag Fast Programming Time Flexible ISP Programming (Byte and Page Mode)

7.3 BLOCK DIAGRAM

Figure 7.1

7.4 PIN DESCRIPTION

Figure 7.2

VCC GND

Supply voltage. Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the

timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally

being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, Port 2 uses strong internal pull-ups when emitting 1s.

Table 7.1 Alternate Functions of Port1

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table.

Table 7.2 Alternate Functions of Port3

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for Internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

7.5 MEMORY ORGANISATION

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.

7.5.1 Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.

7.5.2 Data Memory The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).

EXAMPLE: MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). EXAMPLE: MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

7.6 FUNCTIONAL DESCRIPTION The function of the pins of microcontroller AT89S52 used in the TELEVOTING MACHINE can be described as follows:

Pin no 1,2,3,4 of PORT 1 are connected to get the vote data input from 74154 (BCD to DECIMAL decoder) for four different candidates. Pin no 5,6,7,8 are connected to four push-button switches to check the vote data casted for individual candidate. Pin no 9 is connected to the reset button to reset the microcontroller automatically when we switch on the power. It is a Power on reset. Pin no 10 of PORT 3 is connected to a push-button switch to check the total vote caste for all the candidates. Pin no 11 and 12 of PORT 3 are connected to two push-button switches (R-1 and R-2) to reset or clear all the vote data. To reset the data firstly we will press the R-1 button then press the R-2 button and again press the R-1 button. Then all the vote data has to be cleared from the AT24c02 flash memory. Crystal is connected to the pin no 18(XTAL 1) and pin no 19(XTAL 2) providing 11.0592 MHz frequency. Pin no 20 is connected to the ground (GND). Pin no 21 and 22 of PORT 2 are connected to pin no 5(SDA- serial data) and pin no 6 (SCL- serial clock input) of AT24c02 flash memory.

 Pin no 26, 27, 28 of PORT 2 are connected to the pin no 4, 5, 6 of LCD display. Pin no 26 is connected to RS (register select), pin no 27 is connected to R/W (read/write select) and pin no 28 is connected to En(chip enable signal) of LCD. Pin no 31( EA/Vpp) should be strapped to VCC for internal program executions, this pin also receives the 12-volt programming enable voltage (VPP) during flash programming. Pin no 32 39 of PORT 0 are connected to the DB0-DB7 (8-bit) data lines of LCD display. Pin no 40 is connected to the positive supply (Vcc).

CHAPTER 8 LIQUID CRYSTAL DISPLAY

8.1 INTRODUCTION

Figure 8.FFFF FIG. 8.1 Liquid Crystal Display also called as LCD is very helpful in providing user interface as well as for debugging purpose. The most common type of LCD controller is HITACHI 44780 which provides a simple interface between the controller & an LCD. These LCD's are very simple to interface with the controller as well as are cost effective. The most commonly used ALPHANUMERIC displays are 1x16 (Single Line & 16 characters), 2x16 (Double Line & 16 character per line) & 4x20 (four lines & Twenty characters per line). The LCD requires 3 control lines (RS, R/W & EN) & 8 (or 4) data lines. The number on data lines depends on the mode of operation. If operated in 8-bit mode then 8 data lines + 3 control lines i.e. total 11 lines are required. And if operated in 4-bit mode then 4 data lines + 3 control lines i.e. 7 lines are required. How do we decide which mode to use? Its simple if you have sufficient data lines you can go for 8 bit mode & if there is a time constrain i.e. display should be faster then we have to use 8-bit mode because basically 4-bit mode takes twice as more time as compared to 8-bit mode.

8.2 PIN DESCRIPTION

Figure 8.2

Table 8.1 Pin Description of LCD

Pin 1 2 Pin 3 4 5

Symbol Vss Vdd Symbol Vo RS R/W

Function Ground Supply Voltage Function Contrast Setting Register Select Read/Write Select

6 7-14 15 16

En DB0-DB7 A/Vee K

Chip Enable Signal Data Lines Gnd for the backlight Vcc for backlight

1.RS(Register Select) When RS is low (0), the data is to be treated as a command. When RS is high (1), the data being sent is considered as text data which should be displayed on the screen.

2. R/W(Read/Write) When R/W is low (0), the information on the data bus is being written to the LCD. When RW is high (1), the program is effectively reading from the LCD. Most of the times there is no need to read from the LCD so this line can directly be connected to GND thus saving one controller line.

3. E(enable) The ENABLE pin is used to latch the data present on the data pins. A HIGH - LOW signal is required to latch the data. The LCD interprets and executes our command at the instant the EN line is brought low. If you never bring EN low, your instruction will never be executed.

4. D0-D7 The 8 bit data pins D0-D7 are used to send information to the LCD or read the contents of the LCDs internal registers. .To display any character on LCD micro controller has to send its ASCII value to the data bus of LCD. For e.g. to display 'AB' microcontroller has to send two hex bytes 41h and 42h respectively LCD display used here is having 16x2 size. It means 2 lines each with 16 characters. In 4-bit mode the data is sent in nibbles, first we send the higher nibble and then the lower nibble. To enable the 4-bit mode of LCD, we need to follow special sequence of initialization that tells the LCD controller that user has selected 4-bit mode of operation. We call this special sequence as resetting the LCD. Following is the reset sequence of LCD.

Wait for about 20mS Send the first init value (0x30) Wait for about 10mS Send second init value (0x30) Wait for about 1mS Send third init value (0x30) Wait for 1mS Select bus width (0x30 - for 8-bit and 0x20 for 4-bit) Wait for 1mS

8.3 LCD CONNECTIONS IN 4-BIT MODE

Figure 8.3

Sending data/command in 4-bit Mode The common steps are:

Mask lower 4-bits Send to the LCD port Send enable signal Mask higher 4-bits Send to LCD port Send enable signal

8.4 FUNCTIONAL DESCRIPTION

8.4.1 Writing and reading the data from the LCD Writing data to the LCD is done in several steps: 1) Set R/W bit to low 2) Set RS bit to logic 0 or 1 (instruction or character) 3) Set data to data lines (if it is writing)

4) Set E line to high 5) Set E line to low

Read data from data lines (if it is reading): 1) Set R/W bit to high 2) Set RS bit to logic 0 or 1 (instruction or character) 3) Set data to data lines (if it is writing) 4) Set E line to high 5) Set E line to low

EXAMPLE:

Fig. 8.4 8.5 LCD COMMAND CODES 1. CLEAR DISPLAY SCREEN

2. 4 5 6. 7. 8. A C E F. 10. 14. 18. 1C 80 C0 38

RETURN HOME DECREMENT CURSOR ( SHIFT CURSOR TO LEFT) SHIFT DISPLAY RIGHT. INCREMENT CURSOR ( SHIFT CURSOR TO RIGHT) SHIFT DISPLAY LEFT DISPLAY OFF, CURSOR OFF DISPLAY OFF CURSOR ON DISPLAY ON CURSOR OFF DISPLAY ON CURSOR BLINKING DISPLAY ON CURSOR BLINKING. SHIFT CURSOR POSITION TO LEFT SHIFT CURSOR POSITION TO RIGHT SHIFT THE ENTIRE DISPLAY TO THE LEFT SHIFT THE ENTIRE DISPLAY TO THE RIGHT FORCE CURSOR TO BEGINNING OF IST LINE FORCE CURSOR TO BEGINNING OF 2ND LINE 2 LINES AND 5 X 7 MATRIX

8.5.1 Checking the busy status of LCD The code to check the status of LCD whether it is busy or not is as follows: WAIT_LCD: SETB EN CLR RS SETB RW MOV DATA, #0FFh ;Start LCD command ;It's a command ;It's a read command ;Set all pins to FF initially

MOV A,DATA JB ACC.7,WAIT_LCD CLR EN CLR RW RET

;Read the return value ;If bit 7 high, LCD still busy ;Finish the command ;Turn off RW for future commands

Thus, our standard practice will be to send an instruction to the LCD and then call our WAIT_LCD routine to wait until the instruction is completely executed by the LCD. This will assure that our program gives the LCD the time it needs to execute instructions and also makes our program compatible with any LCD, regardless of how fast or slow it is.

8.5.2 Initializing the LCD The code to initialize the LCD is as follows: INIT_LCD: SETB EN CLR RS MOV DATA, #38h CLR EN LCALL WAIT_LCD SETB EN CLR RS MOV DATA, #0Eh CLR EN LCALL WAIT_LCD

SETB EN CLR RS MOV DATA, #06h CLR EN LCALL WAIT_LCD RET Having executed this code the LCD will be fully initialized and ready for us to send display data to it.

8.5.3 Clearing the display The code to clear the LCD display is as follows: CLEAR_LCD: SETB EN CLR RS MOV DATA,#01h CLR EN LCALL WAIT_LCD RET we may clear the LCD at any time by simply executing an LCALL CLEAR_LCD.

8.5.4 Writing text to the LCD The code to write any text to the LCD is as follows: WRITE_TEXT:

SETB EN SETB RS MOV DATA,A CLR EN LCALL WAIT_LCD RET The WRITE_TEXT routine that we just wrote will send the character in the accumulator to the LCD which will, in turn, display it. Thus to display text on the LCD all we need to do is load the accumulator with the byte to display and make a call to this routine.

AT24c02 FLASH MEMORY

9.1 INTRODUCTION The / AT24C01A/0204/08A/16A provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is

optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin MiniMAP (MLP 2x3), 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

9.2 FEATURES Low-voltage and Standard-voltage Operation 2.7 (VCC = 2.7V to 5.5V) 1.8 (VCC = 1.8V to 5.5V) Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility Write Protect Pin for Hardware Data Protection 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes Partial Page Writes Allowed Self-timed Write Cycle (5 ms max) High-reliability Endurance: 1 Million Write Cycles

 Data Retention: 100 Years

9.3 BLOCK DIAGRAM

Fig. 9.1 9.4 PIN DESCRIPTION

Figure 9.2 SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).

The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground.

The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to ground. The AT24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects and can be connected to ground.

Table 9.1 Pin Description of Flash Memory

WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal Read/Write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in table 9.2

Table 9.2 Status of Write Protect pin

9.5 MEMORY ORGANISATION AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires a 7-bit data word address for random word addressing. AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing. AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing. AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.

9.6 DEVICE OPERATION

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time

periods. Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command. STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode. ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2- wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition.

10.3

10.4 ASSEMBLY CODE

Program code is to be written in the asm code and after this, the code is converted into hex code using Keil vision3 and transfer onto the blank chip AT89s52 microcontroller with the help of programmer kit SPIPGM37.

The program code of TELEVOTING MACHINE using AT89s52 microcontroller chip is as follows: LCD_RS LCD_RW LCD_EN SDA SCL KEY 0 EQU KEY1 KEY 2 EQU KEY 3 EQU KEY4 KEY 5 EQU KEY 6 EQU KEY 7 EQU KEY 8 EQU KEY 9 EQU KEY 10 KEY 11 EQU EQU EQU EQU EQU P1.0 EQU P1.2 P1.3 EQU P1.5 P1.6 P1.7 P3.0 P3.1 EQU EQU P2.5 P2.6 P2.7 P2.1 P2.0 P1.1

P1.4

P3.2 P3.3

ORG 0000H LJMP MAIN

ORG 0003H RETI ;ljmp ex0_isr ORG 000BH RETI ;ljmp tim0_isr ORG 0013H RETI ;ljmp ex1_isr ORG 001BH RETI ;ljmp tim1_isr ORG 0023H RETI ;ljmp ser_isr MAIN: LCALL DELAY41 LCALL DELAY41 LCALL DELAY41 LCALL DELAY41 LCALL DELAY41 LCALL DELAY41 MOV 129 , # 040H MOV 137 , # 00H MOV 136 , # 00H MOV 168 , # 00H MOV 184 , # 00H MOV 152 , # 00H MOV 128 , # 0FFH MOV 144 , # 0FFH MOV 160 , # 0FFH MOV 176, # 0FFH CLR WP

LCALL CLR CLR CLR CLR SETB SETB

DELAY41 LCD_RS LCD_RW LCD_EN LED SDA SCL

MAIN1: MOV A , # 0 MOV 45 , A MOV A, #00H CALL READ_RANDOM JC MAIN1 MOV 34 , A MAIN2: MOV A , # 1 MOV 45 , A MOV A, #00H CALL READ_RANDOM JC MAIN2 MOV 35 , A MAIN3: MOV A , # 2 MOV 45 , A MOV A, #00H CALL READ_RANDOM JC MAIN3 MOV 36 , A MAIN4: MOV A, # 3 MOV 45, A MOV , #00H CALL READ_RANDOM

JC MAIN4 MOV 37 , A MAIN5: MOV A , # 4 MOV 45 , A MOV A, #00H CALL READ_RANDOM JC MAIN5 MOV 38 , A MAIN6: MOV A , # 5 MOV 45 , A MOV A, #00H CALL READ_RANDOM JC MAIN6 MOV 39 , A MAIN7: MOV A , # 6 MOV 45 , A MOV A,#00H CALL READ_RANDOM JC MAIN7 MOV 40 , A MAIN8: MOV A , # 7 MOV 45 , A MOV A,#00H CALL READ_RANDOM JC MAIN8 MOV 41, A MAIN9: MOV A, # 8

MOV 45, A MOV A, #00H CALL READ_RANDOM JC MAIN9 MOV 42, A MAIN10: MOV A, # 9 MOV 45, A MOV A, #00H CALL READ_RANDOM JC MAIN10 MOV 43, A SETB WP CLR RST_FLG CLR CLR_FLG1 CLR CLR_FLG2 ;Initialize LCD MOV 128, # 038H LCALL COMMAND_BYTE LCALL DELAY41 MOV 128, # 038H LCALL COMMAND_BYTE LCALL DELAY1 MOV 128, # 038H LCALL COMMAND_BYTE LCALL DELAY1 MOV 128, # 038H LCALL COMMAND_BYTE ;1/16 duty, 5x7 char LCALL DELAY1 MOV 128, # 008H LCALL COMMAND_BYTE LCALL DELAY1 MOV 128, # 00CH LCALL COMMAND_BYTE

LCALL DELAY1 MOV 128, # 006H LCALL COMMAND_BYTE LCALL DELAY1 LCALL DISPLAY MAIN_LP1: LCALL DELAY41 JB KEY0,NXT_KEY1 LJMP ACT_KEY0 NXT_KEY1: JB KEY1,NXT_KEY2 LJMP ACT_KEY1 NXT_KEY2: JB KEY2,NXT_KEY3 LJMP ACT_KEY2 NXT_KEY3: JB KEY3,NXT_KEY4 LJMP ACT_KEY3 NXT_KEY4: JB KEY4,NXT_KEY5 LJMP ACT_KEY4 NXT_KEY5: JB KEY5,NXT_KEY6 LJMP ACT_KEY5 NXT_KEY6: JB KEY6,NXT_KEY7 LJMP ACT_KEY6 NXT_KEY7: JB KEY7,NXT_KEY8

LJMP ACT_KEY7 NXT_KEY8: JB KEY8,NXT_KEY9 LJMP ACT_KEY8 NXT_KEY9: JB KEY9,NXT_KEY10 LJMP ACT_KEY9 NXT_KEY10: JB KEY10,NXT_KEY11 LJMP ACT_KEY10 NXT_KEY11: JB KEY11,NXT_KEY12 LJMP ACT_KEY11 NXT_KEY12: LJMP MAIN_LP1 ACT_KEY1: CLR CLR_FLG1 CLR CLR_FLG2 MOV 33, # '1' JB RST_FLG,INC_CNT1 JMP EXIT_KEY1 INC_CNT1: MOV A , 34 ADD A, #01H DA A MOV 34 , A MOV A , 35 ADDC A, #00H DA A MOV 35 , A MOV A , 42

ADDA, #01H DA A MOV 42 , A MOV A , 43 ADDC A, #00H DAA MOV 43 , A CLR RST_FLG LCALL VOTE_CASTED LCAL SAVE_DATA EXIT_KEY1: LJMP MAIN_LP1 ACT_KEY2: CLR CLR_FLG1 CLR CLR_FLG2 MOV 33 , # '2' JB RST_FLG,INC_CNT2 JMP EXIT_KEY2 INC_CNT2: MOV A , 36 ADD A, #01H DAA MOV 36 , A MOV A , 37 ADDC A, #00H DAA MOV 37 , A MOV A , 42 ADD A, #01H DA A MOV 42 , A MOV A , 43 ADDC A, #00H DA A

MOV 43 , A CLR RST_FLG LCALL VOTE_CASTED LCALL SAVE_DATA EXIT_KEY2: LJMP MAIN_LP1 ACT_KEY3: CLR CLR_FLG1 CLR CLR_FLG2 MOV 33 , # '3' JB RST_FLG,INC_CNT3 JMP EXIT_KEY3 INC_CNT3: MOV A , 38 ADD A, #01H DA A MOV 38 , A MOV A , 39 ADDC A, #00H DA A MOV 39 , A MOV A , 42 ADD A, #01H DA A MOV 42 , A MOV A , 43 ADDC A, #00H DA A MOV 43 , A CLR RST_FLG LCALL VOTE_CASTED LCALL SAVE_DATA

EXIT_KEY3: LJMP MAIN_LP1 ACT_KEY4: CLR CLR_FLG1 CLR CLR_FLG2 MOV 33 , # '4' JB RST_FLG,INC_CNT4 JMP EXIT_KEY4 INC_CNT4: MOV A , 40 ADD A, #01H DA A MOV 40 , A MOV A , 41 ADDC A, #00H DA A MOV 41 , A MOV A , 42 ADD A, #01H DA A MOV 42 , A MOV A , 43 ADDC A, #00H DA A MOV 43 , A CLR RST_FLG LCALL VOTE_CASTED LCALL SAVE_DATA EXIT_KEY4: LJMP MAIN_LP1 ;key to see total vote casted for candidate-1

ACT_KEY5: CLR CLR_FLG1 CLR CLR_FLG2 LCALL DISP_CNT1 MOV 33 , # '5' LJMP MAIN_LP1 ;key to see total vote casted for candidate-2 ACT_KEY6: CLR CLR_FLG1 CLR CLR_FLG2 LCALL DISP_CNT2 MOV 33 , # '6' LJMP MAIN_LP1 ;key to see total vote casted for candidate-3 ACT_KEY7: CLR CLR_FLG1 CLR CLR_FLG2 LCALL DISP_CNT3 MOV 33 , # '7' LJMP MAIN_LP1 ;key to see total vote casted for candidate-4 ACT_KEY8: CLR CLR_FLG1 CLR CLR_FLG2 LCALL DISP_CNT4 MOV 33 , # '8' LJMP MAIN_LP1 ;key to see total number of vote casted ACT_KEY9: CLR

CLR_FLG1

CLR CLR_FLG2 LCALL DISP_TOTAL MOV 33, # '9' LJMP MAIN_LP1 ;key to reset all counters ACT_KEY0: JNB LCALL LCALL CLR CLR SJMP

CLR_FLG2,SKP_ACT0 CLR_CNTRS SAVE_DATA CLR_FLG1 CLR_FLG2 EXIT_ACT0

SKP_ACT0: SETB CLR_FLG1 MOV 33 , # '0' EXIT_ACT0: LJMP MAIN_LP1 ;key to reset all counters ACT_KEY10: JNB CLR_FLG1,EXIT_ACT10 SETB CLR_FLG2 MOV 33 , # 'a' EXIT_ACT10: LJMP MAIN_LP1 ;reset key for enabling new vote casting ACT_KEY11: CLR CLR_FLG1 CLR CLR_FLG2

MOV 33 , # 62H SETB RST_FLG LCALL CAST_VOTE LJMP MAIN_LP1 DISP_TOTAL: MOV 128 , # 001H LCALL COMMAND_BYTE LCALL DELAY41 MOV DPTR,#MSG_TOTAL LCALL WRITE_MSG MOV 128 , # 0C6H LCALL COMMAND_BYTE LCALL DELAY41 MOV A , 43 ANL A,#0F0H SWAP A ADD A,#30H MOV 128 , A LCALL DATA_BYTE MOV A , 43 ANL A, #0FH ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 42 ANL A, #0F0H SWAP A ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 42 ANL A, #0FH ADD A, #30H MOV 128 , A LCALL DATA_BYTE RET

DISP_CNT1: MOV 128 , # 001H LCALL COMMAND_BYTE LCALL DELAY41 MOV DPTR,#MSG_CNT1 LCALL WRITE_MSG MOV 128 , # 0C6H LCALL COMMAND_BYTE LCALL DELAY41 MOV A , 35 ANL A, #0F0H SWAP A ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 35 ANL A, #0FH ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 34 ANL A, #0F0H SWAP A ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 34 ANL A, #0FH ADD A, #30H MOV 128 , A LCALL DATA_BYTE RET

DISP_CNT2: MOV 128 , # 001H

LCALL COMMAND_BYTE LCALL DELAY41 MOV DPTR,#MSG_CNT2 LCALL WRITE_MSG MOV 128 , # 0C6H LCALL COMMAND_BYTE LCALL DELAY41 MOV A , 37 ANL A, #0F0H SWAP A ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 37 ANL A, #0FH ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 36 ANL A, #0F0H SWAP A ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 36 ANL A, #0FH ADD A, #30H MOV 128 , A LCALL DATA_BYTE RET DISP_CNT3: MOV 128 , # 001H LCALL COMMAND_BYTE LCALL DELAY41 MOV DPTR,#MSG_CNT3 LCALL WRITE_MSG

MOV 128 , # 0C6H LCALL COMMAND_BYTE LCALL DELAY41 MOV A , 39 ANL A, #0F0H SWAP A ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 39 ANL A, #0FH ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 38 ANL A, #0F0H SWAP A ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 38 ANL A, #0FH ADD A, #30H MOV 128 , A LCALL DATA_BYTE RET DISP_CNT4: MOV 128 , # 001H LCALL COMMAND_BYTE LCALL DELAY41 MOV DPTR,#MSG_CNT4 LCALL WRITE_MSG MOV 128 , # 0C6H LCALL COMMAND_BYTE LCALL DELAY41 MOV A , 41

ANL A, #0F0H SWAP A ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 41 ANL A, #0FH ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 40 ANL A, #0F0H SWAP A ADD A, #30H MOV 128 , A LCALL DATA_BYTE MOV A , 40 ANL A, #0FH ADD A, #30H MOV 128 , A LCALL DATA_BYTE RET CLR_CNTRS: MOV A, #00H MOV 34 , A MOV 35 , A MOV 36 , A MOV 37 , A MOV 38 , A MOV 39 , A MOV 40 , A MOV 41 , A MOV 42 , A MOV 43 , A MOV 128 , # 001H LCALL COMMAND_BYTE

LCALL DELAY41 MOV DPTR,#MSG_CLR LCALL WRITE_MSG RET VOTE_CASTED: MOV 128 , # 001H LCALL COMMAND_BYTE LCALL DELAY41 MOV DPTR,#MSG4 LCALL WRITE_MSG CLR LED RET CAST_VOTE: MOV 128 , # 001H LCALL COMMAND_BYTE LCALL DELAY41 MOV DPTR,#MSG3 LCALL WRITE_MSG SETB LED RET CLR_LCD: MOV 128 , # 001H LCALL COMMAND_BYTE LCALL DELAY41 RET DISPLAY: MOV 128 , # 080H LCALL COMMAND_BYTE LCALL DELAY1 MOV DPTR,#MSG1 LCALL WRITE_MSG MOV 128 , # 0C0H LCALL COMMAND_BYTE

LCALL DELAY1 MOV DPTR,#MSG2 LCALL WRITE_MSG SETB LED RET WRITE_MSG: MOV A, #00H MOVC A, @A+DPTR CJNE A, #'$',WRITE_CONT RET WRITE_CONT: MOV 128 , A LCALL DATA_BYTE INC DPTR LJMP WRITE_MSG COMMAND_BYTE: CLR LCD_RS LJMP CMD10 DATA_BYTE: SETB NOP

LCD_RS

CMD10: CLR LCD_RW NOP SETB LCD_EN NOP CLR LCD_EN RET DELAY1: MOV

R0, #00H

DELAY10: DJNZ R0, DELAY10 RET DELAY41: MOV MOV

R0, #00H R1, #0FH

DLP410: DJNZ R0, DLP410 DJNZ R1, DLP410 RET SAVE_DATA: CLR WP LCALL DELAY41 SAVE1: MOV A , 34 MOV 44 , A MOV A , # 0 MOV 45 , A MOV A, #00H LCALL WRITE_BYTE JC SAVE1 SAVE2: LCALL DELAY41 MOV A , 35 MOV 44 , A MOV A , # 1 MOV 45 , A MOV A, #00H LCALL WRITE_BYTE JC SAVE2 SAVE3:

LCALL DELAY41 MOV A , 36 MOV 44 , A MOV A , # 2 MOV 45 , A MOV A, #00H LCALL WRITE_BYTE JC SAVE3 SAVE4: LCALL DELAY41 MOV A , 37 MOV 44 , A MOV A , # 3 MOV 45 , A MOV A, #00H LCALL WRITE_BYTE JC SAVE4 SAVE5: LCALL DELAY41 MOV A , 38 MOV 44 , A MOV A , # 4 MOV 45 , A MOV A, #00H LCALL WRITE_BYTE JC SAVE5 SAVE6: LCALL DELAY41 MOV A , 39 MOV 44 , A MOV A , # 5 MOV 45 , A MOV A, #00H LCALL WRITE_BYTE

JC

SAVE6

SAVE7: LCALL DELAY41 MOV A , 40 MOV 44 , A MOV A , # 6 MOV 45 , A MOV A, #00H LCALL WRITE_BYTE JC SAVE7 SAVE8: LCALL DELAY41 MOV A , 41 MOV 44 , A MOV A , # 7 MOV 45 , A MOV A, #00H LCALL WRITE_BYTE JC SAVE8 SAVE9: LCALL DELAY41 MOV A , 42 MOV 44 , A MOV A , # 8 MOV 45 , A MOV A, #00H LCALL WRITE_BYTE JC SAVE9 SAVE10: LCALL DELAY41 MOV A , 43 MOV 44 , A MOV A , # 9

MOV 45 , A MOV A, #00H LCALL WRITE_BYTE JC SAVE10 LCALL DELAY41 SETB WP RET WRITE_BYTE: ; AT24Cxx Byte Write function. ; Called with programmable address in A, byte address in ; register ADDR_LO, data in register ZDATA. ; Does not wait for write cycle to complete. ; Returns CY set to indicate that the bus is not available ; or that the addressed device failed to acknowledge. ; Destroys A. LCALL START JC X49 RL A ORL A , # 160 CLR ACC.0 LCALL SHOUT JC X48 MOV A , 45 LCALL SHOUT JC X48 MOV A , 44 LCALL SHOUT JC X48 CLR C X48: LCALL STOP X49:

; abort if bus not available ; programmable address to bits 3:1 ; specify write operation ; send device address ; abort if no acknowledge

; abort if no acknowledge ; send data ; abort if no acknowledge ; clear error flag

RET READ_CURRENT: ; AT24Cxx Current Address Read function. ; Called with programmable address in A. Returns data in A. ; Returns CY set to indicate that the bus is not available ; or that the addressed device failed to acknowledge. LCALL START JC X45 RL A ORL A , # 160 SETB ACC.0 LCALL SHOUT JC X44 LCALL SHIN LCALL NAK CLR C X44: LCALL STOP X45: RET READ_RANDOM: ; AT24Cxx Random Read function. ; Called with programmable address in A, byte address in ; register ADDR_LO. Returns data in A. ; Returns CY set to indicate that the bus is not available ; or that the addressed device failed to acknowledge. PUSH 240

; abort if bus not available ; programmable address to bits 3:1 ; specify read operation ; send device address ; abort if no acknowledge ; receive data byte ; do not acknowledge byte ; clear error flag

MOV 240 , A ; Send dummy write command to set internal address. LCALL START JC X47 RL A ORL A , # 160 CLR ACC.0 LCALL SHOUT JC X46 MOV A , 45 LCALL SHOUT JC X46

; abort if bus not available ; programmable address to bits 3:1 ; specify write operation ; send device address ; abort if no acknowledge

; abort if no acknowledge

; Call Current Address Read function. MOV A , 240 LCALL READ_CURRENT JMP X47 ; exit X46: LCALL STOP X47: POP 240 RET START: ; Send START, defined as high-to-low SDA with SCL high. ; Return with SCL, SDA low. ; Returns CY set if bus is not available. SETB SDA SETB SCL NOP

NOP NOP NOP NOP ; Verify bus available. JNB JNB NOP NOP NOP NOP NOP CLR NOP NOP NOP NOP NOP CLR NOP NOP NOP NOP NOP CLR JMP X40: SETB C X41: RET STOP: ; Send STOP, defined as low-to-high SDA with SCL high. ; set error flag SDA, X40 SCL, X40 ; jump if not high ; jump if not high

; enforce setup delay and cycle delay SDA

SCL

C X41

; clear error flag

; SCL expected low on entry. Return with SCL, SDA high. CLR SDA NOP NOP NOP NOP NOP NOP SETB SCL NOP NOP NOP NOP NOP SETB SDA NOP NOP NOP NOP NOP RET

; enforce SCL low and data setup

; enforce setup delay

SHOUT: ; Shift out a byte to the AT24Cxx, most significant bit first. ; SCL, SDA expected low on entry. Return with SCL low. ; Called with data to send in A. ; Returns CY set to indicate failure by slave to acknowledge. ; Destroys A. PUSH 240 MOV 240 , # 8 X42: RLC A ; move bit into CY

MOV SDA, C NOP NOP NOP NOP NOP SETB SCL NOP NOP NOP NOP NOP CLR SCL DJNZ 240 , X42 SETB SDA NOP NOP NOP NOP NOP SETB SCL NOP NOP NOP NOP NOP MOV C, SDA CLR SCL NOP NOP NOP NOP NOP POP 240 RET SHIN:

; output bit ; enforce SCL low and data setup

; raise clock ; enforce SCL high

; drop clock ; release SDA for ACK ; enforce SCL low and tAA

; raise ACK clock ; enforce SCL high

; get ACK bit ; drop ACK clock

; Shift in a byte from the AT24Cxx, most significant bit first. ; SCL expected low on entry. Return with SCL low. ; Returns received data byte in A. PUSH 240 MOV 240 , # 8 X43: SETB SDA NOP NOP NOP NOP NOP SETB SCL NOP NOP NOP NOP NOP MOV C, SDA RLC A CLR SCL NOP NOP NOP NOP NOP DJNZ 240 , X43 NOP NOP NOP NOP NOP POP 240 RET ; make SDA an input ; enforce SCL low and data setup

; raise clock ; enforce SCL high

; input bit ; move bit into byte ; drop clock

ACK: ; Clock out an acknowledge bit (low). ; SCL expected low on entry. Return with SCL, SDA low. CLR SDA NOP NOP NOP NOP NOP SETB SCL NOP NOP NOP NOP NOP CLR SCL NOP NOP NOP NOP NOP RET ; ACK bit ; enforce SCL low and data setup

; raise clock ; enforce SCL high

; drop clock

NAK: ; Clock out a negative acknowledge bit (high). ; SCL expected low on entry. Return with SCL low, SDA high. SETB SDA NOP NOP NOP NOP NOP SETB SCL NOP ; NAK bit ; enforce SCL low and data setup

; raise clock ; enforce SCL high

NOP NOP NOP NOP CLR SCL NOP NOP NOP NOP NOP RET MSG1: DB MSG2: DB MSG3: DB MSG4: DB

; drop clock

' VOTING-MACHINE$'

'IGIT VOTING $'

'*CAST THE VOTE*$'

'**VOTE CASTED**$'

MSG_CLR: DB '**All Cleared**$' MSG_CNT1: DB 'CANDIDATE 1$' MSG_CNT2: DB 'CANDIDATE 2$' MSG_CNT3: DB 'CANDIDATE 3$' MSG_CNT4:

DB

'CANDIDATE 4$'

MSG_TOTAL: DB 'Total Vote Cast$' END

10.5 LIST OF COMPONENTS Table 10.1 List of Components S.NO. 1 LIST OF COMPONENTS 220V, 50HZ, 9V-0-9V CENTRE QUANTITY TAP 1

TRANSFORMER 2 3 4 5 6 7 8 9 S.NO. 10 11 12 7805 VOLTAGE REGULATOR LIQUID CRYSTAL DISPLAY 8 LOUD SPEAKER CONDENSER MICROPHONE 89S52 MICROCONTROLLER 817 OPTOCOUPLER 555 TIMER 4017 DECADE COUNTER LIST OF COMPONENTS APR 9600 9170 DTMF RECEIVER 74154 4LINE TO 16LINE DECODER 2 1 1 1 1 1 1 1 QUANTITY 1 1 1

13 14 15 16 16 17 18 19 20 21 22 23 24 25 26 27 28 29 S.NO. 30 31 32 33 34

24C02 EEPROM LED IN4148 DIODE IN 4007 DIODE 12V RELAY 1000F,16V ELECTROLYTIC CAPACITOR 470 RESISTOR LED PUSH BUTTON SWITCH BAND SWITCH 10K RESISTOR 4.7K RESISTOR 10F,100V ELECTROLYTIC CAPACITOR 22K RESISTOR 100K RESISTOR 3.58 MHZ CRYSTAL OSCILLATOR 0.1F CERAMIC CAPACITOR 330K RESISTOR LIST OF COMPONENTS 1K RESISTOR 27F CERAMIC CAPACITOR .01F POLYSTER CAPACITOR 10F,50V ELECTROLYTIC CAPACITOR 0.01F CERAMIC CAPACITOR

1 7 1 3 1 2 3 7 11 1 5 4 1 2 9 1 4 1 QUANTITY 8 2 3 1 1

35 36 37 38 39 40 41 42

100 RESISTOR 270 RESISTOR 33K RESISTOR BC558 PNP TRANSISTOR 220K RESISTOR 22F CERAMIC CAPACITOR BC 548 NPN TRANSISTOR 11.0592MHZ CRYSTAL OSCILLATOR

1 1 1 2 1 1 5 1

CHAPTER 11 RESULTS AND CONCLUSION

The complete system (including all the hardware components and software routines) is working as per the initial specifications and requirements of our project. Because of the creative nature of the design, and due to lack of time some features could not be fine-tuned and are not working properly. So certain aspects of the system can be modified as operational experience is gained with it.

Initially the landline section in the circuit got hanged after 3 rings & the circuit to automatic switch on the landline section does not work properly as the electromagnetic relay connected earlier consumes more current when circuit is powered on therefore, a remedy to this problem is that we have used reed relay which has low switch & voltage ratings, capable of faster switching speeds and mainly used for temporarily storing information in telephone exchanges.

Also, the voice processor section having APR9600 chip got hanged due to reverse current flow in that section. To avoid this we have connected an op-amp 714 to compensate for the same.

As the users work with the system, they develop various new ideas for the development and enhancement of the circuit. CHAPTER 12 APPLICATIONS

 The practical relevance of this project is that it can be used in TV reality shows where viewers can vote to any participant of their choice.

Further this project can be used practically in various types of selection & voting schemes to be held in schools and colleges for the selection for different posts such as union president or others.

CHAPTER 13 FUTURE SCOPE

 Number of candidates could be increased by using other microcontroller or an 8255 IC.

It could be interfaced with printer to get the hard copy of the result almost instantly from the machine itself.

It could also be interfaced with the personal computer and result could be stored in the central server and its backup could be taken on the backend servers. On adding security and verification features it can be used for central elections and replace the existing machines. On adding the feature of negative voting we can give people one more choice of reducing the votes of misappropriate candidate. other