Twin-tub CMOS process

1. Provide separate optimization of the n-type and p-type transistors 2. Make it possible to optimize "Vt", "Body effect", and the "Gain" of n, p devices, independently. 3. Steps: A. Starting material: an n+ or p+ substrate with lightly doped -> "epitaxial" or "epi" layer -> to protect "latch up" B. Epitaxy" a. Grow high-purity silicon layers of controlled thickness b. With accurately determined dopant concentrations c. Electrical properties are determined by the dopant and its concentration in Si C. Process sequence a. Tub formation b. Thin-Oxide construction c. Source & drain implantations d. Contact cut definition e. Metallization Balanced performance of n and p devices can be constructed. (Substrate contacts are included in Fig.3.10)

(7~8um) or SiO2 ()

Anisotropic Etch

Form p-island (for n-device)

Form n-island (for p-device)

- Grow gate oxide through thermal oxidation - Deposit Doped Polysilicon

Etch Polysilicon

Step (h): n-implantation for source & drain (selfalignment)

Step (i) p-implantation Step (j) - Grow phosphorus glass - Etch glass to form contact cut - Evaporating alumni

3.3 CMOS Process Enhancement (Interconnection) 3.3.1 Metal Interconnect * CMOS circuit = CMOS logic process + Signal/Power/Clock-routing layers - Second-layer of metal (VIA1=M1 to M2) - Note: M1 must be involved in any contact to underlying areas

1. Etch Isolation layer 2.Form a VIA

Contact

(polysilicon, diffusion) - Process steps for two-metal process (Omitted) 3.3.1.2 Poly Interconnect - Polysilicon layer is commonly used as interconnection of signals. Reduce resistance of polysilicon to make long-distance interconnection

- Combine polysilicon with a refractory metal (Silicon + Tantalum)

=20-40/square

=1-5/square

Make long-distance (for interconnect)

3.3.1.3 Local Interconnection

- Local Interconnection allow a direct connection between ploysilicon and diffusion , alleviating the need for area-intensive contacts and metal - Example: Use of Local Interconnect in SRAM (save 25%)

3.3.2 Circuit elements

1. Resistor - Polysilicon (undoped) in static memory cell - Resistive metal (Nichrome) to produce high-value, high-quality resistors in mixed-mode CMOS circuits 2. Capacitors

Geometry

Process Cross Section

- Polysilicon capacitor - Memory capacitor (3-dimensional to increase cap/area) - Example: 1. Trench capacitor (Fig3.18 (a)) 2. Fin-type capacitor (Fig3.18 (b))

3.4 Layout Design Rules - Function: obtain a circuit with optimum yield in an area as well as possible - Performance yield * Conservative design rules * Aggressive design rules Functional circuit Good yield Bad yield Compact circuit/layout for low cost and high speed (A) Line width/spacing Small open circuit Close short circuit (B) Spacing between two independent layers - In process: (a) Geometric features for mask-making and lithographical (b) Interactions between different layers (e.g., poly + diffussion) - Rules: a. Micro()-based rules Industry (submicron) b. Lambda-based rules : e.g.,, 1=0.6um for 1.2 um CMOS process) for 4-1.2um Scalable CMOS process. 2 is the minimum channel length (L). - See Table 3.1 and 3.2