CMOS Technology (6/7/00)

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2.8 - CMOS TECHNOLOGY

INTRODUCTION Objective The objective of this presentation is: 1.) Illustrate the fabrication sequence for a typical MOS transistor 2.) Show the physical aspects of the MOSFET Outline CMOS technology Compatible active devices Summary

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen, 2000

CMOS Technology (6/7/00)

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CMOS TECHNOLOGY Fabrication Fabrication involves the implementation of semiconductor processes to build a MOSFET transistor and compatible passive components as an integrated circuit. N-Well CMOS Fabrication Major Steps 1.) Implant and diffuse the n-well 2.) Deposition of silicon nitride 3.) n-type field (channel stop) implant 4.) p-type field (channel stop) implant 5.) Grow a thick field oxide (FOX) 6.) Grow a thin oxide and deposit polysilicon 7.) Remove poly and form LDD spacers 8.) Implantation of NMOS S/D and n-material contacts 9.) Remove spacers and implant NMOS LDDs 10.) Repeat steps 8.) and 9.) for PMOS 11.) Anneal to activate the implanted ions 12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass) 13.) Open contacts, deposit first level metal and etch unwanted metal 14.) Deposit another interlayer dielectric (CVD SiO2), open vias and deposit second level metal 15.) Etch unwanted metal, deposit a passivation layer and open over bonding pads

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen, 2000

CMOS Technology (6/7/00)

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Major CMOS Process Steps

Step 1 - Implantation and diffusion of the n-wells n-well implant

Photoresist p- substrate

SiO2

Photoresist

Step 2 - Growth of thin oxide and deposition of silicon nitride Si3N4 SiO2 n-well psubstrate
Fig. 2.2-1

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen, 2000

CMOS Technology (6/7/00)

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Major CMOS Process Steps - Continued

Step 3.) Implantation of the n-type field channel stop n- field implant

Photoresist

Si3N4

Photoresist n-well

Pad oxide (SiO2)

p- substrate

Step 4.) Implantation of the p-type field channel stop p- field implant Si3N4

Photoresist n-well

p-

substrate
Fig. 2.2-2

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen, 2000

CMOS Technology (6/7/00)

Page 5

Major CMOS Process Steps - Continued

Step 5.) Growth of the thick field oxide (LOCOS - localized oxidation of silicon) Si3N4 FOX p- substrate
FOX

n-well

Step 6.) Growth of the gate thin oxide and deposition of polysilicon Polysilicon

,,,,,,,,,, ,,,,,,,,,,
FOX
FOX

n-well

p- substrate

Fig. 2.2-3

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen, 2000

CMOS Technology (6/7/00)

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Major CMOS Process Steps - Continued

Step 7.) Removal of polysilicon and formation of the sidewall spacers Polysilicon FOX

p- substrate

,, ,, ,,

SiO2 spacer

FOX

, , ,

Photoresist n-well
FOX FOX

Step 8.) Implantation of NMOS source and drain and contact to n-well (not shown) n+ S/D implant Polysilicon FOX

Photoresist FOX
FOX FOX

n-well

p- substrate

Fig. 2.2-4

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen, 2000

CMOS Technology (6/7/00)

Page 7

Major CMOS Process Steps - Continued

Step 9.) Remove sidewall spacers and implant the NMOS lightly doped source/drains

Polysilicon FOX FOX

p- substrate

, ,

n- S/D LDD implant

,,
Photoresist n-well

FOX FOX

Step 10.) Implant the PMOS source/drains and contacts to the p- substrate (not shown), remove the sidewall spacers and implant the PMOS lightly doped source/drains

Polysilicon FOX

LDD Diffusion FOX

p- substrate

, , ,,
n-well

FOX FOX

Fig. 2.2-5

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen, 2000

CMOS Technology (6/7/00)

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Major CMOS Process Steps - Continued

Step 11.) Anneal to activate the implanted ions n+ Diffusion FOX p+ Diffusion FOX

p- substrate

, ,

,,
n-well

Polysilicon FOX

Step 12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass) n+ Diffusion FOX p+ Diffusion FOX

p- substrate

,,
n-well

Polysilicon BPSG FOX

Fig. 2.2-6

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen, 2000

CMOS Technology (6/7/00)

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Major CMOS Process Steps - Continued

Step 13.) Open contacts, deposit first level metal and etch unwanted metal CVD oxide, Spin-on glass (SOG) Metal 1

FOX p-

substrate

, ,

FOX

,,
n-well

BPSG FOX

Step 14.) Deposit another interlayer dielectric (CVD SiO2), open contacts, deposit second level metall Metal 2 Metal 1

FOX

FOX

p- substrate

,,
n-well

BPSG FOX

Fig. 2.2-7

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen, 2000

CMOS Technology (6/7/00)

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Major CMOS Process Steps - Continued

Step 15.) Etch unwanted metal and deposit a passivation layer and open over bonding pads Metal 2 Passivation protection layer Metal 1

FOX

p- substrate

FOX

,,
n-well

BPSG FOX

Fig. 2.2-8

p-well process is similar but starts with a p-well implant rather than an n-well implant.

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen, 2000

CMOS Technology (6/7/00)

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Approximate Side View of CMOS Fabrication

,,, ,,, ,,, ,,,

2 microns

Passivation

Metal 4 Metal 3

Metal 2

,,,,, ,,
Polysilicon
ECE 4430 - Analog Integrated Circuits and Systems

Metal 1

Diffusion

Fig. 2.2-9

P.E. Allen, 2000

CMOS Technology (6/7/00)

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Silicide/Salicide Technology Used to reduce interconnect resistivity by placing a low-resistance silicide such as TiSi2, WSi2, TaSi2, etc. on top of polysilicon Salicide technology (self-aligned silicide) provides low resistance source/drain connections as well as lowresistance polysilicon.
Polysilicide Metal Polysilicide Metal

FOX

FOX

FOX

,,

Salicide

FOX

Polycide structure

Salicide structure

Fig2.2-10

ECE 4430 - Analog Integrated Circuits and Systems

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CMOS Technology (6/7/00)

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COMPATIBLE ACTIVE DEVICES Lateral Bipolar Junction Transistor P-Well Process NPN LateralVDD Base Emitter Collector

n+

p+ p-well

n+

n+

n-substrate

ECE 4430 - Analog Integrated Circuits and Systems

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CMOS Technology (6/7/00)

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Lateral Bipolar Junction Transistor - Continued Field-aided LateralF 50 to 100 depending on the process
Keep channel from forming VDD Base Emitter VGate Collector

n+

p+ p-well

n+

n+

n-substrate

Good geometry matching Low 1/f noise (if channel doesnt form) Acts like a photodetector with good efficiency

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen, 2000

CMOS Technology (6/7/00)

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Geometry of the Lateral PNP BJT Minimum Size layout of a single emitter dot lateral PNP BJT:
n-well n-well contact p-diffusion contact p-substrate diffusion Base Lateral Collector Emitter 31.2 m

40 emitter dot LPNP transistor (total device area is 0.006mm2 in a 1.2m CMOS process):

71.4 m

Base V SS Lateral Collector V SS Emitter 33.0 m Gate (poly) 84.0 m

Gate

ECE 4430 - Analog Integrated Circuits and Systems

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CMOS Technology (6/7/00)

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Performance of the Lateral PNP BJT Schematic:

Emitter Gate

Base Lateral Collector

Vertical Collector ( V SS )

L vs ICL for the 40 emitter dot LPNP BJT:

150
VCE = 4.0 V

Lateral efficiency versus IE for the 40 emitter dot LPNP BJT:

1.0

130 0.8 Lateral 110

VCE = 0. 4V

VCE = 4.0 V VCE = 0. 4V

Lateral Efficiency 100 A 1 mA

0.6

90

0.4

70 0.2 50 1 nA 10 nA 100 nA 1 A 10 A Lateral Collector Current

0 1 nA

10 nA

100 nA 1 A 10 A Emitter Current

100 A

1 mA

ECE 4430 - Analog Integrated Circuits and Systems

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CMOS Technology (6/7/00)

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Performance of the Lateral PNP BJT - Continued Typical Performance for the 40 emitter dot LPNP BJT: Transistor area Lateral Lateral efficiency Base resistance En @ 5 Hz En (midband) fc (En) In @ 5 Hz In (midband) fc (In) fT Early voltage 0.006 mm2 90 0.70 150 2.46 nV / Hz 1.92 nV / Hz 3.2 Hz 3.53 pA / Hz 0.61 pA / Hz 162 Hz 85 MHz 16 V

ECE 4430 - Analog Integrated Circuits and Systems

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CMOS Technology (6/7/00)

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High Voltage MOS Transistor The well can be substituted for the drain giving a lower conductivity drain and therefore higher breakdown voltage. NMOS in n-well example:
Source
Gate

Oxide

Drain-substrate/channel can be as large as 20V or more.

 
Drain
Polysilicon

Substrate

n+ Source

Channel

n+

p+

n-well

p-substrate

Fig. 2.6-7A

ECE 4430 - Analog Integrated Circuits and Systems

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CMOS Technology (6/7/00)

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Latch-up in CMOS Technology Latch-up Mechanisms 1. SCR regenerative switching action. 2. Secondary breakdown. 3. Sustaining voltage breakdown. Parasitic lateral PNP and vertical NPN BJTs in a p-well CMOS technology:
VDD D G S S G D

,, ,, ,, ,, ,, ,, ,,,,,,,,,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,,,, |   |  
A B
VSS n+ p+ p+ p-well n+ n+ p+ RNRPn- substrate VDD VDD A Vin VSS B Vout B RPVSS VSS
Fig. 2.6-9 +

Fig. 2.6-8

Equivalent circuit of the SCR formed from the parasitic BJTs:

RN-

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CMOS Technology (6/7/00)

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Preventing Latch-Up in a P-Well Technology 1.) Keep the source/drain of the MOS device not in the well as far away from the well as possible. This will lower the value of the BJT betas. 2.) Reduce the values of RN- and RP-. This requires more current before latch-up can occur. 3.) Make a p- diffusion around the p-well. This shorts the collector of Q1 to ground.
n+ p-channel transistor guard bars p+ n-channel transistor guard bars

VDD

VSS

FOX

FOX

FOX

FOX

FOX

p-well

FOX

FOX

n- substrate
Figure 2.6-10

For more information see R. Troutman, CMOS Latchup, Kluwer Academic Publishers.

ECE 4430 - Analog Integrated Circuits and Systems

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CMOS Technology (6/7/00)

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Electrostatic Discharge Protection (ESD) Objective: To prevent large external voltages from destroying the gate oxide.
Electrical equivalent circuit VDD p+ to n-well diode To internal gates n+ to p-substrate diode p+ resistor

Bonding Pad

VSS Implementation in CMOS technology Metal

FOX

n+

FOX n-well

p+

FOX

p-substrate
Fig. 2.6-11

ECE 4430 - Analog Integrated Circuits and Systems

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CMOS Technology (6/7/00)

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Temperature Characteristics of Transistors Fractional Temperature Coefficient 1 x Typically in ppm/C TCF = x T MOS Transistor V T = V(T0 ) + ( T-T 0 ) + , where -2.3mV/C (200K to 400K) = KT-1.5 BJT Transistor Reverse Current, IS: 1 I S 3 1 VG0 = + IS T T T kT/q Empirically, IS doubles approximately every 5C increase Forward Voltage, vD: V G0 - v D 3kT/q vD = - T -2mV/C at vD = 0.6V T

ECE 4430 - Analog Integrated Circuits and Systems

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CMOS Technology (6/7/00)

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Noise in Transistors Shot Noise i2 = 2qIDf (amperes2) where q = charge of an electron ID = dc value of iD f = bandwidth in Hz i2 2 Noise current spectral density = f (amperes /Hz) Thermal Noise Resistor: v2 = 4kTRf (volts2) MOSFET: iD2 = where k = Boltzmanns constant R = resistor or equivalent resistor in which the thermal noise is occurring. gm = transconductance of the MOSFET 8kTgmf (ignoring bottom gate) 3

ECE 4430 - Analog Integrated Circuits and Systems

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CMOS Technology (6/7/00)

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Noise in Transistors - Continued Flicker (1/f) Noise

Ia iD2 = Kf b f f

where Kf = constant (10-28 Faradamperes) a = constant (0.5 to 2) b = constant (1)

Noise power spectral density 1/f

log(f)

Fig. 2.6-12

ECE 4430 - Analog Integrated Circuits and Systems

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CMOS Technology (6/7/00)

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SUMMARY CMOS is a fairly simple, technology which is used primarily for digital circuits The minimum channel length of CMOS tends to decrease by a factor of 1/ 2 every three years (Moores Law) CMOS technology can be used for analog circuits but it would not be the preferred choice if everything else were equal. Active devices compatible with standard CMOS technology are: - Lateral BJTs - Vertical BJTs (not shown) Other considerations - Latchup - Electrostatic Breakdown

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen, 2000