TRANSACTIONS COMMUNICATIONS, IEEE ON NO. COM-27, VOL.

2, FEBRUARY 1979

379

Key Aspects in the Development of a 48-Channel Duobinary PCM Repeater

Abstract-This paper describes the background and the actual circuit designs in the development of the 48-channel modified duobinary PCM line repeater.The reasons for thechoiceofthemodified duobinary coding technique are explained. The equalization requirement of the signal in terms of the channel roll-off factor is obtained by considering the crosstalk penalty, intersymbol interference, and ease of hardware implementation. The hardware implementations of thevarious repeater sections-equalization, clock recovery, and data regeneration-are n circuit design are circuit size, outlined. The main considerations i power consumption, and tolerance to parameter variations. These considerations are of prime importance for the modified duobinary system t o retrofit the existing T1 system. Such requirements resulted i n the extensive use of integrated circuits and thick-fiim hybrids and also in the development of a new clock recovery method for a correlative pulse sequence called the slicer method.

This paper will describe the development of the duobinary line repeater [5] and how the use of integrated-circuit technology made the development possible within the reallife restrictions imposed by the operating environment and economic pressures.

11. DEVELOPMENT BACKGROUND The first part of any development effort must always be the determination of parameter requirements. Theseare the criteria which dictate the techniques and processes used in the development. For the modified duobinary system, this involves the realization that any retrofit system has to tolerate most, if not all, of the installation conditions imposed bythe existing T1 systems. This consideration involves determination of the I. INTRODUCTION types, lengths, age, and mixtures of cable used, the types of N 1962, digital transmission techniques were brought into repeater housings involved, the possible effects of cable splices the telephone company transmission networks with the in- and route junctions, the allowable positions of transmit and troduction of the T1 PCM carrier system. This network con- receive pairs within the cable, and the span powering limitasists of channel banks which digitize and time-division multi- tions imposed by existing installations. plex up to 24 voice channels into a 1.544-Mbit bipolar Examination of these requirements indicates that the retrofit format for transmissionover a repeatered line. The signalis repeater must be designed to transmit and receiveover mixcarried over a repeatered line which utilizes plastic or pulp- tures of cable sizes ranging from less than 25 pair to over 900 insulated paired exchange cable to the receiving channel bank pair and with individual pair wire gauges ranging from 19 to which demultiplexes the signal and converts it back to analog 26 gauge. Pair insulation within the cable can be either plastic form. This system has proven to be immensely successful or pulp. The cable attenuation can be characterized over the because of itslow cost and reliable operation. frequency range of interest by the following: In the years that have followed, increased demands for service have placed a strain on these 24-channel systems and have L =Lo (1) prompted telephone operating companies and manufacturers alike to search for newways to economically increase the capacity of the digital transmission network. Several new where Lo is the loss of the cable measured at frequency fo, systems have emerged from this effort, most of which require and c is the exponent assigned as a function of cable construcinstallation of newcable and/or repeater housings.Among tion and insulation. In general, c = 0.5 for plastic insulated these are T1C and T4 [l] , [2]. cable and 0.58 for pulp insulated cable. One of the new systems provides for the attainment of a 48Using the T1 installation criteria, the requirements are that channel capacity per line via the process of retrofitting the 24- line attenuation may be between 9 and 35 dB and that up to channel repeaters with new 48-channel repeaters, exchanging 25 repeaters can be installed in the same housing with several the 24-channel office repeaters for 48-channeloffice repeaters, housingsusingpairs from the same cable. Cable attenuation and installing a multiplexer to time-division multiplex two 24- figures throughout this paper are measured at fo = 772 kHz. channel PCM signals fromtwo channel banks. This system Because of the large number of existing field installations and uses the correlative technique termed modified duobinary the different models of housings, it is impractical to establish any single criteria relating to all repeater housings. Since it is which was developed by A. Lender [3], [4]. known that the prime factor affecting repeater performance is the amount of interference coupled into a repeater input from Manuscript received June 14,1978;revised October 5,1978. adjacent repeater outputs, laboratory measurements and statisThe authors are with GTE Lenkurt Inc., San Carlos, CA 94070.

(k)c

0090-6778/79/0200-0379$00.75 0 1979 IEEE

380

TRANSACTIONS IEEE

ON COMMUNICATIONS, NO. COM-27, VOL.

2, FEBRUARY 1979

Modulo 2 Algebraic tical characterization of the pair-to-pair coupling loss between Ct wire pairs within the housing were used. Theselosseswere measured at 772 kHz to permit comparison with T1 measurements. Statistical characterization of the measurement for various housings resulted in mean values of pair-to-pair coupling loss ranging from 75 to over 110 dB. [6] Fig. 1. Binary to modified duobinary conversion, where A , are binary The environmental factors dictate that the repeater will be input digits, B j are encoded binary digits, and C j are modified duoexpected to performin temperatures ranging from -40 to binary digits. t6O"C and at altitudes from 0 to 10 000 ft with relative humidity ranging from 5 to 95 percent. Repeater reliability Power Supply Regulator should approach the 610 fits target set for T1 (1 fit = 1 failure in lo9 h) [7]. The requirements imposed by the market dictated that the design result in a relatively low cost unit with no maintenance effort by the customer and the product relatively easy to manufacture. With these basic requirements as detailed, the modified duobinary technique was chosen after studying several coding I processes. Initsrudimentaryform,the binary-to-modified Clack ALBO Control Recovery duobinary conversion is depicted in Fig. 1. The corresponding expressions for binary-to-modified duobinary conversion with Fig. 2. Block diagram of modified duobinary line repeater. letter designations, as in Fig. 1, are
t

Bt/At = 1/(1 t D 2 )Mod 2 Ct/Bj = 1 1 - e-i4rrf I Algebraic

where D At B, Cj

(2) (3)

Huffman delay operator; binary input digits; encoded binary digits; modified duobinary digits; T data clock period, and 1/Tis speed in bits/s. The basic reasons for the choice of this coding process were: 1) Bandwidth compression by afactor of two. The bit speed for a 48-channel modified duobinary system is identical to that of the existing T1C (3.152-Mbit/s) bipolar system with only half bandwidth, ensuring compatibility with the existing digital hierarchy. 2) The shape of the spectral density of a modified duobinary signal with a 100-percent duty cycle pulse is identical t o that of the T1 bipolar signal with 50-percent duty cycle, ensuring compatibility with existing T1 systems. 3) The critical part of the signal spectrum is in a frequency band for which cable parameters are fairly well known and stable. This simplifies the design of equalization circuits in the repeater. 4) There is no dccontent in thetransmitted signal.This simplifies the circuit design because the loss of the lowfrequency part of the transmitted spectrum through the transformers which are required at the output and input of each repeater does not have to be compensated for in the equalization circuitry. 5) The error detection process is similar to and as effective as T1. 6 ) Fault locating signal and procedures are nearly identical to thatof T1 except for ascaling factor. In designing the modified duobinary repeater, its basic format must first be established. Because the regeneration process involved is similar to that of a T1 repeater, a similar functional

design is used. This is shown in Fig. 2. Four basic parameters must be considered. These are 1) the equalization to be employed, 2) the method of clock recovery to be used, 3) the sampling and decision technique, and 4) the power requirements of the unit. Although the basic format of the repeater has been established, as shown in Fig. 2, a considerable latitude remains in defining the characteristics of the various,blocks. Furthermore, it should be pointed out that Fig. 2 shows one regenerative circuit per repeater, but the practical applications require that two of these circuits must be packaged on a 4 X 6-in card and driven from a common power supply.
111. DEVELOPMENT OF THE EQUALIZATION CIRCUITS

The first part of the development problem is to establish the format of the equalization to be applied to the incoming signal pulses. This has a serious impact on the penalties to be paid in the final application. This choice will also determine the shape of the pulse which is applied to the clock recovery and decision circuitry, the designs ofwhich become more heavily dependent on the equalization chosen due to the amount of intersymbol interference in the modified duobinary signal. As the channel roll-off factor a decreases, there islessnoise penalty to be paid, but the decision process in terms of threshold stability and clock positioning becomes more critical. The circuits which determine the margin of the repeater are the automatic line build-out (ALBO) network, the equalization amplifier, and the ALBO control circuit, as shown in Fig. 2. These unitsoperate in a .feedback mode to keepthe signal pulse shape at point A constant if the physical length of the cable separating the repeater from the next upstream repeater has a 9-35-dB attenuation. The equalization amplifier then acts upon this signal to optimally shape it for the decision to be made at point A . This amplifier must shape the signal so thatthe channel (from the upstream repeater to point A ) gain versus frequency characteristic satisfies the Nyquist criterion of preservation of zero crossings.The required channel

CHEUNG et al.: DEVELOPMENT OF 48-CHANNEL PCM REPEATER

381

14

12

10

1/2T Frequency (Hertz)

L
fr

13dB

V(f1 =

Fig. 3. Normalized channel characteristics. 01 is the channel roll-off factor, and 1/2T is the Nyquist rate.
I
1 4

O < f <+T-

9
O " :

[I

- sin

If

-1 ' 2 T ]

J-2T f,
f

G - f

<

+
2T

f,

>

f, +J-

characteristics are shown in Fig. 3. The channel roll-off factor a ! is defined as Excess bandwidth due to roll-off a!= = 2Tf, Nyquist bandwidth
(4)

Rall.off Factor bl for Modified Duobinary Channel. Cable N E X T for PIC Equalization

___

Cable N E X T for Pulp Equalization

where f, isasshowninFig. 3. The characteristics of the ALBO and equalization amplifier determine the effects of interference on the decision process since the noise must also pass through these two networks to decision point A . Graphs for an ALBO which match PIC or the pulp insulated cable appear in Fig. 4. The near end crosstalk (NEXT) penalty A W is defined as

Fig. 4. Crosstalk penalty with varying roll-off factor. Cable length is characterized by attenuation at 112 kHz.

AW= W(1)modified duobinary

- W(l)bipolar

(5)

where W(1) is the rms NEXT appearing at the equalizer output due to one interferer. As the graph shows, anALBO which simulates PIC causes less penalty than one which simulates the pulp insulated cable. The optimum choice for the ALBO characteristic in terms of minimum AW appears to be a representation of PIC cable. With this choice made, it can be seen in Fig. 4 that AW for a 29-dB span would be lessthan 10 dB if the channel roll-off factor is kept to 0.4 or less. The pulse shape at the output of an equalization amplifier which creates an overall channel spectral characteristic, as shown in Fig. 3, can be defined by

u(t) = uo

( F ()

sin ntlT

cos a! ntlT 1 - 4a2t 21T2

where uo is the height of a pulse with no intersymbol interference at the amplifier's output. Because the modified duobinary processallows forintersymbol interference, the signal at the output of the equalizer i s dependentuponthe effects ofprecedingandsucceeding pulses. Computer analysis of (6) indicates that there is a negligible contribution from pulses beyond +4 pulse periods for a! exceeding 0.2 [8]. Using this result, it is easyto generate eye patternsfrom ( 6 ) and codedcombinationsof 8-bit sequences. Some of these eyepatterns areshown in Fig. 5.

Examination of Figs. 4 and 5 indicates that the optimal choice of a! will lie between 0.2 and 0.4. In this range, the margin penalty will not vary by more than 1 dB, a reasonable eye openingis obtained, and the equalization characteristics are realizable. From the system's standpoint, the choiceof a! = 0.2 is preferable since it results in the best noise performance for the repeater. However, from the point of view of intersymbol interference, the larger eye opening and more gradually sloping equalizer characteristic favor the choice of a! = 0.4 or larger because the hardware implementation is simpler. Considering both factors-noiseand intersymbol interference-a choice of a! = 0.25 seems to present a reasonable compromise. The equalization circuits comprise three sections: the ALBO, the gain equalizer, and the delay equalizer. In designing the equalization circuits, final designs are arrived at using experimental results as well as using computer analysis of the circuits. Factors governingdesign selections aresizeand cost of the actual circuit, power consumption, and performance. The ALBO consists of two Bode-type shaping networks [9] connected in tandem, asshown in Fig. 6 . Thisshaping network exhibits variable insertion loss versus frequency characteristics when the resistanceof the variableresistor R, is changed. The ALBO circuit design requires a dynamic range of 26 dB of cable variation since the duobinary repeater needs to operate from 9 to 35 dB of cable loss. This Bode shaping network has the characteristic of providing an insertion loss or gain which provides bettermatching ofcable insertion loss characteristics withinthe signalpassbandand thedynamic range required. Two of these Bode networks are used for added accuracy to meet the required noise performance of the

382

IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. COM-27, NO. 2 , FEBRUARY 1979

Boundaries of Eye Opening

Fig. 5. Computer-generated eye patterns with varying channel roll-off factor CY. H is the maximum height of eye opening at the sampling instant, P is the base-to-peak amplitude of the eye pattern half-way between adjacent sampling instant, and W is maximum width of eye opening at the 50-percent slicing level. (a) CY = 0.2, (b) CY = 0.4, and (c) CY = 0.6.

Fig. 6 . Automatic line build-out circuit. Fig. 7. Gain equalizer circuit.

repeater. Within the operating range of the repeater, the ALBOisdesigned so that its output always appears to be a duobinary signal attenuated by 27dB ofcableloss.If the cable loss to the repeater is 9 dB, the variable resistors R v l and Rv2 will be controlled so that the insertion loss provided by the ALBOis 18 dB. For cable loss of 35 dB, the ALBO will act as an amplifier with the frequency characteristic whch will cancel 8 dB of real cablein the passband. The two variable resistors R v 1 and R v 2 are realized by two diode strings with their currentscontrolled by the ALBO control IC. As the height of the incoming signal varies, the current through the diode strings will vary, causing a change intheir effective resistance, thus maintaining the signal peak at the desired dc reference level. To achieve stability intheflat gainof the network, the amplifiers shown employ feedback. Thegainequalizerimmediatelyfollows the ALBO circuit andisshown in Fig. 7. It consists of two gainandshaping stages and a low-pass filter. The requirement for the transfer function E ( f ) of the gainequalizeriscalculatedusing the following relation:

For one of the gain and shaping has a transfer function of the form

stages shown in Fig. 7, it

where K is the gainof the amplifier. Together with the lowpass filter whichprovides the roll-off attheband-limitfrequency, w l , w 2 , and up ofeachstageare selected using a least squarEs error method on a computer so that the transfer function E ( f ) of thethree sections intandem, neglecting component tolerances, meets the theoretical requirement

MAXIE(f) - Eh(f) I 2

& dB in

the passband.

(9)

The particular designs chosen here involve inductors which add to thecircuit size. Other induc2rless designs which could realize the same transfer function E ( f ) were examined. However, these circuits all exhibitthe characteristics that their circuit Q and natural frequency upare too sensitive to parameter variations and, therefore, are not acceptable. Define the sensitivity of x with respect t o y as
Y ax

where V(f) is theFouriertransform of u ( t ) in (6) which defines the desired output pulse shape of the gain equalizer, P(f) is the pulse spectrum of therepeater output pulses, which are 100-percent duty cycle square pulses, and L(f)is the cable insertion loss characteristics, determined at a maximum equivalent cable loss of 27 dB, using (1) with fo = 772 kHz.

ar'
For the particular design chosen, using (lo),

CHEUNG e t al.: DEVELOPMENT OF 48-CHANNEL PCM REPEATER

383

A
Fig. 8. Delay equalizer section.

Therefore, to maintain a tight control on manufacturing variations and environmental performance, the approach described was chosen. The remaining section of the equalization circuits is the delay equalizer, which is formed by a tandem connection of three of the second-degree constant resistance sections shown in Fig. ,8. The advantages of this design are discussed by Schmidt [lo]. Thisdelay equalizer isused to equalize the group delay introduced by the ALBO and gain equalizer circuits so that the delay of the complete equalization circuit is approximately flat in the passband. Component values are obtained using again the least squares error method on a computer. This three section design is optimum for the 1-percent tolerance on the element values used. The peak-to-peak delay ripple in the passband is 1 percent of the total delay. Compared to activedesigns, this circuit has the disadvantage ofusing many inductors whichincrease the circuit size but has the advantage of better noise performance and no power consumption. The inductor size problem is handled by using miniature inductors and mounting the equalization circuits on thick-film hybrids. Theuse of thick-film hybrids also provides the advantage of allowing each of the equalization circuits to be individually tuned and tested before installing in the repeater unit.
IV. INTEGRATED-CIRCUIT DESIGN The constraints of power consumption and space dictated thatthe remaining circuitry be integrated. The result, after some partitioning, was three custom integrated circuits: the ALBO control, the clock driver, and the regenerator. Two of these circuits, the ALBO control and the clock driver, were fabricated on predeveloped integrated circuits with custom metalization, commonly known as master chips. The advantage of such a choice was fast implementation of our circuits, minimal investment, and the ease with which changes could be made if necessary. The disadvantage, of course, is the lack of circuit density on the IC. This disadvantage, however, was not of major concern aswe did have the room for two ICs, and full custom integration could be done at a later date. The process used for the master chips was bipolar, a common and well-established process. The third IC, the regenerator, is more complex in size and design than the preceeding two and, hence, necessitated a fully custom design. This IC contains the clock amplifier and two edge triggered flip-flops. The two circuits, one linear and one digital, were combined to eliminate the interconnection problem and hence the need for buffering of the squared clock to the flip-flops. The digital circuits made this IC a candidate for an 12L or gold doping as well as bipolar process. 12L was ruled out due to its immaturity as a process, and doping was ruled

Fig. 9. Regenerator integrated circuit.

out because of its effect on thelinear circuits contained in the IC. Hence the standard bipolar process was used. The circuit design for the digital portions was made using emitter-coupled logic (ECL) to provide the speeds required. This use of bipolar
processingand

ECL gave us theresultswerequired.

Fig. 9

shows a photograph of the regenerator integrated circuit. DEVELOPMENT OF CLOCK RECOVERYCIRCUITRY From Fig. 5 , it can be seen that the boundaries of the eye opening are of great importance to clock recovery and sampling. A good approximation of these boundaries may be obtained using the straight lines joining the maximum height and width of the eye opening as shown in Fig. 5(a). If a t = 0 reference is established at the point where the height of the eye opening is the greatest, the boundaries of the eye opening can be defined by top boundaries: [m t t H , -mttH, bottom boundaries:
*

v.

-W < , -W -< 2

t<O
W 2

O< t< -

where H Z maximum height of eye opening at the sampling instant, W maximum width of eye opening at the 50-percent slicing level;

384

IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. COM-27,NO. 2 , FEBRUARY 1979

TABLE I HORIZONTAL QUALITY FACTOR, VERTICAL QUALITY FACTOR, AND MARGIN DEGRADATION AS A FUNCTION OF CHANNEL ROLL-OFF FACTOR A N D CLOCK MISTUNINC (tl T )

-2.1

2.23

.54
.37

4.9
-0.8

-1.8

2.06

-1.6

constraints on the clock in the source multiplexer play a factor inthe selection of the circuit Q . The source clock Other parameters of interest are: P - H/H which is a quality has a tolerance of 100 ppm. With a Q of 1000, the 1.0 X factor which shows the relative size of the signal available after Af/f, offset would cause a3-percent ( t / T ) offset of slicing, which is the method used for clock recovery; and T/W the sampling spike fromtheoptimumpoint. A Q of 500 which is a quality factor indicating the allowable range of clock would cause a 1.6-percent offset of the sampling spike. For mistuning, where P is identical to the base-to-peak amplitude a 3.152-Mbit/s transmission rate, this latter offset would of the eye pattern halfway between adjacent sampling instants, correspond to a 5.0-11s mistuning. Since Table I indicates and T is identical to the pulse period. Table I summarizes thatfor5-percent (15.9-11s) mistuning ina40-percent rollthese parameters for various roll-off factors. off eye pattern a penalty of 0.9 dB is incurred, the Q = 500 The specifications for clock mistuning and jitter can be de- specification would appear to be in the right range. veloped from (1 l ) and Table I. The prime concern in clock Only one method to recover a clock to meet the needs of recovery is that the resultant clock-derived sampling pulse re- the system efisted at the beginning of this project. This mains in the center of the eye over varying conditions of the method involves three rectifications. Because of the power line length,informationtransmitted, and manufacturing. A and size requirements, this method was not the most favorclock offset from theoptimum sampling position results in able. Hence a new method of clock recovery was sought. degradation of the repeater margin. This degradation AM, Through analysis of the correlative properties of various pormay be obtained from (1 1): tions of the equalized signal pulse stream, a new method was discovered. This method has been coined the slicer method. This method was so named because a portion of the equalized signal is sliced off and processed to derive the necessary clock. In its implementation, the sliced portion of the signal is passed through a low-pass filter used for adjusting the phase of the recovered clock with the equalized signals. Then the resultant waveform of the low-pass filter is amplified and then filtered by a crystal filter resulting in a sinusoidal clock. The margin degradation for 5- and 10-percent time shifts in the The studies which led to this method of clock recovery were sampling pulse position expressed as a function of the normal- done on a computer. Pulse sequences 8-bits long were generized pulse period ( t / T )is sho9.m in Table I. These time shifts ated in coded form to simulate the incoming bit stream. All correspond to 17 and 34 of phase shift due to a difference the sequences, without duplication, were generated. This between the center frequency of the tuned clock filter and the resulted in 962 distinct sequences. These sequences were frequency ofthe incoming signal. The fractional mistuning shaped using the overall channel characteristics to produce which would cause these shifts can be calculated fromthe sequences in time that appeared in shape like those expected following equation [ 101 : from the equalization network. The region between the fourth and fifth bit of each sequence tan [,60 = 2Q Af was examined, and the results for each time position for all f, patterns was tallied to produce an ensemble average. The where Q is the tuned circuit parameter expressing the 3-dB process now was to vary the slicinglevelrelative to aunit bandwidth of the clock filter, f , is the center frequency of pulse and explore the results. thetunednetwork, and Af is the difference between the Fig. 10 shows two ensemble averages, one for the slicing level incoming frequency and f,. above the unit pulse height (these peaks are the result of interEquation (13) also helps to determine the circuit Q require- symbol interference) and one below theunit pulse height. Notice that the ensemble average for one peaks as the others ments of the clock recovery filter. Because the total jitter at above theunit pulse the end of a string of N repeaters is inversely proportional to null. The decisionwas made to slice is because of the stronger correlation in the the circuit Q , it is importantthat this factor be as high as height. This opening boundaries.

(+)I

CHEUNG e t al.: DEVELOPMENT 48-CHANNEL OF

PCM REPEATER

385

kT

Pulse Perlod

klT k+llT

Pulse Period

(k+ll T

(a) (b) Fig. 10. Ensemble average of clock recoverydrivesignal at different slicinglevels.(a)Slicinglevel is 0.5 of unitpulse. (b) Slicinglevel is 1.2 of unit pulse.

DISCRETE SPECTRAL COMPONENTS I N dBm

't
I

-100

4--LL
f0

represents the upper 10 percent of the signal, tracking of transistor junctions is important. This tracking is easily provided in the IC by controlling the transistor emitter areas in a ratio to their currents. This enables the slicing voltage to stay within k l percent of its nominal value over temperature. Onefinal problem remains in the clockrecovery process. This is the determination of the Q that is necessary to insure a stable clock. Computer modeling of pseudorandom patterns shows that the peaks which will excite the clock filter occur 8 percent of the time on the average with a short-termminimum occurrence of 2 percent. If we assure this 2-percent average density and desire a clock power loss of no more than 50 percent between these peaks, we can calculate the necessary filter Q by energy stored QE energy lost/radian

2fo

3f0

4fo

Q=

1
- (0.5) (0.02)

= 628.

Fig. 11. Computer-generateddiscretespectraldensity slicing above unit pulse height.

components for

2n Using this filter Q, the maximum offset in the sampling spike defined in (1 3) is 6.8". VI. ALBO CONTROL AND DECISION THRESHOLD GENERATION A requirement in the regeneration decision made in the repeater is whether the equalized signal exceeds a preset threshold level at the sampling instant. When the signal exceeds the preset level at the sampling instant, a new pulse i s transmitted from the output of the repeater. The ALBO control circuitry's function is to control the height of the equalized signal and to provide the decision thresholds for the regenerator circuits. The height of the equalized signaliscontroUed by varying the variable resistors in the ALBO. These resistors are formed by diodes driven by current sources in the ALBO control IC. The resistance is approximately 0.026/1, where I, is the current from the current sources. The relationship of the decision thresholds to the peak level of a singlepulse(i.e., maximum eye opening) is important becausean offset in this relationship cancauseanincrease in the errors made by the repeater. The effect of a change of the threshold with respect to the signal height is a change in margin determined by

SUPPIV

supplv-l Detected Voltage

L. 0

Output to High Q Filter

wv5

Fig. 12. Slicercircuitwhichdrivesahigh-Qfilterfor clock recovery. 01 and 9 2 are the normal and inverted signal input.

ensemble average. Fig. 11 shows the computer-generated discrete spectral density componentsfor slicing above the unit pulse height. Once it was decided to slice above the unit pulse, a slicing level V, had to be established. A reasonable value is midway between the unit pulse and the peak signal due to intersymbol interference. For a in the range of 0.2-0.5, this valueis approximately 1.2 times the unit pulse height. This circuit was integrated to provide control over the tight slicingvoltage tolerances throughout the power supply and temperature variations. The slicer circuit is shown in Fig. 12. Theinput to this circuit is a dc voltage representing the long term peak of the equalized pulse sequence. This voltage is buffered via Ql and Q2 and divided by R1 and R2 toprovide a slicing voltage where desired. Q3 and Q4 are the actual slicers. Their bases are connected to a differential amplifier in the IC which provides both phases qjl and qj2 of the equalized signal at the bias of one V , above common. This bias is necessary to compensate for the V , of the slicer transistors and is provided by a feedback circuit in the differential amplifier. Since the slicedwaveform

where AMT is the margin penalty in decibels, D is the decision threshold in volts, and X is the change in threshold in volts. Using this formula it can be seen that for a 10-percent change in the threshold (X/D = O.l), a margin penalty of 0.8 dB will have to be paid. The system'requirements demand that margin penalties due to equipment design be kept as low as possible. Therefore, a double-threshold (positive and negative) approach was adopted because it is easier to precisely control the relation of positive and negative thresholds than to control the inverted duplication of a signal pulse. Furthermore, this approach allows the thresholds to relate to the received and equalized pulse heights.

386

IEEE TRANSACTIONS ON
vcc

COMMUNICATIONS, VOL.

COM-27, NO. 2, FEBRUARY 1979

83
ALBO Variable Resistance Drive

'rr

Fig. 13. Block diagram of ALBO control IC. ~ V are T the decision threshold voltages suppliedto theregenerator IC.

The ALBO control integrated-circuit establishes a reference voltage from which the regenerator logic decision thresholds are derived. The decision thresholds are also provided in the ALBO chip. Included in the ALBO control ICis a pair of matched current sources whose current is varied to provide the ALBO control. Fig. 13 shows a block diagram of the ALBO control IC.The amplifiers shown are simplified versions of common operational amplifiers. The reference voltage (VREF) governs the ALBO control and threshold voltages. Its amount of tolerance is critical, and, hence, its implementation would be expected to be somewhat complex. However, it is simply a resistor divider. The absolute tolerance of resistors in this IC arespecified at 230 percent. However, theratio of two resistors in the IC can be held to +2percent. Since all of the outputs are relative to the reference voltage, any small power supply errors are canceled by the uniform tracking with respect to this voltage. In the reference voltage, tolerance is 3 percent. T h e increase in tolerance over the resistors is due to loading effects of the three attached circuits. Thus, with a 3-percent tolerance on the reference voltage , the margin penalty [AMT from (1 4)] canbe calculated to be 0.4 dB. Because both VREF and VT track changes in the supply voltage, changes in V& do not affect the pulse-to-decision threshold relationship. In addition, establishment of VREF by a simple resistance ratio makes this portion of the circuitry very stable with respect to temperature variations. Measurements indicated that both thresholds could be easily held within a 2-percent tolerance using this approach. The attributesofintegrated-circuit design techniques also simplified the design of the drive circuitry forthe variable resistors in the ALBO. The variable resistance in the ALBO ( R v l , R v2 in Fig. 7) is supplied by diodes driven by dc current from the ALBO control IC. This current is varied until the peaks of the equalized signal (as determined by the peak detectorinthe clock recovery IC) match VREF.The long memory of the peak detector and the high gain of the ALBO drive amplifier ( U 3 in Fig. 13) combine to ensure a close match of the detected peak voltage to VREF. VII. REGENERATOR CIRCUIT The regenerator circuit performs thefunction assigned to the repeater. The circuitry compares the equalized signal

Differential Recovered Clock

Clock

Clock Arnplifler

Fig. 14. Block diagram of regenerator circuit.

against the preset thresholds atthe sampling instant determined bythe amplified recovered clock and generates the proper polarity output pulse. A block diagram of the IC used to perform this function is shown in Fig. 14. The circuit contains a clock amplifier which amplifies and limits the differential inputs from the clock filter. The positive edges of the resulting square wave clock is used for sampling and comparing the equalized signal against VT. The important characteristic of the clock amplifier is the AM to PM conversion which causes jitter in the transmitted waveform. This AM to PM conversion is related to the gain of the clock amplifier and to the symmetry of its limiting characteristic. This can be seen from Fig. 15. If it is assumed that the clock amplifier output is limited for all hiput levels above t V, or below - V,, the variation (from a minimum of Vl to a maximum of V 2 ) in t$e leading edge of the clock waveform A t can be determined from (1 5) where it is assumed that the limiting voltage level V, is much less than the lowest expected clock input.

assuming t l and t2 << T. Thus if the minimum clock input is 50 mV, the maximum clock is 500 mV, and the limiting threshold (as referred to the input) V, = 2 mV, theoutputjitter would be 2 ns. If an

CHEUNG et al.: DEVELOPMENT OF 48-CHANNEL PCM REPEATER

381

Fig. 15. AM to PM conversion of clock amplifier that causes jitter in the transmitted waveform. V I and V2 are the maximum and minimum sine wave input levels, respectively. VL is the input voltage that causes the amplifier output to limit. The difference between 11 and t 2 is the output jitter.

bias

Output

i
v,,

Fig. 16. Basic clock amplifier cell for squaring the recovered Sine wave.

output-limitedclock pulse is 1.4 V, the required amplifier voltage gain would be 50 dB. The use of integrated-circuit technology for this circuit not only allows for a reduction ofspace but permits the attainment of good limiting characteristics with high gain. By combining the sampling circuits with the clock, problems normally encountered with circuit delays are alleviated. The clock amplifier is connected in three stages and is unique in that allbiasesand the output swingare related to diode drops (VBES). Fig. 16 shows a basic cell to this design. The bias reference is derived from a diodechain. The signal at the base of the differential gain stage is referenced to a value of three VBES. Subtracting one VE for the base-emitterdrop,the result is two VBES across R 2 . The collector resistoris equal in value to the commonemitterresistor R 2 . The currentthrough R2 is 2 v B ~ / R 2 Hence, . the current through R1 is VBE/R2. Since R1 equals R 2 , the drop across R1 is one VBE. The top of the collector resistors are referenced five V B ~ above s ground. Theresultis a collector bias of four VBESwith a peak-to-peak swing capability of two Vms. Since the swing is limited to a minimum level of three VBESand the base on the output side of the differential pair is referenced at three VBES,the stage cannot saturate. Theuse of a capacitor to filter the incoming signal to select its bias for use by the differential pair was made for the ease of implementation. The decision devices comprise a pair of clocked differential

SIGNAL

MASTER FLIP FLOP OUTPUT

3~
~~

SLAVE FLIP FLOP OUTPUT

Fig. 17. Timing diagram for regenerator circuit.

flip-flops. Each phase of the output has a master and a slave stage. During the positive transition of the clock, the master flip-flop becomesoperational and the output change to the state indicating whether the equalized pulses exceed the threshold. On the negative cycle of the clock, the master flipflop locks into the state and the slave flip-flop becomes active, following the master flip-flop. On the next positive cycle of the clock, the slave flip-flop locks onto the data as the master flip-flop again becomes operational, toggling as the, equalized pulse varies around the threshold. Fig. 17 shows a typical timing diagram. The output buffer stage is used to drive the output transistors. This stage is a push-pull type. Since the modified duo-

388

IEEE TRANSACTIONS ON COMMUNICATIONS,

VOL.COM-27,NO.

2, FEBRUARY 1979

Fig. 18. Final version of the modified duobinary repeater. X. CONCLUSION The modified duobinary repeatered line provides a convenient and fully system-compatible way of increasing the capacity of services carried over the present T1 installations. Its structure is such that it fits into the existing plant without interferring with other systems or requiring unusual modification to standard bit-rate structures of line operating speeds. The cost of this advantage is an increased load on the circuit designer to partially make up for the operating margin lost by the coding technique. This means that a great deal of care had VIII. POWER SUPPLY AND OTHER CONSIDERATIONS to be taken to ensure operational and manufacturing stability of repeater parameters. To do this the circuit complexity was Because the system isdesigned to retrofit the existing T1 increased over that used in T1 or T1C repeaters. Because the units, it is desirable that the powering requirements be the size and powering requirements remained the sameas in the same. As in the T1 system, dc power is fed to the repeater T1 system, it was necessary to usedesign techniques which over a loop formed fromthe simplexes of two cable pairs. used both little space and current. The obvious process for the The nominal loop current is 100 mA which is based ona most part was the bipolar integrated-circuit technology. The repeater drop of 11 V. ability to obtain significant size reductions simplified the Because there are two pulse generation circuits per repeater, mechanical design tremendously. The ability to achieve good the design for each must require somewhat less than 50 mA. matching between electrical characteristics of devicesis exProtection against 100-A lightning-induced longitudinal tremely importantin holding tight electrical characteristics surges isalso required. Power supply regulation is accomplished over the environmental range. by using a surge protection zener diode in combination with a It is fair to say that it is unlikely that the modified duobinary low-power temperature-compensated zener forthe positive repeater could have been translated from a laboratorycuriosity supply (Vcc), a standard diode to protect against loss of the to a viable cost-effective unit without the use of integratedpower supply due to reverse current surges, and resistors and circuit design techniques. capacitors for the negative supply (V E ~ and ) filtering. IX. THE MODIFIED DUOBINARY REPEATER Fig. 18 shows the final version of the 48-channel modified duobinary line repeater. The need forthe use of thick-film hybrids and ICs is evident. REFERENCES
[ l ] J. A. Lombardi,R. E. Maurer, and W. P. Michaud, The T1C system, in Int. Conj: on Commun. Con5 Rec., 1975,pp. 39-1[2] P. E. Rubin, The T4 digital transmission system-Overview,

binary output has 100-percent duty cycle, there is a necessity to keep the output drive width to within a tolerance of ?15 ns. To accomplish this over the temperature range of -40 to t6OoC, the output buffer stage has temperature variable current sources which work in conjunction with the buffer stage to account for changes in a transistor on and off times with temperature. This is accomplished using a V , , ratio across a resistor to cause an increase in current at colder temperatures, the inverse of what is normally expected of a current source in an integrated circuit.

39-4.

CHEUNG e t al.: DEVELOPMENT OF 48-CHANNEL PCM REPEATER inZnt. Coni on Commun. Coni Rec., 1975,pp. 48-1-48-4. [3] A. Lender, The duobinary technique for high speed data transmission, IEEE Trans. Commun. Technol., vol. COM-12, pp. 128-135, Dec. 1964. [4] A. Lender, Correlative level coding for binary data transmission,ZEEE Spectrum,pp. 104-115, Feb. 1966. [5] H. W. Cheung, K. T. Tanaka,and J. A. Thomas,48-channel duobinary PCM repeater, in Znt. Coni on Commun. Coni Rec., 1917, pp.302-305. [6] A. Lender and V. Stalick, Engineering the duobinary repeatered line, inInt. Coni on Commun. Coni Rec., 1971, pp. 306-309. [7] H.P. Westman, Ed., Reference Data for Radio Engineers, 5th Ed., pp. 40-21. [8] J. A. Thomas, A simple method ofclock extractionfrom a correlative pulse sequence, inInt. Coni on Cornmun. Coni Rec., 1978. [9] H. W. Bode, Variable equalizer,Bell Syst. Tech. J., vol. 17, pp. 229-244, Apr. 1938. [ l o ] C. E. Schmidt, Delay equalizer, IEEE Wescon Conv. Rec., 1972. [ 111 Transmission Systems for Communications, Bell Telephone Labs, 4th ed., 1970.

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Victor J. Stalick (S59-M61-MY74) was born in Omaha, NE, on June 12, 1938. He received the B.S.E.E. and M.S.E.E. degrees from the University of Wyoming, Laramie, in 1960 and 1966, respectively. From 1966 to 1969, he worked for Collins Radio Company in the development of avionics equipment.From1969to1972,he worked for Litton Electron Tube Division in the development of ATC transponders, VHF/UHF land mobile radios, and TWT amplifiers. In 1972, he joined GTE Lenkurt, San Carlos, CA, and as a member of the PCM Transmission Group he has been engaged in the developmentof the T1C repeatered line equipment, and as the Project Leader in the development of the modified duobinary repeatered line equipment. i . Mr. Stalick is a member of Sigma X

Humphrey W. Cheung was born in Hong Kong, on May 3, 1949. He received the B.S. and M.S. degrees in electrical engineering from the University of California, Los Angeles, in 1972 and 1973, respectively. He joined GTE Lenkurt, San Carlos, CA, in 1974, and became involved in the development work of the duobinaryrepeater inthe PCM Transmission Group. His current work involves receiver designs for optical fiber transmission.

Jay A. Thomas (77) was born in Los Angeles, CA, in 1951. He received the B.S.E.E. degree from California State Polytechnic University, Pomona, CA, in 1973, and theM.S.E.E. degree from the University of Santa Clara, Santa Clara, CA, in 1977. Since hejoinedGTELenkurt, San Carlos, CA, in 1973, he hasbeen involved in the design of PCM repeaters. He is currently the Engineering Project Leader responsible for the development of PCM repeatered line equipment.