EEDG/CE 6301: Advanced Digital Logic

Mehrdad Nourani
Dept. of EE Univ. of Texas at Dallas

Session 01
Introduction

Motivational Discussion

Personal Products
PDA 2G/2.5G Cellular
PDAs

3D Cellular Phones

Video Phone

IP Phone

Cable Cable Modem Modem

Modem

DSL DSL Modem

Bluetooth Products

Digital Still Digital Camera Camcorder

PDA Camera

Network Still Camera

Home Networking

DAB Radio

Digital TV

Internet Audio Player

Digital Video Recorder/Server

iSTB

Technology in the Internet Age

Internet DSP & Analog
1 per Person MANY per Person!

PC Microprocessor

Minicomputer 1 per TTL/Logic Department

Mainframe Transistors 1960s 1970s 1 per Company 1980s 1990s 2000s 2010s
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Source: UTD Seminar by Gene Frantz

PC-Age vs. Internet Age

PC Age
Computer Focus

Non-Real Time Stationary Digital I/O P and Memory

Internet Age
Communication Focus

Source: UTD Seminar by Gene Frantz

Real Time Mobile Analog I/O DSP and Analog

System-on-Chip Integration
Many Devices Per Person Lowest Cost

Analog/RF Input/Output
Internet Interface

DSP + Analog

SOC Integration

Packet
Processor

SOC integration means more than integration of multiple IP digital cores. It means integration of functions that are implemented today in different technologies.
Source: UTD Seminar by Gene Frantz

Technology in the Internet Age

Moores Law is predicted to stagnate toward the end of the decade but SOC Integration has the potential to continue IC cost reduction and to perpetuate growth of Personal Internet Products.
Source: UTD Seminar by Gene Frantz
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Amazing Growth
1971: Intel 4004
2300 Transistors, 750KHz, 60000 Operations/sec $200

2000: DEC Alpha

15.2 Million Transistors, 700MHz,2 Billion Operations/sec $300

Gordon Moore (Intel founder):

If the car industry had been progressing at the rate the semiconductor industry has, today a Rolls-Royce would cost three dollars, could get half-a-million miles per gallon of gas, and would be cheaper to throw away than to pay for parking.

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What is Our Course About?

We need to have a good understanding of three concepts:

VLSI
Technology

Design
Technique

System
Methodology
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SoC: System on a Chip

Prediction: Many SoCs will have > 1 Billion gates How do you create million gate ASICs with same amount of resources? While
Decrease development time Increase functionality and performance Keep small design teams

Important Issues
Design Methodology (Design flow) Tools that support the Methodology IP reuse (Intellectual Property)

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Modeling Types Behavioral model

Explicit definition of mathematical relationship between input and output No implementation information It can exist at multiple levels of abstraction
Dataflow, procedural, state machines,

Structural model
A representation of a system in terms of interconnections (netlist) of a set of defined component Components can be described structurally or behaviorally
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The Y-Chart - Levels of Abstraction

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The Y-Chart - Terminology

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Example: Various Models of NAND Gate

O <= NOT ( A1 AND B1);

Behavioral Model: (Boolean Equation)

Structural Model: (Logic Gate)

Physical Model: (Transistors or Layout Mask)

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Importance of VLSI Test

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Importance of VLSI Testing Test cost will be dominant in this decade [ITRS01]

Cost: Cents/Transistor

New DFTs

ITRS

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Testing for Signal Integrity

Process Variations Shrink of Technology Increase of Frequency Physical Defects

Smaller Design Rules

Wave-Oriented Phenomena

There are only two kinds of designers: the ones who have signal integrity problems, and the ones who will.
[www.chipcenter.com]
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Fatal Problems on First Spin

Overall 61% of new ICs require at least one re-spin
45 40 35 30 25 20 15 10 5 0 Functional Signal Error Integrity Reliability High Power
Analog Tuning Clock Skew Mixed Signal IR Drop Others

[www.deepchip.com]

Firmware Error
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Importance of CAD

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Role of CAD Tools

CAD tools improve productivity Definition: A software program which assists in performing or automates a particular design function Major types: Schematic capture Analyzers/Simulators Synthesis
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Design Complexity and Productivity

Moore's Law
Design Productivity Time (Months)
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CAD Design Approaches

Goal of each CAD design flow methodology is to increase productivity of the design engineer Increasing the abstraction level of the design methodology and tools is one approach:

Gates/eng./month 1.5K - 6K Describe-synthesize

Abstraction Design Data

Design Sizes > 1M gates

300 - 600

Schematic Capture-simulate

100K - 500K gates

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Schematic Capture

wire

labels

Gate primitive
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Schematic Capture Editor Definition: An editor which can be used to create and display an interconnected set of graphic tokens. Graphic token types:
primitives (built-in) new models

Uses of schematics
simulation wiring

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Simulators

Definition: A program which models the response of a system to input stimuli. Types: deterministic and stochastic. Simulation is used to establish design correctness (70% of design time). A model underlies simulation.

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Factors Affecting Design Efficiency

Programming Method Computer Architecture Level of Abstraction Rule: Simulate at the highest level you can, and still get desired information. Rule-of-10: It will be 10 times more costly if the problem is discovered in the next level.

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Importance of HDL

48

Effect of Hardware Description Language (HDL)

The Complexity and Size of Digital Systems leads to Breadboards and prototypes which are too costly Software and hardware interactions which are difficult to analyze without prototypes or simulations Difficulty in communicating accurate design information Want to be able to target design to a new technology while using same descriptions or reuse parts of design (IP)
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Using HDL in Design

Source: VHDL (Z. Navabi - McGraw Hill)

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Using HDL in Simulation

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Using HDL in Synthesis Tools

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Using HDL in Synthesis & Optimization

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The Challenge of Optimization

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Coping with NP-hard Problems

In system level design we confront many NP-hard optimization problems. Simpler sub-problem based on dominate cost or special problem structure problems exhibit structure
optimal solutions found in reasonable time in practice

approximation algorithms heuristic solutions high density of good/reasonable solutions?

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Not a Solved Problem

NP-hard problems
almost always solved in suboptimal manner or for particular special cases

decomposed in suboptimal ways quality of solution changes as dominant costs change (relative costs are changing!) new effects and mapping problems crop up with new architectures, substrates

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Decomposition/Partitioning
Easier to solve
only worry about one problem at a time

Less computational work

smaller problem size

Abstraction hides important objectives

solving 2 problems optimally in sequence often not give optimal result of simultaneous solution Question: Like what?

58

Partitioning
Definition: Given a set of objects O={o1,,on} determine a partition P={p1,,pm} such that p1UUpm=O, pipj= for all i,j, i#j and the cost determined by an objective function f(P) is minimal. NP-complete for general graphs/problems Many heuristics/attacks System designer must do two things:
1. Selecting a set of system components (allocation) 2. Partitioning the systems functionality among those components (partitioning).

Partitioning Issues:
Abstraction level Granularity Estimation

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Partitioning Heuristic
Greedy, iterative
pick one partition that decreases cost (i.e. a user defined metric) and move it repeat

Small amount of:

look past moves that make locally worse randomization

Estimation Metrics:
Fast (usually analytical) estimate of area,time,power,etc. Fidelity of estimation

Quality Metrics:
Hardware/software cost, performance, benchmarking
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Design Space

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Concept of Design Space

There exists no perfect/optimal algorithm for the design of complicated systems The designer moves around in a space The coordinates of the space are optimization criterion: speed, chip area, cost, power, pins, etc. Motion in the space involves tradeoffs

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A 3-Dimensional Design Space

a design

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Example: Speed-Area Tradeoff

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Example: Workstation Cost/Speed Tradeoff

Cost ($)
(C2,S2)
C1 $ 5K

S1 C2

50 MIPS $ 30K
500 MIPS $ 10K 280 MIPS

(C3,S3) (C1,S1)

S2 C3 S3

Speed (MIPS)
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