Data sheet acquired from Harris Semiconductor SCHS167A

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

High Speed CMOS Logic Octal Buffer/Line Drivers, Three-State
Description
The HC240 and HCT240 are inverting three-state buffers having two active-low output enables. The CD74HC241, HCT241, HC244 and HCT244 are non-inverting threestate buffers that differ only in that the 241 has one activehigh and one active-low output enable, and the 244 has two active-low output enables. All three types have identical pinouts.

November 1997 - Revised May 2000

Features
HC/HCT240 Inverting

[ /Title (CD74 HC240 , CD74 HCT24 0, CD74 HC241 , CD74 HCT24 1, CD74 HC244 , CD74

HC/HCT241 Non-Inverting HC/HCT244 Non-Inverting Typical Propagation Delay = 8ns at VCC = 5V, CL = 15pF, TA = 25oC for HC240 Three-State Outputs Buffered Inputs High-Current Bus Driver Outputs Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH

Ordering Information
PART NUMBER CD54HC240F3A CD74HC240E CD74HC240M CD54HCT240F3A CD74HCT240E CD74HCT240M CD74HC241E CD54HCT241F3A CD74HCT241E CD74HCT241M CD54HC244F CD54HC244F3A CD74HC244E CD74HC244M CD54HCT244F CD54HCT244F3A CD74HCT244E CD74HCT244M NOTES: 1. When ordering, use the entire part number. Add the sufx 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 20 Ld CERDIP 20 Ld PDIP 20 Ld SOIC 20 Ld CERDIP 20 Ld PDIP 20 Ld SOIC 20 Ld PDIP 20 Ld CERDIP 20 Ld PDIP 20 Ld SOIC 20 Ld CERDIP 20 Ld CERDIP 20 Ld PDIP 20 Ld SOIC 20 Ld CERDIP 20 Ld CERDIP 20 Ld PDIP 20 Ld SOIC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

2000, Texas Instruments Incorporated

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

Pinout
CD54HC240, CD54HCT240, CD54HCT241, CD54HC244, CD54HCT244 (CERDIP) CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244 (PDIP, SOIC) TOP VIEW
240 1OE 1A0 2Y3 1A1 2Y2 1A2 2Y1 1A3 2Y0 GND 241 244 1OE 1A0 2Y3 1A1 2Y2 1A2 2Y1 1A3 2Y0 1 2 3 4 5 6 7 8 9 241 244 20 VCC 18 1Y0 17 2A3 16 1Y1 15 2A2 14 1Y2 13 2A1 12 1Y3 11 2A0 240 VCC 1Y0 2A3 1Y1 2A2 1Y2 2A1 1Y3 2A0

19 2OE (241) 2OE (240, 244)

GND 10

Functional Diagram
241 AND 244 240 1A0 1A1 1A2 1A3 2A0 2A1 2A2 2 4 6 8 11 13 15 18 16 14 12 9 7 5 3 1 1OE 1OE 2OE 2OE 19 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3

240 17 AND 2A3 244 241

VCC = 20 GND = 10

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . . . . . . 35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .70mA

Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)

Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -6 -7.8 0.02 0.02 0.02 6 7.8 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 160 V V V V V V V V V V V V V V V V A A SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

DC Electrical Specications
(Continued) TEST CONDITIONS PARAMETER Three-State Leakage Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) Three-State Leakage Current NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC VCC to GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL IOZ VI (V) VIL or VIH IO (mA) VCC (V) 6 MIN 25oC TYP MAX 0.5 -40oC TO 85oC MIN MAX 0.5 -55oC TO 125oC MIN MAX 10 UNITS A

-6

4.5

3.98

3.84

3.7

0.02

4.5

0.1

0.1

0.1

4.5

0.26

0.33

0.4

0 0 -

5.5 5.5 4.5 to 5.5

100

0.1 8 360

1 80 450

1 160 490

A A A

IOZ

VIL or VIH

5.5

0.5

10

HCT Input Loading Table

INPUT HCT240 nA0-A3 1OE 2OE HCT241 nA0-A3 1OE 2OE HCT244 nA0-A3 1OE 2OE 0.7 0.7 0.7 0.7 0.7 1.5 1.5 0.7 0.7 UNIT LOADS

NOTE: Unit Load is ICC limit specied in DC Electrical Specications table, e.g., 360A max at 25oC.

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

Switching Specications
CL = 50pF, Input tr, tf = 6ns TEST CONDITIONS 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN TYP MAX -55oC TO 125oC MIN TYP MAX UNITS

PARAMETER HC TYPES Propagation Delay Data to Outputs HC240

SYMBOL

tPLH, tPHL

CL = 50pF 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 5 6 10 8 9 9 12 100 20 17 110 22 19 110 22 19 150 30 26 60 12 10 10 20 125 25 21 140 28 24 140 28 24 190 38 33 75 15 13 10 20 150 30 26 165 33 28 165 33 28 225 45 38 90 18 15 10 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF

Data to Outputs HC241

tPLH, tPHL

CL = 50pF

Data to Outputs HC244

tPLH, tPHL

CL = 50pF

Output Enable and Disable Time

tTHL, tTLH

CL = 50pF

Output Transition Time

tTLH, tTHL

CL = 50pF

2 4.5 6

Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 5, 6) HC240 HC241 HC244 HCT TYPES Propagation Delay Data to Outputs HCT240 Data to Outputs HCT241 Data to Outputs HCT244

CI CO CPD

CL = 50pF CL = 50pF CL = 15pF

5 5 5

38 34 46

pF pF pF

tPHL, tPLH

CL = 50pF CL = 15pF

4.5 5 4.5 5 4.5 5

9 10 10

22 25 25 -

28 31 31 -

33 38 38 -

ns ns ns ns ns ns

tPHL, tPLH

CL = 50pF CL = 15pF

tPHL, tPLH

CL = 50pF CL = 15pF

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

Switching Specications
CL = 50pF, Input tr, tf = 6ns (Continued) TEST CONDITIONS CL = 50pF CL = 50pF CL = 50pF 25oC VCC (V) 4.5 4.5 MIN 10 TYP MAX 30 12 10 -40oC TO 85oC MIN TYP MAX 38 15 10 -55oC TO 125oC MIN TYP MAX UNITS 45 18 10 ns ns pF

PARAMETER Output Enable and Disable Times Output Transition Time Input Capacitance Power Dissipation Capacitance (Notes 5, 6)) HCT240 HCT241 HCT244 NOTES:

SYMBOL tTLH, tTHL tTHL, tTLH CI CPD

5 5 5

40 38 40

pF pF pF

5. CPD is used to determine the dynamic power consumption, per channel. 6. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Test Circuits and Waveforms

tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC INPUT GND tTHL tr = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% tf = 6ns 3V

GND

tTHL

INVERTING OUTPUT

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

6ns OUTPUT DISABLE 90% 50% 10% tPZL 50% 10% tPHZ OUTPUT HIGH TO OFF OUTPUTS ENABLED 90% 50% OUTPUTS DISABLED OUTPUTS ENABLED tPZH 6ns VCC GND

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tr OUTPUT DISABLE 6ns tf 2.7 1.3 tPLZ OUTPUT LOW TO OFF tPHZ OUTPUT HIGH TO OFF OUTPUTS ENABLED 90% 6ns 3V 0.3 tPZL GND

tPLZ OUTPUT LOW TO OFF

10% tPZH

1.3V

1.3V OUTPUTS DISABLED OUTPUTS ENABLED

FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM

FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM

CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244

Test Circuits and Waveforms

(Continued)

OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE

IC WITH THREESTATE OUTPUT

OUTPUT RL = 1k CL 50pF

VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH

NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1k to VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

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Copyright 2000, Texas Instruments Incorporated