1

High Step-up DC/DC Topology and MPPT Algorithm for use with a Thermoelectric Generator
Ian Laird, Student Member, IEEE, and Dylan D.C. Lu, Senior Member, IEEE,

AbstractA thermoelectric generator (TEG) is a low voltage, high current DC power source with a linear V-I characteristic and therefore it is desirable to create a power converter with a topology and control method suited to these attributes. Due to the TEGs low voltage, a topology that produces a high step-up gain for a moderate duty cycle is required to reduce voltage and current stresses within the converter. The linear V-I characteristic produces a P-I characteristic with a atter peak relative to other sources. This can result in large operating point variations while performing maximum power point tracking (MPPT) thus an algorithm with low steady state error is desired. This paper presents a novel high step-up DC/DC converter topology operating with a fractional short-circuit MPPT algorithm for use with a 4.2V, 3.4A (for matched load at T = 270 C) TEG module and a converter output of 180V. Compared to existing high step-up DC/DC converters, the proposed converter achieves higher gain with similar component count. Experimental results are reported to conrm the converter analysis and better performance of the short-circuit MPPT algorithm over the Perturb and Observe (P&O) algorithm. Index TermsThermoelectric energy conversion, DC-DC power conversion, Tracking.

I. I NTRODUCTION EVELOPING sustainable, non-polluting electrical energy is a crucial part of ensuring that the increasing global energy demand is met without affecting the environment in a detrimental way. In order to achieve this, many different energy sources and conversion devices are being used in applications such as centralised generation, small distributed networks and system energy recovery. One conversion device that is showing potential in waste heat recovery applications is the thermoelectric generator (TEG). A TEG is a solid state device that converts a temperature gradient directly into electricity. It consists of a large number of thermocouples that are connected electrically in series and thermally in parallel. The thermocouples are junctions of heavily doped semiconductors. During operation, heat is applied to one junction while it is removed from the other. This causes electrons in the n-type leg and holes in the p-type leg to drift away from the hot junction towards the cold one.
I. Laird and D. Lu are with the School of Electrical and Information Engineering, University of Sydney, NSW, 2006 Australia This project was sponsored by an Australian Postgraduate Award (APA) and the Norman I. Price scholarship Corresponding author contact: ian.laird@sydney.edu.au Copyright c 2013 IEEE. Published in the IEEE Transactions on Power Electronics, Vol. 28, No. 7, pp. 3147-3157, July 2013. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE.

The resulting charge separation produces a voltage across the thermocouple. This is known as the Seebeck voltage and its magnitude is proportional to the temperature difference of the hot and cold junctions [1]. If a load is connected across the thermocouple, a DC current ows. Over the years TEGs have been developed that range from experimental large scale 5 kW units [2] right down to micro-watt systems [3], [4]. At present, commercially and readily available TEGs, from companies such as Kryotherm, Thermonamic and Hi-Z technology, have power levels ranging from 0.5 to 20 W [5], [6]. The V-I characteristic of these modules are linear with short-circuit current values that tend to be of similar or greater magnitude than the open-circuit voltage (e.g. for the HZ-20 module shown in [7], VOC 5V and ISC 16A). Thus these modules are generally considered to be low voltage, high current devices. Applications for these commercial modules have been limited to niche products, however there has been research into utilising TEGs in small scale solar energy systems [8][10]. Ultimately the goal of these projects is to make thermoelectrics a viable part of a DC micro-grid based system much like photovoltaics are now. DC micro-grids tend to operate at 120 to 400 V [11], [12] therefore a converter with a high step-up gain is required in order for a TEG module to interfaced to such a system. Step-up converters are theoretically able to produce innitely high conversion ratios, however in reality the maximum gain is limited by various circuit imperfections such as parasitic components and switch commutation times. Parasitic components degrade not only the gain but also the efciency of the converter. They cause the maximum gain to occur at duty ratios of typically 80 to 90% and a signicant drop off in efciency as the duty ratio moves towards and beyond this point. Switch commutation times place limits on the maximum switching frequency and duty cycle ratio (and therefore the voltage gain) of the converter [13]. Whilst switching frequency can only be improved by using faster switching components, by implementing a different topology the required gain can be achieved with a much smaller duty cycle ratio. As well as this, there are added benets to using lower duty cycles. For example, operating with an extreme duty cycle will mean the inductor current will fall rapidly during the diodes conduction period and hence produce a large electromagnetic interference (EMI) emission. Also the short conduction time will mean larger peak currents for the output diodes in order to produce the same average current. This places a larger stress on the diode similar to that experienced by the switching transistor in a high step-down converter [14]. There is also the chance

that the diode might malfunction as there might not be enough time to fully turn both on and off during its short conduction period [15]. Previous attempts at designing DC/DC converter topologies specically for TEGs have focused on driver and starter circuits that ensure that the converter can operate at very low input voltage. [16] proposed a starter circuit that utilised a triple winding transformer and a nominally-on JFET allowing operation for input voltages as low as 0.3 V. However the converter overall only produced an output of 5 V. Other starter circuits that used a mechanical (reed) switch or a tunnel diode in place of the JFET were analysed in [17]. In [18] a converter based on a charge pump with a variable number of stages was used with a TEG operating on the micro-power scale and produced an output of 1.5 V. A converter that can be used for either a photovoltaic (PV) cell or a TEG is presented in [19] which can operate on an input voltage of 40 mV. As a result of this work there are now readily available low input voltage converters such as the LM2623. While such converters serve their purpose, they are not suited to interfacing a TEG to a high voltage DC bus as is the intention of this paper. There have been various techniques used to create high stepup converters that maintain high efciency. Converters utilising repeated component networks, such as multiplier capacitors or voltage doublers, are described in [20][23]. The advantage of this method is that it usually avoids magnetic components and their associated problems such as the high voltage stresses induced by the leakage inductance of a transformer. The drawback however is that as larger gains are needed more components are required. Typically a gain of N requires N capacitors. Another method, shown in [15], [24], involves using switching blocks either in addition to or replacing inductors and capacitors in a range of classical converters (such as the buck or boost). The advantage of these blocks are that they store less energy in their electric/magnetic elds and thus are smaller, lighter and cheaper than an equivalent transformer. However they do not produce gains as high as transformer based converters. Transformer or coupled inductor converters are well established with well known topologies such as the forward, yback and other topologies described in [25][29]. The voltage gain of standard coupled inductor converters has been further increased by connecting capacitors to the coupled inductor windings in congurations known as voltage multipliers or voltage lifters as shown in [30][36]. Despite these converters experiencing problems due to the leakage of the coupled-inductor, the addition of a voltage multiplier greatly increases the gain whilst only adding a small number of extra components. This makes it a suitable choice for the low to medium power levels of the TEG applications and as a result, a novel topology based on the coupled inductor, voltage multiplier converter conguration will be presented in this paper. Aside from the converter topology, TEGs require a suitable control algorithm to achieve maximum power point tracking (MPPT) of the device. Similar to photovoltaics (PV), there is an operating point that causes a TEG to deliver maximum power. A comprehensive survey of MPPT methods has been outlined in [37] but this was focused on PV. Previous attempts

VC2 + C2 Vi Lm + v1(t) N1

N2 nv1(t) + + VC1

C1

(a) On state
N1 + v1(t) Vi Lm VC2 + C1 VC1 + N2 + nv1(t) C2 Co RL

+ Vo

(b) Off state Fig. 1. Converter 8 switching states

D1 D2 N1 + v1(t) Lm Vi S C1 VC1 + N2 + nv1(t) C2

VC2 + D3 + Vo

Co

RL

Fig. 2.

Proposed high step-up gain converter

at implementing an MPPT with a TEG device have involved using either the perturb and observe [38], [39], incremental conductance [40] or a modied version of open-circuit voltage [41], [42]. This paper implements the fractional short circuit current method MPPT algorithm in the proposed converter due to its low steady state error. The paper is organised as follows. The proposed converter is introduced and its operation explained in Section II. The converter is analysed in terms of voltage gain and efciency in Section III. MPPT algorithm suitability is discussed in Section IV. The converter is built and tested in Section V. Finally conclusions are drawn in Section VI. II. P ROPOSED CONVERTER AND P RINCIPLES OF
OPERATION

As mentioned in section I, the proposed topology is based on the coupled-inductor, voltage multiplier principle. The most basic implementation of this principle, of which an interleaved version can be seen in [32], involves a capacitor being charged by a winding of the coupled-inductor when the switch is on, and then discharging in series with both windings into the load such that the voltages of all three components combine together to boost the output voltage. This principle can be extended such to utilise multiple capacitors such that they

CD 1

CD 1

D1 Ii RS VS + Vi Lm Q CDS N1 VC1 + D2 N2 Lk

VC2 + D3

D1 Io + RL Vo VS Ii RS + Vi Lm Q CDS N1 VC1 + D2 N2 Lk

VC2 + D3

Io + RL Vo

(a) Stage 1 (T0 - T1 )

CD 1 CD 1

(b) Stage 2 (T1 - T2 )

D1 Ii RS VS + Vi Lm Q CDS N1 VC1 + D2 N2 Lk

VC2 + D3

D1 Io + RL Vo VS Ii RS + Vi Lm Q CDS N1 VC1 + D2 N2 Lk

VC2 + D3

Io + RL Vo

(c) Stage 3 (T2 - T3 )

CD 1 CD 1

(d) Stage 4 (T3 - T4 )

D1 Ii RS VS + Vi Lm Q CDS N1 VC1 + D2 N2 Lk

VC2 + D3

D1 Io + RL Vo VS Ii RS + Vi Lm Q CDS N1 VC1 + D2 N2 Lk

VC2 + D3

Io + RL Vo

(e) Stage 5 (T4 - T5 )

CD 1 CD 1

(f) Stage 6 (T5 - T6 )

D1 Ii RS VS + Vi Lm Q CDS N1 VC1 + D2 N2 Lk

VC2 + D3

D1 Io + RL Vo VS Ii RS + Vi Lm Q CDS N1 VC1 + D2 N2 Lk

VC2 + D3

Io + RL Vo

(g) Stage 7 (T6 - T7 ) Fig. 3. Proposed converter stages of operation for mode 2

(h) Stage 8 (T7 - T8 )

charge independently during the switch on stage and discharge in series during the off stage. However the components can also be arranged so that during the on stage one capacitor, along with the windings, discharges into the other capacitor and thus boost it voltage to an even higher voltage. During the off stage, the high voltage capacitor can discharge, in series with the windings, into the load whilst the other capacitor is recharged. In order to realise this concept, equivalent circuits representing both the on and off states of the converter were developed for various arrangements of the components in order to nd a combination that resulted in a desirable gain function. The on and off stage equivalent circuits that resulted from the design process, and that make up the main on and off stages of this papers proposed converter, are shown in Fig. 1. During the on state C2 is placed in series with both the primary and secondary windings so that discharges into and hence boosts the voltage of C1 . During the off stage, C1 discharges in series with both windings into the load whilst C2 is recharged by the

higher voltage secondary winding. To complete the design, switches and diodes were added so that these switching states could be realised. The resulting converter is shown in Fig. 2. The circuit itself operates in one of 4 different modes depending on the circuit parameters. The main difference among the 4 different modes is the sequence and duration of conduction of the three diodes D1 , D2 and D3 . Mode 1 is complete continuous conduction mode (CCM) where the switch and diode D1 conduct for a portion of the switching cycle followed by diodes D2 and D3 conducting for the remainder. Mode 2 is the same as Mode 1 except that the current in D1 reduces to zero before the active switch is turned off. Mode 3 begins as Mode 1 does however D2 and D3 both simultaneously reduce to zero before the switch turns on thus putting the converter in discontinuous conduction mode (DCM). In Mode 4, all three diodes D1 , D2 and D3 reduce to zero within their operation intervals respectively. Therefore Mode 1 has 2 main switching stages, Modes 2 and 3 have 3 stages, and Mode 4 has 4 stages. This section will focus on

the main and transitional operating stages of Mode 2. In order to show the switching stages of the proposed converter it is modelled as follows. The coupled inductor is modelled as an ideal transformer with parallel magnetising and secondary series leakage inductances. The switch and diodes are considered to be ideal, however the switch and diode D1 both have parasitic capacitances placed in parallel with them. Capacitors Ci , Co , C1 and C2 are all assumed to be large enough to maintain constant voltages over the entire switching period. Fig. 3 shows the switching stage diagrams while Fig. 4 shows the key waveforms over a switching period. Below is a description of the switching stages. Prior to Stage 1 diodes D2 and D3 are conducting. Stage 1 [T0 ,T1 ] (Fig. 3a): Switch Q turns on at T0 and its parasitic capacitance CDS begins to discharge via the internal resistance of the switch. As a result diode D3 will stop conducting and its blocking voltage will start to rise. Parasitic capacitance CD1 will also discharge as a result of the voltage on CDS dropping. Leakage inductance Lk discharges through D2 . Stage 2 [T1 ,T2 ] (Fig. 3b): At time T1 CDS is fully discharged. As a result CD1 stops discharging and holds a constant voltage for the duration of the stage. Lk continues to discharge through D2 . Stage 3 [T2 ,T3 ] (Fig. 3c): At time T2 Lk has fully discharged and D2 turns off. Current now begins to ow through Lk in the reverse direction causing it to charge but with reverse polarity. This current also causes CD1 to discharge. Stage 4 [T3 ,T4 ] (Fig. 3d): At time T3 CD1 has fully discharged and D1 is turned on. Energy is transferred from the Vi , Lk and C2 into Lm and C1 , thus causing the current in Lm to increase and that in Lk to decrease. The overall current slope through L1 can either positive or negative as it is the sum of the magnetising and reected leakage currents. Stage 5 [T4 ,T5 ] (Fig. 3e): At time T4 the current in Lk has returned to zero and D1 naturally turns off. Lm continues to charge from Vi and thus its current increases. Stage 6 [T5 ,T6 ] (Fig. 3f): Switch Q turns off at T5 . CDS begins to charge. This in turn causes CD1 to also charge and as a result the blocking voltages of D2 and D3 begin to reduce. The current draw of CD1 also causes Lk to charge. Stage 7 [T6 ,T7 ] (Fig. 3g): At time T6 the voltage across D2 is reduced to zero and it begins to conduct. The blocking across D3 continues to decrease. Stage 8 [T7 ,T8 ] (Fig. 3h): At time T7 the voltage across D3 is reduced to zero and it begins to conduct. Lm , Lk and C1 discharge their energy to C2 and the load. III. C ONVERTER ANALYSIS A. Converter gain In order to determine the converter gain only Stages 4, 5 and 8, where there is signicant energy transfer between the source, energy storage elements and the load, as shown in Fig. 3d, 3e and 3h, are required. Since Lk , CDS and CD1 contribute signicantly to the switch transitions but not the energy transfer they are ignored. The analysis model is shown in Fig. 5. Note that with the absence of Lk , the voltage across Lm for Stage 4 can also be written in two different ways:

vGS(t)

t iDS(t) vDS(t)

t vD1(t) iD1(t) t vD2(t) iD2(t) t iD3(t) vD3(t) t v2(t) t v1(t)

i1(t)

im(t)

t i2(t) T 0 T 1 T2 T 3
Fig. 4.

T4

T5 T6 T7

T8

Switching waveforms of proposed converter for mode 2

vD1(t) + D1 Ii RS Vs + Vi N1 + v1(t) Lm Q vD2(t) + VC1 + + vDS(t) VC2 +

D2

N2 + nv1(t)

D3 vD3(t) +

Io + RL Vo

Fig. 5.

Circuit model for gain analysis

v1 (t) = Vi

or v1 (t) =

VC 1 VC 2 Vi n (1)

TABLE I T OPOLOGY COMPARISON Parameter Capacitors Diodes Gain [30] 3 3

n+2 1D

[31] 3 3
nD +2 1D

[34] 4 4
n(2D )+2 1D

Proposed 3 3
(n1)D +n+2 1D

VC 1 = (n + 1) Vi + VC 2

A similar relationship is also found in Stage 8 as shown:

50

v1 (t) = Vi Vo + VC 1 + VC 2

or

v1 (t) =

VC 2 n (2)

45
40 35 30

n (Vi Vo + VC 1 ) + (n + 1) VC 2 = 0

Vo 25 Vi
20
15 10

Noting that the voltage across Lm during Stage 5 is Vi , the volt-second balance for these three stages is:

[30] [31] [34] Proposed

Vi DT + (Vi Vo + VC 1 + VC 2 ) (1 D) T = 0 Solving (1), (2) and (3) gives the following relations: Vo (n 1) D + n + 2 = Vi 1D VC 1 n+1D = Vi 1D VC 2 nD = Vi 1D

(3)
0 0 0.2 0.4 0.6 0.8 1

(4)

Fig. 6.

Gain comparison of various topologies (n = 5)

(5)

B. Losses and efciency analysis In this section the estimated conduction and switching losses of the converter are modelled and analysed in terms of their effect on the converter efciency. To model the average transformer and semiconductor conduction losses the circuit model shown in Fig. 7 has been used. To simplify the analysis only Mode 1 operation of the converter and thus only the main on and off stages (Fig. 3d and 3h) are considered. All voltages and currents are assumed to be DC for the duration of a switching stage however they may have different values for different stages. The magnetising inductance and capacitors are assumed to have constant current and voltages respectively over the entire switching period. Performing an amp-second on Co gives: Io D + I1of f Io (1 D) = 0 I1of f = Io 1D (11)

(6)

From this we can determine the blocking voltages experienced by the switching devices: VDS = Vo VC 1 VC 2 = 1 Vi 1D (7)

VD1 = Vo Vi VC 2 =

n+1 Vi 1D

(8)

VD 2 = VC 1 Vi =

n Vi 1D n+1 = Vi 1D

(9)

VD3 = Vo Vi VC 2

(10)
ID1 VD1 RD1 nI2 N1 + V1 ILm ICi Q I1 R1 RDS D1 VD2 RD2 Ii RS + Vi IC1 D2 ID2 N2 I2 R2

Table I and Fig. 6 show the gain of the proposed converter compared to a range of other converters that use the same or similar component sets. All converters use a single coupled inductor and a single active switch. The input capacitor is ignored in the total capacitor count as it is common to all the converters. Also only CCM operation is considered to allow for easy comparison between the converters. As can be seen the proposed converter compares favourably with the other converters. Compared to [34] its gain is smaller for duty cycle values of less than approximately 0.5, however it is greater for those above and it achieved with fewer components.

IC2 VC2 + ID3 VD3 RD3 D3 RL ICo Io + Vo

VC1 + IDS

+ nV1

VS

Fig. 7.

Circuit model for loss and efciency analysis

Vo =

DRL (((n 1) D + n + 2) Vi (1 D) (VD1 + VD2 + VD3 ))

(n(1+D )+1)2 RDS 1D

(n(1+D )+D )2 1D

(21)

+ D R1 + (1 + 3D) R2 + (1 D) (RD1 + DRL ) + D (RD2 + RD3 )

Performing an amp-second balance on C1 and using (11) gives: I2on D I1of f (1 D) = 0 Io (12) I2on = D Using (11) and (12) on the amp-balance on C2 produces: I2on D + I2of f I1of f (1 D) = 0 2Io (13) 1D And the amp-second balance on Ci using (11) and (12) is: I2of f = (Ii I1on + I2on ) D + Ii I1of f (1 D) = 0 Ii 2Io I1on = D (14) Since the average current through Lm is constant over the period therefore: I1on + nI2on = I1of f + nI2of f Io Io 2Io Ii 2Io +n = +n D D 1D 1D (n 1) D + n + 2 Io (15) Ii = 1D As before, while Q and D1 are on V1 can be dened in the following ways: V1on = Vi (R1 + RDS ) I1on + RDS I2on (16)

120 Vi=5V, VD1=VD2=VD3=0.6V, RDS=R1=0.025, R2=0.5, RD1=RD2=RD3=0.1, RL=2.25k 100

80

aaaaa

Vo Vi

60

40

n=5 n=10 n=15 n=20

20

0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Fig. 8. Effect of turns ratio on the voltage gain when accounting for transformer and semiconductor conduction losses
1 0.9 0.8 0.7 0.6

0.5
0.4

n=5 n=10 n=15 n=20

0.3
0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Vi=5V, VD1=VD2=VD3=0.6V, RDS=R1=0.025, R2=0.5, RD1=RD2=RD3=0.1, RL=2.25k, tc,on=40ns, tc,off =125ns, fs=100kHz

Fig. 9.

Effect of turns ratio on converter efciency

VC 1 VC 2 + VD1 R1 I1on (R2 + RD1 ) I2on V1on = n+1 (17) Similarly when D2 and D3 are off V1 can be dened in the following ways: V1of f = RD2 I1of f (R2 + RD2 ) I2of f VC 2 VD2 (18) n

Vo Using Io = R and substituting and solving (11) to (20) L produces (21). Using (21) the output power of the converter taking all the conduction losses into consideration can be given by Pocond = Vo Io . However for calculating the converter efciency both the conduction and switching losses need to be considered and thus it can be written as:

Vi Vo + VC 1 VD3 (R1 + RD3 ) I1of f + R2 I2of f V1of f = n+1 n+1 (19) Using (16) and (17) the volt-second on Lm is: VC 2 + VD2 RD2 I1of f + (R2 + RD2 ) I2of f (1 D) n = (Vi (R1 + RDS ) I1on + RDS I2on ) D (20)

= where PQ loss =

Pocond PQ loss Pi

(22)

1 VDSof f IDSon + VD1of f ID1on 6 + VD2of f ID2on +VD3of f ID3on fs (tc,on + tc,of f )

Where VDxof f and IDxon are respectively the blocking voltages and conduction currents that the switch and diodes

TABLE II P ROPOSED CONVERTER COMPONENTS AND PARAMETERS Component/Parameter f Q D1 , D2 , D3 n Lm Core Ci Co , C1 , C2 Value 100 kHz IPB009N03L MBR40250 7.5 25 H 32-580-47 1000 F 22 F

1 Pmax 0.875 0.75 0.625

V, 0.5 VTEG P VMPP

0.375 0.25 0.125 0

VPV IPV

PV V-I TEG V-I PV P-I TEG P-I

ITEG

are subjected to during the switching period, tc,on and tc,of f are the turn-on and turn-off transition times, and fs is the switching frequency. Equations (21) and (22) are plotted for different values of the turns ratio n in Fig. 8 and 9 respectively. As can be seen, as the turns ratio increases the voltage gain function becomes increasingly linear, resulting in higher gains at lower duty cycle values and therefore producing a more even spread of voltage and current stress across the components and allowing for more precise gain control. The overall efciency however decreases over the entire operation range with this increase in turns ratio thus a trade-off must be made between gain, desired operating point and efciency. IV. MPPT ALGORITHM SUITABILITY FOR A TEG The purpose of maximum power point tracking (MPPT) is to move the electrical operating point of a circuit so that the input power source operates at a voltage and current that will cause it to transfer maximum power to the load regardless of whether the load or the input power source itself is changing due to external factors. For the case of TEGs, power output variations are the result of changes in the load current and/or the temperature difference applied across the TEG itself. Research into using MPPT with PV is well established with a wide range of algorithms available to choose from. The three most prevalent methods are the perturb and observe (P&O), incremental conductance (INC) and the fractional open/short-circuit voltage/current (Frac. VOC /ISC ) more commonly known as constant voltage/current (CV/CI). Both P&O and INC are hill-climbing based methods. This means that they operate by measuring the power at a particular operating point, step to a new point and measure the power there. If the power has increased then the algorithm will keep stepping the operating point in the same direction. However it will step in the reverse direction if the power has decreased. The difference between the P&O and INC algorithms is that the P&O, upon reaching the maximum power point (MPP), will oscillate around it as, in its purest form, the algorithm has no condition to stop the stepping. The INC algorithm has a condition that determines if the MPP has been reached. However, in practice this condition is extended to a range around the MPP as it is highly unlikely that a step will land directly on the MPP. Thus the INC algorithm often stops at a point near the MPP rather than exactly on it. The Frac. VOC /ISC method uses the observation that the relationship between the MPP voltage/current and the

0.125

0.25

0.375

IMPP 0.5

0.625

0.75

0.875

Fig. 10. Characteristic comparison of a PV and TEG operating point oscillation

open/short-circuit voltage/current for a PV module is approximately given by VM P P = k1 VOC and IM P P = k2 ISC respectively. Therefore the MPP can be tracked by simply measuring VOC or ISC and calculating the desired operating point. The drawback of this method is that k1 can vary between 0.71 and 0.78 and k2 between 0.78 and 0.92 from module to module and thus must be determined prior to use in the algorithm [37]. Also since the relationship is not actually linear, choosing a particular k value can result in varying levels of steady-state error under changing conditions. Another disadvantage is that in order to operate, the algorithm must periodically stop tracking and measure VOC or ISC and, in doing so, briey reduces the output power to zero. The number of these power outages can be reduced by increasing the length of time between these measurements however this will reduce the responsiveness of the converter to changes in the operating conditions. As a result the Frac. VOC /ISC method is used less frequently with PV modules than the P&O or INC. However it is different for TEGs. Plotting the V-I characteristic of a TEG reveals a linear characteristic that can be modelled by a voltage source in series with a resistor [7]. For this model the voltage source represents the opencircuit voltage of the TEG, which is directly proportional to the temperature difference applied to it, while the resistor is simply the electrical resistance of the TEG. The linear V-I characteristic results in a parabolic P-I characteristic with its maximum located at exactly half of the short circuit current. This is equivalent to half of the open circuit voltage and thus k1 = k2 = 0.5. Unlike PV modules this ratio does not change regardless of operating conditions. It should be noted that the TEG resistance varies slightly with temperature however this only changes the gradient of the V-I characteristic and not its linear nature. Therefore the advantage of this method over a hill-climbing algorithm is the reduced oscillations in the control signal at steady state. This is of particular importance when considering the performance of an MPPT algorithm for use with a TEG. The V-I and P-I characteristics of a PV and TEG that deliver the same maximum power are shown in Fig. 10. As can be

60

50

40

Vo 30 Vi
20

Experimental Ideal

the value of VOC or ISC and thus can be tracked without re-determination of the operation set point. Also, since the converter only requires the measurement of one parameter, the tracking of load changes can be faster than hill-climbing that requires the measurement of two. Changes in temperature will require the re-measurement of VOC or ISC . However, due to the typical thermal capacitance of a TEG, the rate of change of these values is relatively slow compared to the tracking speed and thus longer intervals between measurements does not signicantly degrade the dynamic response of the algorithm. V. E XPERIMENTAL RESULTS An experimental version of the proposed converter was designed and built for use with a TEP1-12656-0.6 TEG device. The component values are shown in table II. The converter was connected to a 4.2V source to simulate the datasheet specied MPP voltage for a TEP1-12656-0.6 running under the maximum temperature differential (T = 270 C). Similarly a xed output load of 2.655k was connected so that a converter output of 180V resulted in an input current of 3.4A matching the specied MPP current. Fig. 11 shows the voltage gain as a function of duty cycle under these conditions. Replacing the xed load with a variable one and regulating the output to 180V gave the efciency of the converter as a function of the output power as shown in Fig. 12. Overall the European efciency is calculated to be 88.3%. Fig. 13a, 13b, 13c show the switch voltage and L1 and L2 currents respectively for 4.2V input and 180V output. It is worth noting that the switch blocking voltage is only 15V thus allowing the use of a low voltage MOSFET with a low RDSon . Fig. 13d displays the voltages on C1 , C2 and Co which are constant will the exception of a spike on C1 when the leakage inductance rapidly charges during turn on. To test the MPPT steady state performance both a P&O and Frac. ISC algorithm were implemented on a PIC18F4431. The converter was connected to a TEP1-12656-0.6 operating at T = 75 C and T = 175 C. Various loads over the range of 0.5 - 3.5 k were used to vary the converter output voltage that was required to achieve maximum power transfer. Each algorithm was run and the steady state performances are shown in Fig. 14. Fig. 14a and 14b show the converters average input power delivered by the TEG for each operating temperature. As can be seen, running under the P&O algorithm the power delivered has a large variation due to the oscillating nature of the algorithm. The Frac. short-circuit algorithm however delivers a more constant level of power despite some constant error. The error occurs because the algorithm does not track the actual MPP but rather a calculated set-point current whilst the lower power variation is due to the tracking of only the input current as opposed to both the input voltage and current. In addition the steadier input power produced by the Frac. ISC results in a steadier operation voltage for the TEG, as shown in Fig. 14c and 14d, which in turn produces a steadier voltage at the output of the converter as shown in Fig. 14e and 14f. VI. C ONCLUSION In conclusion this paper has presented a novel high stepup converter that utilises the coupled-inductor and voltage

10

0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Fig. 11. Voltage gain versus duty cycle for proposed converter operating with Vi = 4.2V and RL = 2.655k
1 0.95 0.9 0.85 0.8

0.75
0.7 0.65 0.6 0.55 0.5 0 2 4 6 8 10 12 14

Po (W)

Fig. 12. Efciency versus output power for proposed converter operating with Vi = 4.2V and Vo = 180V

seen, for the same variation in output power, the oscillations around the MPP are much larger for a TEG than a PV. If the TEG is connected to the input of a single stage converter with no intermediate energy storage buffer, any variations in the TEG voltage due to MPP oscillations will also be reected at the converters output. Therefore reducing the MPP oscillations will steady the converters output and thus will place a smaller burden on the regulation controls used in subsequent converter stages. Previous work [43] has experimentally compared the perturb and observe, incremental conductance and the fractional open/short circuit voltage/current methods and concluded that the fractional short circuit method produced the least steady state error. Also hill-climbing algorithms require the measurement of both the voltage and current whilst Frac. VOC /ISC only needs one, thus reducing sensing circuitry cost. As mentioned before the drawback of this method is the reduced responsiveness of the converter however this is not signicant when using an MPPT with a TEG. Changes to the MPP are the result of the load or the TEG temperature difference changing. Changes in the load have no effect on

VGS

VGS

IL1 = 2A/div VDS = 5V/div

2.5s/div

2.5s/div

(a) Switch node voltage

(b) L1 current

VGS

VGS Vo = 50V/div

IL2 = 500mA/div

VC1 = 50V/div

VC2 = 50V/div

2.5s/div

2.5s/div

(c) L2 current Fig. 13. Waveforms of proposed converter for Vi = 4.2V and Vo = 180V

(d) C1 , C2 and Co voltage

multiplier principles for use with a TEG or other low voltage, high current power source such as a portable fuel cell unit. It has shown that the proposed converter has a high gain compared to other circuits of similar component counts and transformer turns ratio. The converter gain was derived and the effect of conduction losses on the gain, as well as the overall efciency, were analysed with particular reference to the converters turns ratio. The merits of using a fractional open/shortcircuit algorithm for controlling a TEG were discussed. As the fractional open/short-circuit algorithm experiences reduced oscillations it is therefore more suitable for use with TEG modules which experience larger steady state oscillations than PV modules of the same output power rating. The proposed converter was designed and built for operation with a TEP112656-0.6 module and is able to output 180V for an input of 4.2V. Both P&O and Frac. ISC algorithms were implemented on the converter and the results obtained showed that the Frac. ISC algorithm produced a more stable output over the operation range. R EFERENCES
[1] S. B. Riffat and X. Ma, Thermoelectrics: a review of present and potential applications, Applied Thermal Engineering, vol. 23, no. 8, pp. 913 935, 2003. [Online]. Available: http://www.sciencedirect.com/science/ article/B6V1Y-485P6M3-1/2/10905dcee9791673dcf7fd35280522f9 [2] M. Fisher, J. Kastovich, W. Moreland, and T. Corry, Experimental 5-kw thermoelectric generator, Advanced Energy Conversion, vol. 2, pp. 275 279, 1962, symposium on Thermoelectric Energy Conversion. [Online]. Available: http://www.sciencedirect.com/science/ article/B75D1-498MG7X-1D/2/1276ca7e47b11cb8a7f7cd8c537fb17e

[3] C. Lu, S. P. Park, V. Raghunathan, and K. Roy, Analysis and design of ultra low power thermoelectric energy harvesting systems, in LowPower Electronics and Design (ISLPED), 2010 ACM/IEEE International Symposium on, Aug. 2010, pp. 183 188. [4] E. Carlson, K. Strunz, and B. Otis, A 20 mv input boost converter with efcient digital control for thermoelectric energy harvesting, Solid-State Circuits, IEEE Journal of, vol. 45, no. 4, pp. 741 750, Apr. 2010. [5] Kryotherm, Thermoelectric cooling and power generating solutions, http://www.kryotherm.ru/dir2attz/Kryotherm%20catalog.pdf, product catalog. [6] Thermonamic, Tep1-12656-0.6 module specications, http://www.thermonamic.com/TEP1-12656-0.6-NET3.pdf. [7] S. Lineykin and S. Ben-Yaakov, Modeling and analysis of thermoelectric modules, Industry Applications, IEEE Transactions on, vol. 43, no. 2, pp. 505 512, Mar.-Apr. 2007. [8] D. M. Rowe, A high performance solar powered thermoelectric generator, Applied Energy, vol. 8, no. 4, pp. 269 273, 1981. [Online]. Available: http://www.sciencedirect.com/science/article/ B6V1T-497YSYN-89/2/4ebb63c37b045017c148e9bd38619c8d [9] T. Durst, L. Harris, and H. Goldsmid, Studies of a thermoelectric generator operating from tubular solar collectors, Solar Energy, vol. 31, no. 4, pp. 421 425, 1983. [Online]. Available: http://www.sciencedirect.com/science/article/ B6V50-497T9X9-X8/2/bf970992f2ed0b8c7f49b06e66c4dda7 [10] S. Maneewan, J. Khedari, B. Zeghmati, J. Hirunlabh, and J. Eakburanawat, Investigation on generated power of thermoelectric roof solar collector, Renewable Energy, vol. 29, no. 5, pp. 743 752, 2004. [Online]. Available: http://www.sciencedirect.com/science/article/ B6V4S-4B4YWKY-1/2/a872678729ea1fb1803cc3f46d5ec00e [11] D.-C. Lu and V. Agelidis, Photovoltaic-battery-powered dc bus system for common portable electronic devices, Power Electronics, IEEE Transactions on, vol. 24, no. 3, pp. 849 855, Mar. 2009. [12] A. Kwasinski and C. Onwuchekwa, Dynamic behavior and stabilization of dc microgrids with instantaneous constant-power loads, Power Electronics, IEEE Transactions on, vol. 26, no. 3, pp. 822 834, Mar. 2011.

10

4.1

0.84
4

0.82
3.9

0.8

Average Pi (W)

0.78

Average Pi (W)

0.76

P&O Frac Isc

3.8

P&O Frac Isc

3.7

0.74
3.6

0.72

0.7 0 500 1000 1500 2000 2500 3000 3500 4000

3.5
0 500 1000 1500 2000 2500 3000 3500 4000

Load ()

Load ()

(a) Average Pi , T = 75 C
0.18 0.16 0.14 0.18 0.16 0.14

(b) Average Pi , T = 175 C

Vi standard deviation

0.12 0.1

Vi standard deviation

0.12 0.1

0.08 0.06 0.04 0.02 0 0 500 1000 1500 2000 2500 3000 3500 4000

P&O Frac Isc

0.08 0.06 0.04 0.02 0 0 500 1000 1500 2000 2500 3000 3500 4000

P&O Frac Isc

Load ()

Load ()

(c) Standard deviation Vi , T = 75 C

1.4
1.6

(d) Standard deviation Vi , T = 175 C

1.4

1.2
1.2

Vo standard deviation

Vo standard deviation

0.8

0.6

P&O Frac Isc

0.8

P&O Frac Isc

0.6

0.4
0.4

0.2

0.2

0 0 500 1000 1500 2000 2500 3000 3500 4000

0
0 500 1000 1500 2000 2500 3000 3500 4000

Load ()

Load ()

(e) Vo standard deviation, T = 75 C Fig. 14.

(f) Vo standard deviation, T = 175 C

Characteristics of proposed converter running a TEP1-12656-0.6 for various loads, temperature differences and MPPT algorithms

11

[13] D. Maksimovic and S. Cuk, Switching converters with wide dc conversion range, Power Electronics, IEEE Transactions on, vol. 6, no. 1, pp. 151 157, Jan. 1991. [14] J. Wei and F. Lee, Two novel soft-switched, high frequency, highefciency, non-isolated voltage regulators-the phase-shift buck converter and the matrix-transformer phase-buck converter, Power Electronics, IEEE Transactions on, vol. 20, no. 2, pp. 292 299, Mar. 2005. [15] B. Axelrod, Y. Berkovich, and A. Ioinovici, Switchedcapacitor/switched-inductor structures for getting transformerless hybrid dc-dc pwm converters, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 55, no. 2, pp. 687 696, Mar. 2008. [16] J. Damaschke, Design of a low-input-voltage converter for thermoelectric generator, Industry Applications, IEEE Transactions on, vol. 33, no. 5, pp. 1203 1207, Sep./Oct. 1997. [17] B. Shen, R. Hendry, J. Cancheevaram, C. Watkins, M. Mantini, and R. Venkatasubramanian, Dc-dc converter suitable for thermoelectric generator, in Thermoelectrics, 2005. ICT 2005. 24th International Conference on, Jun. 2005, pp. 529 531. [18] I. Doms, P. Merken, R. Mertens, and C. Van Hoof, Capacitive powermanagement circuit for micropower thermoelectric generators with a 2.1 W controller, in Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, Feb. 2008, pp. 300 615. [19] H. Yu, H. Wu, Y. Wen, and L. Ping, An ultra-low input voltage dcdc boost converter for micro-energy harvesting system, in Information Science and Engineering (ICISE), 2010 2nd International Conference on, Dec. 2010, pp. 86 89. [20] R. D. Middlebrook, Transformerless dc-to-dc converters with large conversion ratios, in Telecommunications Energy Conference, 1984. INTELEC 84. International, Nov. 1984, pp. 455 460. [21] J. Starzyk, Y.-W. Jan, and F. Qiu, A dc-dc charge pump design based on voltage doublers, Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, vol. 48, no. 3, pp. 350 359, Mar. 2001. [22] L. Franco, L. Ptscher, and R. Gules, A new high static gain nonisolated dc-dc converter, in Power Electronics Specialist Conference, 2003. PESC 03. 2003 IEEE 34th Annual, vol. 3, Jun. 2003, pp. 1367 1372 vol.3. [23] R. Guo, Z. Liang, and A. Huang, A family of multimodes charge pump based dc-dc converter with high efciency over wide input and output range, Power Electronics, IEEE Transactions on, vol. 27, no. 11, pp. 4788 4798, Nov. 2012. [24] M. Prudente, L. Ptscher, G. Emmendoerfer, E. Romaneli, and R. Gules, Voltage multiplier cells applied to non-isolated dc-dc converters, Power Electronics, IEEE Transactions on, vol. 23, no. 2, pp. 871 887, Mar. 2008. [25] Q. Zhao and F. Lee, High performance coupled-inductor dc-dc converters, in Applied Power Electronics Conference and Exposition, 2003. APEC 03. Eighteenth Annual IEEE, vol. 1, Feb. 2003, pp. 109 113. [26] S.-M. Chen, T.-J. Liang, L.-S. Yang, and J.-F. Chen, A cascaded high step-up dc-dc converter with single switch for microsource applications, Power Electronics, IEEE Transactions on, vol. 26, no. 4, pp. 1146 1153, Apr. 2011. [27] S. Dwari and L. Parsa, An efcient high-step-up interleaved dc-dc converter with a common active clamp, Power Electronics, IEEE Transactions on, vol. 26, no. 1, pp. 66 78, Jan. 2011. [28] T.-H. Hsia, H.-Y. Tsai, D. Chen, M. Lee, and C.-S. Huang, Interleaved active-clamping converter with zvs/zcs features, Power Electronics, IEEE Transactions on, vol. 26, no. 1, pp. 29 37, Jan. 2011. [29] K.-B. Park, G.-W. Moon, and M.-J. Youn, Nonisolated high step-up stacked converter based on boost-integrated isolated converter, Power Electronics, IEEE Transactions on, vol. 26, no. 2, pp. 577 587, Feb. 2011. [30] R.-J. Wai and R.-Y. Duan, High step-up converter with coupledinductor, Power Electronics, IEEE Transactions on, vol. 20, no. 5, pp. 1025 1035, Sep. 2005. [31] S.-K. Changchien, T.-J. Liang, J.-F. Chen, and L.-S. Yang, Step-up dc-dc converter by coupled inductor and voltage-lift technique, Power Electronics, IET, vol. 3, no. 3, pp. 369 378, May 2010. [32] W. Li, Y. Zhao, Y. Deng, and X. He, Interleaved converter with voltage multiplier cell for high step-up and high-efciency conversion, Power Electronics, IEEE Transactions on, vol. 25, no. 9, pp. 2397 2408, Sep. 2010. [33] Y.-P. Hsieh, J.-F. Chen, T.-J. Liang, and L.-S. Yang, A novel high stepup dc-dc converter for a microgrid system, Power Electronics, IEEE Transactions on, vol. 26, no. 4, pp. 1127 1136, Apr. 2011.

[34] Y.-P. Hsieh, J.-F. Chen, T.-J. Liang, and Y. Lung-Sheng, Analysis and implementation of a novel single-switch high step-up dc-dc converter, Power Electronics, IET, vol. 5, no. 1, pp. 11 21, Jan. 2012. [35] Y. Deng, Q. Rong, W. Li, Y. Zhao, J. Shi, and X. He, Single-switch high step-up converters with built-in transformer voltage multiplier cell, Power Electronics, IEEE Transactions on, vol. 27, no. 8, pp. 3557 3567, Aug. 2012. [36] F. Tofoli, D. de Souza Oliveira, R. Torrico-Bascop e, and Y. Alcazar, Novel nonisolated high-voltage gain dc-dc converters based on 3ssc and vmc, Power Electronics, IEEE Transactions on, vol. 27, no. 9, pp. 3897 3907, Sep. 2012. [37] T. Esram and P. Chapman, Comparison of photovoltaic array maximum power point tracking techniques, Energy Conversion, IEEE Transactions on, vol. 22, no. 2, pp. 439 449, Jun. 2007. [38] L. Chen, D. Cao, Y. Huang, and F. Peng, Modeling and power conditioning for thermoelectric generation, in Power Electronics Specialists Conference, 2008. PESC 2008. IEEE, Jun. 2008, pp. 1098 1103. [39] R.-Y. Kim and J.-S. Lai, Aggregated modeling and control of a boost-buck cascade converter for maximum power point tracking of a thermoelectric generator, in Applied Power Electronics Conference and Exposition, 2008. APEC 2008. Twenty-Third Annual IEEE, Feb. 2008, pp. 1754 1760. [40] , A seamless mode transfer maximum power point tracking controller for thermoelectric generator applications, Power Electronics, IEEE Transactions on, vol. 23, no. 5, pp. 2310 2318, Sep. 2008. [41] H. Nagayoshi, T. Kajikawa, and T. Sugiyama, Comparison of maximum power point control methods for thermoelectric power generator, in Thermoelectrics, 2002. Proceedings ICT 02. Twenty-First International Conference on, Aug. 2002, pp. 450 453. [42] H. Nagayoshi and T. Kajikawa, Mismatch power loss reduction on thermoelectric generator systems using maximum power point trackers, in Thermoelectrics, 2006. ICT 06. 25th International Conference on, Aug. 2006, pp. 210 213. [43] I. Laird, H. Lovatt, N. Savvides, D. Lu, and V. Agelidis, Comparative study of maximum power point tracking algorithms for thermoelectric generators, in Power Engineering Conference, 2008. AUPEC 08. Australasian Universities, Dec. 2008, pp. 1 6.

Ian Laird graduated from the University of Sydney, Australia in 2008 with a BEng (Hons. I) in Mechatronic Engineering. He is currently pursuing his PhD in the elds of thermoelectrics and power electronics at the University of Sydney. His research interests include thermoelectric modelling, DC-DC converter topologies and MPPT algorithms.

Dylan Dah-Chuan Lu (S00 - M04 - SM09) received his B.Eng. (Hons.) and Ph.D. degrees in Electronic and Information Engineering from The Hong Kong Polytechnic University, Hong Kong, in 1999 and 2004 respectively. In 2003, he joined Powere Lab Ltd. as a Senior Engineer. His major responsibilities include project development and management, circuit design, and contribution of research in the area of power electronics. In 2006, he joined the School of Electrical and Information Engineering, The University of Sydney, Australia, where he is currently a Senior Lecturer. He presently serves as a Member of the Editorial Board of International Journal of Electronics, a Member of the Editorial Board of Smart Grid and Renewable Energy, a Member of the Editorial Board of Energy and Power Engineering and an Associate Editor of the Australian Journal of Electrical and Electronic Engineering. His current research interests include power electronics circuits and control for efcient power conversion, lighting, renewable electrical energy systems, microgrid and power quality improvement, and engineering education. He has published over 80 technical articles in the areas of power electronics and engineering education. He has two patents on efcient power conversion. Dr. Lu received the Deans Research Award in 2011 and is also a member of the Institute of Engineers Australia.