2266
9, SEPTEMBER 2010
Nonisolated High Step-up Boost Converter
Integrated With Sepic Converter
Ki-Bum Park, Student Member, IEEE, Gun-Woo Moon, Member, IEEE,
and Myung-Joong Youn, Senior Member, IEEE
Abstract—For a nonisolated high step-up converter, the combi-
nation of a boost converter with a series output module is inves-
tigated in this paper. As a solution to supplement the insufficient
step-up ratio and distribute a voltage stress of a classical boost con-
verter, a sepic-integrated boost (SIB) converter, which provides an
additional step-up gain with the help of an isolated sepic converter,
is proposed. Since the boost converter and the sepic converter share
a boost inductor and a switch, its structure is simple. Moreover, the
SIB converter needs no current snubber for the diodes, since the
transformer leakage inductor alleviates the reverse recovery. The
operational principle and characteristics of SIB converter are pre-
sented, and verified experimentally with a 200 W, 42 V input, 400 V
output prototype converter.
Index Terms—High step-up converter, boost converter, sepic
converter.
I. INTRODUCTION
HE nonisolated high step-up conversion technique finds
T increasing necessities in applications, such as electric
vehicles, uninterrupted power supplies (UPS), high-intensity-
discharge (HID) lamp, fuel cell system, and photovoltaic sys-
tems [14], [15], [18], [21], [24]. In these applications, a classical
boost converter is generally used and it has several advantages,
such as simple structure, continuous input current, and clamped
switch voltage stress to the output voltage. However, it is very
difficult to satisfy both high voltage conversion ratio and high
efficiency at once. This is primarily due to the parasitic resis-
tances, which cause serious degradation in the step-up ratio and
efficiency as the operating duty increases [1]. Moreover, in high-
output voltage applications, a high-voltage rating diode causes
a severe reverse recovery problem, which requires a snubber
circuit [2]–[6]. As a result, a general boost converter would not
be acceptable for high step-up applications. To overcome these
limitations, various types of step-up converters, utilizing the
voltage conversion ability of a transformer, a coupled-inductor,
and a multiplier cell, can be adopted [7]–[24].
Manuscript received September 17, 2009; revised February 22, 2010;
accepted March 10, 2010. Date of current version September 17, 2010. This
work was supported by the Brain Korea 21 Project, the School of Information
Technology, KAIST in Korea. This paper was presented in Power Electronics
Specialists Conference, titled as “Integrated Boost-Sepic Converter for High
Step-up Applications,” June 15–19, 2008, Rhodes, Greece. Recommended for
publication by Associate Editor P. Jain.
The authors are with the Department of Electrical Engineering, Korea
Advanced Institute of Science and Technology, Daejeon 305-701, Korea
(e-mail: parky@rainbow.kaist.ac.kr; gwmoon@ee.kaist.ac.kr; mmyoun@ee.
kaist.ac.kr).
Digital Object Identifier 10.1109/TPEL.2010.2046650
0885-8993/$26.00 © 2010 IEEE
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO.
Fig. 1. Boost converter with series output module.
Current-fed type converters, which easily offer a high step-
up ratio using a transformer, are attractive for high power step-
up applications with multiple switches [7]–[12], [28]. How-
ever, they require snubbers to limit the voltage spike across
switches caused by the existence of transformer leakage in-
ductance, resulting in an additional loss. Moreover, an aux-
iliary circuit is needed for below 0.5 duty operation and the
input current is no longer continuous in this operation. Active
clamp approaches release these problems and reduce switching
losses, but lead to complex structures with increased number of
switches [11], [12]. A coupled-inductor-employed boost con-
verter is also a favorable candidate in low-to-medium power
applications for its simple structure, though the input current
is not continuous as in a general boost converter and an aux-
iliary circuit is also required to suppress the switch voltage
spike [13]–[20]. Particularly, as the auxiliary turns of a coupled
inductor are increased to raise a voltage gain further, an input
current ripple becomes larger in return. Thereby, more input
filter is needed. A voltage multiplier cell or a switch capacitor
circuit can be useful to raise a step-up gain in collaboration
with classical topologies [21]–[24]. As the output voltage is
increased, however, the number of stage is increased, requir-
ing more capacitors and diodes. Besides, the current snubber is
required to reduce the reverse recovery on diode.
To obtain a high step-up ratio in a nonisolated system, the al-
ternative structure, which combines a classical boost converter
with an isolated-type converter as a series output module can be
considered, as shown in Fig. 1. By properly selecting a converter
for a series output module, many advantages, such as high step-
up capability, design flexibility, and distributed voltage stress
can be achieved. Although this architecture can achieve a high
performance, its structure would be complex. To simplify the
circuit, a boost converter and a sepic converter, as a series out-
put module can be simply integrated, as shown in Fig. 2, be-
cause they can share common parts, i.e., a boost inductor LB
and a switch Q. Since this series output module should have
PARK et al.: NONISOLATED HIGH STEP-UP BOOST CONVERTER INTEGRATED WITH SEPIC CONVERTER 2267

Fig. 2. Common parts sharing between boost converter and isolated sepic
converter.

Fig. 3. SIB converter.

a floating output ground, an isolated-type sepic converter is

adopted [1], [25]. As a result, a sepic-integrated boost (SIB)
converter is derived, as shown in Fig. 3. This converter provides
an additional step-up ratio and a distributed voltage stress on de-
vices, while maintaining the advantages of the boost converter,
such as continuous input current and clamped voltage stress on
switch. Moreover, the transformer leakage inductance provides
a current snubbing effect, which alleviates the reverse recovery
problem on diodes.

II. OPERATION PRINCIPLES

In order to perform a mode analysis of SIB converter, several
assumptions are made as follows. The transformer T is modeled
as a magnetizing inductor LM , a leakage inductor Llkg , and an
ideal transformer, with a turn ratio n. The input voltage VS , the
balancing capacitor voltage VCb , the lower module output volt-
age Vo1 , and the upper module output voltage Vo2 are constant.
The switch and diode are ideal.
The basic operation of SIB converter is a combined opera- Fig. 4. Key waveforms of SIB converter. (a) Case I (n > 1). (b) Case II
(n < 1).
tion of a boost converter and a sepic converter with a common
boost inductor and a switch. Each converter is operated with its
original function and an additional effect of the transformer leak-
age inductance Llkg . During the switch-OFF state, Llkg forces and ILm are in a continuous current mode (CCM). Fig. 4(a)
the commutation of the diode current between two converters and (b) shows the key waveforms of case I (n > 1) and case II
slowly from the lower diode Do1 to the upper diode Do2 . The (n < 1), respectively. In case I, ID o 1 is decreased to zero, but not
lower diode current ID o 1 can be decreased to either zero or not, in case II. (This condition will be discussed later.) The detailed
according to the turn ratio n, though both inductor currents ILb operation of each case is presented next.
2268 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 9, SEPTEMBER 2010

Fig. 5. Topological states of case I (n > 1). (a) Mode 1 [t0 ∼ t1 ]. (b) Mode 2 [t1 ∼ t2 ]. (c) Mode 3 [t2 ∼ t3 ]. (d) Mode 4 [t3 ∼ t4 ].

A. Case I (n > 1) Vo1 –VCb –Vo2 /n, and VS –VCb –Vo2 /n is applied to LB . There-
As shown in Fig. 4(a), one period is subdivided into four fore, ILb is decreased less slowly than in mode 3. At t4 , one
modes and their topological states are presented in Fig. 5. Before period is completed and the same operation is repeated.
t0 , both the boost inductor current ILb and the transformer
magnetizing current ILm flow through Do2 . B. Case II (n < 1)
Mode 1 [t0 ∼ t1 ]: The switch Q is turned ON at t0 . Since
The basic operation is similar to that of case I except that
Do2 is still conducting, the entire voltage of VCb + Vo2 /n is
mode 4 is ignored. Therefore, one period is subdivided into
impressed on the transformer leakage inductor Llkg . Therefore,
three modes, as shown in Fig. 4(b). The difference from case I
the transformer primary current Ilkg is increased linearly. Thus,
is as follows.
IQ is increased and ID o 2 is decreased accordingly, resulting
During the interval t2 ∼ t3 , ID o 1 and ID o 2 are commutated.
in a commutation between IQ and ID o 2 . Since Llkg alleviates
However, ID o 1 does not reach zero in this case. When the switch
di/dt of ID o 2 , i.e., Llkg provides a current snubbing effect, the
Q is turned ON at t3 , the current still remains in Do1 , which leads
reverse recovery phenomenon of Do2 can be reduced. Do1 is
to an abrupt current drop of ID o 1 . This results in a considerable
reverse-biased by Vo1 .
reverse recovery current. However, ID o 2 is decreased slowly by
Mode 2 [t1 ∼ t2 ]: At t1 , ID o 2 reaches zero, and both ILb and
Llkg , which is the same as in case I. These two different diode
ILm flow through Q. Ilkg only contains ILm . VS and VCb are
current slopes can be directly observed by IQ during the interval
applied to LB and LM , respectively. Therefore, ILb and ILm
t3 ∼ t0 . In view of a reverse-recovery problem, the operation
are increased linearly. VCb is reflected to the secondary side of
in case I (n > 1), which guarantees a ZCS turn-OFF of Do1 , is
the transformer, thus Do2 is reverse-biased by nVCb + Vo2 .
more desirable.
Mode 3 [t2 ∼ t3 ]: The switch Q is turned OFF at t2 , and the
entire currents of ILb and ILm flow through Do1 , since Llkg pre-
vents the current from flowing through Do2 . VQ is clamped to III. ANALYSIS AND CHARACTERISTICS
Vo1 . VS – Vo1 and −Vo2 /n are applied to LB and LM , respec- The simplified current waveform is presented in Fig. 6. For
tively. Thus, ILb and ILm are decreased linearly. Meanwhile, the purpose of analysis, it is assumed that the time interval
Do2 starts to conduct and VCb + Vo2 /n – Vo1 is impressed on DO TS is zero, and ILb and ILm are constant. The average value
Llkg , forcing Ilkg to decrease slowly. As Ilkg is decreased, ID o 1 is represented by •.
is decreased and ID o 2 is increased accordingly. That is, a com-
mutation between ID o 1 and ID o 2 is progressed. Since ID o 1 has
a gentle slope, the reverse recovery of Do1 can be minimized, A. Case I (n > 1)
i.e., zero-current switching (ZCS) turn-OFF of Do1 is achieved. Considering ID o 1 = ID o 2 = IO , the voltage–second balance
Mode 4 [t3 ∼ t4 ]: ID o 1 reaches zero at t3 , and the entire of LB and LM , and the current–second balance of CB , the
currents of ILb and ILm flow through Do2 . Do1 is blocked by steady-state equations are obtained as (1)–(12).
PARK et al.: NONISOLATED HIGH STEP-UP BOOST CONVERTER INTEGRATED WITH SEPIC CONVERTER 2269

case I and case II.

2(1 − D)
D1 TS = TS (6)
1+n
(1 − D)(n − 1)
D2 TS = TS . (7)
1+n
The average current of ILb is the same as the average input
current Iin as in (8). However, the average current of ILm is the
same as the reflected output current as in (9). That is, as n is
decreased, ILm  is reduced.

1 + nD
ILb  = Iin = IO (8)
1−D
n(1 − D)Iin
ILm  = = nIO . (9)
1 + nD

The current stress on switch is the sum of ILb and ILm as

in (10), and is the same as that of ID o 1 . Fig. 8(a) shows the
current stress on switch normalized by Iin . As n is increased
and the duty cycle is decreased, the current stress on switch is
increased. In case of n = 0, which stands for a conventional
Fig. 6. Simplified current waveform. (a) Case I (n > 1). (b) Case II (n < 1).
boost converter, the current stress equals to Iin . Similarly, as in
(11), the current stress on Do2 is the sum of the reflected ILb
The input–output voltage conversion ratio considering the ef- and ILm in the secondary. Fig. 8(b) shows the current stress on
fect of K (= Llkg /2TS RO ) is presented in (1). Fig. 7(a) shows Do2 normalized by IO , where n = 1 also represents the current
the voltage conversion ratio according to the variation of K, stress on Q and Do1 .
when n = 4. As K increases, a smaller step-up ratio is achieved,
since K provides a damping effect. Therefore, in designing a IQ p eak = ID o 1 p eak = ILb + ILm
SIB converter, the turn ratio and the duty cycle should be se-


1+n 1+n
lected carefully considering the damping effect of K. Although = IO = Iin (10)
1−D 1 + nD
(1) explains in full about the voltage equation, it is complex.

By setting K = 0, an approximated equation can be obtained, 1 1 1+n
ID o 2 p eak = (ILb + ILm ) = IO . (11)
which is a sum of the output voltage equations of the boost n n 1−D
converter and the isolated sepic converter as in (2). With this
approximation, Vo1 , Vo2 , and VCb are obtained as (3)–(5) as The voltage stresses on Q and Do1 are clamped to Vo1 as in a
shown at the bottom of the page. The voltage conversion ratio boost converter. Since Vo1 can be designed several times lower
according to the variation of n is given in Fig. 7(b) with K = 0. than the total output voltage VO , low-voltage rating devices can
In Fig. 7(b), n = 0 stands for the conventional boost converter. be used for Q and Do1 even in high-output voltage applications.
The time interval D1 TS and D2 TS are presented as (6) and The voltage stress on Do2 in steady state would be nVCb + Vo2 ,
(7), respectively, and are determined by the duty cycle D and if the voltage ringing is ignored, and can be expressed as follows:
the turns ratio n. As n decreases, D2 TS decreases and becomes
zero, when n = 1. That is, mode 4 (t3 ∼ t4 ) can be neglected, Vo2
VD o 2 ss = nVCb + Vo2 = nVS + Vo2 = . (12)
if n is smaller than 1. This is the boundary condition between D

VO Dn(1 + n) Llkg
= , K= (1)
VS (1 − D) [n − 1 + ({Kn(1 + n) D + (1 − D)2 } (2nD − n + 1)) /(1 − D)2 (nD + 1)]
2 2TS RO
VO 1 + nD
≈ (2)
VS 1−D
VS
VO 1 ≈ (3)
1−D
nDVS
VO 2 ≈ (4)
1−D
VCb ≈ VS . (5)
2270
Fig. 7. Input–output voltage conversion ratio according to (a) variation of K (n = 4) and (b) variation of n (K = 0).
Fig. 8. Current stress according to variation of n. (a) Current stress on switch Q normalized by Iin . (b) Current stress on diode D o 2 normalized by IO .
B. Case II (n < 1)
The basic steady-state equations are the same as those of case
I, except for ID o 1 and ID o 2 . The lagging edge values of ID o 1
and ID o 2 are expressed in (13) and (14). As n increases, ID o 1 E
decreases, and becomes zero when n = 1. This condition is
matched to the boundary between case I and case II.
1−n
ID o 1 E = IO
1−D
2 sources, charge Coss + Cj 1 , while discharge n2 Cj 2 . Therefore,
ID o 2 E = IO .
1−D
C. Effect of Diode Junction Capacitance
In the previous analysis, the switch and diode are assumed to
be ideal devices, i.e., intrinsic capacitors are not considered, for
analytic purposes. However, in a real operation, these signifi-
cantly affect the operation of SIB converter, and are discussed
as follows. The key waveforms and equivalent circuits consid-
ering the intrinsic capacitors are presented in Fig. 9, where Coss
is the output capacitor of Q, and Cj 1 and Cj 2 are the junction
capacitors of Do1 and Do2 , respectively.
During t0 ∼ t1 , VCb + Vo2 /n is applied to Llkg . Therefore,
after ID o 2 reaches zero at t1 , the resonant circuit on which
VCb + Vo2 /n is impressed is constituted, as shown in Fig. 9(b),
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 9, SEPTEMBER 2010
where n2 Cj 2 is the reflected Cj 2 to the primary. As a result,
by the interaction between Llkg and n2 Cj 2 , the peak voltage
of VD o 2 ideally reaches up to twice the steady-state value, i.e.,
2Vo2 /D. If the reverse recovery is considered, the peak voltage
would be increased further. This additional voltage stress can be
suppressed by a snubber circuit, but a loss occurs [29].
The equivalent circuit after the switch is turned OFF at t2
is presented in Fig. 9(c). Provided that the effect of Llkg is
(13)
small enough, ILb and ILm , which can be considered as current
(14) these charging/discharging currents are divided by the ratio of
capacitance. As a result, some current drop, Idrop in Fig. 9(a),
is occurred on Ilkg , since ILb + ILm is flowing through Llkg .
This current drop slightly changes the shape of ID o 2 and raises
the boundary condition between case I and case II to a higher
value than n = 1. As the capacitance ratio n2 Cj 2 /(Coss + Cj 1 )
is increased, Idrop is increased accordingly.
IV. DIODE VOLTAGE-STRESS DISTRIBUTION METHODS
As presented in (12), the voltage stress across Do2 is higher
than Vo2 . Therefore, a high-voltage rating diode is required,
which leads to a high cost and low performance in high-
output voltage applications. Moreover, the aforementioned volt-
age ringing across the diode makes this problem more severe.
PARK et al.: NONISOLATED HIGH STEP-UP BOOST CONVERTER INTEGRATED WITH SEPIC CONVERTER
Fig. 9. Effect of diode junction capacitance. (a) Key waveforms. (b) Equivalent
circuit [t0 ∼]. (c) Equivalent circuit [t2 ∼ t2 ].
To distribute the voltage stress across the secondary diode,
the SIB converter can be extended to a multiwinding structure,
as shown in Fig. 10(a) and the number of secondary winding can
be increased further. Although multiwindings can distribute the
voltage stress across the diode, the voltage ringing still remains
and it should be suppressed by snubber circuits.
To distribute the voltage stress and limit the voltage ringing
by a simple nondissipative method, two auxiliary clamp diodes
dc2 and dc3 can be employed in series with two main diodes
Do2 and Do3 , respectively, which are parallel to Vo2 as shown
in Fig. 10(b). If the voltage ringings across the main diodes
reach Vo2 , the clamp diodes are conducted. Then, VD o 2 and
VD o 3 are limited by Vo2 . Since only a small ringing current
flows through the clamp diodes, low-current rating diodes can
be used. To properly function this voltage clamping method
without a distortion in the original converter operation, the con-
dition Vo2 > nVCb , is required. If nVCb is higher than Vo2 ,
the powering path from VCb to Vo2 can be formed through
Llkg and two clamp diodes during the switch conducting state.
Therefore, a large current would flow through the clamp diodes
and distort the converter operation. To prevent this problem,
nVCb must be lower than Vo2 to block the clamp diodes during
2271
Fig. 10. Diode voltage-stress distribution methods. (a) Multiwinding struc-
ture. (b) Clamp diode employed structure.
the switch conducting state, and this condition can be approxi-
mately expressed as D > 0.5. This method can also be extended
to multiwinding structures.
V. EXPERIMENTAL RESULTS
A. Design Guideline and Example
To illustrate the design procedure for a 200-W prototype con-
verter with 42 V input and 400 V output operating at 60 kHz,
an example is presented as follows. The required input–output
voltage gain M is 9.52 ( = 400/42), i.e., about 10. To distribute
and limit the voltage stress across the diode in the sepic con-
verter by Vo2 with a nondissipative way, the secondary side is
substituted by the clamp diode structure presented in Fig. 10(b).
Therefore, the nominal duty cycle Dnom should be selected as
above 0.5.
In the converter design, a selection of the switch Q, which
is burdened by the large input current ILb and ILm as well, is
primarily considered with respect to the cost and the efficiency.
As presented in (15) and Fig. 11(a), an rms value of switch
current is decreased as D is increased. That is, a larger D is of
benefit for reducing a switch conduction loss. However, a switch
voltage stress, VS /(1–D), is increased in return, which lead
to a use of higher voltage switch having larger ON-resistance.
Therefore, a D should be selected to accommodate as a low
2272
Fig. 11. (a) Switch current rms value normalized by IO and (b) transformer turn ratio n according to variation of input–output voltage gain M .
voltage stress as possible, while still having a low rms value
of a switch current. To utilize a 200 V switch with a sufficient
margin, therefore, the Dnom is selected as about 0.6.
M −1
IQ rm s ≈ √ IO .
D B. Experimental Results
Considering the Dnom to be 0.6, from (2) and Fig. 11(b),
the required transformer turn ratio n is determined as 5 accord-
ingly. In the prototype design, the damping factor K in (1) is
so small, i.e., merely 0.00015, such that its effect on the output
voltage is negligible. With the selected n and Dnom , from (3)
and (4), Vo1 and Vo2 are designed to be about 100 and 300 V,
respectively. Thereby, the usage of 200 V switch and diode are
allowed for the boost converter and 400 V diodes for the sepic
converter.
The design of the boost inductor LB is the same to that
of a classical boost converter [26]. Considering a current rip-
ple to be 15% of the input current 4.8 A, LB is designed as
600 µH.
As presented in (9), ILm of the transformer has an off-
set current, i.e., the transformer stores an energy like an in-
ductor; therefore, the transformer should be designed like a
flyback transformer, considering its inductance and average
current [26], [27]. Considering a current ripple of ILm equal
to 80% of its average current 2.5 A, LM is designed as
200 µH.
The Llkg of the transformer acts as a current snubber, which
alleviates the reverse recovery on diodes of the sepic converter.
The required inductance for current snubbing effect can be de-
fined by di/dt of a diode current at the switch turn-ON instant.
In order to reduce the reverse recovery sufficiently, di/dt should
be less than 100 A/µs [4]. From (16), which represents the di/dt
of ID o 2 during the interval t0 ∼ t1 of Fig. 4, the minimum in-
ductance, which guarantee di/dt below 100 A/µs is obtained as
210 nH. If the obtained Llkg from a fabricated transformer has
a larger inductance than 210 nH, a reverse recovery would be
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 9, SEPTEMBER 2010
sufficiently alleviated.
dID o 2 VS
≈ . (16)
dt n(1 − D)Llkg
(15)
To verify the SIB converter, the prototype is implemented.
The specification and design parameters obtained from the de-
sign example are presented in Table I.
Fig. 12 shows the key experimental waveforms at a full-
load condition and the overall waveforms are agreed well with
the theoretical analysis. It is shown that the voltage stresses
on switch Q and diode Do1 are limited to the output of boost
converter Vo1 , which is slightly higher than 100 V, neglecting
the voltage spike caused by the parasitic inductance, though VO
is 400 V. There is no reverse recovery on ID o 1 , since it has an
extremely low-current slope, i.e., ZCS turn-OFF is achieved. In
the waveforms of IQ in Fig. 12(a), Ilkg in Fig. 12(b), and ID o 2
in Fig. 12(c), the reverse recovery current from the secondary
diode is alleviated by Llkg although some is still observed. The
current stress on switch Q is over 8 A, which is higher than that
on LB of 5 A, since IQ contains ILm as well as ILb . The current
drop on Ilkg at the switch turn-OFF transition can be seen in
Fig. 12(b) and its corresponding built-up current can be found
from ID o 2 in Fig. 12(c). ILb , which represents the input current
is continuous.
Fig. 12(d) represents the extended waveforms of the sec-
ondary side. It is noted that the voltage ringing across Do2 and
Do3 are limited to the output of sepic converter Vo2 , i.e., about
300 V, by the clamp diodes, though some surge voltage occurs
on Do2 by a parasitic inductance. The current snubbing effect by
Llkg can be observed from the slow di/dt ratio of ID o 2 , roughly
1.2 A/0.1 µs.
Fig. 13 shows the measured efficiency according to the load
variation. Since the SIB converter employs low-voltage rating
switch and diode, i.e., high performance and low cost device,
and the reverse recovery problem is considerably reduced, it can
PARK et al.: NONISOLATED HIGH STEP-UP BOOST CONVERTER INTEGRATED WITH SEPIC CONVERTER 2273

TABLE I
EXPERIMENTAL PARAMETERS

Fig. 12. Key experimental waveforms at full-load condition. (a) V Q , IQ , and ID o 1 . (b) V D o 1 , IL b , and Ilk g . (c) ID o 2 , V D o 2 , and V D o 3 . (d) Extended
waveforms of ID o 2 , V D o 2 , and V D o 3 .
2274
Fig. 13. Measured efficiency.
achieve the efficiency more than 94% along a wide load range.
The maximum efficiency is 95% at a 120-W load condition.
VI. CONCLUSION
For nonisolated high step-up applications, the SIB converter,
which combines a boost converter and an isolated sepic con-
verter with one switch, is introduced in this paper. The SIB
converter can achieve a high-voltage gain with the additional
step-up ability of the isolated sepic converter and distributed
voltage stress, while maintaining the advantages of the boost
converter, such as a continuous input current and a clamped
voltage stress on switch. Moreover, the reverse recovery prob-
lem is well suppressed, since the transformer leakage inductance
alleviates a di/dt ratio of the turn-OFF diode current without ad-
ditional snubber and the voltage stress on the secondary diode
is limited by the clamp diodes. Therefore, the SIB converter is
promising for nonisolated high step-up applications with simple
structure and high efficiency. It is noted that other converters,
which have a boost inductor and a switch as an input stage, can
also be integrated with the boost converter similar to the SIB
converter.
ACKNOWLEDGMENT
The authors would like to thank H.-W. Seong and H.-S. Kim
for their help to set up the experiment.
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PARK et al.: NONISOLATED HIGH STEP-UP BOOST CONVERTER INTEGRATED WITH SEPIC CONVERTER 2275

Ki-Bum Park (S’07) was born in Korea, in 1981. He
received the B.S., M.S., and Ph.D. degrees in elec-
trical engineering from Korea Advanced Institute of
Science and Technology (KAIST), Daejeon, Korea,
in 2003, 2005, and 2010, respectively.
He is currently a Postdoctoral Researcher at
KAIST. His research interests include dc–dc con-
verter, power-factor-correction (PFC) ac–dc con-
verter for server power systems and display power
systems, and display driver circuit.
Dr. Park was recipient of the Best Paper Award
from the International Telecommunications Energy Conference 2009.
Myung-Joong Youn (S’74–M’78–SM’98) was born
in Seoul, Korea, in 1946. He received the B.S. degree
from Seoul National University, Seoul, in 1970, and
the M.S. and Ph.D. degrees in electrical engineering
from the University of Missouri, Columbia, MO, in
1974 and 1978, respectively.
In 1978, he joined the Air-Craft Equipment Divi-
sion, General Electric Company, Erie, PA, where he
was an Individual Contributor on Aerospace Electri-
cal System Engineering. Since 1983, he has been a
Professor at Korea Advanced Institute of Science and
Technology, Daejeon, Korea. His current research interests include the areas of
power electronics and control, which include the drive systems, rotating elec-
trical machine design, and high-performance switching regulators.
Dr. Youn is a member of the Institution of Electrical Engineers, U.K., the
Korean Institute of Power Electronics, the Korean Institute of Electrical Engi-
neers, and the Korea Institute of Telematics and Electronics.

Gun-Woo Moon (S’92–M’00) received the M.S. and

Ph.D. degrees in electrical engineering from Ko-
rea Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 1992 and 1996, respec-
tively.
He is currently a Professor in the Department of
Electrical Engineering, KAIST. His research inter-
ests include modeling, design and control of power
converters, soft-switching power converters, resonant
inverters, distributed power systems, power factor
correction, electric drive systems, driver circuits of
plasma display panels, and flexible ac transmission systems.
Dr. Moon is a member of the Korean Institute of Power Electronics, the
Korean Institute of Electrical Engineers, the Korea Institute of Telematics and
Electronics, the Korea Institute of Illumination Electronics and Industrial Equip-
ment, and the Society for Information Display.