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RAMs

RAMs
If you do not want to instantiate RAM primitives in order to keep your HDL code technology independent, XST offers an automatic RAM recognition capability. XST can infer distributed as well as Block RAM. It covers the following characteristics, offered by these RAM types: Synchronous write Write enable RAM enable Asynchronous or synchronous read Reset of the data output latches Single, dual or multiple-port read Single-port write The type of the inferred RAM depends on its description: RAM descriptions with an asynchronous read generate a distributed RAM macro RAM descriptions with a synchronous read generate a Block RAM macro. In some cases, a Block RAM macro can actually be implemented with Distributed RAM. The decision on the actual RAM implementation is done by the macro generator. Here is the list of VHDL/Verilog templates that will be described below: Single-Port RAM with asynchronous read Single-Port RAM with "false" synchronous read Single-Port RAM with synchronous read (Read Through) Single-Port RAM with Enable Dual-Port RAM with asynchronous read Dual-Port RAM with false synchronous read Dual-Port RAM with synchronous read (Read Through) Dual-Port RAM with One Enable Controlling Both Ports Dual-Port RAM with Enable Controlling Each Port Multiple-Port RAM descriptions If a given template can be implemented using Block and Distributed RAM, XST will implement BLOCK ones. You can use the ram_style attribute to control RAM implementation and select a desirable RAM type. Please refer to the "Design Constraints" chapter for more details. Please note that the following features specifically available with Block RAM are not yet supported: Dual write port Data output reset Parity bits Different aspect ratios on each port Please refer to the "FPGA Optimization" chapter for more details on RAM implementation.

Log File
The XST log file reports the type and size of recognized RAM as well as complete information on its I/O ports during the macro recognition step:

. . . S y n t h e s i z i n gU n i t< r a m i n f r > . R e l a t e ds o u r c ef i l ei sr a m s _ 1 . v h d . F o u n d1 2 8 b i ts i n g l e p o r td i s t r i b u t e dR A Mf o rs i g n a l< r a m > . | a s p e c t r a t i o | 3 2 w o r d x 4 b i t | | | c l o c k | c o n n e c t e d t o s i g n a l < c l k > | r i s e | | w r i t e e n a b l e | c o n n e c t e d t o s i g n a l < w e > | h i g h | | a d d r e s s | c o n n e c t e d t o s i g n a l < a > | | | d a t a i n | c o n n e c t e d t o s i g n a l < d i > | | | d a t a o u t | c o n n e c t e d t o s i g n a l < d o > | | | r a m _ s t y l e | A u t o | |
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RAMs

I N F O : X s t-F o ro p t i m i z e dd e v i c eu s a g ea n di m p r o v e dt i m i n g s ,y o u m a yt a k ea d v a n t a g eo f a v a i l a b l eb l o c kR A Mr e s o u r c e sb y r e g i s t e r i n gt h er e a da d d r e s s . S u m m a r y : i n f e r r e d1R A M ( s ) . U n i t< r a m i n f r >s y n t h e s i z e d . = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = H D LS y n t h e s i sR e p o r t M a c r oS t a t i s t i c s #R A M s : 1 1 2 8 b i ts i n g l e p o r td i s t r i b u t e dR A M:1 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = . . .

Related Constraints
Related constraints are ram_extract and ram_style .

Single-Port RAM with Asynchronous Read

The following descriptions are directly mappable onto distributed RAM only.

The following table shows pin descriptions for a single-port RAM with asynchronous read.
IO Pins Description

clk we a di do VHDL

Positive-Edge Clock Synchronous Write Enable (active High) Read/Write Address Data Input Data Output

Following is the VHDL code for a single-port RAM with asynchronous read.
l i b r a r yi e e e ; u s ei e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s ei e e e . s t d _ l o g i c _ u n s i g n e d . a l l ; e n t i t yr a m i n f ri s p o r t( c l k:i ns t d _ l o g i c ; w e :i ns t d _ l o g i c ; a :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d i :i ns t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ) ; e n dr a m i n f r ; a r c h i t e c t u r es y no fr a m i n f ri s t y p er a m _ t y p ei sa r r a y( 3 1d o w n t o0 ) o fs t d _ l o g i c _ v e c t o r( 3d o w n t o0 ) ; s i g n a lR A M:r a m _ t y p e ; b e g i n p r o c e s s( c l k ) b e g i n i f( c l k ' e v e n ta n dc l k=' 1 ' )t h e n i f( w e=' 1 ' )t h e n

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R A M ( c o n v _ i n t e g e r ( a ) )< =d i ; e n di f ; e n di f ; e n dp r o c e s s ; d o< =R A M ( c o n v _ i n t e g e r ( a ) ) ; e n ds y n ;

RAMs

Verilog Following is the Verilog code for a single-port RAM with asynchronous read.
m o d u l er a m i n f r( c l k ,w e ,a ,d i ,d o ) ; i n p u tc l k ; i n p u tw e ; i n p u t [ 4 : 0 ]a ; i n p u t [ 3 : 0 ]d i ; o u t p u t[ 3 : 0 ]d o ; r e g [ 3 : 0 ]r a m[ 3 1 : 0 ] ; a l w a y s@ ( p o s e d g ec l k )b e g i n i f( w e ) r a m [ a ]< =d i ; e n d a s s i g nd o=r a m [ a ] ; e n d m o d u l e

Single-Port RAM with "false" Synchronous Read

The following descriptions do not implement true synchronous read access as defined by the Virtex block RAM specification, where the read address is registered. They are only mappable onto Distributed RAM with an additional buffer on the data output, as shown below:

The following table shows pin descriptions for a single-port RAM with "false" synchronous read.
IO Pins Description

clk we a di do VHDL

Positive-Edge Clock Synchronous Write Enable (active High) Read/Write Address Data Input Data Output

Following is the VHDL code for a single-port RAM with "false" synchronous read.
l i b r a r yi e e e ; u s ei e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s ei e e e . s t d _ l o g i c _ u n s i g n e d . a l l ; e n t i t yr a m i n f ri s p o r t( c l k:i ns t d _ l o g i c ; w e :i ns t d _ l o g i c ; a :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d i :i ns t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ) ; e n dr a m i n f r ; a r c h i t e c t u r es y no fr a m i n f ri s t y p er a m _ t y p ei sa r r a y( 3 1d o w n t o0 ) o fs t d _ l o g i c _ v e c t o r( 3d o w n t o0 ) ; s i g n a lR A M:r a m _ t y p e ; b e g i n p r o c e s s( c l k ) b e g i n i f( c l k ' e v e n ta n dc l k=' 1 ' )t h e n i f( w e=' 1 ' )t h e n R A M ( c o n v _ i n t e g e r ( a ) )< =d i ; e n di f ; d o< =R A M ( c o n v _ i n t e g e r ( a ) ) ;

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e n di f ; e n dp r o c e s s ; e n ds y n ;

RAMs

Verilog Following is the Verilog code for a single-port RAM with "false" synchronous read.
m o d u l er a m i n f r( c l k ,w e ,a ,d i ,d o ) ; i n p u t c l k ; i n p u t w e ; i n p u t [ 4 : 0 ]a ; i n p u t [ 3 : 0 ]d i ; o u t p u t[ 3 : 0 ]d o ; r e g [ 3 : 0 ]r a m[ 3 1 : 0 ] ; r e g [ 3 : 0 ]d o ; a l w a y s@ ( p o s e d g ec l k )b e g i n i f( w e ) r a m [ a ]< =d i ; d o< =r a m [ a ] ; e n d e n d m o d u l e

The following descriptions, featuring an additional reset of the RAM output, are also only mappable onto Distributed RAM with an additional resetable buffer on the data output as shown in the following figure:

The following table shows pin descriptions for a single-port RAM with "false" synchronous read and reset on the output.
IO Pins Description

clk we rst a di do VHDL

Positive-Edge Clock Synchronous Write Enable (active High) Synchronous Output Reset (active High) Read/Write Address Data Input Data Output

Following is the VHDL code.

l i b r a r yi e e e ; u s ei e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s ei e e e . s t d _ l o g i c _ u n s i g n e d . a l l ; e n t i t yr a m i n f ri s p o r t( c l k:i ns t d _ l o g i c ; w e :i ns t d _ l o g i c ; r s t:i ns t d _ l o g i c ; a :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d i :i ns t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ) ; e n dr a m i n f r ; a r c h i t e c t u r es y no fr a m i n f ri s t y p er a m _ t y p ei sa r r a y( 3 1d o w n t o0 ) o fs t d _ l o g i c _ v e c t o r( 3d o w n t o0 ) ; s i g n a lR A M:r a m _ t y p e ; b e g i n p r o c e s s( c l k ) b e g i n i f( c l k ' e v e n ta n dc l k=' 1 ' )t h e n i f( w e=' 1 ' )t h e n R A M ( c o n v _ i n t e g e r ( a ) )< =d i ; e n di f ; i f( r s t=' 1 ' )t h e n d o< =( o t h e r s= >' 0 ' ) ;

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e l s e d o< =R A M ( c o n v _ i n t e g e r ( a ) ) ; e n di f ; e n di f ; e n dp r o c e s s ; e n ds y n ;

RAMs

Verilog Following the Verilog code.

m o d u l er a m i n f r( c l k ,w e ,r s t ,a ,d i ,d o ) ; i n p u tc l k ; i n p u tw e ; i n p u tr s t ; i n p u t [ 4 : 0 ]a ; i n p u t [ 3 : 0 ]d i ; o u t p u t[ 3 : 0 ]d o ; r e g [ 3 : 0 ]r a m[ 3 1 : 0 ] ; r e g [ 3 : 0 ]d o ; a l w a y s@ ( p o s e d g ec l k )b e g i n i f( w e ) r a m [ a ]< =d i ; i f( r s t ) d o< =4 ' b 0 ; e l s e d o< =r a m [ a ] ; e n d e n d m o d u l e

Single-Port RAM with Synchronous Read (Read Through)

The following description implements a true synchronous read. A true synchronous read is the synchronization mechanism available in Virtex block RAMs, where the read address is registered on the RAM clock edge. Such descriptions are directly mappable onto Block RAM, as shown below (The same descriptions can also be mapped onto Distributed RAM).

The following table shows pin descriptions for a single-port RAM with synchronous read (read through).
IO pins Description

clk we a di do VHDL

Positive-Edge Clock Synchronous Write Enable (active High) Read/Write Address Data Input Data Output

Following is the VHDL code for a single-port RAM with synchronous read (read through).
l i b r a r yi e e e ; u s ei e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s ei e e e . s t d _ l o g i c _ u n s i g n e d . a l l ; e n t i t yr a m i n f ri s p o r t( c l k:i ns t d _ l o g i c ; w e :i ns t d _ l o g i c ; a :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d i :i ns t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ) ; e n dr a m i n f r ; a r c h i t e c t u r es y no fr a m i n f ri s t y p er a m _ t y p ei sa r r a y( 3 1d o w n t o0 ) o fs t d _ l o g i c _ v e c t o r( 3d o w n t o0 ) ; s i g n a lR A M:r a m _ t y p e ; s i g n a lr e a d _ a:s t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ;

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b e g i n p r o c e s s( c l k ) b e g i n i f( c l k ' e v e n ta n dc l k=' 1 ' )t h e n i f( w e=' 1 ' )t h e n R A M ( c o n v _ i n t e g e r ( a ) )< =d i ; e n di f ; r e a d _ a< =a ; e n di f ; e n dp r o c e s s ; d o< =R A M ( c o n v _ i n t e g e r ( r e a d _ a ) ) ; e n ds y n ;

RAMs

Verilog Following is the Verilog code for a single-port RAM with synchronous read (read through).
m o d u l er a m i n f r( c l k ,w e ,a ,d i ,d o ) ; i n p u tc l k ; i n p u tw e ; i n p u t [ 4 : 0 ]a ; i n p u t [ 3 : 0 ]d i ; o u t p u t[ 3 : 0 ]d o ; r e g [ 3 : 0 ]r a m[ 3 1 : 0 ] ; r e g [ 4 : 0 ]r e a d _ a ; a l w a y s@ ( p o s e d g ec l k )b e g i n i f( w e ) r a m [ a ]< =d i ; r e a d _ a< =a ; e n d a s s i g nd o=r a m [ r e a d _ a ] ; e n d m o d u l e

Single-Port RAM with Enable

The following description implements a single-port RAM with a global enable.

The following table shows pin descriptions for a single-port RAM with enable.
IO pins Description

clk en we a di do VHDL

Positive-Edge Clock Global Enable Synchronous Write Enable (active High) Read/Write Address Data Input Data Output

Following is the VHDL code for a single-port block RAM with enable.
l i b r a r yi e e e ; u s ei e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s ei e e e . s t d _ l o g i c _ u n s i g n e d . a l l ; e n t i t yr a m i n f ri s p o r t( c l k:i ns t d _ l o g i c ; e n :i ns t d _ l o g i c ; w e :i ns t d _ l o g i c ; a :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d i :i ns t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ) ; e n dr a m i n f r ; a r c h i t e c t u r es y no fr a m i n f ri s t y p er a m _ t y p ei sa r r a y( 3 1d o w n t o0 ) o fs t d _ l o g i c _ v e c t o r( 3d o w n t o0 ) ;

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s i g n a lR A M:r a m _ t y p e ; s i g n a lr e a d _ a:s t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; b e g i n p r o c e s s( c l k ) b e g i n i f( c l k ' e v e n ta n dc l k=' 1 ' )t h e n i f( e n=' 1 ' )t h e n i f( w e=' 1 ' )t h e n R A M ( c o n v _ i n t e g e r ( a ) )< =d i ; e n di f ; r e a d _ a< =a ; e n di f ; e n di f ; e n dp r o c e s s ; d o< =R A M ( c o n v _ i n t e g e r ( r e a d _ a ) ) ; e n ds y n ;

RAMs

Verilog Following is the Verilog code for a single-port block RAM with enable.
m o d u l er a m i n f r( c l k ,e n ,w e ,a ,d i ,d o ) ; i n p u tc l k ; i n p u te n ; i n p u tw e ; i n p u t [ 4 : 0 ]a ; i n p u t [ 3 : 0 ]d i ; o u t p u t[ 3 : 0 ]d o ; r e g [ 3 : 0 ]r a m[ 3 1 : 0 ] ; r e g [ 4 : 0 ]r e a d _ a ; a l w a y s@ ( p o s e d g ec l k )b e g i n i f( e n ) b e g i n i f( w e ) r a m [ a ]< =d i ; r e a d _ a< =a ; e n d e n d a s s i g nd o=r a m [ r e a d _ a ] ; e n d m o d u l e

Dual-Port RAM with Asynchronous Read

The following example shows where the two output ports are used. It is directly mappable onto Distributed RAM only.

The following table shows pin descriptions for a dual-port RAM with asynchronous read.
IO pins Description

clk we a dpra di spo dpo VHDL

Positive-Edge Clock Synchronous Write Enable (active High) Write Address/Primary Read Address Dual Read Address Data Input Primary Output Port Dual Output Port

Following is the VHDL code for a dual-port RAM with asynchronous read.
l i b r a r yi e e e ; u s ei e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s ei e e e . s t d _ l o g i c _ u n s i g n e d . a l l ;

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e n t i t yr a m i n f ri s p o r t( c l k :i ns t d _ l o g i c ; w e :i ns t d _ l o g i c ; a :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d p r a:i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d i :i ns t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; s p o :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d p o :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ) ; e n dr a m i n f r ; a r c h i t e c t u r es y no fr a m i n f ri s t y p er a m _ t y p ei sa r r a y( 3 1d o w n t o0 ) o fs t d _ l o g i c _ v e c t o r( 3d o w n t o0 ) ; s i g n a lR A M:r a m _ t y p e ; b e g i n p r o c e s s( c l k ) b e g i n i f( c l k ' e v e n ta n dc l k=' 1 ' )t h e n i f( w e=' 1 ' )t h e n R A M ( c o n v _ i n t e g e r ( a ) )< =d i ; e n di f ; e n di f ; e n dp r o c e s s ; s p o< =R A M ( c o n v _ i n t e g e r ( a ) ) ; d p o< =R A M ( c o n v _ i n t e g e r ( d p r a ) ) ; e n ds y n ;

RAMs

Verilog Following is the Verilog code for a dual-port RAM with asynchronous read.
m o d u l er a m i n f r ( c l k ,w e ,a ,d p r a ,d i ,s p o ,d p o ) ; i n p u tc l k ; i n p u tw e ; i n p u t [ 4 : 0 ]a ; i n p u t [ 4 : 0 ]d p r a ; i n p u t [ 3 : 0 ]d i ; o u t p u t[ 3 : 0 ]s p o ; o u t p u t[ 3 : 0 ]d p o ; r e g [ 3 : 0 ]r a m[ 3 1 : 0 ] ; a l w a y s@ ( p o s e d g ec l k )b e g i n i f( w e ) r a m [ a ]< =d i ; e n d a s s i g ns p o=r a m [ a ] ; a s s i g nd p o=r a m [ d p r a ] ; e n d m o d u l e

Dual-Port RAM with False Synchronous Read

The following descriptions will be mapped onto Distributed RAM with additional registers on the data outputs. Please note that this template does not describe dual-port block RAM.

The following table shows pin descriptions for a dual-port RAM with false synchronous read.
IO Pins Description

clk we a dpra di spo dpo

Positive-Edge Clock Synchronous Write Enable (active High) Write Address/Primary Read Address Dual Read Address Data Input Primary Output Port Dual Output Port

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RAMs

VHDL Following is the VHDL code for a dual-port RAM with false synchronous read.
l i b r a r yi e e e ; u s ei e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s ei e e e . s t d _ l o g i c _ u n s i g n e d . a l l ; e n t i t yr a m i n f ri s p o r t( c l k :i ns t d _ l o g i c ; w e :i ns t d _ l o g i c ; a :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d p r a:i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d i :i ns t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; s p o :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d p o :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ) ; e n dr a m i n f r ; a r c h i t e c t u r es y no fr a m i n f ri s t y p er a m _ t y p ei sa r r a y( 3 1d o w n t o0 ) o fs t d _ l o g i c _ v e c t o r( 3d o w n t o0 ) ; s i g n a lR A M:r a m _ t y p e ; b e g i n p r o c e s s( c l k ) b e g i n i f( c l k ' e v e n ta n dc l k=' 1 ' )t h e n i f( w e=' 1 ' )t h e n R A M ( c o n v _ i n t e g e r ( a ) )< =d i ; e n di f ; s p o< =R A M ( c o n v _ i n t e g e r ( a ) ) ; d p o< =R A M ( c o n v _ i n t e g e r ( d p r a ) ) ; e n di f ; e n dp r o c e s s ; e n ds y n ;

Verilog Following is the Verilog code for a dual-port RAM with false synchronous read.
m o d u l er a m i n f r ( c l k ,w e ,a ,d p r a ,d i ,s p o ,d p o ) ; i n p u tc l k ; i n p u tw e ; i n p u t [ 4 : 0 ]a ; i n p u t [ 4 : 0 ]d p r a ; i n p u t [ 3 : 0 ]d i ; o u t p u t[ 3 : 0 ]s p o ; o u t p u t[ 3 : 0 ]d p o ; r e g [ 3 : 0 ]r a m[ 3 1 : 0 ] ; r e g [ 3 : 0 ]s p o ; r e g [ 3 : 0 ]d p o ; a l w a y s@ ( p o s e d g ec l k )b e g i n i f( w e ) r a m [ a ]< =d i ; s p o=r a m [ a ] ; d p o=r a m [ d p r a ] ; e n d e n d m o d u l e

Dual-Port RAM with Synchronous Read (Read Through)

The following descriptions are directly mappable onto Block RAM, as shown in the following figure. (They may also be implemented with Distributed RAM.).

The following table shows pin descriptions for a dual-port RAM with synchronous read (read through).
IO Pins Description

clk we a

Positive-Edge Clock Synchronous Write Enable (active High) Write Address/Primary Read Address
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RAMs

dpra di spo dpo VHDL

Dual Read Address Data Input Primary Output Port Dual Output Port

Following is the VHDL code for a dual-port RAM with synchronous read (read through).
l i b r a r yi e e e ; u s ei e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s ei e e e . s t d _ l o g i c _ u n s i g n e d . a l l ; e n t i t yr a m i n f ri s p o r t( c l k :i ns t d _ l o g i c ; w e :i ns t d _ l o g i c ; a :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d p r a:i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d i :i ns t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; s p o :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d p o :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ) ; e n dr a m i n f r ; a r c h i t e c t u r es y no fr a m i n f ri s t y p er a m _ t y p ei sa r r a y( 3 1d o w n t o0 ) o fs t d _ l o g i c _ v e c t o r( 3d o w n t o0 ) ; s i g n a lR A M:r a m _ t y p e ; s i g n a lr e a d _ a:s t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; s i g n a lr e a d _ d p r a:s t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; b e g i n p r o c e s s( c l k ) b e g i n i f( c l k ' e v e n ta n dc l k=' 1 ' )t h e n i f( w e=' 1 ' )t h e n R A M ( c o n v _ i n t e g e r ( a ) )< =d i ; e n di f ; r e a d _ a< =a ; r e a d _ d p r a< =d p r a ; e n di f ; e n dp r o c e s s ; s p o< =R A M ( c o n v _ i n t e g e r ( r e a d _ a ) ) ; d p o< =R A M ( c o n v _ i n t e g e r ( r e a d _ d p r a ) ) ; e n ds y n ;

Verilog Following is the Verilog code for a dual-port RAM with synchronous read (read through).
m o d u l er a m i n f r ( c l k ,w e ,a ,d p r a ,d i ,s p o ,d p o ) ; i n p u tc l k ; i n p u tw e ; i n p u t [ 4 : 0 ]a ; i n p u t [ 4 : 0 ]d p r a ; i n p u t [ 3 : 0 ]d i ; o u t p u t[ 3 : 0 ]s p o ; o u t p u t[ 3 : 0 ]d p o ; r e g [ 3 : 0 ]r a m[ 3 1 : 0 ] ; r e g [ 4 : 0 ]r e a d _ a ; r e g [ 4 : 0 ]r e a d _ d p r a ; a l w a y s@ ( p o s e d g ec l k )b e g i n i f( w e ) r a m [ a ]< =d i ; r e a d _ a< =a ; r e a d _ d p r a< =d p r a ; e n d a s s i g ns p o=r a m [ r e a d _ a ] ; a s s i g nd p o=r a m [ r e a d _ d p r a ] ; e n d m o d u l e

N o t e T h et w oR A Mp o r t sm a yb es y n c h r o n i z e do nd i s t i n c tc l o c k s ,a ss h o w ni nt h ef o l l o w i n gd e s c r i p t i o n .I nt h i sc a s e ,o n l yaB l o c kR A Mi m p l

The following table shows pin descriptions for a dual-port RAM with synchronous read (read through) and two clocks.
IO pins Description

clk1 clk2 we add1

Positive-Edge Write/Primary Read Clock Positive-Edge Dual Read Clock Synchronous Write Enable (active High) Write/Primary Read Address
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RAMs

add2 di do1 do2 VHDL

Dual Read Address Data Input Primary Output Port Dual Output Port

Following is the VHDL code.

l i b r a r yi e e e ; u s ei e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s ei e e e . s t d _ l o g i c _ u n s i g n e d . a l l ; e n t i t yr a m i n f ri s p o r t( c l k 1:i ns t d _ l o g i c ; c l k 2:i ns t d _ l o g i c ; w e :i ns t d _ l o g i c ; a d d 1:i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; a d d 2:i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d i :i ns t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o 1 :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o 2 :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ) ; e n dr a m i n f r ; architecture syn of raminfr is t y p er a m _ t y p ei sa r r a y( 3 1d o w n t o0 ) o fs t d _ l o g i c _ v e c t o r( 3d o w n t o0 ) ; s i g n a lR A M:r a m _ t y p e ; s i g n a lr e a d _ a d d 1:s t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; s i g n a lr e a d _ a d d 2:s t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; b e g i n p r o c e s s( c l k 1 ) b e g i n i f( c l k 1 ' e v e n ta n dc l k 1=' 1 ' )t h e n i f( w e=' 1 ' )t h e n R A M ( c o n v _ i n t e g e r ( a d d 1 ) )< =d i ; e n di f ; r e a d _ a d d 1< =a d d 1 ; e n di f ; e n dp r o c e s s ; d o 1< =R A M ( c o n v _ i n t e g e r ( r e a d _ a d d 1 ) ) ; p r o c e s s( c l k 2 ) b e g i n i f( c l k 2 ' e v e n ta n dc l k 2=' 1 ' )t h e n r e a d _ a d d 2< =a d d 2 ; e n di f ; e n dp r o c e s s ; d o 2< =R A M ( c o n v _ i n t e g e r ( r e a d _ a d d 2 ) ) ; e n ds y n ;

Verilog Following is the Verilog code.

m o d u l er a m i n f r ( c l k ,e n ,w e ,a d d r a ,a d d r b ,d i ,d o a ,d o b ) ; i n p u tc l k ; i n p u te n ; i n p u tw e ; i n p u t[ 4 : 0 ]a d d r a ; i n p u t[ 4 : 0 ]a d d r b ; i n p u t[ 3 : 0 ]d i ; o u t p u t[ 3 : 0 ]d o a ; o u t p u t[ 3 : 0 ]d o b ; r e g[ 3 : 0 ]r a m[ 3 1 : 0 ] ; r e g[ 4 : 0 ]r e a d _ a d d r a ; r e g[ 4 : 0 ]r e a d _ a d d r b ; a l w a y s@ ( p o s e d g ec l k )b e g i n i f( e n ) b e g i n i f( w e ) r a m [ a d d r a ]< =d i ; r e a d _ a d d r a< =a d d r a ; r e a d _ a d d r b< =a d d r b ; e n d e n d a s s i g nd o a=r a m [ r e a d _ a d d r a ] ; a s s i g nd o b=r a m [ r e a d _ a d d r b ] ; e n d m o d u l e

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RAMs

Dual-Port RAM with One Enable Controlling Both Ports

The following descriptions are directly mappable onto Block RAM, as shown in the following figure.

The following table shows pin descriptions for a dual-port RAM with synchronous read (read through).
IO Pins Description

clk en we addra addrb di doa dob VHDL

Positive-Edge Clock Primary Global Enable (active High) Primary Synchronous Write Enable (active High) Write Address/Primary Read Address Dual Read Address Primary Data Input Primary Output Port Dual Output Port

Following is the VHDL code for a dual-port RAM with one global enable controlling both ports.
l i b r a r yi e e e ; u s ei e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s ei e e e . s t d _ l o g i c _ u n s i g n e d . a l l ; e n t i t yr a m i n f ri s p o r t( c l k :i ns t d _ l o g i c ; e n :i ns t d _ l o g i c ; w e :i ns t d _ l o g i c ; a d d r a :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; a d d r b :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d i :i ns t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o a :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o b :o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ) ; e n dr a m i n f r ; a r c h i t e c t u r es y no fr a m i n f ri s t y p er a m _ t y p ei sa r r a y( 3 1d o w n t o0 ) o fs t d _ l o g i c _ v e c t o r( 3d o w n t o0 ) ; s i g n a lR A M:r a m _ t y p e ; s i g n a lr e a d _ a d d r a:s t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; s i g n a lr e a d _ a d d r b:s t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; b e g i n p r o c e s s( c l k ) b e g i n i f( c l k ' e v e n ta n dc l k=' 1 ' )t h e n i f( e n=' 1 ' )t h e n i f( w e=' 1 ' )t h e n R A M ( c o n v _ i n t e g e r ( a d d r a ) )< =d i ; e n di f ; r e a d _ a d d r a< =a d d r a ; r e a d _ a d d r b< =a d d r b ; e n di f ; e n di f ; e n dp r o c e s s ; d o a< =R A M ( c o n v _ i n t e g e r ( r e a d _ a d d r a ) ) ; d o b< =R A M ( c o n v _ i n t e g e r ( r e a d _ a d d r b ) ) ; e n ds y n ;

Verilog Following is the Verilog code for a dual-port RAM with one global enable controlling both ports.
m o d u l er a m i n f r ( c l k ,e n ,w e ,a d d r a ,a d d r b , d i ,d o a ,d o b ) ;

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i n p u tc l k ; i n p u te n ; i n p u tw e ; i n p u t [ 4 : 0 ]a d d r a ; i n p u t [ 4 : 0 ]a d d r b ; i n p u t [ 3 : 0 ]d i ; o u t p u t[ 3 : 0 ]d o a ; o u t p u t[ 3 : 0 ]d o b ; r e g r e g r e g [ 3 : 0 ]r a m[ 3 1 : 0 ] ; [ 4 : 0 ]r e a d _ a d d r a ; [ 4 : 0 ]r e a d _ a d d r b ;

RAMs

a l w a y s@ ( p o s e d g ec l k )b e g i n i f( e n a ) b e g i n i f( w e a ) r a m [ a d d r a ]< =d i ; r e a d _ a a d d r a< =a d d r a ; r e a d _ a a d d r b< =a d d r b ; e n d e n d a s s i g nd o a=r a m [ r e a d _ a d d r a ] ; a s s i g nd o b=r a m [ r e a d _ a d d r b ] ; e n d m o d u l e

Dual-Port RAM with Enable on Each Port

The following descriptions are directly mappable onto Block RAM, as shown in the following figure.

The following table shows pin descriptions for a dual-port RAM with synchronous read (read through).
IO Pins Description

clk ena enb wea addra addrb dia doa dob VHDL

Positive-Edge Clock Primary Global Enable (active High) Dual Global Enable (active High) Primary Synchronous Write Enable (active High) Write Address/Primary Read Address Dual Read Address Primary Data Input Primary Output Port Dual Output Port

Following is the VHDL code for a dual-port RAM with global enable
l i b r a r yi e e e ; u s ei e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s ei e e e . s t d _ l o g i c _ u n s i g n e d . a l l ; e n t i t yr a m i n f ri s p o r t( c l k :i ns t d _ l o g i c ; e n a :i ns t d _ l o g i c ; e n b :i ns t d _ l o g i c ; w e a :i ns t d _ l o g i c ; a d d r a :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; a d d r b :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d i a :i ns t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o a:o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o b:o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ) ;

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e n dr a m i n f r ; a r c h i t e c t u r es y no fr a m i n f ri s t y p er a m _ t y p ei sa r r a y( 3 1d o w n t o0 ) o fs t d _ l o g i c _ v e c t o r( 3d o w n t o0 ) ; s i g n a lR A M:r a m _ t y p e ; s i g n a lr e a d _ a d d r a:s t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; s i g n a lr e a d _ a d d r b:s t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; b e g i n p r o c e s s( c l k ) b e g i n i f( c l k ' e v e n ta n dc l k=' 1 ' )t h e n i f( e n a=' 1 ' )t h e n i f( w e a=' 1 ' )t h e n R A M( c o n v _ i n t e g e r ( a d d r a ) )< =d i a ; e n di f ; r e a d _ a d d r a< =a d d r a ; e n di f ; i f( e n b=' 1 ' )t h e n r e a d _ a d d r b< =a d d r b ; e n di f ; e n di f ; e n dp r o c e s s ; d o a< =R A M ( c o n v _ i n t e g e r ( r e a d _ a d d r a ) ) ; d o b< =R A M ( c o n v _ i n t e g e r ( r e a d _ a d d r b ) ) ; e n ds y n ;

RAMs

Verilog Following is the Verilog code for a dual-port RAM with synchronous read (read through).
m o d u l er a m i n f r ( c l k , e n a , e n b , w e a , a d d r a , a d d r b , d i a , d o a , d o b ) ; i n p u tc l k ; i n p u te n a ; i n p u te n b ; i n p u tw e a ; i n p u t[ 4 : 0 ]a d d r a ; i n p u t[ 4 : 0 ]a d d r b ; i n p u t[ 3 : 0 ]d i a ; o u t p u t[ 3 : 0 ]d o a ; o u t p u t[ 3 : 0 ]d o b ; r e g[ 3 : 0 ]r a m[ 3 1 : 0 ] ; r e g[ 4 : 0 ]r e a d _ a d d r a ; r e g[ 4 : 0 ]r e a d _ a d d r b ; a l w a y s@ ( p o s e d g ec l k )b e g i n i f( e n a ) b e g i n i f( w e a ) r a m [ a d d r a ]< =d i a ; r e a d _ a d d r a< =a d d r a ; e n d i f( e n b ) r e a d _ a d d r b< =a d d r b ; e n d a s s i g nd o a=r a m [ r e a d _ a d d r a ] ; a s s i g nd o b=r a m [ r e a d _ a d d r b ] ; e n d m o d u l e

Multiple-Port RAM Descriptions

XST can identify RAM descriptions with two or more read ports that access the RAM contents at addresses different from the write address. However, there can only be one write port. The following descriptions will be implemented by replicating the RAM contents for each output port, as shown:

The following table shows pin descriptions for a multiple-port RAM.

IO pins Description

clk we

Positive-Edge Clock Synchronous Write Enable (active High)

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RAMs

wa ra1 ra2 di do1 do2 VHDL

Write Address Read Address of the first RAM Read Address of the second RAM Data Input First RAM Output Port Second RAM Output Port

Following is the VHDL code for a multiple-port RAM.

l i b r a r yi e e e ; u s ei e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s ei e e e . s t d _ l o g i c _ u n s i g n e d . a l l ; e n t i t yr a m i n f ri s p o r t( c l k:i ns t d _ l o g i c ; w e :i ns t d _ l o g i c ; w a :i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; r a 1:i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; r a 2:i ns t d _ l o g i c _ v e c t o r ( 4d o w n t o0 ) ; d i :i ns t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o 1:o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ; d o 2:o u ts t d _ l o g i c _ v e c t o r ( 3d o w n t o0 ) ) ; e n dr a m i n f r ; a r c h i t e c t u r es y no fr a m i n f ri s t y p er a m _ t y p ei sa r r a y( 3 1d o w n t o0 ) o fs t d _ l o g i c _ v e c t o r( 3d o w n t o0 ) ; s i g n a lR A M:r a m _ t y p e ; b e g i n p r o c e s s( c l k ) b e g i n i f( c l k ' e v e n ta n dc l k=' 1 ' )t h e n i f( w e=' 1 ' )t h e n R A M ( c o n v _ i n t e g e r ( w a ) )< =d i ; e n di f ; e n di f ; e n dp r o c e s s ; d o 1< =R A M ( c o n v _ i n t e g e r ( r a 1 ) ) ; d o 2< =R A M ( c o n v _ i n t e g e r ( r a 2 ) ) ; e n ds y n ;

Verilog Following is the Verilog code for a multiple-port RAM.

m o d u l er a m i n f r ( c l k ,w e ,w a ,r a 1 ,r a 2 ,d i ,d o 1 ,d o 2 ) ; i n p u tc l k ; i n p u tw e ; i n p u t [ 4 : 0 ]w a ; i n p u t [ 4 : 0 ]r a 1 ; i n p u t [ 4 : 0 ]r a 2 ; i n p u t [ 3 : 0 ]d i ; o u t p u t[ 3 : 0 ]d o 1 ; o u t p u t[ 3 : 0 ]d o 2 ; r e g [ 3 : 0 ]r a m[ 3 1 : 0 ] ; a l w a y s@ ( p o s e d g ec l k )b e g i n i f( w e ) r a m [ w a ]< =d i ; e n d a s s i g nd o 1=r a m [ r a 1 ] ; a s s i g nd o 2=r a m [ r a 2 ] ; e n d m o d u l e

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