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Evolvable Hardware Applied to Nanotechnology

Omar Paranaiba Vilela Neto


Department of Electrical Engineering, PUC-Rio Rio de Janeiro, Brazil omar@ele.puc-rio.br

Leone Pereira Masiero


Department of Electrical Engineering, PUC-Rio Rio de Janeiro, Brazil masiero@ele.puc-rio.br

Marco Aurlio C. Pacheco


Department of Electrical Engineering, PUC-Rio Rio de Janeiro, Brazil marco@ele.puc-rio.br

Carlos R. Hall Barbosa


Post Graduation Program in Metrology, PUC-Rio Rio de Janeiro, Brazil hall@ele.puc-rio.br

Abstract
This manuscript proposes the automatic design and synthesis of nanometer circuits and the optimization of molecular devices by the evolvable hardware technique. The potential of Evolvable Hardware is investigated by means of three different applications: synthesis of molecular electronic circuits, synthesis and optimization of Quantum-dot Cellular Automata (QCA) and the optimization of OLED (Organic LightEmitting Diodes) parameters. The molecular electronic circuit synthesis is developed using the molecular transistor simulated in SPICE. QCA is a new paradigm used in the development of digital logical circuits, not using the flow of current. This new paradigm allows the development of a new generation of computers, faster and with smaller energy dissipation. Finally, the optimization of OLED parameters is developed using the electrical behavior model of a multi-layer device. In this model, each sub-layer in the emissive layer has a ratio of ETM (Electron Transport Material) and a ratio of HTM (Hole Transport Material). The first results show that the technique is able to synthesize and optimize circuits that perform the logic specified by the user, avoiding noise and other problems that could lead to malfunction. Moreover, the EHW technique is able to optimize the parameters of an organic device, such as OLED.

1. Introduction
This manuscript focuses on the integration of two distinct areas, Nanotechnology and Evolvable Hardware, aiming at improving the development of nanometer computational systems.

Gordon Moore has predicted, in 1965, that the capacity of a computer chip would grow exponentially with time. Since then, the so-called Moores Law had governed the development and performance of microprocessors. All the present success in the area has been achieved due to the miniaturization of transistors, descendants of electromechanical switches on the role of codifying digital information. The use of transistors allowed the development of the electronic circuit technology. However, this technology presents serious drawbacks as device sizes are reduced. One of these problems is the interconnection because distributing signals over large distances involves charging long lines. Remarkable complexity attends the routing of signals on multiple levels. On the other hand, as transistors become smaller, the quantization of charge both in the channel and in the doping layer becomes significant. Finally, current switching results in huge energy dissipation. Also, recent studies show that the spatial limits of conventional electronics will be reached in the next few years and, as a consequence, the continuous development of the area is threatened [1]. Thus, in order to maintain the exponential growth predicted by Moore, it is necessary to study new computational technologies that leverage the quantum effects present in the nanometer scale, in order to define a better way to codify digital information. In this manuscript, two transistorless approaches have been studied and their architecture problems solved by the Evolvable Hardware techniques. Moreover, a large number of devices, in the nanometer scale, have been developed, allowing a great variety of new applications. This manuscript shows the use of Evolvable Hardware techniques to the optimization of Organic Light emitting diodes (OLED), increasing the efficiency.

Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) 0-7695-2614-4/06 $20.00 2006 IEEE

Evolvable Hardware (EHW) refers to circuit or device design and optimization using reconfigurable systems under the control of Genetic Algorithms. In this technique a search and optimization algorithm is employed, having as inputs all possible circuits or devices that can be defined in the search space and providing as solution the implementation of the desired circuit or device. The application of the EHW technique has already shown a significant success on the design of conventional and unconventional circuits [2]. However, the technique has not been thoroughly explored yet on the synthesis and optimization of nanometer circuits and devices, having the potential to be a highly useful tool, allowing a faster development of nanoelectronics. This manuscript presents some applications in the nanotechnology area using Evolvable Hardware Techniques. The main objective is to demonstrate that the computational intelligence techniques are useful tools in the development of new technologies, allowing their optimization. It is structured as follows: section 2 presents an application using EHW and Quantum-Dots Cellular Automata (QCA). Section 3 introduces the synthesis of molecular circuits. Section 4 discusses the use of EHW to optimize OLED parameters. Finally, the section 5 concludes the work and presents future works.

2. EHW applied to QCA


As an alternative to the CMOS-VLSI technology, it has been proposed in 1993 the Quantum-dots Cellular Automata (QCA) paradigm. Differently from the traditional computers, which use the flow of electrical current to transfer information, the QCA technology transfer information by means of the state of polarization of the cells [3][4][5]. QCA is based on binary coding, due to the configuration of charges in the quantum dot cells. All the computational power is provided by the Coulomb interaction between cells, and there is no electrical current flow between cells. Being QCA a new technology, much work is still to be done. Preliminary experimental results have already shown QCA as a viable alternative to the present technologies. QCA cells and some simple devices have already been successfully developed [6][7][8]. Even though the physical implementation of such devices is still being developed, it is necessary to perform studies about the architecture of QCA circuits, in order to anticipate the design of complex computational systems. The design of new logical devices is a non-trivial task because the functionality of QCA circuits is

extremely dependent on the cell positioning and the topology is very different from the traditional circuits. In order to a circuit work correctly, each cell must be placed in such a way that it leverages the interaction with its neighboring cells, thus creating the logical behavior that is necessary to the global functioning of the circuit. To synthesize correct circuits we have used Evolvable Hardware EHW techniques. The goal of this experiment is to evolve a multiplexer with two inputs. The third input is the multiplexer selector. For the synthesis of the multiplexer, the circuit has an additional input cell fixed at binary 1. To the automatic synthesis of the multiplexer, a grid of three Pentiums 4 2.2GHz running in parallel was used. One of these PCs also controls the GA and distributes the simulation to the other computers. The time necessary for ten trials was less than seven hours and in this case more than eighty thousands solutions were evaluated, as we used a coevolutionary approach to evolve the topology and the clocking zone of the circuit. The GA parameters are shown below: Generations: 200 Population: 100 Initial Crossover Rate: 0.9 Final Crossover Rate: 0.75 Initial Mutation Rate: 0.2 Final Mutation Rate: 0.5 GAP: 20% The evaluation function counts the number of hits of the logical gate for all 8 possible input sets. However, in this case a penalty is applied to individuals (solutions) that commit errors when the desired output is zero, in order to avoid the GA to be stuck in local minima, as explained in [2]. In Figure 1, the evolution can be observed by the graph which shows the average fitness of the best individual by generation, in a total of 10 experiments with 200 generations. The minimal fitness value for an individual with the fully correct logic is eight. Observe that the GA finds the correct logic in the fiftieth generation. On the other hand, the random search, on average, didnt reach the correct logic.

Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) 0-7695-2614-4/06 $20.00 2006 IEEE

average of 10 runs
10,0 9,5 9,0 8,5 8,0 7,5 7,0 6,5 6,0 5,5 1 17 33 49 65 81 97 113 129 145 161 177 193
GA
Random

Figure 1: Average best individual by generation.

In this experiment, the GA has found the correct logic in 9 out of 10 experiments, whilst the random search has obtained success in only 4 experiments out of 10. Fig. 2 shows the topology of the best circuit found by the GA, containing 14 cells. For comparison purposes, Fig. 3 shows the topology considered in [10], with 21 cells. Clearly, the circuit synthesized by the GA is smaller and more compact. These features are important in the development of QCA circuits. Smaller circuits have the advantage of being faster and presenting high probabilities of working properly, avoiding the thermo dynamical effects discussed in [5]. Moreover, more compact circuits allow creating denser circuits, using less space to create the logical designs.

Figure 3: Topology of the multiplexer proposed by Niemier [9].

3. Synthesis of Robust Molecular Circuits


The synthesis of molecular circuits involves the use of molecular devices and techniques for the implementation of circuits. The concept of information processing through molecular structures is very complex therefore the main problem is to synthesize robust and efficient molecular systems, due to the variation on the behavior of molecular devices [10]. Thus, the use of techniques that take in consideration such restrictions is desired. The molecular structure studied and used (in simulation) to synthesize molecular circuits was the Molecular Transistor [11], and the technique used for the automatic synthesis was the Evolvable Hardware. Each curve in Figure 4 represents the calculated transistor curve variations.
8 x 10
-11

Current(Ampere)

Figure 2: Topology of the best multiplexer found. The gray scales represent the clocking zones.

0 0

0.5

1.5 Power(Volts)

2.5

Figure 4: Variation of the molecular transistor curve

Each individual of the GA represents a topology of a circuit. To carry this representation, it was developed a technique called adjacency cube, based on the adjacency matrix technique [12]. The adjacency matrix

Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) 0-7695-2614-4/06 $20.00 2006 IEEE

technique is used to represent circuits containing only components with two terminals. The adjacency cube technique is used to represent circuits containing components with two and three terminals. This technique is summarized below. In the adjacency matrix technique, the position of each component in the circuit is represented by one specific position in the matrix, where the line and the column of such position in the matrix represent the two terminals of the component in the circuit. For example, a matrix with dimensions 4x4 represents circuits with 3 nodes and the ground. Then, the element (1, 2) of the matrix (line 1 and column 2) represents a component that is connected between nodes 1 and 2. The adjacency cube, that is the overlapping of several adjacency matrices, can represent components of three terminals. Each dimension of the cube (line, column and depth) represents a terminal of the component in the circuit, as well as in the adjacency matrix. For example, a cube with dimensions 5x5x5 represents circuits with 4 nodes and the ground. The element (2, 3, 1) of the cube (line 2, column 3 and depth 1) represents a component whose terminals are connected to nodes 2, 3 and 1 of the circuit, respectively. The synthesis of a robust inverter was carried through by 4 different experiments: random evolutionary, random co-evolutionary, evolutionary and co-evolutionary. To guarantee the robustness, each circuit was evaluated using each variation of the curve of the used molecular transistor. The parameters used in this experiment are presented: Generations: 100 Population: 100 Initial Crossover Rate: 0.8 Final Crossover Rate: 0.75 Initial Mutation Rate: 0.8 Final Mutation Rate: 0.9 GAP: 20% The fitness of each chromosome is calculated taking into account each variation of the molecular transistor curve. Figure 5 presents the final circuit and Figure 6 present the input and output curves of the circuit for one variation of the molecular transistor curve. The curves for the other two curves of the molecular transistor are quite the same, showing that the synthesized circuit is robust. Figure 7 presents the curves of evolution for each type of experiment and table 1 presents the values of the components of the circuit shown in figure 5.

Figure 5: Final circuit using the adjacency cube with molecular transistor curve variation.

Figure 6: Output curve of the circuit in figure 5 using the left curve of figure 4.

Figure 7: Average best individual by generation. Component Value R1 1K R2 1K Rload ~340M Table 1: Components value.

Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) 0-7695-2614-4/06 $20.00 2006 IEEE

4. OLED Parameters Optimization


Normally, the process of molecular devices development involves two stages: the chemical stage, where the molecules are synthesized, and the physical stage, where their electrical properties are studied. The study and the optimization of OLED (Organic LightEmitting Diode) parameters are associated to the physical stage of the development process. Essentially, the structure of an OLED consists of two electrodes and an emissive layer between them. This layer contains organic light emitting material of two types, called Electron Transporting Material (ETM) and Hole Transporting Material (HTM). The structure of the OLED is shown in Figure 8.

Some mathematical models of the OLEDs electric behavior have been elaborated, as it can be seen in [16] and [17], where a device can be characterized by a set of parameters. Depending on the model, the configuration of the parameters represents one specific characteristic of a device and the parameters optimization depends on the structure of each device. Considering one specific model [16], the optimization is made taking into consideration a structure whose emissive layer has sub-layers, as shown in the Figure 9, and each sub-layer has a ratio of ETM to HTM (for example, one part of ETM for five parts of HTM).

Figure 9: Sub-layer structure device.

Figure 8: Basic OLED Model.

Electroluminescence is the principle of the OLED functioning and its main element is the exciton. An exciton consists on a excited pair electron-hole and is generated inside the emissive layer. When the electron and the hole of one exciton combine, a photon can be emitted. The main challenge in the OLED functioning is to maximize the number of combinations of electron and holes in the emissive layer. But, in an organic composition, the mobility of the holes is much bigger than the mobility of electrons (the term mobility is used to describe the relation between the electron speed and holes speed in a solid material). An exciton can be in one of its two states, singleton and tripleton. One exciton out of four is in a singleton stage. The materials currently used in the emissive layer are typically fluorescent and can only emit light when one exciton is created in the state of singleton. This feature reduces the efficiency of the OLED. To create excitons, a thin film of organic material is placed between electrodes of different work functions, being this thin film the emissive layer. Electrons are injected in the cathode side while holes are injected in the anode side. The electron and the hole move into the emissive layer and can combine to form an exciton [13][14][15].

Therefore, a GA was developed to search devices that have the smaller possible ratio between the applied voltage and current flow. The chromosome representation of the GA determines the ratio of each material (ETM and HTM) in a sub-layer. The ratio of each material is represented by the number of parts that the material can have in relation to the other material. In this work, each material can have at least one part and at most 20 parts in relation to the other material in a sub-layer. Considering that two neighboring layers cannot contain, for each material, a difference bigger than one to five, implying in a restriction in the GA, the structure of the chromosome was defined in the following form: the first two genes contain the values that define the ratio of material on the first internal sub-layer close to the cathode (the external sub-layers only have one type of material, that is, close to the cathode there is only ETM and close to the anode there is only HTM). The remaining genes that correspond to remaining internal sub-layers have values that define the differences between consecutive layers. This difference can be at most equal to 5. Figure 10 illustrates an example of a chromosome representing a device with 5 internal sub-layers.

Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) 0-7695-2614-4/06 $20.00 2006 IEEE

Figure 10: A chromosome with 5 internal sub-layers.

In order to respect the minimum and maximum ratios of material, special genetic operators have been implemented. If a value of a gene implies in a ratio out of the established limits, the signal of this gene is inverted. Using the proposed GA, the results of the experiments were compared with the results presented in table 1 in [16]. Like the results of table 1, five experiments had been carried out varying the values of n and n'. In all experiments, the following parameters of the modeling of the electric behavior and the GA have been used: Electric behavior model parameters: Number of internal sub-layers: 5; Sub-layer width: 10 nm; ETM: Alq3 (e = 1x10-5 cm2/(V.s) e p = 1x10-7 cm2/(V.s)); HTM: NPB (e = 1x10-7 cm2/(V.s) e p = 2x10-4 cm2/(V.s)); Dielectric constant: 3.5 for both pure Alq3 and NPB; Ba: 0.015; Bc: 0.985; The GA parameters used in this experiment are: Generations: 50 Population: 30 Initial Crossover Rate: 0.9 Final Crossover Rate: 0.8 Initial Mutation Rate: 0.3 Final Mutation Rate: 0.5 Initial GAP: 40% Final GAP: 20% Figure 11 presents the evolution average curve of 10 experiments with values of n and n' equal to 2 where the best individual has the configuration 15:5, 14:8, 18:3, 15:6, 13:1 and the value of V/J1/2 is equal to 3,35x10-2.

Figure 11: The evolution curve of the experiment.

As it can be seen in the evolution curve, the indicated values are referring to 1/(V/J1/2), therefore the objective of the GA is to minimize the value of V/J1/2. Table 2 presents the values of V/J1/2 obtained in this work and the values found in table 1 of [16]. n 1 2 1.5 1.5 1 n 1 2 1,5 2 2 V/J1/2 in [16] 22.8 18.0 20.3 19.3 20.9 V/J1/2 obtained 4.66x10-4 3.35x10-2 4.38x10-3 9.86x10-3 2.85x10-2

Table 2: results obtained in [16] and in this work.

5. Conclusion
In this manuscript, the use of EHW techniques on the automatic synthesis and optimization of QCA circuits, synthesis of molecular circuits and optimization of OLED parameters has been proposed and tested. Basic logic circuits and optimized devices have been successfully evolved, with correct functionality and optimized designs. Being a new technology, the nanometer circuits and devices are not clearly established yet. Evolutionary techniques are support tools that, as shown in this work, can aid in the development of correct circuits and devices, avoiding noise and other undesired interferences that could lead to malfunction. The correct use of EHW techniques allows the user to create circuits and devices that have been until now difficult to synthesize. The well succeeded application of the EHW technique on the synthesis of CMOS circuits, together with the good results found in this work, indicate that this technique can be extended to synthesize other nanometer circuits and devices, thus giving momentum to the technological development.

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Tracing a parallel between Semiconductor Electronics and Nanotechnology, 58 years ago the transistor was created, a silicon based micro-structure, which led to the huge technological and scientific advances now observed in the 21st century. In a much shorter period, science will master nanotechnology up to a degree that will allow advances infinitely superior to the semiconductor devices. In this sense, Evolvable Hardware offers tools that aid the development of this field. In this paper, the first results show that this design approach can be able to find efficient novel designs, leading to a faster development of nanometer circuits architecture and devices. We believe that much physical space and working time can be saved in the development of complex circuits, such as a complete processor, by using evolutionary design.

[7] Amlani, I., et al, Digital logic gate using quantum-dot cellular automata, Science. 1999, 289-291. [8] G. L. Snider et al, Experimental demonstration of quantum-dot cellular automata, Semicond.. Sci. Technol., 13, UK 1998, A130-A134. [9] M. Niemier.: Design Digital Systems in Quantum Cellular Automata, Masters thesis, University of Notre Dame, April 2000. [10] Masiero, L. P., Pacheco, M. A. C., Barbosa, C. R. H., Santini, C. C. Molecular circuit design, 2005 NASA/DoD Conference on Evolvable Hardware (EH05) pp. 307-312. [11] Piva, P. G. et al. Field regulation of single-molecule conductivity by a charged surface atom, Department of Physics, University of Alberta - Canada, National Institute for Nanotechnology, National Research Council of Canada Canada, Surface Science Research Centre, University of Liverpool UK. [12] Mesquita, A.; Salazar, F. A.; Canazio, P. P. Chromosome representation through adjacency matrix in evolutionary circuits synthesis, 2002 NASA/DoD Conference on Evolvable Hardware (EH02) pp. 102. [13] M. A. Baldo et al. APL, 75, 4 (1999). [14] M. A. Baldo et al., Nature, 395, 151 (1998). [15] C. Adachi et al., JAP, 90, 5048 (2001). [16] Gusso, A. et al., Modeling of organic light-emitting diodes with graded concentration in the emissive multilayer, Journal of Applied Physics, February 15, 2004, Volume 95, Issue 4, pp. 2056-2062. [17] Weiter, M.; Schauer, F. Modelling of charge carrier transport in organic lightemitting diodes, Faculty of Chemistry, Brno University of Technology, Czech Republic.

6. References
[1] International Technology Roadmap for Semiconductors, 2004 Update, http://www.itrs.net/Common/2004Update/2004Update.htm [2] R. S. Zebulum, M. A. C. Pacheco, M. M. B. R. Vellasco.: Evolutionary Electronics: Automatic Design of Electronic Circuits and Systems by Genetics Algorithms, CRC Press, Boca Raton, Florida, ISBN: 0849308658, 2002.

[3] C. S. Lent, et al, Quantum Cellular Automata,


Nanotechnol., vol. 4, pp 49-57, 1993. [4] P. D. Towgaw, C. S. Lent, Logical Devices implemented using quantum cellular automata, Journal of Applied Physics, v. 75, n. 3, p. 1818-1825 fev. 1994. [5] C. S. Lent, P. D. Towgaw, A Device Architecture for Computing with Quantum Dots, Procceding of the IEEE, v. 85, n. 4, p. 541-557, abr. 1997.

[6] Amlani, I., et al, Demonstration of a functional quantumdot cellular automata cell, J. Vac. Sci. Tech., 1998, 37953799.

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