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Reliability Design
Handbook
No. RDH 376
4D
*-024601
TECHNICAL
LIBRARY
RAC
Refcobility Analysis Center
RADC-GAFB. NY.
iiT Research institute J
Downloaded from http://www.everyspec.com
TECHNICAL
LIBRARY
Hie Reliability Analysis Center is a OoD Information Analysis Center
operated by NT Research Institute
under contract to the Rome Air Development Center, AFSC
The Reliability Analysis Center (RAC) is a service for the dissemination of reliability information
concerning integrated circuits, hybrid devices, discrete devices (transistors, diodes) and selected
non-electronic parts employed in military, space and commercial applications.
The RAC analyzes and disseminates information that is generated during all phases of device
fabrication, testing, equipment assembly and operation. RAC data files are continually updated
through information collected by R&D, testing laboratories, device and equipment manufacturers,
government agencies and field installations.
REQUESTS FOR TECHNICAL ASSISTANCE AND INFORMATION ON AVAILABLE RAC SERVICES
AND PUBLICATIONS MAY BE DIRECTED TO:
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Reliability Analysis Center
Rome Air Development Center (RBRAC)
Griff iss Air Force Base, NY 13441
Telephone: 315/330-4151
Autovon: 587-4151
ALL OTHER REQUESTS SHOULD BE DIRECTED TO:
Rome Air Development Center
RBRD/Anthony J. Feduccia
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Telephone: 315/330-4920
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1
RELIABILITY ANALYSIS CENTER
A DoD Information Analysis Center
RELIABILITY DESIGN HANDBOOK
March 1976
R. T. Anderson
IIT Research Institute
10 W . 35th Street
Chicago, IL 60616
Under Contract to:
Rome Air Development Center
Griffiss Air Force Base, NY 13441
Catalog No. RDH-376
Approved for Public Release, Distribution Unlimited
A
1 9 7 5 , I I T Research I nstitute
A l l Rights Reserved
T hird Printing - June 1 9 7 7
PREFA CE
T his Rel iabil ity Design Handbook is intended to serve as a tool for
designers of mil itary equipment and, in particul ar, for designers of
equipment items that woul d typical l y make up avionics systems. T he
handbook provides guidel ines for use by design engineers to assure the
achievement of a rel iabl e end product. From the standpoint of design,
it is consistent with, and extends, basic concepts and rel iabil ity
improvement techniques described in MI L- HDBK- 21 7 B. Specifical l y, the
handbook provides design information, factors, and parameters, and other
engineering data affecting rel iabil ity. I n addition, the handbook
describes the approach to rel iabl e design, incl udes theoretical and
cost considerations and describes methods covering such considerations
as part control , derating, environmental resistance, redundancy and
design eval uation.
T he foresight of A ir Force Systems Command and Rome A ir Devel opment
Center in recognizing the need for a comprehensive guidance document to
aid el ectronic design engineers in achieving design rel iabil ity goal s
provided the impetus for preparation of this handbook.
T he cooperation and technical direction of T homas Del l acave, RA DC
Project Engineer, in bringing this handbook to fruition is grateful l y
acknowl edged. I I T Research I nstitute is indebted to the many RA DC and
contractor personnel who provided much of the reference material and
who contributed guidance and constructive criticism during the research
effort.
T his handbook was prepared by I I T Research I nstitute (HT RI ),
Chicago, I l l inois, under contract to RA DC. T he work was directed by
R. T . A nderson, Manager of Rel iabil ity, with technical contributions by
many I I T RI staff members.
I I T Research I nstitute
1 1 1
T A BLE O F CO NT ENT S
Section Page
Preface iii
1 I NT RO DUCT I O N 3
1 .1 Purpose and Scope of the Handbook 3
1 .2 I ntroduction to Rel iabil ity Engineering 4
1 .2.1 Rel iabil ity and Life Characteristics ... 4
1 .2.2 Rel iabil ity Degradation 1 0
1 .2.3 Rel iabil ity Growth 1 2
1 .3 O rganization of the Handbook 1 3
References 1 4
2 RELI A BI LI T Y T HEO RY A ND A PPLI CA T I O N 1 7
2.1 Basic Rel iabil ity T heory 1 7
2.1 .1 Exponential Fail ure Model 1 7
2.1 .2 System Model ing Concepts 22
2.1 .3 Part Fail ure Model ing 3 2
2.2 Managing for Rel iabil ity 3 8
2.3 Rel iabil ity Eval uation T ool s During Devel opment . 4 3
2.3 .1 Prediction T echniques 4 3
2.3 .2 Fail ure Mode A nal ysis T echniques 4 9
2.3 .3 Rel iabil ity T esting 5 4
References 60
3 . MI LI T A RY A I RBO RNE SYST EMS 65
3 .1 T rends in A vionics 65
3 .2 T he A vionics Environment 7 0
3 .3 Equipment Rel iabil ity State- of- the- A rt 7 6
3 .4 Summary and Concl usion: 1 9 7 5 A vionics T rends . . 7 8
References 8 0
T A BLE O F CO NT ENT S (Cont'd)
Section Page
4 RELI A BI LI T Y DESI GN DA T A 8 3
4 .1 Design to Maximize I nherent Rel iabil ity 8 7
4 .1 .1 Part Sel ection and Control 8 7
4 .1 .1 .1 Part Control 8 7
4 .1 .1 .2 Part Sel ection Guidel ines .... 9 1
4 .1 .1 .3 Part Screening 1 0 5
4 .1 .2 Derating 1 3 5
4 .1 .2.1 T emperature- Stress Factors. . . . 1 3 5
4 .1 .2.2 Specific Derating Guidel ines. . . 1 4 2
4 .1 .3 Environmental Resistance 1 7 1
4 .1 .3 .1 Environmental Factors 1 7 1
4 .1 .3 .2 Environmental Resistance
Provisions 1 7 7
4 .1 .3 .3 General Packaging Considerations. 1 8 3
4 .1 .4 Redundancy 1 8 5
4 .1 .4 .1 General Concepts 1 8 5
4 .1 .4 .2 Redundancy T echniques 1 9 3
4 .1 .4 .3 Design Exampl es 1 9 3
4 .1 .5 Design Simpl ification and A nal ysis .... 21 5
4 .1 .5 .1 Design Simpl ification 21 5
4 .1 .5 .2 Degradation A nal ysis 21 8
4 .1 .5 .3 O verstress and T ransient A nal ysis 225
4 .2 Design to Minimize Rel iabil ity Degradation
During Production and Use 25 1
4 .2.1 Contributions to Rel iabil ity Degradation . 25 1
4 .2.2 Design for Ease of I nspection and
Maintenance 25 7
4 .2.2.1 Hardware Partitioning 25 7
4 .2.2.2 Faul t Diagnosis 262
4 .2.2.3 Prediction of I ncipient Fail ure . 268
vi
T A BLE O F CO NT ENT S (Cont'd)
Section
4 .3 Design
4 .3 .1
4 .3 .2
4 .3 .3
References
A ppendix A
A ppendix B
A ppendix C
A ppendix D:
to Cost
Design to Cost O verview
Defining Cost and Rel iabil ity T argets. . .
4 .3 .2.1 Concept and Val idation Phase. . .
4 .3 .2.2 Devel opment and Production Phase,
4 .3 .2.3 Bal anced Design Management. . . ,
Meeting Cost and Rel iabil ity T argets . . .
Definitions, A bbreviations and Symbol s. .
Bibl iography (A nnotated) ,
Comparative Fail ure Rates for
Monol ithic Microcircuits. . .
Characteristics and Fail ure Rates
of Standard El ectron T ubes. . . .
Page
27 5
27 5
28 5
28 5
29 4
3 0 2
3 0 7
3 27
3 3 3
3 4 5
3 5 7
3 8 5
vii
LI ST O F FI GURES
Figure Page
1 - 1 Life Characteristic Curve 5
1 - 2 Stress Versus Strength Distributions 7
1 - 3 Rel iabil ity Growth Process During Design
and Devel opment 1 3
2- 1 Components of Fail ure 1 8
2- 2A Rel ationship Between Mission A ccompl ishment
Equipment Performance and Circuit Rel iabil ity 23
2- 2B Rel ationship Between Mission A ccompl ishment,
Performance, and Circuit Rel iabil ity (Continued) ... 24
2- 3 Bl ock Diagram of B- l I ntegrated O ffensive A vionic
Systems Under Computer Control 3 0
2- 4 Cal cul ations for System Rel iabil ity 3 1
2- 5 Part Fail ure Model (Conceptual ) 3 3
2- 6 Rel iabil ity Life Cycl e A ctivities 4 0
2- 7 Rel iabil ity Program El ements 4 2
2- 8 Cl assification of Rel iabil ity Eval uation T echniques. . 4 4
2- 9 Stress A nal ysis - Rel iabil ity Prediction Worksheet . . 4 7
2- 1 0 Radar System Hierarchy (Partial Listing) 5 0
2- 1 1 FMECA Worksheet 5 1
2- 1 2 Faul t T ree A nal ysis 5 3
2- 1 3 Rel iabil ity Growth Pl ot 5 7
2- 1 4 Rel iabil ity T esting O ptions 60
3 - 1 Estimation of Usage 65
3 - 2 A WG- 9 Radar System 67
3 - 3 Digital A vionics T rend 69
3 - 4 T emperature A l titude Profil es for A vionic Equipment. . 7 3
3 - 5 Vibration Requirements for A vionic Equipment 7 4
3 - 6 A vionics Equipment Rel iabil ity (A nal og) 7 7
I X
LI ST O F FI GURES (Cont'd)
Figure Page
4 - 1 Design Bal ancing A ctivities 8 3
4 - 2 Effect of Current on O perating Life
(T ypical Characteristic) 1 1 9
4 - 3 Rel iabil ity Screens 1 25
4 - 4 Screening Effectiveness 1 3 3
4 - 5 Stress/T emperature Pl ot for Group I T ransistor
(Sil icon, NPN) 1 3 8
4 - 6 T ypical Derating Graph 1 3 9
4 - 7 A ctual Constant Junction T emperature Curve 1 4 1
4 - 8 Mul tipoint Derating Curve for 1 N3 263 Power Diode ... 1 4 2
4 - 9 Microcircuit, Max O perating Junction T emp, 1 25 C . . . 1 4 5
4 - 1 0 Microcircuit, Max O perating Junction T emp, 1 5 0 C ... 1 4 6
4 - 1 1 Microcircuit, Max O perating Junction T emp, 1 7 5 C ... 1 4 7
4 - 1 2 Semiconductor, Max O perating Junction T emp, 1 0 0 C. . . 1 4 8
4 - 1 3 Semiconductor, Max O perating Junction T emp, 1 25 C. . . 1 4 9
4 - 1 6 Semiconductor, Max O perating Junction T emp, 20 0 C. . . 1 5 2
4 - 1 7 Resistor, Fixed, Carbon Composition (RCR) 1 5 3
4 - 1 8 Resistor, Fixed, Metal fil m (RLR, RNR) 1 5 4
4 - 1 9 Resistor, Power, Wirewound (RER, RWR) 1 5 5
4 - 20 Resistor, Precision, Wirebound (RBR) 1 5 6
4 - 21 Capacitor, MI CA (CM) 1 5 7
4 - 22 Capacitor, Ceramic, T emp Compensating 1 5 8
4 - 23 Capacitor, Paper- Pl astic or Metal l ized (CPV, CH)
Max T emp, 1 25 C 1 5 9
4 - 24 Capacitor, A ir T rimmer 1 60
Figure Page
4 - 25 Capacitor, Ceramic, GP, Max T emp, 8 5 C 1 61
4 - 26 Capacitor, Ceramic, GP, Max T emp, 1 25 C 1 62
4 - 27 Capacitor, Paper- Pl astic or Metal l ized (CPV, CH) . . . 1 63
4 - 28 Capacitor, T antal um, Wet El ectrol yte (CLR) 1 64
4 - 29 Capacitor, T antal um, Sol id (CSR) 1 65
4 - 3 0 Capacitor, Gl ass (CY) 1 66
4 - 3 1 Redundancy T echniques 1 8 6
4 - 3 2 Decreasing Gain in Rel iabil ity as Number of A ctive
El ements I ncreases 1 9 1
4 - 3 3 Rel iabil ity Gain for Repair of Simpl y Paral l el
Redundant El ement at Fail ure 1 9 2
4 - 3 4 Simpl e Paral l el Redundancy 1 9 4
4 - 3 5 Bimodal Redundancy 1 9 5
4 - 3 6 Dupl ex Redundancy 1 9 6
4 - 3 7 Majority Voting Redundancy 1 9 7
4 - 3 8 Standby Redundancy 1 9 8
4 - 3 9 Precision Regul ated Vol tage Suppl y 20 0
4 - 4 0 Redundant Regul ated Vol tage Suppl y 20 1
4 - 4 1 Rel iabil ity Comparison of Simpl e Redundant and
Nonredundant Vol tage Suppl ies 20 2
4 - 4 2 Basic T ransistor Circuit 20 3
4 - 4 3 Quad Redundant T ransistor Circuit 20 5
4 - 4 4 Comparison of Rel iabil ity for Quad Redundant and
Non- Redundant T ransistor Circuit 20 6
4 - 4 5 T 8 Counter Circuit 20 7
4 - 4 6 T wo O ut of T hree Majority Vote Redundant * 8 Counter . 20 8
xi
Figure Page
4 - 4 7 Rel iabil ity Comparison for Redundancy and Non-
Redundant i 8 Counter Configuration 20 9
4 - 4 8 Non- Redundant RF A mpl ifier Channel 21 1
4 - 4 9 Standby Redundant T wo Channel RF Receiver 21 2
4 - 5 0 Rel iabil ity Comparison of Redundant and Non- Redundant
RF Receiver Channel s 21 3
4 - 5 1 Bool ean Reduction of Logic El ements 21 7
4 - 5 2 A l ternative Fil ter Designs 21 9
4 - 5 3 Degradation Characteristics Due to A ging 220
4 - 5 4 Resistance Change of 1 /8 Watt, Fixed Metal Fil m
Resistors During 20 0 0 Hours of O peration (Percentage
Change in Resistance) 222
4 - 5 5 Square Pul se T riggering Vol tage for T ypical Low Level
I ntegrated Circuit 227
4 - 5 6 Latch Up Response 227
4 - 5 7 2N2222 O verstress Fail ure Data 229
4 - 5 8 O verstress Fail ure Data for Eight T ransistors 229
4 - 5 9 T ransistor Protection 23 1
4 - 60 SCR Protection 23 2
4 - 61 CMO S Protection 23 3
4 - 62 CMO S Handl ing Precautions 23 3
4 - 63 T T L Protection 23 4
4 - 64 Diode Protection 23 5
4 - 65 Pul se Waveform 23 6
4 - 66 Wire- Wound Resistors 23 7
4 - 67 Metal Fil m Resistors 23 8
4 - 68 Carbon- Composition Resistors 23 9
xii
Figure Page
4 - 69 Pul se Width vs. Maximum Pul se Vol tage 24 1
4 - 7 0 Pl ot of Reverse Energy for Fail ure for the 3 5 WVDC
Sol id T antal um Devices 24 4
4 - 7 1 Capacitor Pul se Response 24 6
4 - 7 2 Faul t T ree Diagram for Qual ity Defects 25 5
4 - 7 3 Modul arization Design 25 8
4 - 7 4 Design for Functional Modul arization 260
4 - 7 5 T he DoD Resource A l l ocation Process 27 6
4 - 7 6 T rade Rel ations Between Program O bjectives
(Bal anced Design) 27 9
4 - 7 7 R&M and Cost Methods 28 0
4 - 7 8 Cost Versus Rel iabil ity 28 9
4 - 7 9 Cost Versus Maintainabil ity 29 0
4 - 8 0 O ptimum Cost A l l ocation A pproach 29 3
4 - 8 1 Design to Cost Program Phases 29 5
4 - 8 2 Design to T arget Cost Model 29 6
4 - 8 3 Work Breakdown Structure 3 0 0
4 - 8 4 LRU- Unit Production Cost 3 0 4
4 - 8 5 MI S Record Format 3 0 6
4 - 8 6 MI S I nformation Fl ow 3 0 8
4 - 8 7 Part Standardization- Cost Savings 3 1 5
4 - 8 8 Drawing Standardization Comparison Composite of
A l l Drawings 3 1 7
4 - 8 9 Production I mpact of a Burn- I n Program 3 20
4 - 9 0 Predicted MT BF vs. Cost 3 24
xm
LI ST O F T A BLES
T abl e Page
2- 1 Environmental Symbol I dentification and Description ... 3 5
2- 2 Parts with Mul ti- Level Qual ity Specifications 3 6
2-3 TTQ - Quality Factors 36
2- 4 Representative Part Fail ure Rate Cal cul ations 3 8
3 - 1 A vionics Matrix 66
3 - 2 A WG- 9 Radar System 68
3 - 3 Environmental Conditions 7 2
4 - 1 Ground Rul es for Part Sel ection and Control 8 8
4 - 2 Microcircuit Sel ection Guidel ines 9 3
4 - 3 A ppl ication Notes for I C's 9 4
4 - 4 Semiconductor Sel ection Guidel ines 9 7
4 - 5 A ppl ication and Sel ection Guidel ines for Semiconductors . 9 8
4 - 6 Resistor Sel ection Guidel ines 9 9
4 - 7 A ppl ication and Sel ection Guidel ines for Resistors. ... 1 0 1
4 - 8 Capacitor Sel ection Guidel ines 1 0 0
4 - 9 A ppl ication and Sel ection Guidel ines for Capacitors . . . 1 0 6
4 - 1 0 El ectron T ube Sel ection Criteria 1 1 2
4 - 1 1 Sel ection Criteria for T ransformers and I nductors .... 1 1 3
4 - 1 2 Rel ay Sel ection Criteria 1 1 4
4 - 1 3 A ppl icabl e MI L Specifications for Rel ays 1 1 5
4 - 1 4 Generic Fail ure Rates (x 1 0 " ) for Rel ays and
I nductive Devices (Derived from MI L- HDBK- 21 7 B) 1 1 6
4 - 1 5 Sel ection Criteria for Switches 1 1 7
4 - 1 6 Fail ure Rates for Generic Switch T ypes (x 1 0 "
6
) 1 1 8
4 - 1 7 Connector Sel ection Criteria 1 20
xv
LI ST O F T A BLES (Cont'd)
T abl e Page
4 - 1 8 Sel ection Criteria for Waveguides and Rel ated Equipment. . 1 21
4 - 1 9 A ppl ication and Use of Waveguides and Rel ated Equipment. . 1 22
4 - 20 Sel ection Criteria for Cabl es 1 23
4 - 21 Fail ure Mode Distribution for T ransistors and
I ntegrated Circuits 1 27
4 - 22 Microcircuit Defects/Screens 1 28
4 - 23 Comparison of Screening Methods 1 3 1
4 - 24 Screening Sequence - Method 5 0 0 4 - MI L- ST D- 8 8 3 1 3 3
4 - 25 Fal l out from MI L- ST D- 8 8 3 T ests 1 3 4
4 - 26 Screening T est Costs for Cl ass B Devices 1 3 4
4 - 27 Discrete Semiconductor Base Fail ure Rate Parameters. . . . 1 3 7
4 - 28 Base Fail ure Rates for Group I T ransistors (Sil icon, NPN). 1 3 8
4 - 29 Microel ectronic Device Derating Chart 1 4 4
4 - 3 0 Derating for Coil s, Chokes and T ransformers 1 67
4 - 3 1 Rel ay Derating Chart 1 68
4 - 3 2 Connector Derating Chart 1 69
4 - 3 3 Environmental Stresses, Effects and Rel iabil ity
I mprovement T echniques in El ectronic Equipment 1 7 2
4 - 3 4 Rel iabil ity I mprovement Potential at Reduced T emperatures. 1 7 9
4 - 3 5 Design Guidel ines to Reduce Component O verheating 1 8 1
4 - 3 6 Packaging T rade- O ffs 1 8 4
4 - 3 7 Redundancy T echniques 1 8 7
4 - 3 8 T ypical Circuit A nal ysis T echniques 224
4 - 3 9 Damage Energies 24 2
4 - 4 0 Ceramic Capacitors 24 3
4 - 4 1 Sol id T antal um Capacitors 24 3
xvi
LI ST O F T A BLES (Cont'd)
T abl e Page
4 - 4 2 Fail ure Level s of Common Capacitors 24 8
4 - 4 3 Production Process and A ssociated Defects 25 3
4 - 4 4 Ease of Maintenance Guidel ines 25 9
4 - 4 5 Design Guidel ines for T est Points 265
4 - 4 6 Cause and Effect of Secondary Effects 27 0
4 - 4 7 T ypes of Design- to- Cost Programs 27 7
4 - 4 8 Hypothetical Design to Cost Program 28 6
4 - 4 9 Prel iminary Design UPC WorksheetPhase 1 29 7
4 - 5 0 Prel iminary Design UPC Worksheet (Compl eted)- - Phase 1 . . 29 9
4 - 5 1 Unit Product Cost Matrix 3 0 1
4 - 5 2 Function - Subassembl y Matrix 3 0 3
4 - 5 3 Sel ecting the O ptimum T ransistor 3 1 3
4 - 5 4 Comparison for Design to A dd a Diode 3 1 4
4 - 5 5 MT T F of A l ternative T ube Designs 3 1 6
4 - 5 6 A PQ- 1 1 3 Production T est Fail ure Experience 3 1 9
4 - 5 7 Cost/Rel iabil ity Working Data 3 22
4 - 5 8 Costs and MT BF for A l l Combinations of Rel iabil ity Screens 3 23
XVI 1
SECT I O N 1
I NT RO DUCT I O N
1 .1 Purpose and Scope of the Handbook
1 .2 I ntroduction to Rel iabil ity Engineering
1 .2.1 Rel iabil ity and Life Characteristics
1 .2.2 Rel iabil ity Degradation
1 .2.3 Rel iabil ity Growth
1 .3 O rganization of the Handbook
SECT I O N 1
I NT RO DUCT I O N
1 .1 Purpose and Scope of the Handbook
T his handbook has been prepared to serve as a tool for designers
of mil itary equipment and systems. T he purpose of the handbook is to
provide information and direction to the designer which wil l hel p him
engineer rel iabil ity into an equipment during its basic design stage.
T o this end, it provides design data and guidel ines for those safety,
mission, maintenance and cost factors which together form the working
el ements of rel iabil ity engineering, system engineering and cost
effectiveness.
T his handbook is primaril y intended for use in the design of new
equipment(s) or systems which are l argel y composed of el ectronic parts
and components. However, it can al so be used for the design of systems
which encompass both nonel ectronic and el ectronic parts, as wel l as for
the modification of existing systems.
T his handbook embodies a preventive approach to rel iabil ity. From
the standpoint of design, it extends basic concepts and rel iabil ity
improvement parameters which are described in MI L- HDBK- 21 7 B, " Rel iabil ity
Prediction of El ectronic Equipment" . I n addition to compl ementing this
document, the attendant handbook describes the overal l approach to
rel iabl e design, incl uding theoretical , practical and cost considerations.
I t describes methods for considering such areas as component sel ection,
derating, thermal and environmental design eval uation, redundancy, part
improvement and part screening techniques.
T he fol l owing pages (Section 1 .2 and its subsections) provide an
introductory overview of rel iabil ity engineering techniques, establ ish
the theme for the remainder of the handbook and, in general , identify
broad measures which can be taken to impl ement rel iabil ity during
design.
1 .2 I ntroduction to Rel iabil ity Engineering
A n effective rel iabil ity engineering program begins with the recog-
nition that the achievement of a high l evel of actual use rel iabil ity is
a function of design as wel l as al l l ife cycl e activities. Design
establ ishes the inherent rel iabil ity potential of a system, and the
transition from the paper design to hardware resul ts in an actual system
rel iabil ity bel ow this inherent l evel . A ccordingl y, its assessment must
be approached first via its design characteristics (which establ ish an
upper l imit of rel iabil ity), and then in conjunction with a series of
modifying factors that account for production, operation and maintenance
degradation.
T herefore, del iberate and positive measures must be taken during
design and devel opment which enhance inherent rel iabil ity by forcing the
design to be iterated, and minimize degradation by el iminating potential
fail ures and manufacturing fl aws prior to production and operational use.
Such measures demand that al l rel iabil ity activities be effectivel y
managed during the entirety of system devel opment. Rel iabil ity efforts
start with designsel ecting the best parts, appl ying part derating con-
cepts, incorporating screening techniques and/or designing redundancy
into the system. I t incl udes both purchasing practices and specifica-
tions which insure the procurement of rel iabl e components. I t ranges
from adequate test methods and assembl y processes to effective formal
systems for accuratel y reporting, anal yzing and correcting fail ures
which occur during use. Many times, onl y a l ittl e additional effort is
needed to assure acceptabl e fiel d rel iabil ity. I n contrast, the con-
sequences of unrel iabil ity in the fiel d are severe- - high cost and
excessive maintenance downtime.
1 .2.1 Rel iabil ity and Life Characteristics
Rel iabil ity has been described as " qual ity in the time dimension" .
I t is cl assical l y defined as the probabil ity that an item wil l perform
satisfactoril y for a specified period of time under a stated set of use
conditions. From a functional point of view, in order for an item to
be rel iabl e, it must do more than meet an initial factory performance or
qual ity specificationit must al so operate satisfactoril y for an accept-
abl e period of time in the fiel d appl ication for which it is intended.
T he cl assical definition of rel iabil ity, stated above, stresses
four el ements, namel y: probabil ity, performance requirements, time and
use conditions. Probabil ity is that quantitative term which expresses
the l ikel ihood of an event's occurrence (or nonoccurrence) as a val ue
between 0 and 1 . Performance requirements are those criteria which
cl earl y describe or define what is considered to be satisfactory opera-
tion. T ime is the measure of that period during which one can expect
satisfactory performance. Use conditions are the environmental condi-
tions under which one expects an item to function.
Determining rel iabil ity, therefore, invol ves the understanding of
several concepts which rel ate to these four definitional el ements.
A mong such concepts is that of a fail ure rate which can vary as a func-
tion of age. A fail ure rate is a measurement of the number of mal func-
tions occurring per unit of time. I n order to show the variation in
fail ure rate, separate consideration is given to three (3 ) discrete
periods when viewing the fail ure characteristics of a product or item
over its l ife span (and then considering a l arge sampl e of its popul a-
tion). T hese periods are shown in Figure 1 - 1 and are described bel ow.
o
I Infant
Mortality
Period |
n Useful
Life
Period
in Wearout or
End of Life
Pe/iod
Increasing Age (Hours/Cycles)-* W
FigH LIFE CHARACTERISTIC CURVE (Ref. I)
I I nfant Mortal ity Period
I nitial l y, the item popul ation exhibits a high fail ure rate. T his
fail ure rate decreases rapidl y during this first period (often cal l ed
the " infant mortal ity" , " burn- in" or debugging period), and stabil izes
at an approximate val ue (at time T g) when the weak units have died out.
I t may be caused by a number of things: gross buil t- in fl aws due to
faul ty workmanship (manufacturing deviations from the design intent),
transportation damage or instal l ation errors. T his initial fail ure rate
is unusual l y pronounced in new equipment. Many manufacturers provide a
" burn- in" period for their product, prior to del ivery, which hel ps to
el iminate a high portion of the initial fail ures and assists in estab-
l ishing a high l evel of operational rel iabil ity. Exampl es of earl y
fail ures are:
Poor wel ds or seal s
Poor sol der joints
t Poor connections
t Dirt or contamination on surfaces or in material s
Chemical impurities in metal or insul ation
t Voids, cracks, thin spots in insul ation or
protective coatings
I ncorrect positioning of parts
Many of these earl y fail ures can be prevented by improving the control
over the manufacturing process. Sometimes, improvements in design or
material s are required to increase the tol erance for these manufacturing
deviations, but fundamental l y these fail ures refl ect the " manufactur-
abil ity" of the component or product and the control of the manufacturing
process. Consequentl y, these earl y fail ures woul d show up during:
t I n- process and final tests
t Process audits
Life tests
Environmental tests
I I Useful Life Period
T he item popul ation, after having been burned- in, reaches its l owest
fail ure rate l evel , which is normal l y characterized by a rel ativel y
constant fail ure rate, accompanied by negl igibl e or yery gradual changes
due to wear. T his second period (between T
and T
w
as seen in Figure 1 - 1 )
is cal l ed the useful l ife period, and is characterized mainl y by the
occurrence of stress rel ated fail ures. T he exponential fail ure distribu-
tion is widel y used as a mathematical model to approximate this time
period. T his period varies among hardware types, is the interval usual l y
given most weight in design rel iabil ity action, and is the most signifi-
cant period for rel iabil ity prediction and assessment activities.
Figure 1 - 2 shows the interaction of stress and strength rel ative to
the time periods identified in Figure 1 - 1 . Figure 1 - 2(A ) il l ustrates the
distribution of a typical stress/strength density curve for an item
having l ow rel iabil ity and/or inadequate design margin. T he shaded area
indicates that stress exceeds strength a certain percentage of the time,
with resul tant fail ure. Note that for items having an inadequate design
margin, instantaneous stress frequentl y exceeds the average strength.
T his is shown in Figure 1 - 2(C).
Large Region of Stress/
Strength Interference Where
Failures Can Occur
Strength
Stress/Strength
(A)
Small Region of Stress/
Strength Interference
Where Failures Can
Occur
Strength
>
o
c
cr
0)
Instantaneous
Stress Levels
Weak (Infant
Mortality)Units
Average Strength
(High Margin)
Average Strength
(Low Margin)
Average Stress Level
Failure
Large Stress/Strength
Difference
Reduced Strength Due
to Aging
'B Time 'W
(C)
Stress/ Strength
(B)
Fig 1-2 STRESS VERSUS STRENGTH DISTRIBUTIONS (Ref I)
I n contrast, Figure 1 - 2(B) shows the separation of the stress/strength
distribution indicative of a high design safety factor (adequate design
margin) and high rel iabil ity. O ccasional l y, random increases in the
l evel of a stress or a combination of stresses causes a device to fail .
T his is al so shown in Figure 1 - 2(C). For el ectronic devices and compo-
nents, experience has shown that excessive temperature and vol tage l evel s,
either steady state, transient or changing at rapid rates, are the two
most destructive stresses. Humidity, vibration, shock and al titude al so
contribute to the fail ure of design strength devices.
I l l Wearout Period
T he third and final l ife period occurs when the item popul ation
reaches the point where the fail ure rate starts to increase noticeabl y
(T w). T his point is identified as the end of useful l ife or the start of
wearout. Beyond this point on the time axis, the fail ure rate increases
rapidl y. When the hardware fail ure rate due to wearout becomes unaccept-
abl y high, repl acement or repair of the item shoul d be made. Repl acement
schedul es (of critical short- l ife components) are based on the recogni-
tion of this fail ure rate.
Wearout fail ures, as shown in Figure 1 - 1 and 1 - 2, are due* primaril y
to deterioration of the design strength of the device as a consequence
of operation and exposure to environmental fl uctuations. Deterioration
resul ts from a number of famil iar chemical and physical phenomena:
t Corrosion or oxidation
I nsul ation breakdown or l eakage
I onic migration of metal s in vacuum or on surfaces
Frictional wear or fatigue
Shrinkage and cracking in pl astics.
O ptimizing rel iabil ity invol ves the consideration of each and al l
of these three l ife periods. Earl y fail ures must be el iminated by
systematic procedures of control l ed screening and burn- in tests. Stress
rel ated fail ures must be minimized by providing adequate design margin.
Wearout must be el iminated by timel y preventive repl acement or short- l ife
component parts. T hus, al l major factors which infl uence (and degrade)
a system's operational rel iabil ity must be addressed during design (using
appropriate techniques described l ater) to optimize and control system
rel iabil ity.
I n order to introduce several additional concepts, consider for the
moment that portion of Figure 1 - 1 denoted as the useful l ife period.
During this time period, rel iabil ity is described by means of the singl e
parameter exponential distribution:
8
R(t) = e"
U
where:
R(t) is the probabil ity that'the item wil l operate without
fail ure for the time period, t (usual l y expressed in
hours), under stated operating conditions;
e is the base of the natural l ogarithms, equal to 2.7 1 8 2...;
X is the item fail ure rate (usual l y expressed in fail ures
per hour), and is a constant for any given set of stress,
temperature and qual ity l evel conditions. I t is deter-
mined for parts and components from l arge scal e data
col l ection and/or test programs.
When appropriate val ues of A and t are inserted into the above
expression, the probabil ity of success (i.e., rel iabil ity) is obtained
for that time period.
T he reciprocal of the fail ure rate is defined as the mean time
between fail ures (MT BF)
MT BF = 1 /A
T he MT BF is primaril y a figure of merit by which one hardware item can
be compared to another. I t is a measure of the fail ure rate (A ) during
the useful l ife period. T he document used to establ ish fail ure rates
(A ) for the constituent el ectronic parts (resistors, semiconductors,
etc.) used in systems and equipment is MI L- HDBK- 21 7 B . A more defini-
tive discussion of MI L- HDBK- 21 7 B is given in Section 2.1 .3 .
Rel iabil ity estimates prepared in accordance with MI L- HDBK- 21 7 B
techniques refl ect the inherent (or potential ) rel iabil ity of a system
as defined by its engineering documentation, its stress and safety
factors and gross environmental appl ication, manufacturing and qual ity
factors. T hese estimates are indicative of the upper l imit or rel i-
abil ity potential as depicted by the useful l ife period in Figure 1 - 1 .
However, these estimates do not refl ect the expected system performance
after initial manufacturing and many times do not refl ect expected per-
formance when operated and maintained in its actual fiel d environment.
T he sections which fol l ow discuss how degradation in rel iabil ity can
occur during the periods which encompass production and operation of the
equipment or system, and how rel iabil ity can grow from a degraded l evel
back up to that which approaches the inherent or potential val ue of the
system.
1 .2.2 Rel iabil ity Degradation
T he resul ts of numerous data col l ection efforts have shown that the
rel iabil ity of fiel ded equipment and systems is degraded from three to
3
ten times the potential predicted during design . T he transition from a
paper design to production to fiel d operations introduces degradation
factors which constrain the expected rel iabil ity. T his section provides
a brief discussion of these factors which can be broadl y divided into
manufacturing and production factors, system operation and maintenance
activities.
I n order to assess the magnitude of the rel iabil ity degradation due
to manufacturing, the impact of manufacturing processes (i.e., the process
induced defects, the efficiency of conventional manufacturing and qual ity
control inspection, and the effectiveness of rel iabil ity screening tech-
niques) must be eval uated. I n addition to the l atent defects attributabl e
to purchased parts and material s, assembl y errors can account for sub-
stantial degradation. A ssembl y errors can be brought about by operator
l earning, motivational or fatigue factors. Manufacturing and qual ity
control inspections and tests are provided to minimize degradation from
these sources and to weed out the more obvious defects. No inspection
process can remove al l defects which inhabit an item presented for inspec-
tion. A certain number of defective items wil l escape the process, be
accepted and be pl aced in fiel d operation. More importantl y, these gross
defects are overshadowed by unknown numbers of l atent defects, the resul ts
of weakened parts, which can fail under the proper conditions of stress-
usual l y during fiel d operation. Factory screening tests are designed to
appl y a stress of given magnitude over a specified duration to remove
these kinds of defects. A s is the case with conventional inspection
processes, screening tests are mrt 1 0 0 % effective.
1 0
From the preceding discussion, it is evident that the assessment of
rel iabil ity degradation due to production invol ves estimating the number
of defects induced during fabrication and assembl y processes minus the
number removed by conventional qual ity control tests and inspections.
Section 4 .2.1 of this handbook provides further detail s concerning
rel iabil ity degradation resul ting from production processes.
Degradation in rel iabil ity al so occurs as a resul t of system opera-
tion. Wearout, with aging as the dominant fail ure mechanism, can shorten
or reduce the useful l ife. Situations al so occur in which a mil itary
system may be cal l ed upon to operate beyond its design capabil ities
because of an unusual mission requirement or to avoid a ground threat.
T hese situations coul d cause il l effects to its constituent parts. O per-
ational abuses due to rough handl ing, extended duty cycl es or negl ected
maintenance can contribute material l y to rel iabil ity degradation, which
eventual l y resul ts in fail ure. T he degradation can be a resul t of the
interaction of man, machine and environment. T he transl ation of the
factors which infl uence operational rel iabil ity degradation into correc-
tive procedures requires a compl ete anal ysis of functions performed by
man and machine, pl us fatigue and/or stress conditions which coul d
degrade operator performance.
Degradation in inherent rel iabil ity can al so occur as a resul t of
3
maintenance activities. Studies have shown that excessive handl ing
brought about by frequent preventive maintenance or poorl y executed
corrective maintenance (e.g., instal l ation errors) have degraded system
rel iabil ity. Several trends in system design have reduced the need to
perform adjustments or make continual measurements to verify peak per-
formance. Extensive repl acement of anal og with digital circuitry,
incl usion of more buil t- in test equipment and use of faul t tol erant
circuitry are indicative of these trends. T hese factors, al ong with
greater awareness of the cost of maintenance, have brought changes for
ease of maintenance whose by- product has been increased system rel iabil -
ity. I n spite of these trends, the maintenance technician remains a
primary cause of rel iabil ity degradation. T he effects of poorl y trained,
poorl y supported or poorl y motivated maintenance technicians on rel i-
abil ity degradation require careful assessment and quantification.
1 1
1 .2.3 Rel iabil ity Growth
Rel iabil ity growth represents the resul tant action taken to hasten
a hardware item toward its rel iabil ity potential either during devel op-
ment or during subsequent manufacturing or operation. During earl y
devel opment, the achieved rel iabil ity of a newl y fabricated item, or an
off- the- board prototype, is much l ower than its predicted rel iabil ity.
T his is due to initial design and engineering deficiencies as wel l as
manufacturing fl aws. T he rel iabil ity growth process, when formal ized and
appl ied as an engineering discipl ine, al l ows management to exercise
control , al l ocate resources and maintain visibil ity into activities
designed to achieve a mature system prior to ful l production or fiel d
use.
T he basic concepts associated with a rel iabil ity growth process and
its appl ication to newl y fabricated hardware invol ve consideration of
hardware test, fail ure, correction and retest activities. Specifical l y,
rel iabil ity growth is usual l y an iterative test- fail - correct process.
T here are three essential el ements invol ved in achieving rel iabil ity
growth, namel y:
(1 ) Detection and anal ysis of hardware fail ures,
(2) Feedback and redesign of probl em areas,
(3 ) I mpl ementation of corrective action and retest.
T he rate at which hardware rel iabil ity grows is dependent on how rapidl y
these three el ements can be accompl ished and, more importantl y, how
wel l the corrective action sol ves the probl em identified. During earl y
devel opment and test activities, the achieved rel iabil ity (or MT BF) is
wel l bel ow that predicted on the basis of design anal yses and anal ytical
predictions. A s devel opment and test efforts progress and probl em areas
become resol ved, measured rel iabil ity val ues approach the inherent
(design based) val ue. Figure 1 - 3 depicts this process.
1 2
r
Predicted Reliability
(i.e., Reliability
Potential)
Reliability Growth
^During Development
Reliability Growth
During Production
Reliability of Initial
Production Hardware
Reliability of Initial
Prototype Hardware
Fig 1-3 RELIABILITY GROWTH PROCESS DURING DESIGN
AND DEVELOPMENT
Figure 1 - 3 al so shows that a decrease in rel iabil ity occurs at the
onset of production. T his is primaril y due to workmanship errors
resul ting from unfamil iar operations, process discrepancies and qual ity
oversights which drive rel iabil ity bel ow expected l evel s. A s production
continues and skil l increases, measured rel iabil ity again approaches
the inherent val ue. Later sections of this handbook wil l describe tech-
niques by which rel iabil ity growth can be model ed and appl ied to the
devel opment of A ir Force Systems.
1 .3 O rganization of the Handbook
T he handbook is comprised of three (3 ) major sections containing
introductory material , background information and guidel ines for rel i-
abl e design. Definitions and an annotated bibl iography are al so
incl uded. T he fol l owing summarizes its contents:
Rel iabil ity T heory and A ppl ication (Section 2)
Provides the designer with an overview of the more significant
rel iabil ity concepts, formul ae and eval uation techniques used
by rel iabil ity engineers in assuring that rel iabil ity is
designed into the system.
1 3
A irborne Systems (Section 3 )
I dentifies the typical avionics systems and describes specific
equipment cl asses, their compl exity and their approximate rel i-
abil ity l evel s. T he intent is to show, in general , the rel a-
tionship between performance, compl exity and rel iabil ity.
Rel iabil ity Design Data (Section 4 )
Comprises the main body of this handbook and provides guidel ines
for rel iabl e design covering component sel ection, derating,
design simpl ification, environmental resistance, redundancy,
and tol erance eval uation. I n addition, basic design approaches
to hel p minimize rel iabil ity degradation due to production and
maintenance are al so covered. Design- to- cost guidel ines are
provided in this section.
REFERENCES
1 . Bazovsky, I ., Rel iabil ity T heory and Practice, Prentice- Hal l ,
Engl ewood Cl iffs, New Jersey, 1 9 61 .
2. Mil itary Standardization Handbook 21 7 B (DoD), " Rel iabil ity Pre-
diction of El ectronic Equipment, " 20 September 1 9 7 4 .
3 . Research Study of Radar Rel iabil ity and I ts I mpact on Life Cycl e
Costs for the A PQ- 1 1 3 , - 1 1 4 , - 1 20 and - 1 4 4 Radar Systems, General
El ectric Company, A erospace El ectronic Systems Department,
Utica, New York, A ugust 1 9 7 2.
1 4
SECT I O N 2
RELI A BI LI T Y T HEO RY A ND A PPLI CA T I O N
2.1 Basic Rel iabil ity T heory
2.1 .1 Exponential Fail ure Model
2.1 .2 System Model ing Concepts
2.1 .3 Part Fail ure Model ing
2.2 Managing for Rel iabil ity
2.3 Rel iabil ity Eval uation T ool s During Devel opment
2.3 .1 Prediction T echniques
2.3 .2 Fail ure Mode A nal ysis T echniques
2.3 .3 Rel iabil ity T esting
SECT I O N 2
RELI A BI LI T Y T HEO RY A ND A PPLI CA T I O N
2.1 Basic Rel iabil ity T heory
T he previous section of this handbook introduced fundamental rel i-
abil ity engineering concepts. T his section expands upon those concepts
to provide a more detail ed understanding of how design activities can
infl uence hardware rel iabil ity. T he subsections which fol l ow treat basic
rel iabil ity theory, management for rel iabil ity and rel iabil ity eval ua-
tion tool s used during system devel opment.
2.1 .1 Exponential Fail ure Model
T he l ife characteristic curve shown in Section 1 (Figure 1 - 1 ) can
be further defined by three fail ure components which predominate during
the three periods of an item's l ife. Figure 2- 1 il l ustrates these com-
ponents in terms of an equipment hazard rate, z(t). T he hazard rate can
be simpl y stated as the conditional probabil ity of fail ure and wil l be
defined l ater. T he fail ure components shown in Figure 2- 1 incl ude:
(1 ) Earl y Fail ure- - due to design and qual ity- rel ated manufacturing
fl aws and which have a decreasing hazard rate.
(2) Stress Rel ated Fail ure- - due to appl ication stresses and which
have a constant hazard rate.
(3 ) Wearout Fail ures- - due to aging and/or deterioration and which
have an increasing hazard rate.
Examination of Figure 2- 1 indicates that:
(1 ) T he infant mortal ity period is characterized by a high but
rapidl y decreasing hazard rate that is comprised of:
(a) a high qual ity fail ure component
(b) a constant stress rel ated fail ure component
(c) a l ow wearout fail ure component.
(2) T he useful l ife period is characterized by a constant hazard
rate that is comprised of:
1 7
00
Hazard
Rate Z(t)
I
Infant
Mortality
Quality
"Failures
Equipment Life Periods
n
Useful Life
Overall Life
Characteristic Curve
Stress Related
Failures f
'B
Time
w
m
Wearout
S
/
.Wearout
Failures
Fig 2-1 COMPONENTS OF FAILURE
(a) a l ow (and decreasing) qual ity fail ure component
(c) a l ow (but increasing) wearout fail ure component.
Note: T he combination of al l three components resul ts in a constant
hazard rate because the decreasing qual ity fail ures and increasing
wearout fail ures tend to offset each other, and because the stress
rel ated fail ures exhibit a rel ativel y l arge ampl itude.
(3 ) T he wearout period is characterized by an increasing
hazard rate that is comprised of:
(a) a negl igibl e qual ity fail ure component
(c) an initial l y l ow but rapidl y increasing wearout
fail ure component.
T he general approach to rel iabil ity for el ectronic systems is to
minimize earl y fail ures by emphasizing factory test and inspection and
preventing wearout fail ures by repl acing short l ife parts. Consequentl y,
the useful l ife period characterized by stress rel ated fail ures is the
most important period, and the one to which design action is primaril y
addressed.
Figure 2- 1 il l ustrates that during the useful l ife period the hazard
rate is constant. A constant hazard (or fail ure) rate is described by
the exponential fail ure distribution. T hus, the exponential fail ure
model refl ects the fact that the item must represent a mature design
whose fail ure rate, in general , is primaril y comprised of stress rel ated
fail ures. T his means that earl y fail ures have been minimized, and wear-
out is not noticeabl e or is beyond the period of concern. T he magnitude
of this fail ure rate is directl y rel ated to the stress/strength ratio of
the item.
T he exponential model can be derived from the basic notions of
probabil ity . When a fixed number, N , of components are repeatedl y
tested, there wil l be, after a time t, N components which survive the
test and N
f
components which fail . T he rel iabil ity or probabil ity of
survival is at any time t during the test:
1 9
N
s
N
s
R(t)

=
N ^
=
lN 7f V T
Since N = N - N
f
; rel iabil ity can be written:
N - N, N-
R(t) = -V ^ = 1 - J-* 1 - F (t)
0 0
and
dt N
0
dt
nz)
i
where
f(t). = the fail ure density function, i.e., the probabil ity
that a fail ure wil l occur in the next time increment dt.
T he hazard rate z(t) is defined as the ratio of the fractional
fail ure rate to the fractional surviving quantity, that is, number of
the original popul ation stil l operating at time t, or simpl y the condi
2
tional probabil ity of fail ure .
z(t)
= mi= f(t)
Z[Z)
Rtt) l - F(t)
t
1 - /f(t)dt
o
for the exponential distribution
f(t) = A e'
U
z(t) = x
I n general , it can be assumed that the hazard rate of el ectronic
el ements and systems remains constant over practical interval s of time,
and that z(t). = A .. Hence, A ^ , a constant, represents the expected
number of random fail ures per unit of operating time of the i
tn
el ement,
i.e., the fail ure rate. T hus, when a constant fail ure rate can be
assumed:
20
- dR(t)
i
f(t)
1
3 ^
z(t)
i
=

x
1
=
Rl tT 7
=
R(t).
Sol ving this differential equation for R(t)
i
gives the exponential
distribution function commonl y used in rel iabil ity prediction:
- x.t
R(t)
i
= e '
A l so, the mean time to fail ure can be determined by:
oo
MT BF = fR(t)dt,
o
so that, when a constant fail ure rate x. can be assumed:
" - A , t
MT BF,
>, /< $
T he above expressions for R(t). and MT BF. are the basic mathematical
rel ationships used in rel iabil ity prediction. I t must be emphasized,
however, that these expressions were derived based on the fundamental
assumption that the fail ure rate of the item under consideration is a
constant.
T he emphasis on the exponential distribution in rel iabil ity work
makes it worthwhil e to discuss the use of this function as a fail ure-
probabil ity model . T he mechanism underl ying the exponential rel iabil ity
function is that the hazard rate (or the conditional probabil ity of fail -
ure in an interval given survival at the beginning of the interval ) is
independent of the accumul ated l ife.
T he use of this type of " fail ure l aw" for compl ex systems is judged
appl icabl e because of the many forces that can act upon the item and
produce fail ure. A s stated previousl y, the stress/strength rel ationship
and varying environmental conditions resul t in effectivel y random
fail ures.
21
A nother factor for assuming the exponential distribution in l ong-
l ife compl ex systems is the so- cal l ed " approach to a stabl e state, "
wherein the system hazard rate is effectivel y constant regardl ess of the
fail ure pattern of individual parts. T his state resul ts from the mixing
of part ages when fail ed el ements in the system are repl aced or repaired.
O ver a period of time, the system hazard rate oscil l ates, but this cycl ic
movement diminishes in time and approaches a stabl e state with a constant
hazard rate.
A third argument for assuming the exponential distribution is that
the exponential can be used as an approximation of some other function
over a particul ar interval of time for which the true hazard rate is
essential l y constant.
Subsequent paragraphs in Section 2.1 which describe system and part
fail ure model s used for predicting R are based on the assumption that the
constant hazard rate is appl icabl e and that the item is operating within
the fl at portion of its characteristic curve.
2.1 .2 System Model ing Concepts
T o eval uate the rel iabil ity of systems and equipment, a method is
needed to refl ect the rel iabil ity connectivity of the many part types
having different stress- determined fail ure rates that woul d normal l y make
up a compl ex equipment. T his is accompl ished by establ ishing a rel ation-
ship between equipment rel iabil ity and individual part/item fail ure rates.
Prior to discussing these rel ationships, it woul d be useful to dis-
cuss system rel iabil ity objectives first. For mil itary systems, rel i-
abil ity must be eval uated from the fol l owing three separate, but rel ated,
standpoints:
(1 ) Rel iabil ity as it impacts personnel safety.
(2) Rel iabil ity as it impacts mission success.
(3 ) Rel iabil ity as it impacts unschedul ed maintenance or
l ogistic factors.
Each of these basic rel iabil ity considerations bears a rel ationship
to the fail ure modes and mechanisms which impact safety, mission success
and unschedul ed maintenance. Figures 2- 2a and 2- 2b provide an exampl e
22
Antenna
Transmitter
Radar
Master
Oscillator
Microwave
Circuits
Radar
Receiver
Pulse Mode
Processor
Doppler
Single Target
Doppler
Clutter
Processor
Doppler
Filter
Bank
R,R
o
Display
Antenna
Controller
Airborne Radar
Driver Amplifier
Circuit (Refer to
Figure 2-2B)
Fig 2-2A RELATIONSHIP BETWEEN MISSION ACCOMPLISHMENT
EQUIPMENT PERFORMANCE AND CIRCUIT RELIABILITY
23
Part Failure Mode
Failure Mode Impact
Safety Mission
Unscheduled
Maintenance
01 Short
R4 Short
Cl Open
Rl Open
R2 Short
R3 Open
CR1 Short
01 Open
Cl Short
Rl Short
R2 Open
R3 Short
R4 Open
CRI Open
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Failure Mode Matrix
Failure Modes Whose Probability of
Occurrence Impacts Safety-R -h(PI)(P2)
PI P2 P3 P4 P5 P6 P7 P8
/QT\/64\/CI^^
~~AShortMShort hvOpen h~u)pen HShortHOpen HShort hi Open r~
Failure Modes Whose Probability of
Occurrence Impacts Mission Success- R^/j I"(PI) (P8)
PI4 TO PI2 PTl PIO PI
Failure Modes Whose Probability of Occurence Impacts
Unscheduled Maintenance - R^j* l"(PI) (PI4)
Safety, Mission, 8 Unscheduled Maintenance Reliability
Fig 2-2B RELATIONSHIP BETWEEN MISSION ACCOMPLISHMENT,
PERFORMANCE, 8 CIRCUIT RELIABILITY (CONT.)
24
of how these concepts appl y even at the circuit l evel of compl exity.
Figure 2- 2a shows a typical driver circuit within the system architecture
of a typical airborne radar. Figure 2- 2b indicates the rel iabil ity im-
pl ications of various fail ure modes in this circuit.
Figure 2- 2b identifies those parts whose specific fail ure modes
woul d resul t in a safety hazard. Simil arl y, the functioning of those
parts whose fail ure modes woul d cause mission abort are indicated.
Final l y, it is indicated that unschedul ed maintenance depends on the
proper functioning of al l el ements. For critical mil itary systems,
these considerations are defined in contractual documents and are usual l y
specified quantitativel y in terms of probabil ity of success (rel iabil ity)
or mean- time- between- fail ure (MT BF), as appl icabl e.
Regardl ess of which of the particul ar safety, mission or unschedul ed
maintenance considerations are being addressed, the rul es for rel iabil ity
connectivity are appl icabl e. T hese rul es impl y that fail ures are stress
rel ated and the exponential fail ure distribution is appl icabl e.
Each of the diagrams shown in Figure 2- 2b represents a serial rel i-
abil ity configuration. Fail ure of any one part in the series woul d
resul t in fail ure of the equipment. Further, it may be assumed that
fail ure of any part woul d occur independentl y of the operation of other
components.
I n general , the serial equipment configuration may be represented
by the fol l owing bl ock diagram:
I nput
Rj(t) R
2
(t) R
n
(t) O utput
Rel iabil ity of the series configuration is the product of the rel iabil
ities of the individual bl ocks:
R
s
(t) = Rjft) R
2
(t) ... R.(t) .- . R
n
(t)
where
R (t) is the series rel iabil ity, and R^ t) is the rel iabil ity
of the " i
th
" bl ock for the time " t" .
25
T he concept of constant fail ure rate al l ows the computation of
system rel iabil ity as a function of the rel iabil ity of parts and com-
ponents to be accompl ished in the fol l owing manner:
" - A .t - A .t - X
9
t - A t
R(
t
) * T Je ' - e " e
2
e
n
1 = 1
This can be simplified:
- (A .t+ A
9
t+ ... + A t) - (A , + A
9
+ ... + Xjt
R(t) = e
l

2

n
= e
l

n
T he general form of this expression can be written:
n
R(t) = exp
- * I
X
i
L i = l J
A nother important rel ationship is obtained by considering the j
tn
sub-
system fail ure rate (A .) to be equal to the sum of the individual fail -
j
ure rates of n independent el ements of the subsystems such that:
n
Tl'i
1 = 1
Revising the MTBF formulas to refer to the system rather than an indiv-
idual element gives the mean-time-between-failures of the system as:
MT BF
=
i =
l
A .. n
1
si
i th
Successive estimates of the j
z
subsystem fail ure rate can be made by
combining l ower l evel fail ure rates using
n
1=1
where
A .. = the fail ure rate of the i
tn
component in the j
tn
l evel
J
subsystem
A - = fail ure rate of j
th
l evel subsystem.
J
26
Equipment rel iabil ity is therefore a combination of the fail ure
rates of the parts from which the equipment is buil t. A s previousl y
stated, these part fail ure rates can combine in series so that if any
part fail s, the equipment fail s. T hey can al so combine in paral l el so
that when a part fail s there is another part to perform the same func-
tion.
T he more compl ex configuration woul d consist of equipment items
or parts operating both in series and paral l el combinationstogether
with the various permutations. A paral l el configuration accounts for
the fact that al ternate part or item configurations can be designed to
insure equipment success. A two el ement paral l el rel iabil ity configura-
tion is represented by the fol l owing bl ock diagram:
I nput O utput
I n order to eval uate the rel iabil ity of paral l el configurations,
consider, for the moment, that a rel iabil ity val ue (for any configura-
tion) is synonomous with probabil ity (i.e., probabil ity of successful
operation) and can take on val ues ranging between 0 and 1 . I f we
represent the rel iabil ity by the symbol and its compl ement (i.e.,
unrel iabil ity) by the symbol Q, then from the fundamental notion of
probabil ity,
R + Q = 1
R = 1 - Q
From the above, it can be seen that a probabil ity can be associated
with successful operation (rel iabil ity) as wel l as with fail ure (unrel i-
abil ity). For a singl e bl ock (on the bl ock diagram), the above rel ation-
ship is val id. However, for the two el ement paral l el rel iabil ity
configuration shown, two paths for successful operation exist and the
above rel ationship becomes:
27
(R
1
+ Q
1
)(R
2
+ Q
2
)
=

l
A ssuming that R. = R and Q, = Q (i.e., the bl ocks are identical ), this
can be rewritten as
(R + Q)
2
= 1
Upon expansion, this becomes
R
2
+ 2RQ + Q
2
= 1
Recal l that rel iabil ity represents the probabil ity of successful
operation. T his condition is represented by the first two terms of the
above expression. T hus, the rel iabil ity of the paral l el configuration
can be represented by:
R = R
2
+ 2RQ
2
Note that either both branches are operating successful l y (the R term),
or one has fail ed whil e the other operates successful l y (the 2RQ term).
Substituting the val ue of R = 1 - Q into the above expression, we
obtain
R
p
= (1 - Q)
2
+ 2(1 - Q)Q
= 1 - 2Q + Q
2
+ 2Q- 2Q
2
R
p
= 1 - Q
2
T o obtain an expression in terms of rel iabil ity onl y, the substitution
Q = 1 - R can be made which yiel ds:
R
p
= l - (l - R)U- R)
Returning to the more general case where R, f R~ , this may be
expressed:
R
p
= l - a- RjXl - Rg)
By simil ar reasoning, it can be shown that, for n bl ocks connected in a
paral l el rel iabil ity configuration, the rel iabil ity of the configuration
can be expressed by:
28
Rp(t) l - d- RjJd- Rg) ... (1 - R
n
)
T he series and paral l el rel iabil ity configurations (and combinations of
these), as described above, represent the basic concepts invol ved in
estimating the rel iabil ity of compl ex equipment. A further el aboration
of paral l el rel iabil ity configurations (redundancy techniques) is given
in Section 4 .1 .4 of this handbook.
T he serial and paral l el rel iabil ity concepts presented in the pre-
ceding paragraphs establ ish the mathematical framework for the rel iabil -
ity connectivity of various el ements. T heir appl ication can be
il l ustrated to show both the benefits and penal ties of redundancy when
considering safety, mission and unschedul ed maintenance rel iabil ity.
For exampl e, a simpl ified equipment composed of three functional el ements
(as shown bel ow) can be used to il l ustrate the technique.
Radar
A l timeter (1 )
Radar
A l timeter (2)
Computer
Processor (3 )
El ements 1 and 2 are identical and represent one form of functional
redundancy operating in series with El ement 3 . A practical exampl e of
this configuration can be taken from the B- l avionics suite. Referring
to Figure 2- 3 , it can be seen that redundant I nertial Navigation Systems
(I NS) and/or Radar A l timeters are associated with El ements 1 and 2.
El ement 3 represents the computer processor, which uses the output of
each el ement to arrive at a substantial l y more accurate position fix or
al titude profil e control .
Rel iabil ity bl ock diagrams can be defined corresponding to non-
redundant serial , safety, mission and unschedul ed maintenance rel iabil ity.
A s described initial l y in this section, the rel iabil ity bl ock diagrams
depict onl y those functional el ements which must operate properl y to
meet that particul ar rel iabil ity requirement. Figure 2- 4 depicts the
29
NAV/Weapons
INS Unit-I
LN- 155
I/O
Cr\
INS Unir-2
LN-155
I
I
LLLTV
I
FLIR
h
Servo
?
FWD. Look Radar
APO-144
TFR Radar
AP0-I46
Radar Altimeter
APN-194
Avionic Control
Mass
Storage
Nov.
Control
Weapon
Control
FLR
Term
TFR
Term
<=

I/O
Doppler Radar
APN- 185

Data
Entry
b
L
Radar Altimeter
APN-194
r
i/o
Stores Management
SRAM
I7v
Nuclear
Bombs
Conv.
Bombs
7^rz_:_A_
Mission/Traffic Control
Controls/Display
Rear
Station
Front
Station
3E=3F-
CITS
PO
Central Integ.
Test System
A/V
CITS
Air Vehicle Electronics
c
I l_
Multiple A/V
Systems
Note Presence Of Redundant Internal Navigation and Radar Altimeter Systems
Fig 2-3 BLOCK DIAGRAM OF B-l INTEGRATED OFFENSIVE AVIONIC
SYSTEMS UNDER COMPUTER CONTROL
30
R
Serial
=
V
R
2" -
R
n
R
l
=

0
"
8 5
where R
?
= 0 .8 5
R = e"
U
K
n
e
R
3
= 0 .9 9
MT BF = i t = 1 0 0 hours
Paral l el
=

1
" Cl - W(l - R)
= 2R- R
2
Rel iabil ity
Requirement
Rel iabil ity Bl ock
Diagram
Cal cul ated
Val ues
1 . Serial
(Nonredundant)
Rel iabil ity
R = R
X
R
3
= 0 .8 4
MT BF = 5 7 5 hrs
-1 i \ -m-
2. Safety
(or Mission)
Rel iabil ity
R
=
2
[
R
1 -
R
fl
R
3
= 0 .9 7
Equival ent MT BF
= 3 0 3 0 hrs
r
l
'

hi 3 U
H 2 f
3 . Unschedul ed
Maintenance
Rel iabil ity
R = R
1
R
2
R
3
= 0 .7 2
MT BF = 29 8 hrs
"i
!
h
-LZ>-LJ_h
Fig. 2- 4 CA LCULA T I O NS FO R SYST EM RELI A BI LI T Y
3 1
various bl ock diagrams, rel iabil ity formul as and typical val ues corre-
sponding to these requirements. Figure 2- 4 indicates that the use of
redundancy provides a significant increase in safety and mission rel iabil -
ity numerics above that of a serial or nonredundant configuration; however,
it imposes a penal ty by adding an additional serial el ement in the un-
schedul ed maintenance chain.
2.1 .3 Part Fail ure Model ing
A s indicated previousl y, prediction is an integral task of rel iabil -
ity devel opment programs. T he basic concept which underl ies rel iabil ity
prediction and the cal cul ation of rel iabil ity numerics is that system
fail ure is a refl ection of part fail ure. T herefore, a method for esti-
mating part fail ure rates is needed. T he most direct approach to esti-
mating part fail ure rates invol ves the use of l arge scal e data col l ection
efforts to obtain the rel ationships (i.e., model s) between engineering
and rel iabil ity variabl es. T his approach util izes control l ed test data
to:
(a) derive rel ationships between design and generic rel iabil ity
factors, and
(b) devel op factors for adjusting the rel iabil ity to estimate fiel d
rel iabil ity when considering appl ication conditions.
T hese data have been reduced through physics- of- fail ure techniques
3
and are incl uded in MI L- HDBK- 21 7 B in a form suitabl e for estimating
stress- rel ated fail ure rates. MI L- HDBK- 21 7 B provides guidance during
design and al l ows individual part fail ure rates to be combined within a
suitabl e system rel iabil ity model (see Section 2.1 .2) to arrive at an
estimate of system rel iabil ity.
Part fail ure model s (see Figure 2- 5 ) vary with different part types:
however, their general form is:
where:
X . is the total part fail ure rate.
3 2
Stress Level 3
Stress Level 2
Stress Level I
* Where Stress Levels 1,2,
etc., Represent Fixed
Values Of Applied Stress
(e.g. Voltage, Power, etc.)
Temp
Failure Rate
Adjustment Factor
T
E "A
W
B

^n
Values
X
y
l
PART
X
b
(7T
E
)(7r
A
)(7r
Q
)... (7T
n
)
Fig 2- 5 PA RT FA I LURE MO DEL (Conceptual )
x , is the base fail ure rate. T he val ue is obtained from reduced
part test data for each generic part category, where the data is
general l y presented in the form of fail ure rate versus normal ized
stress and temperature factors. T he part's primary l oad stress
factor and its factor of safety are refl ected in this basic
fail ure rate val ue. A s shown in Figure 2- 5 , the val ue of A . is
general l y determined by the anticipated stress l evel (e.g.,
power and vol tage) at the expected operating temperature. T hese
val ues of appl ied stress (rel ative to the part's rated stress)
represent the variabl es over which design control can be exercised
and which infl uence the item's ul timate rel iabil ity.
3 3
I T is the environmental adjustment factor which accounts for the
infl uences of environments other than temperature, and is rel ated
to the mil itary operating condition (vibration, humidity, etc.)
under which the item must perform. T hese environmental cl asses
have been defined in MI L- HDBK- 21 7 B. T abl e 2- 1 defines each cl ass
3
in terms of its nominal environmental conditions. Depending
upon the specific part type and styl e, the val ue of T V may vary
from 0 .2 up to 1 20 . T he missil e l aunch environment is usual l y
the most severe and general l y dictates the highest val ue of T T
F
.
Val ues of Hr for microel ectronic devices have been added to
T abl e 2- 1 to characterize this range for a particul ar part type.
I T . is the appl ication adjustment factor. T his factor depends on the
appl ication of the part, and takes into account secondary stress
and appl ication factors that are considered to be " rel iabil ity-
significant" .
T T Q is the qual ity adjustment factor used to account for the degree
of manufacturing control with which the part was fabricated and
tested prior to its shipment to the user. Many parts are covered
by specifications which have several qual ity l evel s. T abl e 2- 2
3
identifies parts with mul til evel qual ity specifications.
T abl e 2- 3 shows actual val ues of - rr
n
for the various qual ity l evel s
w 3
for microel ectronics and discrete transistors.
T T is the symbol for a number of additional adjustment factors which
account for cycl ic effects, construction cl ass and other factors
that modify fail ure rate.
T he data used as the basis to devel op MI L- HDBK- 21 7 B consisted of both
control l ed test data and fiel d data. T he control l er test data directl y
rel ated stress/strength variabl es on a wide variety of parts and was
suitabl e to establ ish the base fail ure rates (A , ).
Base fail ure rates, in general , have been establ ished from tests
conducted under accel erated stress conditions which speed up the aging
process. Stress l evel s were defined, time to fail ure data was recorded
and al l fail ure modes were identified. Part fail ure rates derived under
accel erated stress conditions were then converted to normal operating
3 4
T abl e 2- 1 ENVI RO NMENT A L SYMBO L I DENT I FI CA T I O N A ND DESCRI PT I O N
Environment
* E
Symbol Nominal Environmental Conditions Val ue
Ground, Benign G
B
Nearl y zero environmental stress with optimum
engineering operation and maintenance.
0 .2
Space, Fl ight S
F
Earth orbital . A pproaches Ground, Benign condi-
tions without access for maintenance. Vehicl e
neither under powered fl ight nor in atmospheric
re- entry.
0 .2
Ground, Fixed G
F
Conditions l ess than ideal to incl ude instal l a-
tion in permanent racks with adequate cool ing air,
maintenance by mil itary personnel and possibl e
instal l ation in unheated buil dings.
1 .0
Ground, Mobil e
(and Portabl e)
G
M
Conditions more severe than those for Gp; mostl y
for vibration and shock. Cool ing air suppl y may
al so be more l imited, and maintenance l ess
uniform.
4 .0
Naval ,
Shel tered
N
S
Surface ship conditions simil ar to Gr but sub-
ject to occasional high shock and vibration.
4 .0
Naval ,
Unshel tered
N
U
Nominal surface shipborne conditions but with
repetitive high l evel s of shock and vibration.
5 .0
A irborne,
I nhabited
A
I
T ypical cockpit conditions without environ-
mental extremes of pressure, temperature,
shock and vibration.
4 .0
A irborne,
Uninhabited
A
U
Bomb- bay, tail , or wing instal l ations where
extreme pressure, temperature and vibration
cycl ing may be aggravated by contamination
from oil , hybraul ic fl uid, and engine exhaust.
Cl asses I and l a equipment of MI L- E- 5 4 0 0
shoul d not be used in this environment.
6.0
Missil e,
Launch
M
L
Severe conditions of noise, vibration, and
other environments rel ated to missil e, l aunch
and space vehicl e boost into orbit, vehicl e
re- entry and l anding by parachute. Conditions
may al so appl y to instal l ation near main
rocket engines during l aunch operations.
1 0 .0
*
Val ues for monol ithic microel ectronic devices.
3 5
T abl e 2- 2 PA RT S WI T H MULT I - LEVEL QUA LI T Y SPECI FI CA T I O NS
Part Qual ity Designators
Microel ectronics A , B, B- 1 , B- 2, C
Discrete Semiconductors JA NT XV, JA NT X, JA N
Capacitors, Establ ished Rel iabil ity (ER) L, M, P, R, S
Resistors, Establ ished Rel iabil ity (ER) M, P, R, S
Table 2-3 TT
Q
- QUALITY FACTORS
Microel ectronic Qual ity Factors
Qual ity Level
or Screen Cl ass Description
A
B
B- l
B- 2
C
D
MI L- M- 3 8 5 1 0 , Cl ass A (JA N)
MI L- M- 3 5 8 1 0 , Cl ass B (JA N)
MI L- ST D- 8 8 3 , Method 5 0 0 4 , Cl ass B
Vendor Equival ent of MI L- ST D- 8 8 3 ,
Method 5 0 0 4 , Cl ass B
MI L- M- 3 8 5 1 0 , Cl ass C (JA N)
Commercial (or non- MI L ST D) part, with
no screening beyond the manufacturer's
regul ar qual ity assurance practices. T he
indicated T T Q val ue represents an average
for al l grades of commercial parts.
1
2
5
1 0
1 6
1 5 0
T ransistor Qual ity Factors
JA NT XV
JA NT X
JA N
LO WER
Val ues of T T Q shown are appl icabl e to
MI L- S- 1 9 5 0 0 transistor covering l inear,
l ogic switching and high frequency
appl ications.
0 .2
0 .4
2.0
1 0 .0
3 6
conditions through knowl edge of the test accel eration factors. A ccel er-
ation factors were determined through detail ed anal yses of accel erated
test fail ures invol ving physics- of- fail ure studies to determine mech-
anisms of fail ure.
T he aging process has been characterized via rate process model s,
4
attributed to A rrhenius and Eyring, that are a resul t of both empirical
data and theoretical considerations. T hese rate process model s form the
basis of physics- of- fail ure and accel erated test techniques and provide
a rel ationship between stress (el ectrical and thermal ), time and fail ure
rate. T he A rrhenius model takes the fol l owing general form.
-cjl
x
b
-
Kl
e
K = a constant
c = a constant depending on the activation energy of the
individual part type fail ure mechanism
T = absol ute temperature in K.
T he Eyring model incl udes an additional temperature factor (T ):
- Cp/T
X
b
= K^ e
T he individual constants are, of course, different in val ue from those
of the A rrhenius model .
Neither of these rel ationships have been proven to be exact model s
of the time- stress combination with respect to fail ure rates. T hey are
merel y approximations, useful in conjunction with a certain set of con-
ditions.
A l though l aboratory control l ed test data provide val ue information
as to the upper l imit or potential rel iabil ity of parts, appl ication
factors and the use environment prevent real ization of this potential .
Fiel d data col l ection and anal ysis efforts have indicated part fail ure
rates wel l above those determined from l aboratory testing. T o account
for the adverse infl uence of the appl ication environment and to al ign
the base fail ure rate (x, ) with fiel d experience, a series of T T factors,
as previousl y defined, have been devel oped to account for specific
3 7
production, operation and maintenance and appl ication environment stress
factors.
MI L- HDBK- 21 7 B compl etel y describes fail ure rate model s, fail ure rate
data and adjustment factors to be used in estimating the fail ure rate for
the individual generic part types. T abl e 2- 4 presents a tabul ation of
several model s, their base fail ure rates (x
b
), associated -n factors and
fail ure rate val ues for several representative part types. T he specific
procedures for deriving the fail ure rates differ according to part cl ass
and type.
T abl e 2- 4 REPRESENT A T I VE PA RT FA I LURE RA T E CA LCULA T I O NS
Factors
Model
V alues
x
b
"
E
* Q
Y * T 2
C
l
c
2
* R
w
cy
P
6
(xl 0 ~
6
)
Monol ithic Bipol ar
Microel ectronic
Device
Xp= (T T J_ ) (T T Q) (^ ^ T T J
+ C
2
T T
E
)
6 . 0 5 . 0 1. 0 1. 9 0. 006 0. 002 0 .1 1 5
F i x ed Resi stor
0. 0015 3. 0 5 . 0 1. 6 0 .0 9 6
F i x ed Capaci tor
A
p
= A
b
(7 T
E
)(T T
cv
)(7 V
Q
) 0. 003 24. 0 1. 0 2.0 0 .1 4 4
2.2 Managing for Rel iabil ity
Studies have shown that for compl ex avionics systems, the attainment
of rel iabil ity goal s during the devel opment phase has not guaranteed
achievement of the same rel iabil ity l evel in the fiel d. T ypical l y,
rel iabil ity has been found to be degraded by a factor ranging from 3 to
1 0 during operation and maintenance phases fol l owing production. T his
is due to many factors among which are:
3 8
(a) Lack of an effective R&M program
Depth, time and sophistication of R&M efforts during equipment
devel opment wil l significantl y impact the rel iabil ity achieved in the
fiel d.
(b) I mperfect maintenance
General l y, al l maintenance actions are reported; hence, actions due
to fal se al arms, secondary fail ures, maintenance induced fail ures and
adjustments are refl ected in the fiel d rel iabil ity numeric.
(c) I naccurate accounting of operating time
Fiel d rel iabil ity refl ects the ratio of total operating hours to
number of maintenance actions. Many times operating time estimates are
based on " on- l ine" operating time onl y. I f based on total operating
time (i.e., check out time and operating time), the fiel d rel iabil ity
wil l much more cl osel y approximate the rel iabil ity demonstrated during
devel opment.
A s indicated in Section 1 .2, achievement of high fiel d rel iabil ity
is the resul t of good management. A rel iabil ity program must be pl anned
and impl emented during devel opment. A control system must be establ ished
that incl udes provisions for:
(a) A ccuratel y predicting and anal yzing rel iabil ity by devel oping
and appl ying a rel iabil ity model that accounts for design,
production and fiel d appl ication factors.
(b) Forcing out defects through a strong aggressive rel iabil ity
growth program.
(c) Simul ating fiel d conditions in R&M performance and demonstra-
tion tests.
I n general , management and control of system rel iabil ity must be
based on a recognition of the system's l ife cycl e beginning at concept,
extending through design and production and ending at removal of the
system from the inventory. T he ul timate objective of the management
effort is to achieve acceptabl e fiel d rel iabil ity. T hus, the achieve-
ment of an acceptabl e fiel d rel iabil ity for any given system invol ves
numerous tasks which must occur prior to fiel d use. Figure 2- 6 depicts
3 9
Brood
Conceptual
Phase
Validation
Phase
Full Scale
Development
Phase
Production
Phase
Deployment
Phase
Fig. 2-6 RELIABILITY LIFE CYCLE ACTIVITIES
some of the activities which must be structured, schedul ed and impl e-
mented in order that fiel d rel iabil ity objectives are met, and which are
keyed to hardware devel opment mil estones. T hey represent an approach to
a wel l rounded rel iabil ity engineering program. Shown are both govern-
ment and contractor efforts to:
(1 ) I nitiate rel iabil ity activities in the conceptual phase and
earl y val idation phases of devel opment.
(2) Perform system anal ysis invol ving tradeoff decisions beginning
during the l ater conceptual phase and continuing through the
devel opment phase.
(3 ) Structure RFP requirements which cover rel iabil ity, its growth
and demonstration test requirements.
(4 ) Eval uate and sel ect contractor(s).
(5 ) Monitor contractor performance during devel opment.
(6) Perform rel iabil ity al l ocations, predictions and fail ure
mode and effects anal yses.
(7 ) Conduct growth and demonstration tests.
(8 ) Sel ect and procure component parts.
(9 ) A ssess degradation factors for production and fiel d use.
(1 0 ) Col l ect fiel d data to measure actual fiel d rel iabil ity.
O f particul ar interest to the design engineer is the set of rel i-
abil ity activities which must occur during system devel opment. Standard
rel iabil ity program provisions are ful l y defined in A FSCP- 8 0 0 - XX,
" Rel iabil ity and Maintainabil ity (R&M) Management Guicfe" . T he document
expl ains how to insure appropriate l evel s of rel iabil ity and maintain-
abil ity over the l ife cycl e of systems and equipment through effective
management actions by staff, program office and contractor personnel .
Figure 2- 7 , taken from A FSCP- 8 0 0 - XX, l ists the el ements of a hard-
ware rel iabil ity program and shows the importance of each el ement during
the l ife cycl e phases of devel opment. T his l ist general l y fol l ows the
outl ine of MI L- ST D- 7 8 5 A , " Rel iabil ity Program for Systems and Equipment
Devel opment and Production" . MI L- ST D- 7 8 5 A is the basic standard for
4 1
El ement
Requirements Definition
Rel iabil ity Model
Rel iabil ity Prediction
Rel iabil ity A pportionment
Fail ure Modes A nal ysis
Design for Rel iabil ity
Parts Sel ection
Design Review
Design Specifications
A cceptance Specifications
Rel iabil ity Eval uation T ests
Fail ure A nal ysis
Data System
Qual ity Control
Environmental T ests
Rel iabil ity A cceptance T ests
Life Cycl e Phase
Conceptual
xxxxxxxxxx <xxxxxxA A A A hA
XXXXX (XXXXXXXXXX) xxxxx
XXXXX (XXXXXXXXXX) XXXXX
00000 )0000000000(I00000
00000
00000
)0000000000
)XXXXXXXXXX
Val idation
ooooo )XxxxxxxxxxhA A A A A
00000 )XXXXXXXXXX)XXXXX
XXXXXXX (XXXXXXXXXX)X
xxx(xxxxxxxA A A A A
XXXXX
XX
Ful l Scal e
Devel opment
XXXXX
xxxxxxxxxxx
XXXXXXXXXX)XXXXX
xxxxxxxxxxxxxxxxxxxxxxc O O O O O O O O O O C 0 0 0 0 0 0 0 0 0 0
xxxxxxxxxx);xxxxxxxxxxxc
0 0 0 0 0 0 0 0 0 0 )XXXXXXXXXXX)xxxxxxxxxxooooooooooo
Production Depl oyment
O O O O O O O O O O C 0 0 0 0 0 0 0 0 0 0
.A A A A A /A
...A A A A A ooooooooo
First contract
KEY
Desirabl e activity (for highest success
probability)
oooooo Necessary activity (errors sel dom disastrous)
xxxxxx Very important activity (errors often
disastrous)
A A A A A A Critical activity (errors usual l y
disastrous)
Low key activity (to update previous
resul ts)
Figure 2- 7 RELI A BI LI T Y PRO GRA M ELEMENT S
1 0
4 2
pl anning rel iabil ity programs for Department of Defense devel opment and
production contracts.
2.3 Rel iabil ity Eval uation T ool s During Devel opment
Rel iabil ity eval uation techniques can be cl assified into the cate-
gories shown in Figure 2- 8 . T he figure indicates that various model s
are used to apportion rel iabil ity requirements to various l evel s of
hardware within the total system, and to predict the design's inherent
rel iabil ity. T he estimates become benchmarks for subsequent rel iabil ity
assessment efforts. O ther rel iabil ity efforts are concerned with trading
and measuring the growth of rel iabil ity during the devel opment effort,
and with assuring that rel iabil ity is not degraded during production or
during operation and maintenance activities. A l though several methods
and techniques are empl oyed during the devel opment effort to eval uate
rel iabil ity, they al l rel y on prediction techniques to provide a quanti-
tative measure of rel iabil ity.
Rel iabil ity prediction, fail ure modes and effects anal ysis (FMEA )
and rel iabil ity growth techniques represent those prediction and design
eval uation methods that provide a quantitative measure of how rel iabl y
the design wil l perform. A dditional l y, these techniques hel p determine
where the design can be improved. Since specified rel iabil ity goal s
have become common contractual requirements which must be met al ong with
functional performance requirements, it is evident that these quantita-
tive eval uations need to be appl ied during the design stage to guarantee
that the equipment wil l function as specified for a given duration under
the operational and environmental conditions of intended use. T hese
rel iabil ity eval uation tasks are described in the subsections which
fol l ow.
2.3 .1 Prediction T echniques
Rel iabil ity prediction is the process of quantitativel y assessing
the rel iabil ity of a system or equipment during its devel opmentprior
to l arge scal e fabrication and fiel d operation. During design and
devel opment, predictions serve as quantitative guides by which design
al ternatives can be judged for rel iabil ity. Rel iabil ity predictions
al so provide criteria for rel iabil ity growth and demonstration testing,
l ogistics cost studies and various other devel opment efforts.
4 3
Reliability
Evaluation
Techniques
Allocation,
Prediction
And Assessment
Models
Allocation
Series
Models
Agree
Weighting
Models
R Assurance
Techniques
Other
Evaluation
Techniques
Prediction Assessment Production Operation
Maintenance
MIL-HDBK-
217
Bayesian
Techniques
Probabilistic
Design
FMEA
I
R Growth
" I
Systems
Reviews
I
Failure
Analysis
Fig 2-8 CLASSIFICATION OF RELIABILITY EVALUATION TECHNIQUES (Ref. 6)
T hus, rel iabil ity prediction is a key to system devel opment and
al l ows rel iabil ity to become an integral part of the design process. T o
be effective, the prediction technique must rel ate engineering variabl es
(the l anguage of the designer) to rel iabil ity variabl es (the l anguage of
the rel iabil ity engineer).
A prediction of rel iabil ity is obtained by determining the rel iabil -
ity of the l owest system l evel item and proceeding through intermediate
l evel s until an estimate of system rel iabil ity is obtained. T he predic-
tion methodol ogy is dependent on the avail abil ity of: (1 ) accurate
eval uation model s that refl ect the rel iabil ity connectivity of the l ower
l evel items and (2) substantial fail ure data that has been anal yzed and
reduced to a form suitabl e for appl ication to the l ow l evel items.
T here are various formal prediction procedures, based on theoretical
and statistical concepts that differ in the l evel of data on which the
prediction is based. T he specific steps for impl ementing tfciese procedures
are described in detail in rel iabil ity handbooks. A mong the procedures
avail abl e are parts count methods and stress anal ysis techniques. Fail -
ure rate data for both methods are avail abl e in MI L- HDBK- 21 7 B.
T he parts count method provides an estimate of rel iabil ity based on
a count by part type (resistor, capacitor, integrated circuit, transistor,
etc.). T his method is appl icabl e during proposal and earl y design studies
where the degree of design detail is l imited. I t invol ves counting the
number of parts of each type, mul tipl ying this number by a generic fail -
ure rate for each part type and summing up the products to obtain the
fail ure rate of each functional circuit, subassembl y, assembl y and/or
bl ock depicted in the system bl ock diagram. T he advantage of this method
is that it al l ows rapid estimates of rel iabil ity in order to quickl y
determine the feasibil ity (from the rel iabil ity standpoint) of a given
design approach. T he technique uses information derived from avail abl e
engineering information and does not require detail ed part- by- part stress
and design data.
T he stress anal ysis technique invol ves the same basic steps as the
part count technique. However, the stress anal ysis technique requires
the use of detail ed part model s (as shown in Section 2.1 .3 ) pl us cal cul a-
tion of circuit stress val ues for each part prior to determining its
4 5
fail ure rate. Each part is eval uated in its el ectrical circuit and
mechanical assembl y appl ication based on an el ectrical and thermal
stress anal ysis. O nce part fail ure rates are establ ished, a combined
fail ure rate for each functional bl ock in the rel iabil ity diagram can
be determined. T o facil itate cal cul ation of part fail ure rates, work-
sheets based on part fail ure rate model s are normal l y prepared to aid
in the eval uation. Figure 2- 9 depicts a worksheet patterned after in-
formation derived from MI L- HDBK- 21 7 B. T hese worksheets are prepared for
each functional circuit in the system. When compl eted, these sheets
provide a tabul ation of circuit part data incl uding: part description,
el ectrical stress factors, thermal stress factors, basic fail ure rates,
the various mul tipl ying or additive environmental and qual ity adjust-
ment factors, and the final combined part fail ure rates. T he variation
in part stress factors (both el ectrical and environmental ) resul ting
from changes in circuitry and packaging is the means by which rel iabil ity
is control l ed during design. Considerations for and effects of reduced
stress l evel s (derating) which resul t in l ower fail ure rates are treated
in Section 4 .1 .3 .
Both the parts count and the stress anal ysis methods of predicting
rel iabil ity rel y on part fail ure rate data obtained from MI L- HDBK- 21 7 B.
However, not al l parts used in el ectronic system design are incl uded in
MI L- HDBK- 21 7 B. For those parts not covered by 21 7 B, where l ittl e sup-
porting data is avail abl e, care must be exercised in estimating their
fail ure rates. I n general , estimating fail ure rates for parts having
l imited fail ure data invol ves comparative eval uations or special tests
and studies.
Comparative eval uations invol ve the extrapol ation of fail ure data
from wel l documented parts to parts having l ittl e or no fail ure data
provided simil arity exists. Simil arity refers to those performance,
type, cl ass, construction, material or rating parameters by which the
comparison can be made. T o remain val id, extrapol ation must account for
the differences between the parts compared as wel l as their simil arities
and must be supported by detail ed rational e.
Eval uations must incl ude modes of fail ure, production history and
other factors bearing on rel iabl e operations.
4 6
STRESS ANALYSIS - RELIABILITY PREDICTION WORKSHEET
ENGINEERING DATA RELIABILITY ANALYSIS
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Fig 2-9 STRESS ANALYSIS - RELIABILITY PREDICTION WORKSHEET
Part test efforts usual l y require extended time periods and/or
l arge quantities of parts before statistical l y confident fail ure rates
can be establ ished. Costs associated with l arge scal e part testing may
be difficul t to justify for l ow usage parts.
I n another direction, efforts to rel ate rel iabil ity to system func-
tion and performance l evel , as exempl ified by the " Rel iabil ity Prediction
T echniques for Conceptual Phases of Devel opment" , have produced inter-
esting resul ts. Strong correl ations have been found between radar per-
formance variabl es (such as peak power, pul se width, antenna gain, etc.)
and MT BF characteristics. T hese techniques, based on the anal ysis of
system fail ure data, provide a means for rel ating predictions to actual
system use history and through mathematical methods such as regression
anal ysis, to major performance parameters.
o
I n addition, newer techniques are currentl y avail abl e which al l ow
estimates to be made of the time requirements needed to bring a newl y
devel oped system to rel iabil ity maturity (RPM). A t l ower l evel s of
assembl y, the concepts rel ated to the forced defect approach to sub-
assembl y testing are appl icabl e. T hese techniques al l ow for quantitative
estimation of the rel iabil ity growth process which heretofore, for the
most part, was ignored in the design and production process. Rel iabil ity
growth techniques are discussed in Section 2.3 .3 .
T he actual prediction techniques used for any given system vary
depending on the phase of system devel opment. Consequentl y, each pre-
diction effort is eval uated in view of the devel opment phase which it
represents. For exampl e, a gross rel iabil ity prediction (based on rough
parts count or based on function/performance l evel s) may be compl etel y
adequate during the prel iminary design and definition phase. I t woul d
serve as the basis to determine if the inherent rel iabil ity of the design
is feasibl e and is within the " design to" requirements establ ished by
cost of ownership studies, and consequentl y can be used as the basis
(from a rel iabil ity standpoint) to proceed to the detail ed design stage.
A s further information becomes avail abl e, a gross prediction woul d not
be adequate. A t this time, possibl y, a part- by- part rel iabil ity pre-
diction, based on stress anal ysis techniques, woul d be required,
4 8
Figure 2- 1 0 is a partial l ist of a radar system hierarchy. T he l ife
cycl e phases of a radar devel opment program are al so l isted. T he figure
shows that, as the program progresses from conceptual to detail ed design,
hardware is defined at a l ower l evel of the assembl y. Rel iabil ity pre-
diction, al l ocation and assessment is required to predict rel iabil ity and
shoul d be continual l y updated to refl ect the greater l evel of hardware
definition. A l so l isted in Figure 2- 1 0 are rel iabil ity prediction tech-
niques appropriate to the l evel of design definition.
2.3 .2 Fail ure Mode A nal ysis T echniques
Under the heading of fail ure mode anal ysis, two techniques are gen-
eral l y used, namel y, (1 ) fail ure mode, effects and critical ity anal ysis,
and (2) faul t tree anal ysis. Fail ure mode, effects and critical ity
anal ysis represents a " bottom- up" approach whil e faul t tree anal ysis
represents a " top- down" approach. Both represent anal ytical approaches
for assessing the consequences of fail ure.
Fail ure mode and effects anal ysis is an iterative documented process
of a systematic nature performed to identify basic faul ts at the part
l evel and determine their effects at higher l evel s of assembl y. T he
fail ure mode and effects anal ysis can be performed util izing either actual
fail ure modes from fiel d data or hypothesized fail ure modes derived from
design anal yses, rel iabil ity prediction activities and experiences rel a-
tive to the manner in which parts fail . I n their most compl ete form,
fail ure modes are identified at the part l evel , which is usual l y the
l owest l evel of direct concern to the equipment designer. I n addition to
providing insight into fail ure cause and effect rel ationships, the fail ure
mode and effects anal ysis provides the discipl ined method for proceeding
part- by- part through the system to assess fail ure consequences (see
Figure 2- 2B). Fail ure modes are anal ytical l y induced into each component,
and fail ure effects are eval uated and noted, incl uding severity and fre-
quency (or probabil ity) of occurrence. A s the first mode is l isted, the
corresponding effect on performance at the next higher l evel of assembl y
is determined. T he resul ting fail ure effect becomes, in essence, the
fail ure mode that impacts the next higher l evel . I teration of this process
resul ts in establ ishing the ul timate effect at the system l evel . O nce
the anal ysis has been performed for al l fail ure modes, it is usual l y the
4 9
Reliability Prediction
Techniques
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Part Counts
Gross Stress
Analysis
Semi Empirical
Formula
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Amplifier
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Amplifier
Power
Supplies
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Empirical Formula Tran-
sistors
TWT
Capac-
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Resis-
tors
Fig 2-10 RADAR SYSTEM HIERARCHY(PARTIAL LISTING)
case that each effect or symptom at the system l evel is caused by several
different fail ure modes at the l owest l evel . T his rel ationship to the
end- effect provides the basis for grouping the l ower l evel fail ure modes.
Using this approach, probabil ities for the occurrence of the system
effect can be cal cul ated, based on the probabil ity of occurrence of the
l ower l evel fail ure modes (i.e., modal fail ure rate times time). Based
on these probabil ities, and a severity factor assigned to the various
system effects, a critical ity number can be cal cul ated. Critical ity
numerics provide a method of ranking the system l evel effects derived
previousl y. Critical ity numerics al so provide the basis for corrective
action priorities, engineering change proposal s or fiel d retrofit actions.
Figure 2- 1 1 depicts a convenient format for documenting the information
generated during fail ure mode, effects and critical ity anal yses.
FA I LURE MO DE,
System LRU
EFFECT S A ND CRI T I CA LI T Y A NA LYSI S
D
-
Page of
Circuit Date
Eng'r
Fail ure Part
Part Mode Effect
Circuit System Fail ure
Effect Effect Frequency Critical ity
Figure 2- 1 1 FMECA WO RKSHEET
Faul t tree anal ysis (FT A ) is a tool that l ends itsel f wel l to
anal yzing fail ure modes found during design, factory test or fiel d data
returns. T he faul t tree anal ysis procedure can be characterized as an
iterative documented process of a systematic nature performed to identify
basic faul ts, determine their causes and effects, and establ ish their
probabil ities of occurrence. T he approach invol ves several steps, among
which is the structuring of a highl y detail ed l ogic diagram which depicts
5 1
basic faul ts and events that can l ead to system fail ure and/or safety
hazards. Next is col l ecting basic faul t data and fail ure probabil ities
for use in computation. T he next step is using computational techniques
to anal yze the basic faul ts, determine fail ure mode probabil ities, and
establ ish critical ities. T he final step invol ves formul ating corrective
suggestions which, when impl emented, woul d el iminate (or minimize) those
faul ts considered critical . T he steps invol ved, the diagrammatic el e-
ments and symbol s, and methods of cal cul ation are shown in Figure 2- 1 2.
T his procedure can be appl ied at any time during a system's l ife
cycl e. However, it is considered most effective when appl ied:
(a) during prel iminary design, on the basis of design information
and a l aboratory or engineering test model , and
(b) after final design, prior to ful l scal e production, on the
basis of manufacturing drawings and an initial production
model .
T he first of these is performed to identify fail ure modes and for-
mul ate general corrective suggestions (primaril y in the design area).
T he second is performed to show that the system, as manufactured, is
acceptabl e with respect to rel iabil ity and safety. Corrective actions
or measures, if any, resul ting from the second anal ysis woul d emphasize
control s and procedural actions that can be impl emented with respect to
the " as manufactured" design configuration.
T he outputs of the anal ysis incl ude:
(a) A detail ed l ogic diagram that depicts al l basic faul ts and
conditions that must occur to resul t in the hazardous condi-
tion^ ) under study.
(b) A probabil ity of occurrence numeric for each hazardous
condition under study.
(c) A detail ed faul t matrix that provides a tabul ation of al l
basic faul ts, their occurrence probabil ities and critical ities,
and the suggested change or corrective measures invol ving
circuit design, component part sel ection, inspection, qual ity
control , etc., which, if impl emented, woul d el iminate or
minimize the hazardous effect of each basic faul t.
5 2
Process Steps
Foult Tree
Diagramming
Collecting Bosic
Fault Data
Computing Probability
Numerics
Determining
Criticalities
Formulating
Corrective Action
Recommendations
Part Failure Rates
Human Performance
Human Error Rate
Application Factors
Computation n
AND Gate - P(A) P(Xj)
I n
OR Gate - P(A) - I - [ I-P(X|)]
Where P(A) - Output Probability
P(Xj) Probability Of ith input
n Number Of Inputs
Cnticality P(X|) P(H/X()
Where- P(H/X,) Is The Conditional
Probability Of The Overall Fault
Condition Given That The Bosic
Fault (X|) Has Occurred.
Areas For Redesign
Component Part Selection
Design / Procurement Criteria
Maintenance Procedures
Inspection Procedures
Quality Controls
o
o
Fault Tree Symbols
An Event Or Fault Resulting From The
Combination Of More Basic Faults
And Which Can Be Further Developed
A Basic Fault (Usually A Specific Circuit,
Part Or Human Error) Which Con Be
Assigned A Probability Of Occurrence
A Fault Not Developed Further Because
Of Lack Of Information, Time, Or Value
In Doing So
AND Gate The Output Event Occurs
Only When All The Input Events Are
Present
OR Gote - The Output Occurs When One
Or More Of The Input Events Are Present.
O

Inhibit Gate - Similar To An
AND Gate, However, Used
To Include Application Of
A Conditional Event
An Event Expected To Occur
In Normol Operation
Fig. 2-12 FAULT TREE ANALYSIS
2.3 .3 Rel iabil ity T esting
Rel iabil ity testing during system devel opment can be divided into
two major cl assifications:
(1) Reliability Growth
(2 ) Reliability Demonstration.
Rel iabil ity growth tests are for the purpose of detecting rel iabil ity
probl ems. Rel iabil ity demonstration tests are for the purpose of proving
rel iabil ity. Basic concepts associated with each of these test cl asses
are discussed in this subsection.
Rel iabil ity growth can be general l y defined as the improvement
process during which hardware rel iabil ity increases to an acceptabl e
l evel . A s indicated in Section 1 .2.3 , the measured rel iabil ity of newl y
fabricated hardware is much l ess than the potential rel iabil ity estimated
during design, using standard handbook techniques. T his definition encom-
passes not onl y the technique used to graph increases in rel iabil ity
(i.e., " growth pl ots" ) but al so the management/resource al l ocation
o
process which causes hardware rel iabil ity to increase. Both are dis-
cussed here.
T he purpose of a growth process, especial l y a rel iabil ity growth
test, is to achieve acceptabl e rel iabil ity in fiel d use. A chievement of
acceptabl e rel iabil ity is dependent on the extent to which testing and
other improvement techniques have been used during devel opment to " force-
out" design and fabrication fl aws, and on the rigor with which these fl aws
are anal yzed and corrected. A primary objective of growth testing is to
provide methods by which hardware rel iabil ity devel opment can be dimen-
sioned, discipl ined and managed as an integral part of overal l devel op-
ment. Rel iabil ity growth testing al so provides a technique for extrapo-
l ating the current rel iabil ity status (at any point during the test) to
some future resul t. I n addition, it provides methods to assess the
magnitude of the test- fix- retest effort prior to the start of devel opment,
thus al l owing tradeoff decisions.
5 4
Many of the model s for rel iabil ity growth represent the rel iabil ity
of the system as it progresses during the overal l devel opment program.
A l so, it is commonl y assumed that these curves are nondecreasing, that is,
once the system's rel iabil ity has reached a certain l evel , it wil l not
drop bel ow this l evel during the remainder of the devel opment program.
I t is important to note that this assumes that any design or engineering
changes made during the devel opment program do not decrease the system's
rel iabil ity.
I f, before the devel opment program has begun, the exact shape of the
rel iabil ity growth curve is known for a certain combination of system
design and devel opment effort, then the model is a deterministic one.
I n this case, the amount of devel opment effort needed to meet the rel i-
abil ity requirement coul d be determined, and the sufficiency of the
design woul d al so be known.
I n most situations encountered in practice, the exact shape of the
rel iabil ity growth curve wil l not be known before the devel opment program
begins. O ne may, however, be wil l ing to assume that the curve bel ongs to
some particul ar cl ass of parametric rel iabil ity growth curves. T he
anal ysis then reduces to a statistical probl em of estimating the unknown
parameters from the experimental data. T hese estimates may be revised as
more data are obtained during the progress of the devel opment program.
Using these estimates, the program manager can monitor and project the
rel iabil ity of the system and make necessary decisions accordingl y.
For compl ex el ectronic/el ectromechanical avionic systems, the model
used most often for rel iabil ity growth processes, and in particul ar rel i-
8 9
abil ity growth testing, is one original l y publ ished by J. T . Duane. '
Essential l y, this model provides a deterministic approach to rel iabil ity
growth such that the system MT BF versus operating hours fal l s al ong a
straight l ine when pl otted on l og- l og paper. T hat is, the change in MT BF
during devel opment is proportioned to T
a
where T is the cumul ative operat-
ing time and a is the rate of growth corresponding to the rapidity with
which faul ts are found and changes made to permanentl y el iminate the
basic causes of the faul ts observed.
5 5
I n order to structure a growth test program (based on the Duane
model ) for a newl y designed system, a detail ed test pl an is necessary.
T his pl an must describe the test- fix- retest concept and show how it wil l
be appl ied to the system hardware under devel opment. T he pl an must
incorporate the fol l owing:
(a) Val ues for specified and predicted (inherent) rel iabil ities.
Methods for predicting rel iabil ity (model , data base, etc.)
must al so be described.
(b) Criteria for rel iabil ity starting points, i.e., criteria for
estimating the rel iabil ity of initial l y fabricated hardware,
must be determined. For avionics systems, the initial rel i-
abil ity for newl y fabricated systems has been found to vary
between 1 0 and 3 0 % of their predicted (inherent) val ues.
(c) Rel iabil ity growth rate (or rates) must be defined. T o support
the sel ected growth rate, the rigor with which the test- fix-
retest conditions are structured must be compl etel y defined.
(d) Cal endar time efficiency factors, which define the rel ationship
of test time, corrective action time and repair time to cal endar
time, must be determined.
Note that each of the factors l isted above impacts the total time
(or resources) which must be schedul ed to grow rel iabil ity to the speci-
fied val ue. Figure 2- 1 3 il l ustrates the concepts described above.
I n addition, Figure 2- 1 3 graphical l y depicts the four el ements
needed to structure and pl an a growth test program described above.
T hese four el ements are further described as fol l ows:
(1 ) I nherent rel iabil ity- - represents the val ue of design rel iabil ity
estimated during prediction studies, and may correspond to the
val ue above that specified in procurement documents. O rdinar-
il y, the contract specified val ue of rel iabil ity is somewhat
l ess than the inherent val ue. T he rel ationship of the inherent
(or specified) rel iabil ity to the starting point greatl y infl u-
ences the total test time.
5 6
en
^4
1000
(I) Predicted (Inherent) MTBF
3
O
100
CD
(I) Specified (Acceptable)MTBF
Minimum Growth Rate
(2) Initial MTBF Or Starting Point
10
100 1000 10,000
(4) Cumulative Operating Time Under Test Conditions (Hours)
100,000
Fig 2-13 RELIABILITY GROWTH PLOT
(2) Starting point- - represents an initial val ue of rel iabil ity
for the newl y manufactured hardware usual l y fal l ing within the
range of 1 0 - 3 0 % of the inherent or predicted rel iabil ity.
Estimates of the starting point can be derived from prior
experience or are based on percentages of the estimated inher-
ent rel iabil ity. Starting points must take into account the
amount of rel iabil ity control exercised during the design pro-
gram and the rel ationship of the system under devel opment to
the state- of- the- art. Higher starting points minimize test
time.
(3 ) Rate of growthdepicted by the sl ope of the growth curve
which is, in turn, governed by the amount of control , rigor and
efficiency by which fail ures are discovered, anal yzed and cor-
rected through design and qual ity action. Rigorous test pro-
grams which foster the discovery of fail ures, coupl ed with
management- supported anal ysis and timel y corrective action,
wil l resul t in a faster growth rate and consequentl y l ess total
test time.
(4 ) Cal endar time/test time- - represents the efficiency factors
associated with the growth test program. Efficiency factors
incl ude repair time and operating/nonoperating time as they
rel ate to cal endar time. Lengthy del ays for fail ure anal ysis,
subsequent design changes, impl ementation of corrective action
or short operating periods wil l extend the growth test period.
Figure 2- 1 3 shows that the val ue of the parameter a can vary between
0 .1 and 0 .6. A growth rate of 0 .1 can be expected in those programs
where no specific consideration is given to rel iabil ity. I n those cases,
growth is l argel y due to sol ution of probl ems impacting production and
from corrective action taken as a resul t of user experience. A growth
rate of 0 .6 can be real ized if an aggressive, hardhitting rel iabil ity
program with management support is impl emented. T his l atter type program
must incl ude a formal stress oriented test program designed to aggravate
and force defects and vigorous corrective action.
5 8
Figure 2- 1 3 shows the requisite hours of operating and/or test time
and continuous effort required for rel iabil ity growth. I t shows the
dramatic effect that the rate of growth (a) has on the cumul ative operat-
ing time required to achieve a predetermined rel iabil ity l evel . For
exampl e, Figure 2- 1 3 shows, for a product whose MT BF potential is 1 0 0 0 hr,
that 1 0 0 , 0 0 0 hr of cumul ative operating time is required to achieve an
MT BF of 20 0 hr when the growth rate is 0 .1 . A nd, as previousl y stated, a
0 .1 rate is expected when no specific attention is given to rel iabil ity
growth. However, if the growth rate can be accel erated to 0 .6 (by growth
testing and formal fail ure anal ysis activities), then onl y 3 0 0 hr of
cumul ative operating time is required to achieve an MT BF of 20 0 hr.
Rel iabil ity demonstration tests are designed for the purpose of
proving, with statistical confidence, a specific rel iabil ity requirement;
not specifical l y to detect probl ems, or to grow rel iabil ity. T he test
takes pl ace after the design is frozen and its configuration is not al l ow-
ed to change. However, in practice, some rel iabil ity growth may occur
because of the deferred correction of fail ures observed during the test.
Rel iabil ity demonstration is specified in most mil itary system pro-
curement contracts and invol ves, in many instances, formal testing con-
ducted per MI L- ST D- 7 8 1 B. T his standard defined test pl ans, environmental
exposure l evel s, cycl e times and documentation required to demonstrate
formal l y that the specified MT BF requirements of the equipment have been
achieved. Demonstration tests are normal l y conducted after devel opment
has been compl eted but before high rate production has been initiated.
Demonstration tests are normal l y conducted after growth tests in the
devel opment cycl e using initial production hardware.
A s previousl y indicated, rel iabil ity demonstration testing, conducted
per MI L- ST D- 7 8 1 B, carries with it a certain statistical confidence l evel - -
and the more demonstration testing, the more confidence. T he more rel i-
abil ity growth testing that is performed, the higher the actual rel iabil ity.
Depending on program funding and other constraints, system testing may
fol l ow one of two options. T he first option maximizes growth testing
and minimizes demonstration testing resul ting in a high MT BF at a l ow
confidence. O ption two minimizes rel iabil ity growth testing with a
resul tant l ower MT BF at higher confidence. T hese concepts are shown
graphical l y in Figure 2- 1 4 .
5 9
.
GD
c
O
<D
k.
O
c
Growth Test
Time ( Option I)
-N#-
Growth Test
Time (Option 2)
Demonstration
Test Time
(Option I)
Demonstration
Test Time
(Option 2)
Option I MTBF
Option 2 MTBF
Test Time
Fig. 2- 1 4 RELI A BI LI T Y T EST I NG O PT I O NS
REFERENCES
2. Myers, R., Wong, K., and Gordy, H., Rel iabil ity Engineering for
El ectronic Systems, John Wil ey and Sons, New York, 1 9 64 .
3 . Mil itary Standardization Handbook 21 7 B, Rel iabil ity Prediction
of El ectronic Equipment, September 1 9 7 4 .
4 . Vaccaro, J., and Gorton, H. (RA DC and Battel l e Memorial I nstitute),
Rel iabil ity Physics Notebook, RA DC- T R- 65 - 3 3 0 , A D 624 7 69 , O ctober
1 9 65 .
5 . Mil itary Standard 7 8 5 A , Rel iabil ity Program for Systems and Equip-
ment Devel opment and Production, March 1 9 69 .
60
6. A nderson, R., Kos, D., and Schil l er, J. (I T T RI ), Rel iabil ity and
Maintainabil ity Pl anning Guide for A rmy A viation Systems and
Components, R&M Division, Directorate for Product A ssurance,
U.S. A rmy A viation Systems Command, St. Louis, Missouri, Jul y 1 9 7 4 .
7 . James, L.E., Sheffiel d, T .S., and Pl ein, K.M. (Hughes A ircraft Co.),
Study of Rel iabil ity Prediction T echniques for Conceptual Phases of
Devel opment, Final Report, Rome A ir Devel opment Center, RA DC- T R- 7 4 -
23 5 , O ctober 1 9 7 4 .
8 . Sel by, J. and Mil l er, S. (General El ectric), " Rel iabil ity Pl anning
and Management- RPM, " Symposium for Rel iabil ity and Maintainabil ity
T echnol ogy for Mechanical Systems, Washington, P.C. A O A , A pril 1 9 7 2,
Costs for the A PQ- 1 1 3 , - 1 1 4 , - 1 20 and - 1 4 4 Radar Systems, General
El ectric Co., A erospace El ectronic Systems Department, Utica, New
York, A ugust 1 9 7 2.
1 0 . Rel iabil ity and Maintainabil ity Management Guide, A ir Force Systems
Command, A FSCP 8 0 0 - , 1 9 7 4 .
1 1 . Mil itary Standard 7 8 1 B, Rel iabil ity T ests: Exponential Distribution,
1 9 67 .
61
SECT I O N 3
MI LI T A RY A I RBO RNE SYST EMS
3 .1 T rends in A vionics
3 .2 T he A vionics Environment
3 .3 Equipment Rel iabil ity State- of-
the- A rt
3 .4 Summary and Concl usion:
1 9 7 5 A vionics T rends
SECT I O N 3
MI LI T A RY A I RBO RNE SYST EMS
T he objective of this section is to provide a general overview of
mil itary el ectronic system design trends and the rel iabil ity design
issues and circumstances that surround them. A irborne el ectronics are
emphasized because they are most chal l enging to the designer. Constraints
in size, weight, vol ume and operational environment are general l y much
more restrictive for airborne systems than they are for ground based
equipments. T he factors are discussed rel ative to trends that are evident
today in avionics, the avionics environment over which rel iabil ity must
be provided, and an engineering judgment of current equipment rel iabil ity
state- of- the- art.
3 .1 T rends in A vionics*
O ver the l ast decade, the use of integrated circuits has increased
dramatical l y across al l portions of the RF spectrum in the areas of l ow
to medium power l evel . T he situation is approximatel y as shown in
Figure 3 - 1 , and has impacted favorabl y on the general question of rel i-
abil ity, maintainabil ity, and cost effectiveness of avionic systems.
Conventional Parts And Packaging
o *-
o o.
CD
66 68 70 72 74
ESTIMATION OF USAGE
T he material in Sections 3 .1 and 3 .4 is based on the references numbered
1 through 5 at the end of this chapter.
65
T abl e 3 - 1 is il l ustrative of avionics equipment trends in modern day
mil itary aircraft. T he avionics suite typical l y incl udes navigation,
communication, radar, penaids, I FF, internal control , displ ay and informa-
tion systems. A sampl ing of different types of aircaft is given for
comparison. Figure 3 - 2 and T abl e 3 - 2 exempl ify the system compl exity of
a typical mul timode radar. System compl exity has a strong bearing on
rel iabil ity and is considered further in Section 3 .3 .
T abl e 3 - 1 A VI O NI CS MA T RI X
A - 1 0
(Basic)
A - 1 0
(Night)
A - 1 0
(A dv) F- 1 5 F- 1 6
RF- 4 C|
(A dv)
F- 1 0 61
(A dv) B- l
NA VI GA T I O N
NA VSET
O MEGA
LO RA N
I NERT I A L
DO PPLER
A I R DA T A
T A CA N
I LS/MLS
RA DA R A LT I MET ER
RA DA R (A I R/GRO UND)
RA DA R (T A /T F)
A HRS
UHF A DF

t

0

t

t

t
FLI GHT CO NT RO L
SA S A VA I DS
A FCS A VA I DS
SA S DI GI T A L
A FCS DI GI T A L

t

t

t

CO MMUNI CA T I O NS
UHF
HF
VHF
I FF T RA NS
I FF I NT ER
DI GI T A L LI NK
DO WN LI NK
I NT ERCO M

t
0

t
t
t
t

*
EW
RHA W/ECM
ELI NT /ECM

CO NT RO LS/
DI SPLA YS
I NST RUMENT S
CO NT RO LS
HUD
HSD
VSD
MFD

t

t

t

t

t
t
t

t

*
M
I
s
S
I
0
N
FI RE
CO NT RO L
RA DA R (A /A )
MI SSI LE SUPPO RT
A I R GND (CCJP)
A I R GND FI XREF
A I R A I R (HLGS)
ST O RES MGMNT
LA SER SEEKER
LA SER RA NGER

t

t

t

SENSO RS
EO
CA MERA
SLA R
VI R
DA T A A NNO T A T I O N

t
1 I
A I RCRA FT
PRO PULSI O N CO NT RO L
FUEL MA NA GEMENT
FLI GHT HI ST O RY
FLI GHT ENVELO PE CNT RL t
t

t

1 *

*
66
c
X X
oo
CYI RADAR
1 ANTENNA I QQ
IR
RECEIVER
SYNCHRONIZER
I
TRANSMITTER
I
MICROWAVE
CIRCUITS
ANTENNA
CONTROLLER
IR
PROCESSOR
PO WER
RA DA R
MA ST ER
O SCI LLA T O R
XX X X X

o oooo
I
RADAR
RECEIVER
x
X
Hi
X
PULSE MODE
PROCESSOR
TARGET RANGE
xxxxxxxxxx DOPPLER
SINGLE TARGET
SPEED TRACKER
PSTT ANGLE
COMMANDS
**PDSTT ANGLE
COMMANDS
xxxxxxxxxx XXX.
MEASURED
ANGLES
x fcO
x 0
x 1 0
TARGET RANGE RATE
ooo
DOPPLER
CLUTTER
PROCESSOR
OOO
SCAN CENTER COMMANDS
oooooooooooooooooooooo
DOPPLER
FILTER
BANK
" 5
XXXXXXXXXXXXXXX
MEASURED
ANGLES
STT ANGLE COMMANDS
<:
AIM- 54A
PHOENIX
/\
C AIM - 7E / AIM-7F
SPARROW
^L
C AIM-96
^ SIDEW NDER^^
MEASURED
ANGLES
n
T A RGET S RA NGE A ND RA NGE RA T E

AT
I
DETAIL DATA DISPLAY
OO o oooooooooooooooooo
RANGE AND RANGE RATE
oooooo ooooooooa
DIGITAL
COMPUTER
COMPUTER PROCESSED
TARGET DATA
DATA LINK
INERTIAL DATA
MISSILE
AUXILIARIES
AIR-TO-GROUND
WEAPONS^-
LEGEND
PULSE SINGLE TARGET TRACK (PSTT)
OOOO TRACK WHILE-SCAN (TWS)
X X X XX
PULSE
TRACK
DOPPLER SINGLE TARGET
(PDSTT)
GUN
TACTICAL
INFORMATION
DISPLAY
AVIONICS,
PILOTS DISPLAYS
AND CONTROLS
Fig. 3-2 AWG-9 RADAR SYSTEM
T abl e 3 - 2 A WG- 9 RA DA R SYST EM
Analog
F uncti onal
Complex i ty
(Esti mate of
Equi valent
Seri es Acti ve
Elements)
Esti mated
Reli abi li ty
MT BF
(K H r)
(Sec. 33)
1. Radar Radar f uncti oni ng as pulse
Doppler sensor f or long and
i ntermedi ate ranges or as
conventi onal pulse radar f or
long and especi ally sh ort ranges
200-400 0. 08 -0. 16
2. Antenna Broadband, slotted planar array 1-5 20-100
Antenna Controller 10-20 3-6
Mi crowave Ci rcui ts 1-5 20-100
3. T ransmi tter 1) Uses gri dded pulse T WT f or
pulse Doppler mode and
Ph oeni x gui dance
5 0-100 0. 04-0. 8
2) Uses separate CW T WT f or
Sparrow target i llumi nati on
Synch roni zer 5 -10 6 -12
Master Osci llator 5 -10 6 -12
4. Recei ver 25 -5 0 0. 9-1. 8
Doppler Clutter Processor 10-20 3-6
Doppler F i lter Bank 10-20 3-6
Doppler Si ngle T arget Used f or Sparrow target
Speed Processor i llumi nati on mode
5 -10 6 -12
Pulse Mode Processor 5 -10 6 -12
5 . Detai l Data Di splay Storage tube 5 -10 6 -12
Si splay
1

Inf 0rmati
n
10" di ameter CRT
5 -10 6 -12
6 . Di gi tal Computer (Equi valent Analog Complex i ty) 25 -5 0 0. 9-1. 8
7. Data Li nk System (Equi valent Analog Complex i ty) 25 -5 0 0. 9-1. 8
8 . Inerti al Inf ormati on System 5 0-100 0. 4-0. 8
9. IR Recei ver 5 0-100 0. 4-0. 8
IR Processor 25 -5 0 0. 9-1. 8
10. Power System 5 0-100 0. 4-0. 8
11. Mi ssi le Aux i li ari es
AIM-5 4A Ph oeni x
AIM-7E/F Sparrow
AIM-9G Si dewi nder
5 0-100
5 0-100
5 0-100
0. 4-0. 8
0. 4-0. 8
0. 4-0. 8
68
A most significant trend, from the point of view of system archi-
tecture, is the trend toward digital el ectronics. T his is indicated by
the use of digital fl y- by- wire to repl ace mechanical l inkages and hydraul ic
systems, the use of digital mul tipl exing to repl ace extensive bundl es of
individual cabl es, and the use of computers to oversee and control the
various avionics systems.
T he ol d situation, indicated in Figure 3 - 3 a, shows the avionics
structure of the F- 4 E and indicates that each avionics function al ong
with its attendant control s, displ ays, and computer, represented essen-
tial l y a separate individual entity. T he new concept, indicated in
Figure 3 - 3 B, shows the tendency toward a general commonal ity that extends
from a control computer to a common avionics bus and integrated displ ays.
A wide range of potential advantages appears to favor this digital
avionics concept. T his incl udes the fol l owing:
(A) F -4E Avi oni cs System Arch i tecture
Opti cal
Si gh ts and
Computi ng
Gyro
Analog
Computer
Controls
Di splay
Inerttal
Attack Ai rData Measure-
Radar Sensors ment
Uni t
Analog Analoq Analog
Computer Computer
i < i
1
Controls
Di splay
Controls
Di splay Di splay
Weapon
Release
Ana 1og
Weapon
Deli very
Computer
Atti tude
H eadi ng
and
Ref erence
Uni t
Ana 1 oq
Computer
o
Di recti on
Indi cator/
H ori 2. SU.
r ~\r n
Analog
N avi gati on
Computer
(B) Digital A vionics Concept
Mi gh t
Control - Di splays
Propulsi on
Enqi nes
J Stores
Mqtnt
Central
Process Inn
Electri cal
Power
ECM
Gui dance
N avi gati on
Data
Multi plex
Bus
_ Weapons
Deli very
1 1
Communi cati ons Sensors
Fig. 3-3 DIGITAL AVIONICS TREND
69
Digital information can general l y be transmitted and processed
faster and more fl exibl y than anal og information.
Large scal e integrated- circuit (LSI ) computers can provide much
higher data processing capacities at a fraction of the cost and
size of preceding generation equipment.
t Digital avionics hol ds out the promise of significant system
rel iabil ity improvement and system cost reduction. I mproved
system rel iabil ity stems from the fact that digital avionics
offers commonal ity, and hence widespread use, of a l imited number
of modul ar subsystems among different aircraft. Furthermore, the
resul tant modul arity tends to improve maintainabil ity and provide
ready potential for future growth. Modifications and future
expansions of avionics packages woul d tend to be readil y achieved
by pl ugging different modul es into the basic core system.
T he fol l owing sections consider the avionics environment over which rel i-
abil ity must be provided and the impact of equipment compl exity on the
MT BF potential .
3 .2 T he A vionics Environment
T he avionics environment can impose rel ativel y severe operating con-
ditions on equipment with regard to conditions of temperature, al titude,
shock, vibration, humidity, sand and dust, etc. T he general mil itary
specification defining these service boundaries (primaril y for operation
in manned aircraft) is MI L- E- 5 4 0 0 . I n this specification, four cl asses
of equipment are del ineated according to the fol l owing temperature-
al titude regime:
Cl ass 1 - - Equipment designed for 5 0 , 0 0 0 ft al titude and continuous
sea l evel operation over the temperature range of
- 5 4 to + 5 5 C.
Cl ass 1 A Equipment designed for 3 0 , 0 0 0 ft al titude and continuous
sea l evel operation over the temperature range of - 5 4
to + 5 5 C.
Cl ass 2 - - Equipment designed for 7 0 , 0 0 0 ft al titude and continuous
sea l evel operation over the temperature range of - 5 4
to + 7 1 C.
7 0
Cl ass 3 - - Equipment designed for 1 0 0 , 0 0 0 ft al titude and continu-
ous sea l evel operation over the temperature range of
- 5 4 to + 9 5 C.
Cl ass 4 - - Equipment designed for 1 0 0 , 0 0 0 ft al titude and continu-
ous sea l evel operation over the temperature range of
- 5 4 to + 1 25 C.
T he operating boundaries for these cl asses of equipment are indicated in
T abl e 3 - 3 , and in Figures 3 - 4 and 3 - 5 . T he operating requirements are
as fol l ows:
(1 ) Each cl ass of equipment is to be exposed to the temperature
conditions shown in T abl e 3 - 3 . T he ambient temperature within
the specified temperature ranges may remain constant for l ong
periods or may vary at a rate as high as 1 per second.
(2) Each cl ass of equipment must operate under the conditions
and within the ranges l isted in col umn I , I I , I I I and VI I of
T abl e 3 - 3 .
(3 ) T he equipment in a nonoperating condition must withstand l ong
periods of exposure to the temperature extremes and thermal
shock as l isted in T abl e 3 - 3 .
(4 ) Each cl ass of equipment must meet the al titude conditions
l isted in col umn VI I I of T abl e 3 - 3 , both for continuous
operation and exposure in a nonoperating condition. T he al ti-
tude may remain constant for l ong periods or vary at a rate as
high as 0 .5 in. of mercury per second.
(5 ) T he equipment is required to operate under the appl icabl e
temperature- al titude combinations shown in Figure 3 - 4 .
(6) T he equipment is required to withstand the effects of humidities
up to 1 0 0 percent, incl uding conditions wherein condensation
takes pl ace in and on the equipment. T he equipment shal l with-
stand the above conditions during operating and nonoperating
conditions.
(7 ) When normal l y mounted (with vibration isol ators in pl ace, if
any), the equipment shal l operate satisfactoril y when subjected
7 1
T abl e 3 - 3 ENVI RO NMENT A L CO NDI T I O NS
ro
Equipment O perating
Equipment
O perating and
Nonoperating Equipment Nonoperating
T emperature extremes for the chamber
(without external cool ing provisions)
Combined
T emperature
A l titude
T emperature
Shock A l titude
T emperature
Extremes
T emperature
Shock
Equipment
Cl ass
I
Continuous
I I
I ntermittent
I I I
Short- T ime I V V VI VI I VI I I I X X
Cl ass 1
Cl ass 1 A
Cl ass 2
Cl ass 3
Cl ass 4
- 5 4 C
to
+ 5 5 C
- 5 4 C
to
+ 5 5 oc
- 5 4 C
to
+ 7 1 C
- 5 4 C
to
+ 9 5 C
- 5 4 C
to
+ 1 25 oc
3 0 min
+ 7 1 oc
3 0 min
+ 7 1 oc
3 0 min
+ 9 5 oc
3 0 min
+ 1 25 oc
3 0 min
+ 1 5 0 C
1 0 min
+ 1 5 0 oc
1 0 min
+ 260 C
Curve
A
Curve
A
Curve
A
Curve
A
Curve
A
Curve
B
Curve
B
Curve
B
Curve
B
Curve
B
Curve
C
Curve
C
- 5 4 C
to
+ 7 1 oc
- 5 4 C
to
+ 7 1 oc
- 5 4 oc
to
+ 9 5 oc
- 5 4 C
to
+ 1 25 oc
- 5 4 C
to
+ 1 5 0 oc
Sea Level
to
5 0 , 0 0 0 ft
Sea Level
to
3 0 , 0 0 0 ft
Sea Level
to
7 0 , 0 0 0 ft
Sea Level
to
1 0 0 , 0 0 0 ft
Sea Level
to
1 0 0 , 0 0 0 ft
- 62 C
to
+ 8 5 oc
- 62 oc
to
+ 8 5 oc
- 62 C
to
+ 9 5 oc
- 62 C
to
+ 1 25 C
- 62 C
to
+ 1 5 0 C
- 62 C
to
+ 8 5 oc
- 62 C
to
+ 8 5 C
- 62 C
to
+ 9 5 oc
- 62 C
to
+ 1 25 oc
- 62 C
to
+ 1 5 0 C
h, Kft h, Kft
-50 0 100 200 T,C
Fig. (A) Class I Equipment
100
90
80
70
/VAV
60
50
40
30
\Â
20
10
/AsJ A li i i i
0
-50 0 100 200
T,C
Fig.(B) Class 2 Equipment
h, Kft h, Kft
100
90
80
70
60
5 0
40
30
20
I 0
0
//\\\

\ Â
Jr /
B
-
ii IV i i
-50 0 100 200
Fig.(C) Class 3 Equipment
Vc -50 0 100 200 T,C
Fig.(D) Class 4 Equipment
Note: Refer To Table 3-3 For Use Of A,B,C
Fig. 3-4 TEMPERATURE ALTITUDE PROFILES FOR AVIONIC EQUIPMENT
73
.30
.10 -
.05
036
A
0)
-c
o
c
c
.01
<D
-o
3
*-
"5.
E
<
0)
A
3
O
.001
.0001
1 1 1 1 l ll| l illllll| 1 1 r~r
- Ace eleration Levels G(Peak)
-

Curve TU OH
1
V.42c\ 2G
\ Y Curve I, El, 12
\ \ / ,Curveiai2
-
' \ V
Curvel \ \
\\
l0G
Curve IK ^\ V
-
Curve II A \ \
-
-
Curve I
\5G\ \
Equipment Designed For \ \ \
Operation In Aircraft \ \ \
-

Curve H Equipment Designed For V \
Operation On Isolators With \ \
Isolators Removed. \ \
V^
- Curve HI Equipment Designed For \
Dperation In Helicopters. \
\-
-
Curve 12
i i i
Equipment Designed For Operation In \
Both Aircraft And Helicopters
1 1 III 1 1 1 1 (1 III 1 1 L_l_
a>
3
Q.
E
<
JO
3
O
Q
.30
.10 =-
.05
.036
.01
.001 =r
.0001 -
5 10 100
Frequency In Cycles Per Second
500
.00001 -
1 1 1 1 1 1 I1| 1 1 1 T T IITj - Tr 1 1 I mi F
Acceleration Levels G (Peak)
-
Curve niA 332A

v \
V42G\,2G CurveIA,HIA a I2A -
Y \ y Curve IA a UTA -
CurvelA \\
- \\ IOG -
z-
Curve IHA "\\
-
m
-
- -
- -
-
Curve HA ' y. \\ JQ
-
B- \ \V
2 G
Curve IA Equipment Designed \x\\
-=
For Operation In \ \\ -
Aircraft \ \\
_ Curve HA Equipment Designed For \ \\ _
Operation On Isolators \ \\
With Isolators Removed. \ \\...
- Curve mA Equipment Designed For \ \\
~
Operation In Helicopters. \ \\ -
. Curve 32: A Equipment Designed For \ > L _
Operation In Both Aircraft \
And Helicopters. \
i i i i mil i i i i i ml i i i i i ml
SLZ
10 100 1000
Frequency In Cycles Per Second
Fig 3-5 VIBRATION REQUIREMENTS FOR AVIONIC EQUIPMENT
to vibration within the frequency range and ampl itude as
shown on Figure 3 - 5 and specified in the detail equipment
specification.
(8 ) Equipment normal l y mounted on isol ators must operate satis-
factoril y with isol ators removed when subjected to vibration
within the frequency range and ampl itude as shown on curve I I
or I I A of Figure 3 - 5 .
(9 ) Consol e control s l ocated in the cockpit area shal l conform
to curve I or I A , except that the ampl itude shal l not exceed
5 g.
(1 0 ) Equipment (with vibration isol ators in pl ace, if any) shoul d
not suffer damage or subsequentl y fail to provide the performance
specified in the detail equipment specification when subjected
to 1 8 impact shocks of 1 5 g, consisting of three shocks in
opposite directions al ong each of three mutual l y perpendicul ar
axes, each shock impul se having a time duration of 1 1 + 1 mil l i-
seconds. T he maximum " g" shal l occur at approximatel y 5k mil l i-
seconds.
(1 1 ) With excursion stops or bumpers in pl ace and with maximum rated
l oad appl ied in a normal manner, the mounting base, individual
isol ators, or other attaching devices must be capabl e of with-
standing at l east 1 2 impact shocks of 3 0 g, consisting of two
shocks in opposite directions al ong each of three mutual l y
perpendicul ar axes. Each shock impul se shal l have a time dura-
tion of 1 1 + 1 mil l iseconds. T he " g
n
val ue is to be within
+ 1 0 percent. Maximum " g" val ue shal l occur at approximatel y
bh mil l iseconds. Bending and distortion are permitted; however,
there shal l be no fail ure to the attaching joints and the
equipment of dummy l oad shal l remain in pl ace.
(1 2) T he equipment shal l withstand, in both an operating and non-
operating condition, exposure to sand and dust particl es as
encountered in operational areas of the worl d.
7 5
(1 3 ) T he equipment must withstand, in both an operating and non-
operating condition, exposure to fungus growth as encountered
in tropical cl imates. O veral l spraying of the equipment must
not be necessary to meet this requirement.
(1 4 ) T he equipment must withstand, in both an operating and non-
operating condition, exposure to sal t- sea atmosphere.
(1 5 ) T he equipment must not cause ignition of an ambient- expl osive-
gaseous mixture with air when operating in such an atmosphere.
T his, in brief, is a representative overview of the avionics environment,
and the severe operational conditions under which airborne el ectronic
equipment must perform rel iabl y and consistentl y over its operational
l ife.
3 .3 Equipment Rel iabil ity State- of- the- A rt
Figure 3 - 6 is abstracted from the famil iar chart of MI L- ST D- 7 5 6.
T he graphical portrayal of the rel iabil ity situation around 1 9 65 gives
the MT BF of a number of different anal og type avionic equipments. T he
MT BF data was obtained from operator and pil ot observations.
I t is interesting to make a comparison of the then prevail ing vacuum
tube technol ogy operational in the earl y 1 9 60 's, rel ative to the pre-
dominantl y sol id state technol ogy avail abl e today. T he comparison indi-
cates that, in the area of l ow to medium power signal l evel appl ication,
the 1 9 7 5 technol ogy has undergone approximatel y an order of magnitude
improvement in inherent rel iabil ity.
A bol d extrapol ation based on this situation thus suggests that the
equipment rel iabil ity curve for 1 9 7 5 be shifted up by one order of magni-
tude as shown in Figure 3 - 6.
A s rough reference points to describe functional compl exity, the
fol l owing series active el ement counts woul d be representative of avionic
equipments at opposite ends of this spectrum:
7 6
Functional Complexity (Series Active Elements)
Note: An Active Element Is Defined As A Device Which Controls Or Converts
Energy. A Typical Example Would Be A Transistor And Associated Circuitry.
Fig. 3-6 AVIONICS EQUIPMENT RELIABILITY (ANALOG)
77
Functional Predicted
Compl exity MT BF
(Series A ctive) (Hrs)
El ements
Mul timode Radar 20 0 1 60
VHF T rans/Rcvr 3 0 20 0 0
T hese two points are pl otted on the equipment rel iabil ity trendl ine for
1 9 7 5 .
3 .4 Summary and Concl usion: 1 9 7 5 A vionics T rends
T he dial ogue of this section has been conducted within the context
of trends. A n attempt to predict the exact makeup of future generation
avionics suites has been avoided. T he justification for this position
is cl ear if one considers that the designers of the 1 9 5 0 's coul d not
have visual ized many of the avionic devel opments that evol ved in the
1 9 60 's, for exampl e, the Wil d Weasel el ectronic warfare system, or the
l aser seeker trackers and smart bombs which began appearing at the end
of that decade. What has been highl ighted here, then, are trends- - trends
which are exampl ified by the current avionics on the F- 1 5 , F- 1 6, B- l ,
et al _ . T he immediate overview and its near- term projection is approxi-
matel y as shown in T abl e 3 - 1 .
T echnol ogy today has evol ved al ong the l ine from vacuum tube to
transistor, and from discrete to integrated circuitry. Ramifications of
this evol ution are most evident in the digital area which has seen the
rapid devel opment and widespread use of ful l size integrated circuit
digital computers and microprocessors. From the point of view of avionics,
these devices appear to have arrived in time to handl e the resul tant com-
pl exity caused by the drive for ever increasing avionic systems perform-
ance. I t is a major fact, that has been witnessed by avionics system
evol ution over the past two decades, that the ever- increasing drive for
performance has negativel y impacted on the issues of compl exity, rel i-
abil ity and cost. T he tradeoff between the first two factors is indi-
cated in Figure 3 - 6. More wil l be said about the l ast factor bel ow.
T he fol l owing paragraphs comment first on the abil ity of digital computers
and microprocessors to handl e the resul tant compl exity. T he next two
paragraphs then deal with the abil ity of the new integrated- circuit
technol ogy to address the issues of rel iabil ity and cost.
7 8
Rel ative to the issue of compl exity, the question that is being
raised today is whether new aircraft integrated avionics systems shoul d
use a central ized mul tiprocessor to perform al l or most of the individ-
ual subsystem computer functions, or whether there shoul d be distributed
computation facil ities with a central executive computer to direct the
operations. A point that may decide this issue, and one that is becoming
increasingl y more important today, is the probl em of computer software.
I deal l y, avionics mission software shoul d be easy to structure and docu-
ment, inexpensive to modify and independent of the specific computer or
sensor hardware being used. I n this regard, system devel opment trends
coul d be adversel y affected if avionics software proves to be cost-
prohibitive and unmanageabl e.
Rel ative to the issue of rel iabil ity and cost, a question that is
currentl y under review is whether future avionics equipment shoul d be
constructed from a famil y of standard el ectronic modul es (SEM). Potential
benefits of adopting standard modul es are indicated by the Navy experi-
ence with the standard hardware program (SHP).
I n this program, standard modul es today appear to be showing fail ure
rates of onl y 0 .1 to 0 .0 1 per mil l ion operating hours, and 8 0 % of the
present catal og of standard modul es sel l for under $ 60 . However, there
are al so other points to consider here. O ne of the more basic ones has
to do with the increased weight/vol ume penal ty that modul arization wil l
impose (which may thus pl ace a l imit on performance growth) and bears on
the question of whether the el ectronics technol ogy has reached a suffi-
cient l evel of maturity to be ready for standardization (digital type
functions). I t is easy to recal l that in the earl y 1 9 5 0 's the sub-
miniature vacuum tube was the smal l est active- el ement el ectronic device.
Soon thereafter, the transistor began making its appearance in mil itary
el ectronics, and by the l ate 1 9 5 0 's, a micromodul e program woul d have
been based on transistor technol ogy. Subsequentl y, in the earl y 1 9 60 's,
a transistor micromodul e program woul d in turn have been made obsol ete
by the emerging microcircuit devel opment. A decade since then has seen
a 1 0 0 :1 increase in the number of active el ements that can be fabricated
on a singl e semiconductor chip. I t is not cl ear whether this trend is to
continue into the next decade.
7 9
I n the final anal ysis, however, the overriding factor may turn out
to be what is increasingl y becoming recognized as a way of l ife. I t is
that the driving force today can no l onger be determined sol el y by the
need for increased performance. Rather, it is becoming more responsive
to the economic pressure to reduce acquisition and l ife- cycl e costs. I n
this regard, it might be possibl e to greatl y improve rel iabil ity and
control and reduce costs by going to a standard modul e phil osophy. I t
might work as fol l ows. T he widespread use and avail abil ity of SEM's
woul d tend to resul t in l ow modul e costs. Widespread avail abil ity of
SEM's woul d, in turn, tend to reduce the time required to design and buil d
prototypes of new avionics systems and speed the transition into produc-
tion. A vail abil ity of l ow cost SEM's in the fiel d might then make it
economical l y sensibl e to discard rather than to faul t isol ate and repair.
I n turn, a discard- on- fail ure maintenance concept woul d tend to reduce
the training and skil l l evel s required for maintenance. I t woul d al so
ease the perennial l ogistics probl em of obtaining repl acements for devices
no l onger being manufactured. T he SEM's in use woul d be functional l y
equival ent even though they might represent different generations of
technol ogy.
T his then seems to be a fair representation of some of the major
issues and circumstances that surround the state of avionics today.
REFERENCES
1 . Kil patrick, P.S., Mitchel l , P.D., Scal es, E.A ., " A ircraft A vionics
T rade- off Study, " Vol . I I , Final Report, A D 9 1 5 8 8 1 L, September 1 9 7 3 .
2. Mil l er, B., " A WG- 9 Provides Mul ti- T arget Capabil ity, " A viation Week
and Space T echnol ogy, March 1 2, 1 9 7 3 .
3 . Ul samer, E., " How Computers Wil l Fl y T omorrow's A irpl anes, " A ir Force
Magazine, Jul y 1 9 7 2.
4 . Kl ass, P.J., " USA F Weighing Standardized Modul es, " A viation Week and
Space T echnol ogy, September 1 6, 1 9 7 4 .
5 . Kl ass, P.J., " Standard Modul e Rol e Studies to Begin, " A viation Week
and Space T echnol ogy, September 23 , 1 9 7 4 .
8 0
Section 4
RELI A BI LI T Y DESI GN DA T A
4 .1 Design to Maximize I nherent Rel iabil ity
4 .2 Design to Minimize Rel iabil ity Degradation
During Production and Use
4 .3 Design to Cost
SECT I O N 4
RELI A BI LI T Y DESI GN DA T A
During a period of high cost and rapid infl ation, the key to an
effective mil itary system is the achievement of a bal ance between per-
formance, rel iabil ity and other system factors at a minimum cost. T he
key to achieving this bal ance hinges on the real ization that total cost
of ownership is driven by system attributes apart from strict performance
requirements. Rel iabil ity is one such attribute. Poor rel iabil ity (and
the factors which cause it) resul t in high fiel d- support cost and,
consequentl y, high cost of ownership. T he interrel ationship among the
system parameters which give rise to design bal ance are depicted in
Figure 4 - 1 . T he figure shows that the various parameters for performance,
R, M, and cost are tradeoff variabl es to arrive at " design to" target
goal s which represent a bal anced design.
INPUTS
Design Requirements
Size
Weight
-Power Consumption
Performance
Reliability Factor
Derating
Redundancy
Part Selection
Environmental
Protection
Cost Factors
Part (Material Cost)
Labor Rates
Overhead
Other Factors
Maintainability
Scheduling
Design Balancin
Activities
9
"Design To"
For Targets
R,M,C And
Performance
[ t
Values Of
R,M,C And
Performance
From Design
\ }
Management
Tracking,
Trade-Offs
8t Target
Adjustment
Fig. 4-1 DESIGN BALANCING ACTIVITIES
83
T his section of the handbook emphasizes the " design to" phil osophy
in terms of specific rel iabil ity and cost guidel ines which can be appl ied
during design. I ncl uded are three major subsections:
(1 ) " Design to" Maximum I nherent Rel iabil ity, paragraph 4 .1 .
(2) " Design to" Minimize Rel iabil ity Degradation During
Production and Use, paragraph 4 .2
(3 ) " Design to" Cost, paragraph 4 .3 .
8 4
Section 4 .1
DESI GN T O MA XI MI ZE I NHERENT RELI A BI LI T Y
4 .1 .1 Part Sel ection and Control
4 .1 .1 .1 Part Control
4 .1 .1 .2 Part Sel ection Guidel ines
4 .1 .1 .3 Part Screening
4 .1 .2 Derating
4 .1 .2.1 T emperature- Stress Factors
4 .1 .2.2 Specific Derating Guidel ines
4 .1 .3 Environmental Resistance
4 .1 .3 .1 Environmental Factors
4 .1 .3 .2 Environmental Resistance Provisions
4 .1 .3 .3 General Packaging Considerations
4 .1 .4 Redundancy
4 .1 .4 .1 General Concepts
4 .1 .4 .2 Redundancy T echniques
4 .1 .4 .3 Design Exampl es
4 .1 .5 Design Simpl ification and A nal ysis
4 .1 .5 .1 Design Simpl ification
4 .1 .5 .2 Degradation A nal ysis
4 .1 .5 .3 O verstress and T ransient A nal ysis
4 .1 Design to Maximize I nherent Rel iabil ity
4 .1 .1 Part Sel ection and Control
A diversified compl ement of el ectronic parts is avail abl e to struc-
ture modern mil itary el ectronic systems. T hese parts constitute the
buil ding bl ocks from which systems are fashioned and, as such, greatl y
impact hardware rel iabil ity. Since the rel iabil ity of the end item is
dependent upon these buil ding bl ocks, the importance of sel ecting and
appl ying the most effective parts cannot be overemphasized.
T he task of sel ecting, specifying, assuring proper design appl ica-
tion and, in general , control l ing parts used in compl ex el ectronic
systems is a major engineering task. Part sel ection and control is a
mul tidiscipl inary undertaking invol ving the best efforts of component
engineers, fail ure anal ysts and rel iabil ity engineers as wel l as design
engineers. Numerous control s, guidel ines and requirements must be for-
mul ated, reviewed and impl emented during the devel opment effort. T abl e
4 - 1 presents a simpl ified l ist of the ground rul es and activities needed
to assure that this task is adequatel y considered. T he subsections which
fol l ow provide detail ed information, data and specific guidel ines for the
general ground rul es l isted in T abl e 4 - 1 . Subsection 4 .1 .1 .1 covers part
control ; subsection 4 .1 .1 .2 provides specific part sel ection data and
guidel ines as they appl y to each generic part cl assification and sub-
section 4 .1 .1 .3 covers part screening.
4 .1 .1 .1 Part Control
Part control activities comprise a l arge segment of the total effort
for part sel ection, appl ication and procurement. T he effort encompasses
tasks for standardization, approval , qual ification and specification of
parts which meet performance, rel iabil ity and other requirements of the
evol ving design. T his subsection of the handbook provides further
detail s with regard to these control tasks, indicates their importance
within the part sel ection process and provides appropriate design guid-
ance. El ectronic parts that comprise any el ectronic equipment constructed
for mil itary purposes are under the cognizance of the Mil itary Parts
Control A dvisory Group, l ocated in the Directorate of Engineering Stand-
ardization at the Defense El ectronics Suppl y Center (DESC). T his group
8 7
T abl e 4 - 1 GRO UND RULES FO R PA RT SELECT I O N A ND CO NT RO L
a) Determine part type needed to perform the required
function and the environment in which it is expected
to operate.
b) Determine part critical ity.
Does part perform critical functions (i.e., safety or
mission critical )?
t Does part have l imited l ife?
Does part have l ong procurement l ead time?
t I s the part rel iabil ity sensitive?
I s the part a high cost item or does it require
formal Qual ification testing?
c) Determine part avail abil ity.
t I s part on a Preferred Part List?
t I s part a Standard MI L item avail abl e from a
qual ified vendor?
What is normal del ivery cycl e?
t Wil l part continue to be avail abl e throughout the
l ife of the equipment?
I s there an acceptabl e in- house procurement document
on the part?
A re there mul tipl e sources avail abl e?
d) Estimate expected part stress in its circuit appl ication.
e) Determine rel iabil ity l evel required for the part, in its
appl ication.
f) Determine the efficiency of burn- in or other screening
methods in improving the part's fail ure rate (as required).
g) Prepare an accurate and expl icit part procurement
specification, where necessary. Specifications shoul d
incl ude specific screening provisions, as necessary to
assure adequate rel iabil ity.
h) Determine actual stress l evel of the part in its intended
circuit appl ication. I ncl ude fail ure rate cal cul ations per
MI L- HDBK- 21 7 B.
i) Empl oy appropriate derating factors consistent with
rel iabil ity prediction studies.
j) Determine need for nonstandard part and prepare a request
for approval as outl ined in MI L- ST D- 7 4 9 or MI L- ST D- 8 9 1 .
8 8
promotes standardization in part sel ection and appl ication. By using
standard parts in new equipment design and devel opment programs, much
time and effort can be saved whil e obtaining better equipment performance
in addition to simpl er and better l ogistics support.
DESC promotes usage of standard parts and manages standardization
probl ems for parts which are initial l y characterized as nonstandard but
whose repetitive usage makes their standardization necessary.
DESC, as DoD's standardization manager, works cl osel y with the
mil itary services and industry in devel oping an effective standardiza-
tion program for new systems.
T herefore, the general rul e for part sel ection is that wherever
possibl e, standard devices shoul d be used. Standard devices may be
defined as those which by virtue of systematic testing programs and a
history of successful use in equipment have demonstrated their abil ity
to consistentl y function within certain specific el ectrical , mechanical
and environmental l imits and, as a resul t, have become the subject of
mil itary (MI L) specifications. MI L specifications which thoroughl y
del ineate a part's substance, form and operating characteristics exist,
or are in preparation, for practical l y eyery known type of el ectronic
component. Mil itary Standards exist which cover the subject of testing
methods appl icabl e to MI L- specified components. For exampl e:
MI L- ST D- 20 2, T est Methods for El ectronic Parts
MI L- ST D- 7 5 0 , T est Methods for Semiconductor Devices
MI L- ST D- 8 8 3 , T est Methods for Microel ectronic Devices.
I n addition, Mil itary Standards exist which l ist by MI L designation those
parts or devices which are preferred for use in mil itary equipment. For
exampl e:
MI L- ST D- 1 5 62, List of Standard Microcircuits
MI L- ST D- 7 0 1 , List of Standard Semiconductors
MI L- ST D- 1 9 9 , Sel ection and Use of Resistors
MI L- ST D- 1 9 8 , Sel ection and Use of Capacitors.
Brief descriptions of these standards are given in the bibl iography
section of this handbook (A ppendix B).
8 9
I n conjunction with part standardization, nonstandard part approval
must be considered. Nonstandard part approval is comprised of activities
to document and secure authorization to use the part in the system.
Mil itary- ST D- 8 9 1 outl ines the functions of a Part A dvisory Group or a
Part Control Board operating under both government and contractor cogniz-
ance and which provides the necessary mechanism for securing approval of
nonstandard parts.
T he qual ification of nonstandard parts shoul d incl ude detail ed and
formal submittal of data to support approval request. T his data must be:
(1 ) statistical test data, (2) anal ytical data for components that are
simil ar to a standard part, or (3 ) a combination of statistical and
anal ytical data. (Note: T hose components that require formal statistical
test data for qual ification shoul d be identified as critical items.)
T he sel ection process shoul d incl ude design eval uation, rel iabil ity
history review, construction anal ysis, fail ure mode and effects anal ysis
and cost effectiveness studies as necessary. T he control effort shoul d
incl ude the devel opment of meaningful procurement specifications which,
when compl eted, refl ect a bal ance between design requirements, QA and
rel iabil ity needs consistent with apportionment studies and vendor capab-
il ities, and which cover:
l ot acceptance testing,
QA provisions (incl uding incoming inspection),
qual ification testing, if required.
A wel l control l ed part program invol ves establ ishing a vendor con-
trol program, audits of vendor processes, the establ ishment of source
inspection, where appl icabl e, and the preparation of associated documenta-
tion. T he part control effort incl udes identifying al l critical parts,
equipment/components, and other items considered critical from any of
the fol l owing standpoints:
mission and safety sensitive (fail ure impacts mission success
and fl ight safety, i.e., fl ight safety critical ),
rel iabil ity sensitive (from earl y R studies, apportionments, etc.),
have l imited l ife,
t are high cost items,
9 0
have l ong procurement l ead times,
t require formal statistical qual ification testing.
Pl anning for critical item control must incl ude control s for special
handl ing, the identification of critical item characteristics to be
inspected or measured during incoming inspection, material review proce-
dures, traceabil ity criteria and periodic audits. A l l items considered
fl ight safety critical must be coded. Detail ed documentation must be
prepared that describes procedures, tests, test resul ts, and efforts to
reduce the degree of critical ity of each item.
4 .1 .1 .2 Part Sel ection Guidel ines
T his subsection presents rel iabil ity information to aid in the
sel ection of el ectronic parts for a specific design appl ication. I n-
cl uded are guidel ines for:
(a) Microcircuits (paragraph 4 .1 .1 .2.1 )
(b) Semiconductors (paragraph 4 .1 .1 .2.2)
(c) Resistors (paragraph 4 .1 .1 .2.3 )
(d) Capacitors (paragraph 4 .1 .1 .2.4 )
(e) O ther Parts (paragraph 4 .1 .1 .2.5 )
4 .1 .1 .2.1 Microcircuits
I n general , there are two major cl asses of microcircuits:
Monol ithic
Hybrid.
A monol ithic microcircuit is characterized by a singl e sil icon chip,
suitabl y packaged and performing wel l - defined functions. T his character-
ization encompasses varying degrees of compl exity up to and incl uding
LSI and may incl ude purel y digital functions or l inear appl ications.
Monol ithic microcircuits cover most forms of current technol ogy, e.g.,
T T L, MO S, CMO S, etc.
I n contrast, hybrid microcircuits resul t from combining various
el ectronic, component, material and manufacturing technol ogies into
miniature el ectronic interconnections and packaging. Normal l y, fil m
circuits are combined with chip and discrete components on a substrate.
9 1
I ntegrated and compl ex monol ithic circuits can be incl uded within a
hybrid.
Before deciding which cl ass of microcircuit best meets the needs of
a particul ar appl ication, careful consideration shoul d be given to con-
struction, parameters, size, cost and rel iabil ity constraints as they
rel ate to the specific design. T rade- off studies shoul d be performed
covering such factors as:
t Comparison of total costs. T his incl udes devel opment costs for
each type pl us cost of fabrication and testing.
Comparison of circuit parameter requirements such as resistance
tol erances, tracking, temperature coefficient, speed, vol tage
l evel s, and el ectrical isol ation with the parameter l imitations
of monol ithic and hybrid circuits.
Comparison of package size requirements to the space avail abl e.
Eval uation of circuit power dissipation and the thermal resist-
ances of the packaged circuit to insure acceptabl e temperatures
on the substrate.
For monol ithic I C's, numerous standard devices (l isted in MI L- ST D-
1 5 62) are avail abl e from which sel ections can be made (see A ppendix C).
Because hybrids are essential l y custom- made devices, a simil ar standard-
izing document does not currentl y exist. I n recognition of the increas-
ing usage of hybrid devices, the approach to rel iabl e hybrids has been
via test and inspection techniques. Mil itary ST D- 8 8 3 A (T est Methods for
Microel ectronic Devices) incl udes a section for internal visual inspec-
tion of hybrid devices (Method 20 1 7 of MI L- ST D- 8 8 3 A ). Revisions to this
standard which woul d establ ish additional test methods for hybrids are
contempl ated.
T he sel ection of a specific microcircuit type is governed by the
guidel ines depicted in T abl e 4 - 2. A s previousl y indicated, the expected
rel iabil ity l evel of parts and of microcircuits in particul ar must be
incorporated into the sel ection process. A ppendix C contains a l isting
of integrated circuits taken from MI L- ST D- 1 5 62 and represents devices
which are considered to be standard and acceptabl e for use in mil itary
equipment.
9 2
T abl e 4 - 2 MI CRO CI RCUI T SELECT I O N GUI DELI NES
1 . MI L- ST D- 1 5 62, List of Standard Microcircuits.
2. MI L- M- 3 8 5 1 0 , Microcircuits, General Specifications For.
T his document defines screening per MI L- ST D- 8 8 3 , " T est
Methods and Procedures for Microel ectronics" .
3 . Historical test data (simil ar appl ication) or other
engineering information and/or data that provides
assurance that the device is sufficientl y rugged and
rel iabl e for the appl ication (e.g., previous use in
A ir Force equipment, comparabl e appl ication, or GFE).
4 . MI L- HDBK- 1 7 5 , " Microel ectronic Device Data Handbook"
(A ppl ication data).
NO T E: When a desired device is not covered by MI L- M- 3 8 5 1 0 ,
a new specification or drawing shoul d be prepared and
coordinated with potential manufacturers of the device.
T o assist the contractor in these actions, the Depart-
ment of Defense Rel iabil ity A nal ysis Center l ocated at
RA DC, Griffiss A FB, Rome, New York, maintains a com-
prehensive up- to- date data base on environmental
operating capabil ities fail ure rates, fail ure modes and
mechanisms, and fabrication techniques covering hybrid
and monol ithic microcircuits.
T he fail ure rates incl uded in A ppendix C are onl y intended to be
used as comparative guides to designers in the sel ection and appl ica-
tion of microcircuits. T hese fail ure rates were cal cul ated according
to MI L- HDBK- 21 7 B prediction methods using general ized design and
appl ication assumptions.
I n addition, T abl e 4 - 3 provides fail ure mode and rate information
for digital and l inear microcircuits. T he information incl uded in this
tabl e is intended to be used for comparing the rel iabil ity aspects of
microcircuits and to aid in sel ecting the optimum device for a given
9 3
T abl e 4 - 3 A PPLI CA T I O N NO T ES FO R I C'S
Microcircuit
T ype
A ppl ication Notes
Fail ure
information* ^
Fail ure rate
Range
(F/1 0 * - " hrs)
DI GI T A L
Fail ure indicators:
mechanical anomal y
(VI S) - 1 %
O pens (pin to pin) - 20 %
Shorts (pin to pin) - 22%
O peration degradation - 5 7 %
0 .0 3 2- 0 .3 4 4
T T L Standard: I ntended for use in impl ementing
l ogic functions where speed and power require-
ments are not critical . T his famil y offers a
ful l spectrum of l ogic functions in various
packages. T ypical gate power dissipation is
1 0 mW with a typical propagation del ay time of
1 0 ns. T hese devices exhibit a fanout of 1 0
when driving other standard T T L devices usual l y
used to perform general purpose switching and
l ogic functions.
Low Power: Empl oyed in l ogic design where l ow
power dissipation is the primary concern.
T hese devices have a typical gate power dissi-
pation of 1 mW with a typical propagation del ay
time of 3 0 ns. T ypical l y, these devices wil l
drive onl y one standard T T L device but exhibit
a fanout of 1 0 when l oaded by other l ow power-
devices. Low power generates l ess heat and
therefore al l ows for greater board densities.
Lower current l evel s al so introduce l ess noise
and reduce constraints on power suppl ies.
High Speed: Used to impl ement high speed l ogic
functions in digital systems. T hese devices
empl oy a Darl ington output configuration to
achieve a typical propagation del ay time of
6 ns. T he typical gate power dissipation is
23 mW. T hese devices can drive up to 1 2
standard T T L devices and exhibit a fanout of 1 0
when driving other high speed devices. Com-
monl y used in high speed memories and central
processor units.
Schottky: Used when ul tra- high speeds are de-
sired. T hese devices empl oy shal l ow diffusions
and smal l er geometries which l ower internal
capacitance to reduce del ay time and sensitiv-
ity to temperature variation. T ypical del ay
time is 3 ns and power dissipation is 1 9 mW.
However, this power dissipation increases with
frequency. T hese devices can drive 1 2 standard
T T L devices and up to 1 0 Schottky devices.
Noise immunity is reduced due to the nonsatur-
ated switching operation. A ground pl ane is
recommended for interconnections over 6 in.
l ong and twisted- pair l ines for distances over
1 0 in.
Constituent fail ure modes:
Surface defects - 6%
O xide defects - 4 %
Diffusion defects - 2*
Metal l ization defects - 5 0 %
Bond/wire defects - 1 3 %
Die attach bond - 1 1 %
Cracked die - 1 %
Package - 1 3 %
0 .0 3 2- 0 .1 8 0
CMO S Used where l ow power is extremel y desirabl e and
high speeds are not essential . T he typical
power dissipation is 1 0 mW (at 1 0 kHz) and in-
creases with frequency. T ypical del ay time is
5 0 ns. A typical fanout for CMO S l oads is 5 0 ,
whil e onl y 1 for standard T T L l oads. Noise
immunity is typical l y 1 .5 V for CMO S compared
to 0 .4 V for standard T T L devices. T his makes
these devices useful in high noise environ-
ments. Handl ing precautions shoul d be given
consideration due to susceptibil ity to over-
stress from el ectrostatic discharge. Most
commonl y empl oyed in medical el ectronics, cal -
cul ators, watches, cl ocks and automotive sys-
tems. T hese devices are highl y tol erant of
power suppl y vol tage variation and wil l operate
anywhere in the range of 3 to 1 5 vol ts.
Constituent fail ure modes:
Surface defects - 27 %
O xide defects - 1 6%
Diffusion defects - 9 %
Metal l ization defects - 25 %
Bond/wire defects - 1 5 %
Package - 8 %
0 .0 4 4 - 0 .3 4 4
9 4
T able 4-3 APPLICAT ION N OT ES F OR IC' S (Conti nued)
Mi croci rcult
type
Appli cati on notes
F ai lure ^ i S* *
i nf ormati on*
{F
/?S? h rs)
ECL Intended f or use i n di gi tal systems requi ri ng
h i gh swi tch i ng speeds and moderate power di s-
si pati on. T ypi cal propagati on delay ti me i s
2 ns and typi cal power di ssi pati on i s 25 mW.
Operati on requi res a -5 . 2 V supply and properly
termi nated li nes or control i mpedance ci rcui t
boards. T h e logi c levels (-0. 9 V and -1. 7 V )
are not as easi ly detected as th ose of T T L
devi ces. Intended f or use In h i gh speed sys-
tems such as central processors, memory con-
trollers, peri ph eral equi pment, Instrumentati on
and di gi tal communi cati ons. A typi cal f anout
1s 15 wh en dri vi ng ECL devi ces.
Prevalent f ai lure modes: 0. 05 6 -0. 08 8
Bond di e attach
Metalli zati on def ect
Bond/wi re def ects
(F ai lure percentages not
avai lable)
Programmable
ROM
Used i n systems h avi ng nonvolati le memory re-
qui rements. N i ch rome f usi ble li nks allow f or
custom f i eld programmi ng to ai d system proto-
typi ng. Programmi ng procedures must be
closely regulated to prevent f use " Grow-Back" .
Usef ul i n i mplementi ng h ardware algori th ms
and mi croprogrammi ng.
Learni ng f actor (" L) i s 0. 28 0
especi ally appli cable due to
addi ti onal step requi red f or
programmi ng.
Prevalent f ai lure modes:
Metalli zati on def ect
Surf ace/ox i de def ect
Package def ects
(F ai lure percentages not
avai lable)
LIN EAR Intended f or use 1n si gnal ampli f i cati on
detecti on and transmi ssi on, and voltage regu-
lati on. Large power di ssi pati on li mi ts pack-
agi ng densi ty and requi res consi derati on of
th ermal desi gn parameters. Ex tensi vely used In
communi cati ons, controls, i nstrumentati on and
Inf ormati on systems.
F ai lure i ndi cators: 0. 096 -0. 208
mech ani cal anomaly
(V IS) - IX
Opens (pi n to pi n) - 9%
Sh orts (pi n to pi n) - 7t
Operati onal degradati on - 8 3*
Consti tuent f ai lure modes:
Surf ace def ects - 5 4
Ox i de def ects - 2 %
Di f f usi on def ects - 2 %
Metalli zati on def ects - 18 *
Bond/wi re def ects - 8 X
Di e attach bond - 9%
Cracked di e - IX
Package - 6 X
F ai lure i ndi cators are devi ce f ai lure modes wh i ch i denti f y th e f ai lure condi ti on by vi sual, elec-
tri cal or mech ani cal measurements wi th out perf ormi ng any destructi ve analyses. F or th e purpose of accumu-
lati ng stati sti cs, pi n-to-pi n testi ng sh ould be perf ormed on f ai lures f i rst, to establi sh an open or sh ort
and veri f y th e f ai lure, wh i ch th en i s classi f i ed as an operati onal degradati on. Mech ani cal anomaly occurs
wh en a vi sual or mech ani cal def ect ex i sts and electri cal perf ormance i s sti ll wi th i n speci f i cati ons.
T h e operati onal degradati on f ai lure Indi cator subclassi f Rati ons are as f ollows:
Di gi tal:
Stuck H i gh
Stuck Low
Output Unstable/Errati c
N o Output Si gnal (only ref ers to cases wh ere th e f ai lure cannot be classi f i ed as stuck h i gh or
l ow and th ere i s no output response to an Input si gnal)
Parameter out of tolerance
Li near:
H ardover Posi ti ve Match ed/saturated)
H ardover N egati ve (latch ed/saturated)
Output Unstable/F luctuates/Errati c
Output Cli pped
Latch ed/Saturated (oth er th an at ex tremes)
N o Output Si gnal (ref ers only to cases wh ere th e f ai lure cannot be classi f i ed 1n any of th e
above categori es and th ere i s no output response to an i nput si gnal)
Parameter out of tolerance
Consti tuent f ai lure modes i denti f y th e consti tuent of th e mi croci rcult and Its def ecti ve condi ti on
wh i ch resulted i n th e f ai lure i ndi cator.
T h e rel ative occurrence data presented was deri ved f rom malf uncti on reports collected i ndustry-wi de
by th e Reli abi li ty Analysi s Center. T h e quali f i cati on and screeni ng tests of MIL-M-38 5 10 f or JAN parts
may sh i f t th ese di stri buti ons to th ose modes not easi ly detected. F or ex ample, th e h i gh i nci dence of
metalli zati on def ects i n T T L may be reduced by appropri ate emph asi s on pre-cap vi sual i nspecti on and
metalli zati on process control.
95
design appl ication. T he tabl e l ists the device cl ass and type, appl ica-
tion notes, fail ure information and fail ure rate range. T he information
presented in T abl e 4 - 3 , when modified to el iminate the effects of pack-
aging, is appl icabl e to I C chips used within hybrid microcircuits. T he
range of fail ure rates l isted for each type was computed from MI L- HDBK-
21 7 B using val ues for adjustment factors ranging from worst case to
optimum appl ication conditions.
4 .1 .1 .2.2 Semiconductor Devices
Expanding technol ogy, widespread use and the economics of l arge
vol ume production have resul ted in a prol iferation of discrete semi-
conductor devices. T here exists a wide variety of functional cl assifica-
tions based upon el ectrical characteristics, such as l ow or high power,
switching time, internal capacitance, and forward current, avail abl e to
the designer. I n addition, there are several categories rel ating to
semiconductor device material and its physical configuration. I n total ,
there are thirty- five official l y recognized functional and constructional
cl assifications of semiconductor device types. T hese types can be found
in MI L- ST D- 7 0 1 .
T he sel ection of a specific semiconductor device is governed by the
guidel ines depicted in T abl e 4 - 4 . A s shown in this tabl e, the governing
specification for discrete semiconductor devices is MI L- S- 1 9 5 0 0 . T his
basic'document and its appended detail ed specification sheets establ ish
the general and specific requirements incl uding definitions, abbrevia-
tions and symbol s, el ectrical characteristics, el ectrical , mechanical
and environmental requirements, styl es, test methods, qual ity assurance
provisions, and qual ification and inspection procedures for al l semi-
conductor devices.
MI L- ST D- 7 0 1 provides a l isting of those MI L- S- 1 9 5 0 0 devices which
are considered to be standard or are preferred for use in DoD equipments.
Fail ure rates for these devices can be cal cul ated in accordance with
MI L- HDBK- 21 7 B.
T abl e 4 - 5 provides additional information for discrete semiconductor
devices. I ncl uded in this tabl e are typical appl ications for the type of
semiconductor l isted, a cross referencing of standard types derived from
MI L- ST D- 7 0 1 and a l ist of fail ure rates against each semiconductor type.
9 6
T abl e 4 - 4 SEMI CO NDUCT O R SELECT I O N GUI DELI NES
1 . MI L- ST D- 7 0 1 , " Lists of Standard Semiconductor Devices" .
2. MI L- S- 1 9 5 0 0 E, " Semiconductor Devices, General Specifica-
tion For" (" JA NT XV" or " JA NT X" devices).
3 . Historical T est data (simil ar appl ication) or other
engineering information and/or data that provides assur-
ance that the device is sufficientl y rugged and rel iabl e
for the appl ication (e.g., previous use in mil itary
equipment).
NO T E: I n sel ecting semiconductor devices it is important to
remember that in MI L- S- 1 9 5 0 0 the val ues specified for
" ratings" , " maximum ratings" , or " absol ute maximum
ratings" are based on the " absol ute system" and are
not to be exceeded under any service or test condi-
tions. T hese ratings are l imiting val ues beyond which
the serviceabil ity of any individual semiconductor
device may be impaired. I t fol l ows that a combination
of al l the absol ute maximum ratings cannot normal l y be
attained simul taneousl y. Combinations of certain
ratings may be obtained onl y if no other singl e maximum
rating is exceeded. Unl ess otherwise specified, the
vol tage, current and power ratings are based on con-
tinuous dc power conditions at free air ambient
temperature of 25 + 3 C. For pul sed or other condi-
tions of operation of simil ar nature, the current,
vol tage and power dissipation ratings are a function
of time and duty cycl e.
9 7
T abl e 4 - 5 A PPLI CA T I O N A ND SELECT I O N GUI DELI NES FO R SEMI CO NDUCT O RS
Semiconductor type A ppl ication
MI L- ST D- 7 0 1
T abl e No.
Fail ure rate
F/1 0
6
hrs
Diodes, sil icon Low power rectifiers I 0 .68
general purpose A xial l ead power rectifiers I I 0 .68
Power diodes I I I 0 .68
High vol tage rectifier I V 0 .68
assembl ies
Switching diodes V
0 .68
Mul tipl e diode arrays VI 0 .68
Diodes, sil icon Vol tage reference diodes VI I 0 .8 5
vol tage reference Low l evel forward- vol tage
reference diodes
VI I I 0 .8 5
Vol tage regul ator diodes I X 0 .8 5
Current regul ator diodes XI V 0 .8 5
Rectifiers, T hyristors XI X 0 .9 0
sil icon control l ed XX 0 .9 0
Diodes, sil icon Fast recovery XI 8 .1
microwave detector Detector X 1 2.0
microwave mixer Mixer X 1 6.0
Diodes, germanium T unnel diodes XI I 1 .7
microwave detector Detector X 3 5 .0
Mixer X 61 .0
Diode, varactor Vol tage variabl e capacitor XI I I 8 .1
T ransistor, Low power and switching XXI 0 .9 8
sil icon NPN High power > 5 w XXI I I 0 .9 8
Radio frequency XXV 0 .9 8
Darl ington XXVI I I 0 .9 8
Dual transistor, XXVI 1 .9 6
differential ampl ifier
Low power chopper XXXI I 0 .9 8
Low power dual emitter XXXI I I 0 .9 8
chopper
T ransistor, Low power and switching XXI I 1 .6
sil icon PNP High power > 5 w XXI V 1 .6
Radio frequency XXV 1 .6
Dual transistor, XXVI 3 .2
differential ampl ifier
Low power chopper XXXI I 1 .6
T ransistor, Compl imentary NPN/PNP XXVI I 2.5 8
sil icon, dual
T ransistor, Fiel d effect N channel XXX 2.7
sil icon, FET Fiel d effect P channel XXX 2.7
Fiel d effect, dual unitized XXXI 5 .4
N channel
9 8
Because of the prol iferation of device types, proven technol ogy and
device standardization, semiconductor fail ure modes are wel l establ ished
and can be effectivel y control l ed during processing. Consequentl y,
fail ures usual l y occur on a random basis during normal operation within
the useful l ife of the device. T abl e 4 - 5 incl udes fail ure rate informa-
tion for each semiconductor type. T he fail ure rates shown were taken
from Section 3 .0 of MI L- HDBK- 21 7 B under the airborne inhabited environ-
ment.
4 .1 .1 .2.3 Resistors
A s a generic cl ass of el ectronic devices, resistors have been wel l
documented by MI L specifications and standards. Consequentl y, a sel ec-
tion from among a variety of avail abl e standard types and styl es can be
made. For economic reasons, standard resistors are normal l y produced in
l arge productions runs, making the sel ection of standard devices even
more attractive. Note, however, that there are exceptions. Extremel y
tight- tol erance fixed resistors and certain precision type variabl e
resistors, which require a unique output vol tage curve, taps or stacking
configuration, may be difficul t or expensive to procure or possess
questionabl e rel iabil ity. Resistor sel ection is governed by the guide-
l ines given in T abl e 4 - 6.
T abl e 4 - 6 RESI ST O R SELECT I O N GUI DELI NES
1 . MI L- ST D- 1 9 9 , " Resistors, Sel ection and Use of"
2. T he 3 9 0 0 0 series of Establ ished Rel iabil ity Mil itary
Specifications.
3 . Historical test data (simil ar appl ication) or other
mil itary equipment, comparabl e appl ication or GFE).
NO T E: For sel ecting particul ar resistors for specific appl ica-
tions, the qual ified product l ist shoul d be consul ted for
a l ist of qual ified sources prior to procurement commitments,
9 9
I n addition to these sel ection criteria, T abl e 4 - 7 presents further
considerations to be empl oyed when sel ecting resistors. T he resistor
types shown, together with their appropriate MI L specification styl e
designations and appl icabil ity to new design, refl ect the provisions of
MI L- ST D- 1 9 9 .

T he generic fail ure rates given in the tabl e are taken from MI L-
HDBK- 21 7 B and are provided for purposes of comparison. T he fail ure
rates refl ect an airborne inhabited environment and an M qual ity l evel .
4 .1 .1 .2.4 Capacitors
Simil ar to resistors, capacitors have been thoroughl y investigated
for operational characteristics, identified for form, function and
appl icabl e ratings, and documented for procurement, test, qual ification
approval , qual ity control and standardization within MI L specifications
and standards. Like resistors, they are normal l y produced in l arge pro-
duction runs which tends to keep unit pieces l ow priced and promotes
standardization. Capacitor sel ection is governed by the guidel ines given
in T abl e 4 - 8 .
T abl e 4 - 8 CA PA CI T O R SELECT I O N GUI DELI NES
1 . MI L- ST D- 1 9 8 , " Capacitors, Sel ection and Use of" .
2. T he 3 9 0 0 0 series of Establ ished Rel iabil ity Mil itary
Specifications.
3 . Historical test data (from simil ar appl ication) or other
engineering information and/or data that provides assurance
that the device is sufficientl y rugged and rel iabl e for the
appl ication (e.g., previous use in mil itary equipment,
comparabl e appl ication, or GFE).
NO T E: I n sel ecting particul ar capacitors for specific appl ica-
tions, the qual ified product l ist shoul d be consul ted
for a l ist of qual ified sources prior to procurement
commitments.
1 0 0
T abl e 4 - 7 A PPLI CA T I O N A ND SELECT I O N GUI DELI NES FO R RESI ST O RS
Mil itary
specifications
T ype Styl es A ppl ication notes Fail ure Modes
Fail ure rate
(F/1 0 * hrs)
MI L- R- 1 1 Composition
insul ated
I nactive for new design. Use MI L- R- 3 9 0 0 8
MI L- R- 26 Wire- wound
(power type)
RW29 RW3 7
RW3 1 RW3 8
RW3 3 RW4 7
RW3 5 RW5 7
See data on MI L- R- 3 9 0 0 7 0 .3 3
MI L- R- 9 3 Wire- wound
(accurate)
I nactive for new design. Use MI L- R- 3 9 0 0 5
MI L- R- 1 0 5 0 9 Fil m (high
stabil ity)
RN7 5
See data on MI L- R- 5 5 1 8 2 0 .0 23
MI L- R- 1 1 8 0 4 Fil m (power type) RD60
RD65
RD7 0
Use where power dissipation equival ent to
MI L- R- 3 9 0 0 7 are required and where ac per-
formance must be considered. RD60 , RD65 ,
and RD7 0 are considered uninsul ated.
SHO RT S- - Humidity or sal t air can cause shunt
paths on surface of resistor and shorting
between spiral s.
0 PENS- - Can be caused by mechanical damage.
O peration at RF above 1 0 0 MHz may produce
inductive effects on spiral l ed units.
1 .3
MI L- R- 1 8 5 4 6 Wire- wound power
type (chassis
mounted)
RE7 7 RE8 0
See data on MI L- R- 3 9 0 0 9 0 .65
MI L- R- 2268 4 Fil m (insul ated) I nactive for new design. Use MI L- R- 3 9 0 1 7
MI L- R- 3 9 0 0 5 Wire- wound
(accurate)
establ ished
rel iabil ity
R8 R5 2 RBR5 6
RBR5 3 RBR5 7
RBR5 4 RBR7 1
RBR5 5 RBR7 2
Styl es RBR5 2, 5 3 , 5 4 , 5 5 , 5 5 , and 7 1 are
preferred for new design. Preferred re-
sistance tol erances are O .H and
1 .0 X.
SHO RT SA ppl ication of over- vol tage can cause
insul ation breakdown between windings.
O PENS- - Resistors empl oy pl astic or ceramic
bobbins which are subject to mechanical dam-
age, resul ting in open windings. O peration
over 5 0 kHz can produce inductive and intra-
windl ng capadtl ve effects.
0 .1 5
(power type)
establ ished
rel iabil ity
RWR7 4 RWR8 1
RWR7 8 RWR8 4
RWR8 0 RWR8 9
Use for l arge power dissipation where ac
performance 1 s not vital (e.g., as vol tage
dividers, or bl eeders in power suppl ies).
Satisfactory for use at frequencies up to
20 kHz even though the ac characteristics
are control l ed. T he use of tapped resis-
tors shoul d be avoided; the insertion of
taps weakens the resistor mechanical l y and
l owers the effective power rating. Resis-
tors are not suitabl e for use above 5 0 kHz.
SHO RT S- - Rarel y occur, but can happen due to
intrawl nding insul ation breakdown.
0 PENS- - Usual l y occur due to mechanical damage
suffered by the resistor or from winding burn-
out due to the wattage rating or the rated
continuous working vol tage being exceeded.
0 .0 66
T abl e 4 - 7 A PPLI CA T I O N A ND SELECT I O N GUI DELI NES FO R RESI ST O RS (Page 2)
Mil itary
Specifications
T ype Styl es A ppl ication Notes Fail ure Modes
Fail ure rate
(F/1 0
6
hrs)
MI L- R- 3 9 0 0 3 Composition
(insul ated)
RCR0 5
RCR0 7
RCR20
RCR3 2
RCR4 2
Use for general appl ications where initial
tol erance needs to be no tighter than 5%
and l ong term stabil ity under ful l y rated
operating conditions needs to be no better
than t 1 5 %. Resistance increases up to 20 %
during storage in humidity. O peration of
the resistor at rated l oad wil l drive out
the noisture and bring the resistor val ue
back to within tol erance.
Both shorts and opens very rarel y occur un-
l ess resistor is so over- l oaded or over-
heated as to cause the phenol ic case or
thermo- setting binder material to carbonize.
I n high impedance circuits, the fail ure mode
is general l y a short; in l ow impedance cir-
cuits, the fail ure mode 1 s open. High
" JO HNSO N" noise l evel s are present in resis-
tor val ues above 1 .0 megohm.
DRI FT RF wil l produce capacitive effects
end- to- end. O peration at VHF or higher fre-
quency reduces effective resistance due to
diel ectric l osses (the " Boel l o" effect).
0 .0 0 4 8
(power type)
establ ished
rel iabil ity
RER4 0 RER60
RER4 5 RER65
RER5 0 RER7 0
RER5 5 RER7 5
Use where a l ower tol erance and a greater
power dissipation is required for a given
unit size than is provided by MI L- R- 3 9 0 0 7
resistors, and where ac performance is not
critical . T he power dissipating capacity
of these resistors is dependent upon the
area of heat sink upon which is it mounted.
SHO RT S- - May occasional l y occur due to 1 ntra-
winding insul ation breakdown.
0 PENS- - May occasional l y occur due to damage
to the winding, poor winding to terminal
connection, etc., suffered during fabrica-
tion.
0 .1 3
MI L- R- 3 9 0 1 7 Fil m (insul ated)
establ ished
rel iabil ity
RLR0 5
RLR0 7
RLR20
RLR3 2
RLR4 2
Resistors have semi- precision characteris-
tics and smal l sizes. T he sizes and
wattage ratings are comparabl e to MI L- R-
3 9 0 0 8 units and stabil ity l ies between
MI L- R- 3 9 0 0 8 and MI L- R- 5 5 1 8 2. Ful l power
operating temperature shoul d not exceed
7 0 C. Resistance- temperature characteris-
tic is 20 0 PPM/C.
SHO RT S or O PENS may occur 1 f resistor is
poorl y fabricated or over- l oaded 1 n appl ica-
tion. O peration at RF above 1 0 0 MHz may
produce inductive effects on spiral - cut
types.
0 .0 2
MI L- R- 5 5 1 8 2 Fil m
establ ished
rel iabil ity
RNR5 0
RNR5 5
RNR60
RNR65
RNR7 0
Use where high stabil ity, l ong l ife, rel i-
abl e operation and accuracy are required.
Resistors are particul arl y suited for high
frequency appl ications. A ppl ication
exampl es incl ude: high- frequency, tuned
circuit l oaders, tel evision side- band
fil ters, rhombic antenna terminators, radar
pul se equipment, and metering circuits.
SH0 RT S- - May occasional l y occur because of
protuberances on adjacent resistance
spiral s.
0 PENS- - May occasional l y occur due to non-
uniform spiral s resul ting in a too- thin
resistance path.
O peration at 4 0 0 MHz and above wil l resul t
in resistance decrease due to shunt capaci-
tance effects.
0 .0 23
T abl e 4 - 7 A PPLI CA T I O N A ND SELECT I O N GUI DELI NES FO R RESI ST O RS (Page 3 )
Mil itary
Specifications
T ype Styl es A ppl ication notes Fail ure modes
Fail ure rate
(F/1 0
&
hrs)
VA RI A BLE RESI ST O RS
MI L- R- 1 9 Wire- wound (l ow RA 20 Use for noncritical , l ow power, l ow fre- Variabl e resistors as a cl ass of components 6.4
operating RA 3 0 quency appl ications where the character- share many common fail ure modes:
temperature) istics of wirewound devices are more
desirabl e than those of composition.
Common appl ications are bias control s and
vol tage dividers. Wattage rating depends
upon the size and type of heat sink unit is
mounted on. Resistors have high inductance
between windings.
1 . Wire- wound units are inductive, winding-
to- winding, causing resistance drift and
affecting circuitry accuracy.
2. Wire- wound units suffer shorts between
winding l oops due to insul ation breakdown
or contaminants which bridge the insul a-
tion. MI L- R- 22 Wire- wound RP0 5 Use in such appl ications as motor speed 6.0
(power type) RP0 6 control s; l amp dimming; heater and oven
RP1 0 control s; potentiometric uses; appl ications 3 . Windings wil l rupture with sufficient
RP1 5 where vol tage or current variation is re- wear by the wiper arm, resul ting in an
RP20 quired, such as vol tage- divider or bl eeder open circuit.
RP25 circuits.
RP3 0 4 . A l l variabl e resistors can suffer move-
ment of the wiper on the resistance el e-
ment as the resul t of shock or vibration. MI L- R- 9 4 Composition RV4 Rate for ful l - l oad operation at 7 0 C, 20 .0
(insul ated) RV6 otherwise SEE DA T A O N MI L- R- 23 28 5 . I n critical appl ications, the resul tant
change of the output vol tage can consti-
MI L- R- 1 29 3 4 Wire- wound RR0 9 0 0 Use in appl ications requiring cl ose con- tute a " fail ure" of the resistor. 5 .8
precision RR1 0 0 0 formity of the el ectrical output (in terms
RR1 1 0 0 of appl ied vol tage) to the angul ar position 5 . Non- wirewound units become noisier with
RR1 3 0 O of the wiper arm on the resistance el ement. wear l ife, and wil l suffer resistance
RR1 4 0 0 T his functional conformity (whether produc- change due to humidity.
RR20 0 0 ing a l inear or nonl inear output curve with
RR21 0 0 shaft rotation) is avail abl e in tol erances 6. Power ratings for al l variabl e resistors
RR3 0 0 0 ranging from 0 .0 25 X through 1 .0 * . Power
rating is dependent on the size and type of
heat sink upon which resistor is mounted.
are based upon the engagement of the
maximum resistance by the wiper. Exces-
sive currents can be drawn when l ess-
than- maximum resistance is engaged,
resul ting in a burnout of the resistance
MI L- R- 23 28 5 Non- wirewound RVC5 Use where initial setting stabil ity is not 6.7
RVC6 critical and l ong term stabil ity needs to
be no better than 1 20 %. Rated for ful l
l oad operation at 1 25 C.
el ement.
T abl e 4 - 7 A PPLI CA T I O N A ND SELECT I O N GUI DELI NES FO R RESI ST O RS (Page 4 )
2
Mil itary
specifications
Fail ure rate
(F/1 0
6
hrs)
MI L- R- 220 9 7 Non- wirewound
(l ead- screw
actuated)
RJ1 2 RJ24
RJ22 RJ26
RJ5 0
See data on MI L- R- 3 9 0 3 5 Variabl e resistors as a cl ass of components
share many common fail ure modes, (see
preceding page.)
9 .5
MI L- R- 27 20 8 Wire- wound
(l ead- screw
actuated)
RT 26 See data on MI L- R- 3 9 0 1 5 0 .7 0
semi- precis ion
RK0 9 Use where the precision needed is better
than that suppl ied by MI L- R- 1 9 units and
l ess than that suppl ied by MI L- R- 1 29 3 4
units. Power rating is dependent on size
and type of heat sink upon which resistor
is mounted.
6.4
(l ead- screw
actuated)
establ ished
rel iabil ity
RT R1 2
RT R22
RT R24
Use for matching, bal ancing, and adjusting
circuit variabl es in critical appl ications.
For extremel y critical appl ications, use in
conjunction with a fixed resistor, so that
change in wiper setting due to shock or
vibration l imits output vol tage change to a
negl igibl e minimum.
0 .1 4
MI L- R- 3 9 0 3 5 Non- wirewound
(l ead- screw
actuated)
establ ished
rel iabil ity
RJR1 2
RJR1 4
Same as MI L- R- 3 9 0 1 5 7 .9 6
T abl e 4 - 9 presents additional considerations to be empl oyed when
sel ecting capacitors. T he capacitor types shown, together with their
appropriate MI L specification styl e designations and appl icabil ity to
new design, refl ect the provisions of MI L- ST D- 1 9 8 .
T he fail ure rates given in T abl e 4 - 9 have been provided for the sol e
purpose of demonstrating comparative rel iabil ity l evel s of the various
capacitor types. T hese are generic fail ure rates taken from MI L- HDBK-
21 7 B.
4 .1 .1 .2.5 O ther Parts
T he sel ection of the fol l owing devices are governed by the guide-
l ines depicted in T abl es 4 - 1 0 through 4 - 20 and Figure 4 - 2.
El ectron T ubes (T abl e 4 - 1 0 )
I nductive Devices (T abl e 4 - 1 1 )
Rel ays (T abl e 4 - 1 2, 4 - 1 3 and 4 - 1 4 )
Switches (T abl e 4 - 1 5 , 4 - 1 6 and Figure 4 - 2)
Connectors (T abl e 4 - 1 7 )
Microwave Devices (T abl e 4 - 1 8 and 4 - 1 9 )
Cabl es (T abl e 4 - 20 ).
4 .1 .1 .3 Part Screening
A s discussed in Section 1 of this handbook, virtual l y al l manufac-
tured devices exhibit a l ife characteristic which may best be represented
by the bathtub curve shown in Figure 1 - 1 . T his section deal s with the
first segment of the curve, namel y, the " infant mortal ity" or the " earl y
fail ure" period of the equipment's l ife. Experience shows that a newl y
constructed equipment fail s more often during its earl y l ife (i.e.,
during assembl y and testing) than l ater during use in the fiel d.
T his indicates that piece parts received from the suppl ier contain
a certain number of weak devices which tend to fail during initial
testing of subassembl ies or compl ete equipments.
I n order to el iminate the incipient fail ures from the manufacturing
process, qual ity and screening tests can be empl oyed. T he qual ity tests
1 0 5
T abl e 4 - 9 A PPLI CA T I O N A ND SELECT I O N GUI DELI NES FO R CA PA CI T O RS
Mil itary
specification
Fail ure rate
(F/1 0
6
hrs)
FI XED, GLA SS A ND MI CA
MI L- C- 5 Mica diel ectric CM0 5 CM0 7
CM0 6 CM0 8
I nactive for new design. See MI L- C- 3 9 0 0 1
CM1 5 CM3 5
CM20 CM4 5
CM3 0 CM5 0
Use in circuits requiring precise, high-
frequency fil tering, bypassing and coup-
l ing. Use where cl ose impedance l imits are
essential with respect to temperature, fre-
quency and agingsuch as in tuned circuits
which control frequency, reactance, or
phase. Use as padders in tuned circuits,
as secondary capacitance standards, and for
tuning of high frequencies. Capacitors
have good stabil ity and rel iabil ity.
Shorts can occur due to moisture absorption,
or due to internal sol der fl ow resul ting from
excessive heat generated during external
l ead- sol dering.
O pens usual l y resul t from rupture of weak
internal connections due to vibration or
shock.
0 .0 6
MI L- C- 1 0 9 5 0 Mica diel ectric CB5 0 CB61
CB5 5 CB62
CB5 6 CB65
CB5 7 CB66
CB60 CB67
I ntended for use at frequencies up to
5 0 0 MHz. Use in tuned circuits, and in
coupl ing and bypassing appl ications in VHF
and UHF circuits. Units have high rel ia-
bil ity if properl y protected from high
ambient temperature and humidity condi-
tions.
Capacitors are very susceptibl e to sil ver- ion
migration, resul ting in shorts. Migrations
can occur in a few hours when capacitors are
simul taneousl y exposed to dc vol tage stress,
humidity and high temperature.
0 .9 3
MI L- C- 23 269 Gl ass diel ectric I nactive for new design. See MI L- C- 23 269 .
MI L- C- 23 269 Gl ass diel ectric
establ ished
rel iabil ity
(FR: 1 to 0 .0 0 1 )
CYRI O
CYR1 3
CYR1 5
CYR1 7
CYR20
CYR22
CYR3 0
CYR3 2
Capacitors shoul d be used as substitutes
for mica units in appl ications requiring
known rel iabil ity and where the differences
in temperature coefficient and diel ectric
l oss are taken into account. T hey are
stabl e in extreme environmental conditions,
have l ong l ife (3 0 , 0 0 0 hrs and more) and
are very satisfactory for use in missil e-
borne and space equipment. T hese physi-
cal l y- smal l units are resistant to high G
l oads, but are susceptibl e to damage from
mil d mechanical shocks. T herefore, they
shoul d be handl ed careful l y. T hey exhibit
a much higher Q over a wider capacitance
range than mica diel ectric units.
Degradation of diel ectric crystal l ine struc-
ture can occur as the resul t of storage bel ow
4 5 C. T he capacitance wil l decrease with the
decrease in diel ectric constant and the unit
wil l drift out of tol erance.
O pens are frequentl y due to poor connections
of l eads to the pl ates or mechanical damage
to the capacitor. O verheating during exter-
nal sol dering can resul t in internal sol der
fl ow (shorts) or rupture of internal sol der
connection (opens).
0 .0 21
T abl e 4 - 9 A PPLI CA T I O N A ND SELECT I O N GUI DELI NES FO R CA PA CI T O RS (Page 2)
Mil itary
specification
Fail ure rate
(F/W hrs)
MI L- C- 3 9 0 0 1 Mica diel ectric
establ ished
rel iabil ity
(FR: 1 to 0 .0 0 1 )
CMR0 4
CMR0 5
CMR0 6
CMR0 7
CMR0 8
I ntended for use where known orders of
rel iabil ity are required. Fail ure rate
depends al most excl osivel y on unit's ap-
pl ication; e.g., (1 ) with constant temper-
ature, capacitor l ife is inversel y propor-
tional to the 8 th power of the appl ied dc
vol tage, or (2) with constant dc vol tage,
l ife decreases approximatel y 5 0 * per each
1 0 C rise in temperature. Life expectancy
at rated conditions is 5 0 , 0 0 0 hrs, minimum.
(Fail ure rate shown in l ast col umn is taken
from MI L- ST D- 1 9 8 C)
Same comments as given for MI L- C- 5 . 0 .0 0 6
FI XED, ELECT RO LYT I C
MI L- C- 62 El ectrol ytic (dry
el ectrol yte al um-
inum)
Not appl icabl e for airborne equipment use.
MI L- C- 3 9 65 El ectrol ytic (non-
sol id el ectrol yte)
tantal um
I nactive for new design. See MI L- C- 29 0 0 6.
MI L- C- 3 9 0 0 3 T antal um (sol id
el ectrol yte)
establ ished
rel iabil ity
(FR: 2 to 0 .0 0 1 )
CSR1 3 I ntended for use where a known order of
rel iabil ity is required. T hese capacitors
are the most stabl e, rel iabl e and l ong-
l ived el ectrol ytics avail abl e. T hese units
are not temperature sensitive. Limitations
are rel ativel y high l eakage current, smal l
vol tage range (6- 1 20 V) and a maximum al -
l owabl e reverse current of 5 % of rated dc
vol tage at + 25 C to 1 .0 ? at + 1 25 C. Capa-
citors are used where l ow- frequency, pul -
sating dc components are to be bypassed or
fil tered- out and for uses requiring l arge
capacitances, smal l size and the abil ity to
withstand significant shock and vibration
l evel s. Use for fil tering, bypass, coup-
l ing, bl ocking, energy storage and other
l ow vol tage dc appl ications. Capacitors
are avail abl e onl y in pol arized form; use
onl y in dc circuits with the pol arity
observed.
Shorts can occur due to sol der- bal l s created
by internal sol der fl ow resul ting from heat
generated during the external sol dering of
l eads. Shorts due to diel ectric breakdown
are rare due to sel f- heal ing effect of high
l eakage current on the Mn0 2, provided current
is l imited by use of a 3 ohm/vol t l ine resis-
tance in series with the capacitor.
O pens occur mainl y due to poor sol der or wel d
internal connections which rupture during
vibration or shock.
0 .0 5 2
T abl e 4 - 9 A PPLI CA T I O N A ND SELECT I O N GUI DELI NES FO R CA PA CI T O RS (Page 3 )
Mil itary
specification
Fail ure rate
(F/1 0
6
hrs)
MI L- C- 3 9 0 0 6 El ectrol ytic (non-
sol id el ectrol yte)
tantal um
rel iabil ity
establ ished
CLR25
CLR27
CLR3 5
CLR3 7
CLR65
Pol arized foil capacitors (styl es CLR25 and Capacitors are subject to fail ure (shorts)
due to l eakage of the el ectrol yte which can
be caused by wide- range temperature cycl ing,
vibration or agencies which damage the seal .
T he appl ication of reverse vol tage wil l al so
resul t in shorts.
O pens are usual l y associated with faul ts in
external l ead wel ds.
0 .1 1
CLR3 5 ) shoul d be used where l arge capaci-
tance val ues are required and wide tol er-
ances are acceptabl e. Use for bypassing or
fil tering- out l ow frequency pul sating dc
components. When used for l ow frequency
coupl ing in vacuum tube and transistor cir-
cuits, al l ow for l eakage current. Units
shoul d be used onl y in dc circuits with
pol arity properl y observed. I f ac compon-
ents are present, the sum of the peak ac
vol tage pl us the appl ied dc vol tage must
not exceed the dc rated vol tage. A l so,
peak ac vol tage shal l not exceed the ap-
pl ied dc vol tage.
Nonpol arized foil capacitors (styl es CLR27
and CLR3 7 ) are suitabl e for use in ac
appl ications where dc vol tage reversal s
occur. Exampl es: tuned, l ow frequency
circuits; phasing l ow- vol tage ac motors;
computer circuits, in which dc vol tage-
reversal occurs; servo systems.
Sintered- sl ugs (styl e CLR65 ) are used pri-
maril y in l ow vol tage power suppl y fil ter-
ing circuits. Use in dc appl ications
onl y; no reverse vol tage can be tol erated.
MI L- C- 3 9 0 1 8 El ectrol ytic
(al uminum oxide
el ectrol yte)
CU1 3
CU1 5
CU1 7
Use in fil ter, coupl ing, and bypass appl i-
cations in which l arge capacitances are
needed and capacitance excesses over the
nominal val ue can be tol erated. For pol ar-
ized units (styl es CU1 3 and CU1 7 ) the
appl ied ac peak vol tage shoul d never exceed
the appl ied dc vol tage. T he sum of the
appl ied ac peak and dc vol tages shoul d
never exceed the dc rated weaking vol tage.
Use where l ow- frequency, pul sating dc sig-
nal components are to be fil tered out, such
as in B power suppl ies up to 25 0 dc working
vol ts; at pl ate and screen connections to
B+ ; and as cathode bypass units in sel f-
biasing circuits.
Capacitance l oss (drift) wil l occur as the
resul t of the al uminum oxide diel ectric el ec-
tric el ectrochemical l y combining with the
el ectrol yte. O pens can occur by the dissol u-
tion in the el ectrol yte of the l ead between
an el ectrode and the al uminum. Seal degrada-
tion can resul t from use of any type of
hal ogenated sol vent wash. A ppl ication of
vol tage in reverse pol arity wil l burnout
(open) these units.
1 .6
Mil itary
specification
Fail ure rate
(F/1 0
6
hrs)
FI XED, PA PER A ND PLA ST I C
MI L- C- 25 Paper (or paper-
pl astic diel ec-
tric)
I nactive for new design. See MI L- C- 1 9 9 7 8 .
MI L- C- 1 1 69 3 Feed through
radio- interfer-
ence reduction;
ac and dc
CZ23
CZ3 3
CZ4 2
Use in appl ications where it 1 s necessary
to pass l ow- frequency currents through a
chassis or from point- to- point in an equip-
ment and to pass the RF currents (which can
cause interference) to ground by the short-
est possibl e path. T ypical equipment for
the above appl ications are:
(a) rotating machinery
(b) ignition systems
(c) el ectromechanical vol tage regul ators,
vibrators, and switches
(d) el ectronic devices (transmitters,
radar modul ators, thyratrons, etc.).
Same comments as given for MI L- C- 1 9 9 7 8 . 0 .0 1
MI L- C- 1 28 8 9 Bypass radio-
interference
reduction paper
diel ectric, ac
and dc
CA 3 2
CA 3 6
CA 4 7
Use for general purpose appl ications where
suppression of broadband radio interfer-
ence is needed. T hese capacitors are use-
ful in l imiting el ectrical disturbances of
the conducted type onl y. Where maximum
insertion l oss from a bypass capacitor
above 1 MHz is desired, the feed- through
type covered by MI L- C- 1 1 69 3 wil l provide
attenuation over the useful frequency
range.
Principal fail ure modes are shorts due to
entrance of moisture or contaminants if
hermetic seal is ruptured.
O pens are due to poor internal connections
which can rupture due to shock or vibration.
0 .0 2
MI L- C- 1 4 1 5 7 Pl astic (paper-
pl astic) or
pl astic diel ec-
tric, dc, her-
metical l y- seal ed
in metal cases,
establ ished
rel iabil ity
(FR: 1 to 0 .0 0 1 )
I nactive for new design. See MI L- C- 1 9 9 7 8 .
Mil itary
specification
Fail ure rate
(F/1 0
6
hrs)
MI L- C- 1 8 3 1 2 Metal l ized paper
(or pol yester
fil m) diel ectric
I nactive for new design. See MI L- C- 3 9 0 22.
MI L- C- 1 9 9 7 8 Pl astic (or paper
- pl astic) diel ec-
tric
CQR0 7
CQR0 9
CQR1 2
CQR1 3
CQR29
CQR3 2
CQR3 3
Capacitors are intended for use in appl ica-
tions which require high insul ation resis-
tance, l ow diel ectric absorption, or l ow
l oss factor over wide temperature ranges,
and where the ac components of the im-
pressed vol tage is smal l compared to the dc
vol tage rating. I f ac components are pre-
sent, the sum of the dc peak vol tage and
the ac peak vol tage shal l never exceed the
rated dc vol tage, nor shal l the peak ac
vol tage exceed 20 % of the dc vol tage rating
at 60 Hz, 1 5 % at 1 20 Hz, or 1 .0 % at
1 0 , 0 0 0 Hz.
For A ir Force equipment appl ications, do
not use these capacitors above 8 5 C ambient
temperature.
Principal fail ure modes are open, due to poor
internal connections and use at rated vol tage
l evel s in high temperatures.
Shorts can occur due to internal sol der fl ow
caused by excessive heat being appl ied to the
terminal s during external sol dering. Shorts
al so occur due to contaminants in the diel ec-
tric causing momentary breakdown which can
resul t in a carbonization of the pl astic,
which, if extensive enough, wil l resul t in a
permanent short.
0 .0 0 1 2
MI L- C- 3 9 0 22 Metal l ized di-
el ectric, dc
(hermatical l y
seal ed in metal
cases), estab-
l ished rel ia-
bil ity
CHR0 9
CHR1 9
I ntended for use in appl ications where the
ac vol tage component is smal l compared to
the dc vol tage rating and where occasional
periods of l ow insul ation resistance and
momentary breakdown can be tol erated. I f
ac component is present, the sum of the
appl ied dc and the peak ac vol tage shal l
not exceed the rated dc vol tage, and the ac
vol tage shal l not exceed 20 % of the dc
vol tage rating.
O pens occur due to poor internal connections,
which under strong el ectrical or mechanical
stress, wil l rupture.
Shorts can occur due to internal sol der fl ow
as the resul t of overheating the l eads dur-
ing external sol dering.
Momentary shorts occur very frequency because
the diel ectric is so thin, but wil l heal
themsel ves, l osing a smal l amount of capaci-
tance in the process.
0 .0 0 1 2
FI XED, CERA MI C
MI L- C- 1 1 0 1 5 Ceramic diel ec-
tric (general
purpose)
CK60 CK67
CK62 CK68
CK63 CK69
CK65 7 0
CK66 CK7 1
I ntended for use where smal l size, compara-
tivel y l arge capacitance and high insul a-
tion resistance are required. Capacitors
are suitabl e for use as bypass, fil ter and
noncritical coupl ing el ements in high- fre-
quency circuits where appl icabl e capaci-
tance change caused by temperature varia-
tions can be tol erated. (Continued)
Shorts- - can occur due to sil ver ion migration
caused by high humidities coupl ed with the
appl ication of high dc vol tage.
O pens- general l y resul t from damage done to
trie capacitor by handl ing or by the appl ica-
tion of excessive heat during sol dering which
ruptures internal connections.
0 .4 4
T abl e 4 - 9 A PPLI CA T I O N A ND SELECT I O N GUI DELI NES FO R CA PA CI T O RS (Page 6)
Mil itary
specification
Fail ure rate
(F/1 0
6
hrs)
MI L- C- 1 1 0 1 5 (continued) T ypical cases incl ude resistive- capacitive
coupl ing for audio and radio frequency, RF
and I F cathode bypass, etc. Use where
dissipation factor is not critical and
moderate changes due to temperature, vol t-
age and frequency variations, do not affect
proper circuit function.
Shorts can al so occur by internal sol der re-
fl ow due to excessive heat appl ied to l eads
during external sol dering without use of a
proper heat sink procedure.
MI L- C- 3 9 0 1 1 Not appl icabl e, specification cancel l ed.
MI L- C- 3 9 0 1 4 Ceramic diel ec-
tric, establ ished
rel iabil ity
(FT : 1 to 0 .0 0 1 )
CK0 5
CK0 6
CK64
CK7 2
Use in appl ications where the required
rel iabil ity l evel is known. O therwise ap-
pl ication notes are the same as given for
MI L- C- 1 1 0 1 5 .
Same as MI L- C- 1 1 0 1 5 . 0 .0 4 4
VA RI A BLE
MI L- C- 8 1 Ceramic diel ec-
tric
CV1 1
CV21
CV3 1
Capacitors are intended for use where fine
tuning adjustments are periodical l y re-
quired. T hey are frequentl y used in RF,
I R, oscil l ator, phase shifter, and discrim-
inator stages. Capacitance and adjustment
are rel ativel y l inear. Capacitance change
with temperature change in nonl inear; al so
the temperature sensitivity over the capa-
citance range is nonl inear. Do not use
these units for temperature compensation.
T hese are smal l - size trimmers which are
rel ativel y stabl e under shock and vibra-
tion. Where greater stabil ity is required,
air trimmers shoul d be used.
Same comments as given for MI L- C- 1 1 0 1 5 . 2.4
MI L- C- 9 2 A ir diel ectric
(trimmer)
CT 0 4
CT 1 2
CT 1 6
Same appl ications as given for MI L- C- 8 1
units, except that these units are more
stabl e with temperature. Vol tage ratings
for these units range from 5 0 VDC (CT 0 4 )
through 7 0 0 VDC (CT 1 2).
Shorts can occur due to presence of contamin-
ation within the capacitor. Contaminants
frequentl y are due to threat wear or to gol d
pl ating shaken l oose by vibration.
O pens resul t from col d internal sol der con-
nections rupturing during external sol dering
operations.
1 .0
T abl e 4 - 1 0 ELECT RO N T UBE SELECT I O N CRI T ERI A
1 . MI L- ST D- 20 0 , " El ectron T ubes, Sel ection of" .
2. MI L- E- 1 , " El ectron T ubes, General Specification for" .
3 . MI L- ST D- 4 5 4 C, " Standard General Requirements for El ectronic
Equipment" , Requirement No. 29 .
A ppendix D presents a l isting of el ectron tubes which have
been excerpted from MI L- ST D- 20 0 . T ube types l isted in
MI L- ST D- 20 0 are those devices which meet the fol l owing
criteria:
a) T he tube shal l be considered by representatives of the
mil itary departments the best avail abl e type for
current appl ication.
b) T he tube shal l have been in production, and continued
avail abil ity shal l be reasonabl y certain.
c) T he tube shal l have an approved mil itary specification.
A ppendix D provides a l ist of fail ure rates for tubes taken
from MI L- HDBK- 21 7 B. T hese fail ure rates are from one to three
orders of magnitude greater than semiconductor devices cur-
rentl y in use. T hese fail ure rates are provided mainl y for
comparison and shoul d be used onl y when no semiconductor
device can be found to cover the specific design situation.
I n the case of high power/high frequency tubes, careful
coordination with the tube manufacturers is recommended.
Note that tubes, in general , possess much shorter useful
l ife periods than semiconductor devices.
4 . Historical test data (simil ar appl ications) or other engineer-
ing information and/or data that provides assurance that the
device is sufficientl y rugged and rel iabl e for the appl ica-
tion (e.g., previous use in mil itary equipment, comparabl e
appl ication or GFE).
1 1 2
T abl e 4 - 1 1 SELECT I O N CRI T ERI A FO R T RA NSFO RMERS A ND I NDUCT O RS
1 . MI L- ST D- 1 28 6, " T ransformers, I nductors and Coil s,
Sel ection and Use of" .
2. Establ ished Rel iabil ity Specifications:
MI L- T - 3 9 0 1 3 , " T ransformers and I nductors, A udio
and Power"
MI L- T - 3 9 0 26, " T ransformers, Pul se, Low Power"
3 . I n accordance with MI L specifications: '
MI L- T - 27 , " T ransformers and I nductors"
MI L- C- 1 5 3 0 5 , " Coil s, RF and T ransformers, RF & I F"
MI L- T - 21 0 3 8 , " T ransformers, Pul se"
4 . Historical test data (from simil ar appl ications or other
mil itary equipment, comparabl e appl ication or GFE).
A l ist of fail ure rates for generic types of transformers
and inductors is given in T abl e 4 - 1 4 . T his l ist, derived
from MI L- HDBK- 21 7 B, provides comparative val ues for various
inductive devices.
1 1 3
T abl e 4 - 1 2 RELA Y SELECT I O N CRI T ERI A
1 . MI L- ST D- 1 3 4 6, " Rel ays, Sel ection and Use of"
(A ppl icabl e mil itary specifications are l isted in
T abl e 4 - 1 3 .)
2. MI L- ST D- 4 5 4 C, " Standard General Requirements for
El ectronic Equipment" , Requirement No. 5 7 .
3 . MI L- R- 3 9 0 1 6, " Rel ays, El ectromagnetic, Establ ished
Rel iabil ity, General Specification for" .
4 . Historical test data (from simil ar appl ications or other
equipment, comparabl e appl ication or GFE).
Where use of a nonstandard device is necessary, request for
approval of this device shal l be made to mil itary agencies
according to the requirements and procedures of MI L- ST D- 7 4 9 .
A l ist of fail ure rates for generic types of rel ays is given
in T abl e 4 - 1 4 . T his l ist, derived from MI L- HDBK- 21 7 B, pro-
vides comparative val ues for various rel ay types.
1 1 4
T abl e 4 - 1 3 A PPLI CA BLE MI L SPECI FI CA T I O NS FO R RELA YS
a) Low current rel ays (up to 1 0 amps). Low current rel ays
up to 1 0 amperes shal l conform to MI L- R- 5 7 5 7 . However,
rel ay appl ications requiring high in- rush current
capabil ities (i.e., motor and control l er functions) may
be in accord with MI L- R- 61 0 6, as appl icabl e.
b) High current rel ays. Rel ays used in high current
appl ications shal l conform to MI L- R- 61 0 6.
c) T ime del ay rel ays. T hermal time del ay rel ays shal l
conform to MI L- R- 1 9 64 8 . El ectronic, incl uding sol id
state, time del ay rel ays shal l conform to MI L- R- 8 3 7 26.
d) Sol id state tel egraph rel ay assembl ies. Sol id state
passive tel egraph rel ays shal l conform to MI L- R- 27 7 7 7 .
e) Establ ished rel iabil ity rel ays. Establ ished rel iabil ity
rel ays shal l conform to MI L- R- 3 9 0 1 6.
f) Reed rel ays. Reed rel ays shal l conform to MI L- R- 5 7 5 7 .
g) Rel ay sockets. When rel ay sockets are required, they
shal l conform to MI L- S- 1 28 8 3 .
1 1 5
- 6,
T abl e 4 - 1 4 GENERI C FA I LURE RA T ES (x 1 0 "
b
) FO R RELA YS A ND
I NDUCT I VE DEVI CES (Derived from MI L- HDBK- 21 7 B)
CT >
Part T ype
Mr-
e EnvironmentI ncreasing Seve r i cy >
Ground
Benign
Space
Fl ight
Ground
Fixed
A irborne
I nhabited
Naval
Shel tered
Ground
Mobil e
A irborne
Uninhabited
Naval
Uninhabited
Missil e
Launch
RELA YS
1 . General Purpose 0 .1 3 0 .1 3 0 .3 0 1 .3 1 .6 2.6 2.6 3 .2 1 6.0
2. Contactor,
High Current
0 .4 3 0 .4 3 1 .0 4 .5 5 .5 5 .6 8 .8 1 1 .0 3 6.0
3 . Latching 0 .1 2 0 .1 2 0 .29 1 .3 1 .6 1 .6 2.5 3 .1 1 6.0
4 . Reed 0 .1 1 0 .1 1 0 .26 1 .1 1 .4 1 .4 2.2 2.7 1 4 .0
5 . Meter Movement
and Bi- Metal
2.4 2.4 5 .7 25 .0 3 0 .0 3 1 .0 4 9 .0 61 .0 3 1 0 .0
I NDUCT I VE DEVI CES
1 . Pul se T ransformer 0 .0 0 1 2 0 .0 0 1 2 0 .0 0 27 0 .0 0 7 5 0 .0 0 8 3 0 .0 0 4 5 0 .0 1 4 0 .0 1 1 0 .0 1 5
2. A udio T ransformer 0 .0 0 25 0 .0 0 25 0 .0 0 66 0 .0 1 8 0 .0 2 0 .0 1 1 0 .0 3 4 0 .0 27 0 .0 3 6
3 . Power T ransformers
and Fil ters
0 .0 0 7 5 0 .0 0 7 5 0 .0 21 0 .0 5 6 0 .0 64 0 .0 3 4 0 .1 2 0 .0 9 6 0 .1 1
4 . RF T ransformers
and Coil s
0 .0 0 9 6 0 .0 0 9 6 0 .0 22 0 .0 6 0 .0 66 0 .0 3 6 0 .1 1 0 .0 8 4 0 .1 2
T abl e 4 - 1 5 SELECT I O N CRI T ERI A FO R SWI T CHES
1 . MI L- ST D- 1 1 3 2, " Switches and A ssociated Hardware,
Sel ection and Use of" .
2. Requirements 5 8 of MI L- ST D- 4 5 4 C, " Standard General
Requirements for El ectronic Equipment" . MI L- ST D- 4 5 4 C,
Requirement 5 8 requires that:
a) Switches and associated hardware shal l be sel ected
from MI L- ST D- 1 1 3 2 and shal l conform to the appl ic-
abl e specifications l isted therein.
b) Switches other than those l isted in MI L- ST D- 1 1 3 2
shal l conform to one of the fol l owing specifications:
MI L- S- 1 228 5 , Switch, T hermostatic
MI L- S- 1 5 7 4 3 , Switches, Rotary, Encl osed
MI L- S- 1 8 3 9 6, Switches, Meter and Control ,
Naval Shipyard
MI L- S- 21 60 4 , Switches, Rotary, Mul tipol e and
Sel ector T ype
MI L- S- 28 7 0 5 , Switch, Leaf Spring, (Pil e- up
Contacts; Lever, Push, T urn;
I l l uminated and Nonil l uminated)
General Specification for.
3 . Historical test data (from simil ar appl ications) or other
equipment, comparabl e appl ication or GFE).
A l ist of fail ure rates for generic switch types is given in
T abl e 4 - 1 6. T he rel ationship between contact l ife versus l oad
characteristics is shown in Figure 4 - 2.
1 1 7
T abl e 4 - 1 6 FA I LURE RA T ES FO R GENERI C SWI T CH T YPES (x 1 0 "
6
)
00
Switch Type
Use Environment
Ground
Benign
Space
Flight
Ground
Fixed
Airborne
Inhabited
Naval Ground
Sheltered Mobile
Airborne
Uninhabited
Naval
Uninhabited
Missile
Launch
1. Toggle 0.17 0.17 0.57 6.8 0.68 2 .9 8.6 4.0 114.0
2 . Pushbutton 0.11 0.11 0.38 4.6 0.46 1.9 5.7 2 .7 76.0
3. Sensitive 0.2 7 0.2 7 0.90 11.0 1.1 4.5 14.0 6.3 180.0
4. Rotary 0.42 0.42 1.4 17.0 1.7 6.9 2 1.0 9.7 2 80.0
400
300
O
o
c
o
u
0>
D
or
c
0)
o
0>
0.
200
100
Resistive L
Standard S
1000 V.
Contact Sp
.oad
Jwitch
>acing
\
\
\
\
Inductive Load
Standard Switch
1000 V.
Contact Spacing
^
^
"^-~

100 1000 10,000 100,000
Operating Life (Cycles)
1,000,000
Fig. 4-2 EFFECT OF CURRENT ON OPERATING LIFE
CHARACTERISTIC)
(TYPICAL
119
T abl e 4 - 1 7 CO NNECT O R SELECT I O N CRI T ERI A
1
1 . A pproved styl e of Mil itary Specification.
2. MI L- ST D- 4 5 4 C, " Standard General Requirements
for El ectronic Equipment" , Requirement No. 1 0 ,
Notice 3 , 1 May 1 9 7 2.
3 . MI L- P- 1 1 268 (EL), " Parts, Material s and Processes
Used in El ectronic Equipment" .
4 . Historical test data (from simil ar appl ications)
or other engineering information and/or data that
provides assurance that the device is sufficientl y
rugged and rel iabl e for the appl ication (e.g.,
previous use in mil itary equipment, comparabl e
appl ication or 6FE).
*
1 20
T abl e 4 - 1 8 SELECT I O N CRI T ERI A FO R WA VEGUI DES
A ND RELA T ED EQUI PMENT
1 . MI L- ST D- 1 3 27 , " Fl anges, Coaxial and Waveguides; and
Coupl ing A ssembl ies, Sel ection of" .
2. MI L- ST D- 1 3 28 , " Coupl ers, Directional (Coaxial Line,
Waveguide and Printed Circuit), Sel ection of" .
3 . MI L- ST D- 1 3 29 , " Switches, RF Coaxial , Sel ection of" .
Equipment" , Requirement No. 5 3 .
T abl e I of MI L- ST D- 4 5 4 rel ates specific types of waveguide equip-
ment to the appl icabl e MI L specification.
Listings of waveguides, directional coupl ers, fl anges, coupl ing
assembl ies and RF switches are given in Mil itary Standards 1 3 27 ,
1 3 28 and 1 3 29 , respectivel y. Microwave equipments l isted in
MI L- ST D- 1 3 27 , 1 3 28 and 1 3 29 are those which meet the fol l owing
criteria:
a) T he microwave equipment shal l be considered by govern-
ment representatives the best avail abl e type for the
current appl ication.
b) T he microwave equipment shal l have been in production,
and continued avail abil ity shal l be reasonabl y certain.
c) T he microwave equipment shal l have an approved mil itary
specification.
T abl e 4 - 1 9 which fol l ows provides additional guidel ines for
appl ication of waveguides and rel ated equipment.
1 21
T abl e 4 - 1 9 A PPLI CA T I O N A ND USE O F WA VEGUI DES
A ND RELA T ED EQUI PMENT
T he fol l owing requirements of MI L- ST D- 1 3 27 , 1 3 28 and 1 3 29
appl y to the use, in mil itary equipment, of waveguides and
rel ated equipment:
a) Mil itary equipment and assembl ies shal l compl y with their
performance specification requirements when using l isted
fl anges and coupl ing assembl ies which are from manu-
factured l ots possessing acceptabl e material and physical
characteristics.
b) Directional coupl ers used in mil itary equipment shal l be
from l ots possessing acceptabl e material and physical and
el ectrical characteristics and shal l in no manner degrade
the operational characteristics of the equipments in which
used.
c) Coaxial switches used in mil itary appl ications shal l be
representative of manufactured l ots possessing acceptabl e
material and physical and el ectrical characteristics and
shal l in no manner degrade the operational characteristics
of the equipment in which used.
d) Request for use of waveguide and rel ated equipment not
l isted in these standards. When a contractor has deter-
mined that a fl ange or coupl ing assembl y not l isted in
these standards is required, a written request for use of
a nonstandard part shal l be made in accordance with
MI L- ST D- 7 4 9 .
General Design Considerations
a) Material s. When sel ecting parts, consideration shal l be
given to corrosion resistance of material s and the proper
protection of dissimil ar metal combinations.
b) Fabrication or rigid assembl ies. MI L- HDBK- 660 shal l be
used as a guide in the fabrication of rigid assembl ies
1 22
T abl e 4 - 20 SELECT I O N CRI T ERI A FO R CA BLES
Equipment" , Requirement No. 66.
2. A n approved Mil itary Specification styl e.
3 . Historical data (simil ar appl ication) test data or other
engineering information that provides assurance that the
cabl e is sufficientl y rugged and rel iabl e for the appl ica-
tion (e.g., previous use in mil itary equipment, comparabl e
appl ication or GFE). Note: When the use of a nonstandard
cabl e is considered necessary, request for approval for its
use shal l be submitted to the mil itary according to the
procedures of MI L- ST D- 7 4 9 .
T he fol l owing requirements of MI L- ST D- 4 5 4 C appl y to the sel ec-
tion of cabl es:
Sol id or strandedEither sol id or stranded conductors may be
used- - within the restrictions of the particul ar wire or cabl e
specification- - except that (a) onl y stranded wire shal l be used
in aerospace appl ications, and (b) for other appl ications,
stranded wire shal l be used when so indicated by the equipment
specification. Specifical l y, stranded wire shal l be used for
wires and cabl es which are normal l y fl exed in use and servicing
of the equipment, such as cabl es attached to the movabl e hal f
of detachabl e connectors.
SizeConductors shal l be of such cross- section, temper, and
fl exibil ity as to provide ampl e and safe current- carrying
capacity and strength. I n general , wire shal l not be smal l er
than size 22. Smal l er wire may be used when benefits can be
obtained with no l oss in performance. Specifical l y, smal l er
wire may be used in cabl es having l arger numbers of wires and
adequate support against vibration. Smal l er size wire may be
used when necessary for wel ding of el ectronic interconnections.
1 23
are those that reduce the number of defective devices from production
l ines by means of inspection and conventional testing. T he screens are
those which remove inferior devices and reduce the hazard rate by
methods of stress appl ication.
T he purpose of rel iabil ity screening is to compress the earl y fail -
ure period and reduce the fail ure rate to acceptabl e l evel s as quickl y
as possibl e. Figure 4 - 3 il l ustrates the appl ication of a time stress
at the part l evel and shows, comparativel y, how rel iabil ity screening
can improve the part fail ure rate. I t al so shows that, by appl ying a
higher temperature stress of 1 25 C instead of 1 0 0 C, comparabl e fail ure
rate l evel s can be achieved in 1 0 0 hours instead of 24 0 hours.
T he term " screening" can be said to mean the appl ication to an
el ectronic device of a stress test, or tests, which wil l reveal inherent
weaknesses (and thus incipient fail ures) of the devices without destroy-
ing the integrity of the device. T his procedure, when appl ied equal l y
to a group of simil ar devices manufactured by the same processes, is
used to identify sub- par members of the group without impairing the
structure or functional capabil ity of the " good" members of the group.
T he rational e for such action is that the inferior devices wil l
fail and the superior devices wil l pass, provided the tests and stress
l evel s are properl y sel ected. I f the fail ed units are removed from the
group, the remaining devices are those which have demonstrated the
abil ity to withstand stress and their rel iabil ity under normal rated
operating conditions can therefore be assumed.
Screening can be done (a) by the part manufacturer, (b) by the user
in his own facil ities, or (c) by an independent testing l aboratory.
No matter which agency is empl oyed to do the screen tests, the user
shoul d first acquaint himsel f with the efficacy of the screening tests
used by the vendor in normal production. I f such screens exist, and
are effective, screens can be designed to suppl ement the vendor's tests;
if the vendor's tests are unsatisfactory, the screening program wil l
have to be a comprehensive one.
When particul ar fail ure modes or mechanisms are known or suspected
to be present (as indicated in subsection 4 .1 .1 .2), a specific screen
shoul d be sel ected to detect these unrel iabl e el ements.
1 24
2.5
2.0
t
<D
O
en
< v
k.
5
.
0.5
1 \ <fl
\\
I
1 \ \ <o
1 \ \ *

X
00
2
m
k_
X
o
CM
\\ '

i
I00C Stress
125C Stress
225C Stress
100
200
No. Of Hours
300 400
Fig. 4-3 RELIABILITY SCREENS
125
T abl e 4 - 21 shows the fail ure mode distribution for standard sil icon
transistors and integrated circuits: SSI , MSI , LSI (T I data), and
integrated circuits technol ogies, T T L, CMO S (RA C data).
A detail ed understanding of the device characteristics, material s,
packaging and fabrication techniques rel ative to the fail ure mode dis-
tribution shown in T abl e 4 - 21 is essential in sel ecting a meaningful
screen at reasonabl e cost. Devices that perform the same function may
be fabricated with different material s (e.g., al uminum l eads instead of
gol d on an integrated circuit). T he effectiveness of a screen is
material - dependent. For exampl e, the stress l evel that is effective
for gol d may be ineffective for al uminum because of the difference in
mass. T he x- ray screen is effective for gol d, but al uminum and sil icon
are transparent to x- rays. Some screens are effective for p- n- isol ated
integrated circuits but ineffective for diel ectrical l y isol ated devices.
O nl y a thorough knowl edge of the device to be screened and the effective-
ness and l imitations of the various tests can produce a useful and rel i-
abl e screening procedure.
Screening tests are particul arl y wel l suited to discrete semicon-
ductor and microel ectronic devices due to their material /process depend-
ency. MI L- ST D- 8 8 3 A forms the basis for sel ecting meaningful screening
tests for microel ectronic devices. Note that T X semiconductors are
screened and burned- in in a manner comparabl e to MI L- ST D- 8 8 3 .
T abl es 4 - 22 and 4 - 23 , reproduced from MI L- HDBK- 1 7 5 , provide a
l isting of microcircuit defects/screens and a comparison of screening
methods, respectivel y.
T he critical ity of the component part appl ication and the required
l evel of rel iabil ity has an important bearing on the stress l evel s and
number of tests that shoul d be incl uded in the overal l part screening
procedure. T he part screen procedure must al so be cost effective and
must meet time and funding constraints.
Figure 4 - 4 shows rel ative cost estimates for various part cl asses.
I t can be seen that the most cost effective screen is cl ass B of MI L-
ST D- 8 8 3 .
1 26
T abl e 4 - 21 FA I LURE MO DE DI ST RI BUT I O N FO R T RA NSI ST O RS A ND I NT EGRA T ED CI RCUI T S
Failure Mode
TI Data in ** RAC Data in %**
Transistor SSI MSI LSI MOS/LSI TTL CMOS
Metallization 6 10 18 26 7 50 25
Diffusion 10 8 12 25 13 2 9
Foreign Material
Miscellaneous 6
5
5
11
12
13
13
1
21
} }
Oxide 31 18 20 13 33 4 16
Bonding 38 14 7 4 5 13 15
Die Attach
Packaging
9 5 3 2 5 25 8
Misapplication 35 17 4 15
100 100 100 100 100 100 100
Data publ ished in the Proceedings of the I EEE, February 1 9 7 4 (C.6. Peattie, et^ aj_ .; El ements of
Device Rel iabil ity).
* *
Data suppl ied by Rel iabil ity A nal ysis Center, RA DC.
T abl e 4 - 22 MI CRO CI RCUI T DEFECT S/SCREENS
Point at Which a
Rel iabil ity- I nfl uencing
Variabl e is I ntroduced
Fail ure Mechanism Fail ure Mode
Fail ure Detection
Method
Sl ice
Preparation
Disl ocations and stacking
faul ts
Degradation of junction
characteristics
I nitial el ectrical test;
operational - l ife tests
Nonuniform resistivity Unpredictabl e component
val ues
I rregul ar surface I mproper el ectrical
performance and/or
shorts, opens, etc.
operational - l ife tests
Cracks, chips, scratches
(general handl ing damage)
O pens, possibl e shorts
in subsequent metal l i-
zation
visual (precap); thermal
cycl ing
Contamination Degradation of junction
characteristics
Visual (precap); thermal
cycl ing; high- temperature
storage; reverse bias
Passivation
Cracks and pin hol es El ectrical breakdown in
oxide l ayer between
metal l ization and sub-
strate; shorts caused
by faul ty oxide diffu-
sion mask
High- temperature storage;
thermal cycl ing; high-
vol tage test; operating- l ife
test; visual (precap)
Nonuniform thickness Low breakdown and in-
creased l eakage in the
oxide l ayer
vol tage test; operating- l ife
test; visual (precap)
Masking
Scratches, nicks,
bl emishes in the photo
mask
O pens and/or shorts Visual (precap); initial
el ectrical test
Mi sal ignment O pens and/or shorts Visual (precap); initial
el ectrical test
I rregul arities in photo-
resist patterns (l ine
widths, spaces, pinhol es)
Performance degradation
caused by parameter
drift, opens, or shorts
Visual (precap); I nitial
el ectrical test
Etching
I mproper removal of oxide O pens and/or shorts or
intermittents
Visual (precap); initial
el ectrical test; operational -
l ife test
Undercutting Shorts and/or opens in
metal l ization
el ectrical test
Spotting (etch spl ash) Potential shorts Visual (precap); thermal
storage; operational - l ife
test
Contamination (photo-
resist, chemical residue
Low breakdown; in-
creased l eakage
el ectrical test; thermal
storage; operational - l ife
test; reverse bias
Diffusions
I mproper control of
doping profil es
resul ting from unstabl e
and faul ty passive and
active components
thermal cycl ing; operational -
l ife test; initial el ec-
trical test
1 28
T abl e 4 - 22 MI CRO CI RCUI T DEFECT S/SCREENS (Page 2)
Point at Which a
Rel iabi1 i ty- I nf1 uenc i ng
Fail ure Detection
Method
Metal l ization
Scratched or smeared
metal l ization (handl ing
damage)
O pens, near opens,
shorts, near shorts
Visual (precap; thermal
cycl ing; operational - l ife
test
T hin metal l ization to
insufficient deposition
or oxide steps
O pens and/or high-
resistance intracon-
nections
operational - l ife test;
thermal cycl ing
O xide contamination-
material incompatibil ity
O pen metal l ization to
poor adhesion
thermal cycl ing; opera-
tional - l ife test
Corrosion (chemical
residue)
O pens 1 n metal l ization Visual (precap); high-
temperature storage;
tional l ife test
Misal ignment and contam-
inated contact areas
High contact resistance
or opens
el ectrical test; high-
tional - l ife test
I mproper al l oying
temperature or time
O pen metal l ization,
poor adhesion, or
shorts
high- temperature storage;
tional - l ife tests
Die
Separation
I mproper die separation
resul ting in cracked or
chipped dice
O pens and potential
opens
Visual (precap); thermal
cycl ing; vibration; mechan-
ical shock; thermal shock
Die
Bonding
Voids between header and
die
caused by overheating
X- ray; operational - l ife;
accel eration, mechanical
shock; vibration
O verspreading and/or
l oose particl es of
eutectic sol der
Shorts or intermittent
shorts
Visual (precap); X- ray;
monitored vibration;
monitored shock
Poor die- to- header bond Cracked or l ifted die Visual (precap); accel er-
ation; shock, vibration
Material mismatch Lifted or cracked die T hermal cycl ing; high-
accel eration
Wire
Bonding
O verbonding and under-
bonding
Wire weakened and
breaks or is inter-
mittent; l ifted bond;
open
A ccel eration; shock;
vibration
Material incompatibil ity
or contaminated bonding
pad
Lifted l ead bond T hermal cycl ing; high-
accel eration, shock, vibra-
tion
Pl ague formation O pen bonds H1 gh- temperature storage;
thermal cycl ing; accel era-
tion, shock, vibration
I nsufficient bonding pad
area or spacings
O pens or shorted bonds O perational - l ife test;
accel eration, shock,
vibration; visual (precap)
1 29
T abl e 4 - 22 MI CRO CI RCUI T DEFECT S/SCREENS (Page 3 )
Point at Which a
Rel iabi1 i ty- I nfl uencing
Fail ure Detection
Method
Wire
Bonding
(continued)
I mproper bonding pro-
cedure or control
O pens, shorts, or
intermittent operation
el ectrical test; accel era-
I mproper bond al ignment O pen and/or shorts Visual (precap); initial
el ectrical test
Cracked or chipped die O pen Visual (precap); high-
temperature storage; thermal
cycl ing; accel eration, shock,
vibration
Excessive l oops, sags, or
l ead l ength
Shorts to case, sub-
strate, or other l eads
Visual (precap); X- ray;
accel eration, shock,
vibration
Nicks, cuts, and abra-
sions on l eads
Broken l eads causing
opens or shorts
Visual (precap); accel era-
Unremoved pigtail s Shorts or intermittent
shorts
Visual (precap); accel era-
tion, shock, vibration,
X- ray
Final
Seal
Poor hermetic seal Performance degradation;
shorts or opens caused
by chemical corrosion
or moisture
Leak tests
I ncorrect atmosphere
seal ed in package
caused by inversion and
channel ing
O perational - l ife test;
reverse bias; high- tempera-
ture storage, thermal
cycl ing
Broken or bent external
l eads
O pen circuit Visual ; l ead fatigue tests
Cracks, voids in kovar-
to- gl ass seal s
Shorts and/or opens in
the metal l ization
caused by a l eak
Leak test; el ectrical test;
high- temperature storage;
vol tage test
El ectrol ytic growth of
metal s or metal l ic com-
pounds across gl ass seal s
between l eads and metal
case
I ntermittent shorts Low- vol tage test
Loose conducting par-
ticl es in package
I ntermittent shorts A ccel eration; monitored
vibration; X- ray; monitored
shock
I mproper marking Compl etel y inoperative El ectrical test
1 3 0
T abl e 4 - 23 CO MPA RI SO N O F SCREENI NG MET HO DS
Screen Defects Effectiveness Cost Comments
I nterval visual Lead dress I nexpensive T his is a mandatory screen for high-
inspection Metal l ization
O xide
Particl e
Die bond
Wire bond
Contamination
Corrosion
Substrate
to moderate rel iabil ity devices. Cost wil l depend
upon the depth of the visual inspection.
I nfrared Design (thermal ) êry good Expensive For use in design eval uation onl y.
X- Ray Die bond Excel l ent Moderate T he advantage of this screen is that
Lead dress (gol d) Good the die- to- header bond can be examined
Particl e Good and some inspection can be performed
Manufacturing Good after encapsul ation. However, some
(gross errors) material s are transparent to X- rays
Seal Good (i.e., A l and Si) and the cost may be
Package Good as high as six times that of visual
Contamination Good inspection, depending upon the com-
pl exity of the test system.
High temperature El ectrical (sta- Good Very T his is a highl y desirabl e screen.
storage bil ity)
Metal l ization
Bul k sil icon
Corrosion
inexpensive
T emperature Package Good Very T his screen may be one of the most
cycl ing Seal
Die bond
Wire bond
Cracked substrate
T hermal mismatch
inexpensive effective for al uminum l ead systems.
T hermal shock Package
Seal
Die bond
Good I nexpensive T his screen is simil ar to temperature
cycl ing but induces higher stress
l evel s. A s a screen it is probabl y no
better than temperature cycl ing. Wire bond
Cracked substrate
T hermal mismatch
Constant Lead dress Good Moderate A t 20 , 0 0 0 - 0 stress l evel s, the effec-
accel eration Die bond
Wire bond
Cracked substrate
tiveness of this screen for al uminum is
questionabl e.
Shock Lead dress Poor Moderate T he drop- shock test is considered
(unmonitored) inferior to constant accel eration.
However, the pneupactor shock test may
be more effective. Shock tests may be
destructive.
Shock Particl es Poor Expensive Visual or X- ray inspection is preferred
(monitored) I ntermittent short
I ntermittent open
Fair
Fair
for particl e detection.
Vibration Lead dress Poor Expensive T his test may be destructive. Except
fatigue Package
Die bond
Wire bond
Cracked substrate
for work hardening, it is without
merit.
Vibration vari- Package Fair Expensive
abl e frequency Die bond
(unmonitored) Wire bond
Substrate
Vibration vari- Particl es Fair yery T he effectiveness of this screen for
abl e frequency Lead dress Good expensive detecting particl es is part- dependent.
(monitored) I ntermittent open Good
1 3 1
T abl e 4 - 23 CO MPA RI SO N O F SCREENI NG MET HO DS (Continued)
Screen Defects Effectiveness Cost Comments
Random vibration
(unmonitored)
Package
Die bond
Wire bond
Substrate
Good Expensive T his is a better screen than VVF
(unmonitored) especial l y for space-
l aunch equipment, but it is more
expensive.
Random vibration
(monitored)
Particl es
Lead dress
I ntermittent open
Fair
Good
Good
Very
expensive
T his is one of the most expensive
screens; when combined with onl y fair
effectiveness for particl e detection,
it is not recommended except in very
special situations.
Hel ium l eak test Package
Seal s
Good Moderate T his screen is effective for
detecting l eaks in the range of
1 0 "
8
to 1 0 "
1 0
A ttm cc/sec.
1 Radifl o l eak
test
Package
Seal s
Good Moderate T his screen is effective for l eaks in
the range of 1 0 "
8
to 1 0 ~
1 2
A ttm cc/sec.
Nitrogen bomb
test
Package
Seal s
Good I nexpensive T his test is effective for detecting
l eaks between the gross- and- fine- l eak-
detection ranges.
Gross- l eak test Package
Seal s
Good I nexpensive Effectiveness is vol ume- dependent.
Detects l eaks greater than
1 0 A ttm cc/sec.
High- vol tage
test
O xide Good I nexpensive Effectiveness is fabrication dependent.
I sol ation
resistance
Lead dress
Metal l ization
Contamination
Fair I nexpensive
I ntermittent
operation l ife
Metal l ization
Bul k sil icon
O xide
I nversion/
channel ing
Design
Parameter drift
Contamination
Good Expensive Probabl y no better than ac operating
l ife.
A c operating
l ife
Metal l ization
Bul k sil icon
O xide
I nversion/
channel ing
Design
Parameter
Contamination
Very good Expensive
Dc operating
l ife
Essential l y the
same as intermit-
tent l ife.
Good Expensive No mechanisms are activated that coul d
not be better activated by ac l ife
tests.
High- temperature
ac operating
l ife
Same as ac
operating l ife
Excel l ent Very
expensive
T emperature acts to accel erate fail ure
mechanisms. T his is probabl y the most
expensive screen and one of the most
effective.
High- temperature
reverse bias
I nversion/
channel ing
Poor Expensive
1 3 2
I Commerciol
_ MIL-STD883
Class C
2 3 4
Relative COST
__ Captive
5 Line
Fig. 4-4 SCREEN IN G EF F ECT IV EN ESS
T able 4-24 li sts all th e requi red screens f or classes A, B and C of
MIL-ST D-8 8 3, Meth od 5 004. (N ote th at a burn-i n test i s requi red f or
classes A and B only. ) T h e ef f ecti veness of th ese screens i s sh own i n
T able 4-25 . F i nally, th e cost ranges of screeni ng tests f or class B
devi ces are li sted i n T able 4-26 .
T able 4-24 SCREEN IN G SEQ UEN CE - MET H OD 5 004 - MIL-ST D-8 8 3
Reli abi li ty Classes
Screen A B C
Internal V i sual Condi ti on A Condi ti on B Condi ti on B
Stabi li zati on Bake 24 h 24 h 24 h
T h ermal Sh ock 15 cycles and 15 cycles or 15 cycles or
T emperature Cycle 10 cycles 10 cycles 10 cycles
Mech ani cal Sh ock 20,000 g no no
Centri f uge 30,000 g 30,000 g 30,000 g
H ermeti ci ty yes yes yes
Cri ti cal Electri cal
Parameters
yes no no
Burn-i n 16 8 + 72 h 16 8 h no
F i nal Electri cal yes yes yes
X-Ray Radi ograph yes no no
Ex ternal V i sual yes yes yes
133
T abl e 4 - 25 FA LLO UT FRO M MI L- ST D- 8 8 3 T EST S
21
Screen A verage % Fal l out Range (%)
Precap Visual 1 5 2.0 - 4 5
Hermeticity 5 0 .1 - 1 0
Burn- in 3 0 .1 - 20
El ectrical T esting 5 1 .3 - 1 2
External Visual 4 0 .1 - 8
T abl e 4 - 26 SCREENI NG T EST CO ST S FO R CLA SS B DEVI CES
21
MI L- ST D- 8 8 3 Method Min. T ypical ($ ) Max.
1 ) Precap Visual I nspection
Condition B
0 .1 5 0 .25 3 .0 0
2) High- T emperature Storage 0 .0 1 0 .0 5 0 .1 0
3 ) T emperature Cycl ing 0 .0 5 0 .1 0 0 .1 0
4 ) Constant A ccel eration 0 .0 5 0 .1 0 0 .25
5 ) Fine Leak 0 .0 5 0 .1 0 0 .25
6) Gross Leak 0 .0 5 0 .1 0 0 .20
7 ) Burn- in 0 .25 0 .5 0 5 .0 0
8 ) Final El ectrical
T otal Cl ass B
0 .25
0 .8 6
0 .5 0
1 .7 0
2.0 0
1 0 .9 0
Note that T abl e 4 - 26 covering screening costs is provided for com-
parative purposes onl y. I ts intent is to il l ustrate rel ative cost
differences (up to 20 to 1 ) for screening tests on devices of varying
compl exity. For a simpl e integrated circuit l ogic gate, screening tests
wil l be l ower. For LSI devices, the cost wil l approach the maximum
indicated.
1 3 4
4 .1 .2 Derating
T he guidel ines in the preceding section on parts sel ection and
control assume that the parts are inherentl y rel iabl e and capabl e of
withstanding the stresses to which they wil l be submitted.
A dditional improvement in part and, ul timatel y, equipment rel iabil ity
can be real ized by appl ying the techniques of derating. Derating can be
defined as the operation of a part at l ess severe stresses than those
for which it is rated. I n practice, derating can be accompl ished by
either reducing stresses or by increasing the strength of the part.
Sel ecting a part of greater strength is usual l y the most practical
approach.
Derating is effective because the fail ure rate of most parts tends
to decrease as the appl ied stress l evel s are decreased bel ow the rated
val ue. T he reverse is al so true: the fail ure rate increases when a
part is subjected to higher stresses and temperature. T he fail ure rate
model of most parts is stress and temperature dependent. T his depend-
ence is discussed more ful l y in the subsection fol l owing (4 .1 .2.1 ).
Specific derating criteria are given in subsection 4 .1 .2.2.
4 .1 .2.1 T emperature- Stress Factors
T he temperature- stress effect can best be observed by studying
MI L- HDBK- 21 7 B fail ure rate model s. T he parts fail ure rate model (dis-
cussed in Section 2.1 .3 ) for discrete semiconductors is expressed as
fol l ows:
x
p "
x
b^ E
X7 T
A
X7 T
S2
Xl T
C
X7 T
Q^
where
A is the part fail ure rate
A . is the base fail ure rate
* E
Environmentaccounts for infl uence of environmental factors
other than temperature. (See T abl e 2- 1 , Section 2.1 .3 .)
T T Q Qual ityaccounts for effects of different qual ity l evel s
7 T A ppl icationaccounts for effect of appl ication in terms of
circuit function
1 3 5
Tip Complexityaccounts for effect of multiple devices in a single
package
TT
S2
Voltage Stressadjusts model for a second electrical stress
(application voltage) in addition to wattage included within
V-
T he equation for the base fail ure rate, A . , is:
X
= A exD

NT
,
v
exp 27 3 + T + (A T )S
A
b
Mexp
27 3 + T + (A T )S
exp
T
M
where
A is a fail ure rate scal ing factor.
Ny, T
M
and P are shaping parameters.
T is the operating temperature in degrees C, ambient or case, as
appl icabl e.
A T is the difference between maximum al l owabl e temperature with no
junction current or power (total derating) and the maximum
al l owabl e temperature with ful l rated junction current or power.
S is the stress ratio of operating el ectrical stress to rated
el ectrical stress.
T he val ues for the shaping parameters and constraints are shown in
T abl e 4 - 27 (taken from MI L- HDBK- 21 7 B). T he resul ting base fail ure rate
(A . ) for a SI , NPN transistor is shown in T abl e 4 - 28 al so taken from
MI L- HDBK- 21 7 B. Figure 4 - 5 is derived from T abl e 4 - 28 . I t is evident
that the onl y variabl es of the equation for the base fail ure rate (A .)
are T ; the operating temperature, A T , the difference between maximum
temperatures in de- energized and energized state and S, the el ectrical
stress ratio.
T abl e 4 - 28 and Figure 4 - 5 show how A . varies with temperature and
stress. T he data presented is based on the typical maximum junction
temperature of 1 7 5 C (ful l y derated) and 25 C for the maximum tempera-
ture at which ful l rated operation is permitted.
1 3 6
T abl e 4 - 27 DI SCRET E SEMI CO NDUCT O R BA SE FA I LURE RA T E PA RA MET ERS
Group
Part T ype
X
b
Constants
A N
T
T
M
P T
T ransistors
I
I I
I I I
Si, NPN
Si, PNP
Ge, PNP
Ge, NPN
0 .1 3
0 .4 5
6.5
21 .0
- 1 0 5 2
- 1 3 24
- 21 4 2
- 2221
4 4 8
4 4 8
3 7 3
3 7 3
1 0 .5
1 4 .2
20 .8
1 9 .0
1 5 0
1 5 0
7 5
7 5
FET 0 .5 2 - 1 1 62 4 4 8 1 3 .8 1 5 0
Unijunction 3 .1 2 - 1 7 7 9 4 4 8 1 3 .8 1 5 0
Diodes
I V
V
VI
VI I
VI I I
Si, Gen. Purpose
Ge, Gen. Purpose
0 .9
1 26
- 21 3 8
- 3 5 68
4 4 8
3 7 3
1 7 .7
22.5
1 5 0
7 5
Zener/A val anche 0 .0 4 - 8 0 0 4 4 8 1 4 1 5 0
T hyristors 0 .8 2 - 20 5 0 4 4 8 9 .5 1 5 0
Microwave
Ge, Detectors
Si, Detectors
Ge, Mixers
Si, Mixers
0 .3 3
0 .1 4
0 .5 6
0 .1 9
- 4 7 7
- 3 9 2
- 4 7 7
- 3 9 4
3 4 3
4 23
3 4 3
4 23
1 5 .6
1 6.6
1 5 .6
1 5 .6
4 5
1 25
4 5
1 25
Varactor,
Step Recovery &
T unnel
0 .9 3 - 1 1 62 4 4 8 1 3 .8 1 5 0
1 3 7
T abl e 4 - 28 BA SE FA I LURE RA T ES FO R GRO UP 1 T RA NSI ST O RS
(SI LI CO N, NPN)
T
(C)
S
0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1 .0
0
1 0
20
25
3 0
4 0
5 0
0 .0 0 3 4
0 .0 0 3 8
0 .0 0 4 3
0 .0 0 4 6
0 .0 0 4 0
0 .0 0 5 4
0 .0 0 60
0 .0 0 4 1
0 .0 0 4 6
0 .0 0 5 1
0 .0 0 5 4
0 .0 0 5 7
0 .0 0 64
0 .0 0 7 1
0 .0 0 4 8
0 .0 0 5 4
0 .0 0 60
0 .0 0 64
0 .0 0 67
0 .0 0 7 5
0 .0 0 8 4
0 .0 0 5 7
0 .0 0 64
0 .0 0 7 1
0 .0 0 7 5
0 .0 0 7 9
0 .0 0 0 9
0 .0 1 0
0 .0 0 67
0 .0 0 7 5
0 .0 0 8 4
0 .0 0 8 9
0 .0 0 9 6
0 .0 1 0
0 .0 1 2
0 .0 0 7 9
0 .0 0 8 9
0 .0 1 0
0 .0 1 0
0 .0 1 1
0 .0 1 3
0 .0 1 5
0 .0 0 9 5
0 .0 1 0
0 .0 1 2
0 .0 1 3
0 .0 1 4
0 .0 1 7
0 .0 20
0 .0 1 1
0 .0 1 3
0 .0 1 5
0 .0 1 7
0 .0 1 8
0 .0 23
0 .0 29
0 .0 1 4
0 .0 1 7
0 .0 20
0 .0 23
0 .0 25
0 .0 3 3
0 .0 1 8
0 .0 23
0 .0 29
0 .0 3 3
5 5
60
65
0 .0 0 64
0 .0 0 67
0 .0 0 7 1
0 .0 0 7 5
0 .0 0 7 9
0 .0 0 8 4
0 .0 0 8 9
0 .0 0 9 5
0 .0 1 0
0 .0 1 0
0 .0 1 1
0 .0 1 2
0 .0 1 3
0 .0 1 4
0 .0 1 5
0 .0 1 7
0 .0 1 8
0 .0 20
0 .0 23
0 .0 25
0 .0 29
0 .0 3 3
7 0
7 5
8 0
0 .0 0 7 5
0 .0 0 7 9
0 .0 0 8 4
0 .0 0 8 9
0 .0 0 9 5
0 .0 1 0
0 .0 1 0
0 .0 1 1
0 .0 1 2
0 .0 1 8
0 .0 1 4
0 .0 1 5
0 .0 1 7
0 .0 1 8
0 .0 20
0 .0 23
0 .0 25
0 .0 29
0 .0 3 3
8 5
9 0
9 5
0 .0 0 8 9
0 .0 0 9 5
0 .0 1 0
0 .0 1 0
0 .0 1 1
0 .0 1 2
0 .0 1 3
0 .0 1 4
0 .0 1 5
0 .0 1 7
0 .0 1 8
0 .0 20
0 .0 23
0 .0 25
0 .0 29
0 .0 3 3
1 0 0
1 0 5
1 1 0
0 .0 1 0
o: on
0 .0 1 2
0 .0 1 3
0 .0 1 6
0 .0 1 3
0 .0 1 7
0 .0 1 8
0 .0 20
0 .0 23
0 .0 25
0 .0 29
0 .0 3 3
1 1 5
1 20
1 25
0 .0 1 3
0 .0 1 4
0 .0 1 5
0 .0 1 7
0 .0 1 0
0 .0 20
0 .0 23
0 .0 25
0 .0 29
0 .0 3 3
1 3 0
1 3 5
1 4 0
0 .0 1 7
0 .0 1 8
0 .0 20
0 .0 23
0 .0 25
0 .0 29
0 .0 3 3
1 4 5
1 5 0
1 5 5
0 .0 23
0 .0 25
0 .0 29
0 .0 3 3
1 60 0 .0 3 3
.0 3 4
r
.0 3 0 -
1 0 .9 .8 .7 .6 .5 .4 .3 2 .|
10 20 40 60 80 100 120 140 160 180
Temp CO
Fig. 4-5 Stress/Temperature Plot For Group I Transistor (Silicon, NPN)
138
T he data show that at higher temperatures ( 1 0 0 C) and at el ectrical
stress higher than 4 0 % (even at l ower temperatures) the sl opes of the
curves (and the fail ure rate) increase drastical l y.
Since semiconductors as wel l as most el ectronic parts are sensitive
to temperature, the thermal anal ysis of any design shoul d accuratel y
provide the ambient temperatures needed for proper appl ication of the
part. O f course, l ower temperatures produce better rel iabil ity but can
al so produce increased penal ities in terms of added l oads (or constraints)
on control l ing the system's environment. T he thermal anal ysis shoul d be
part of the design process and incl uded in al l the tradeoff studies
covering equipment performance, rel iabil ity, weight, vol ume, environ-
mental control requirements, and above al l , cost.
Derating procedures vary with different types of parts and their
appl ication. Resistors are derated by decreasing the ratio of operating
power to rated power. Capacitors are derated by maintaining the appl ied
vol tage at a l ower val ue than the vol tage for which the part is rated.
Semiconductors are derated by keeping the power dissipation bel ow the
rated l evel .
T he first step in the procedure for derating el ectronic parts in-
vol ves the use of derating curves, which usual l y rel ate derating l evel s
to some critical environmental or physical factor. Such curves are
typical l y incl uded in the part specification. A typical derating curve
for semiconductors is shown in Figure 4 - 6.
o
UJ
<
(r
Q.
1.0
d .5 -
<
ID
\-
O
<
0-
Fig
Maximum Use
Rating
Ts
T
A
0r

T
C
T
max
4-6 TYPICAL DERATING GRAPH
139
I n Figure 4 - 6,
T <* is the temperature derating point (usual l y 25 C)
T
MA X
is

the

maximum
Junction temperature
T is the ambient temperature
T
c
is the case temperature.
Maximum junction temperature (T ^ ny) is normal l y 1 7 5 C for sil icon and
1 0 0 C for germanium devices. A l though usual l y 25 C, T
$
can be other
val ues of temperature.
T his conventional derating approach makes the approximate assumption
that the thermal resistance, e, from ambient or case to junction is a
constant, and that the junction temperature is:
W
e
JA
P
J
or
T
J
=

T
C
+

9
JC
P
J
where
T .
T
A
T
C
6
JA
s junction temperature
s ambient temperature
s case temperature
s thermal resistance (ambient to junction, C per watt)
o,
8 , p is thermal resistance (case to junction, C per watt)
Pj is power (watts) dissipated at junction.
T hese equations indicate that operation anywhere al ong the derating l ine
between T <. and T ^ wil l resul t in a junction temperature equal to T ^
A X
and that the thermal resistance (e) is constant at a val ue:
fl

T
MA X"
T
S o
r
, ..
6 = n C/watt
(rating)
where
P/ .. % is power rating (watts) at temperature T c-
1 4 0
T h i s assumpti on of constant th ermal resi stance i s approx i mate. F or
many common transi stors, th e assumpti on i s close and conservati ve because
th ei r actual th ermal resi stance h as only a sli gh tly negati ve slope as a
f uncti on of th e temperature of th e bulk semi conductor materi al. An actual
curve of constant juncti on temperature f or th ese devi ces resembles
F i gure 4-7.
max
Fig . 4 - 7 A CT UA L CO NST A NT JUNCT I O N T EMPERA T URE CURVE
As sh own i n F i gure 4-7, i f th e curvature of T , = T . ^ curve i s
large, th en th e assumpti on of th e dotted strai gh t li ne can lead to
appreci able error. T h e f act th at th e curvature of T , = T ^ can be
di f f erent f or th e two cases of ref erenci ng e
1A
or e
i r
i s one reason wh y
di f f erences may be obtai ned i n usi ng th ese two rati ngs i n predi cti on
computati ons.
T h i s assumpti on error may be very large f or some devi ces. T h i s i s
recogni zed by suppli ers wh o speci f y a multi poi nt derati ng curve to
approx i mate, more closely, th e ex treme curvature i n th e constant
curve. An ex ample i s th e derati ng curve f or th e 1N 326 3 power T , = T
MAX
di ode, F i gure 4-8 , wh ere th e th ree rati ng poi nts are 16 0 amps at 125 C,
120 amps at 15 0C, 0 amps at 175 C. As sh own i n F i gure 4-8 , th e two
poi nt li near derati ng assumpti on f rom 16 0 amps at 125 C would h ave
resulted i n an 8 0 amps rati ng at 15 0C i nstead of th e actual rati ng of
120 amps. T h i s would h ave caused a th i rd or more of th e devi ce capabi li ty
to be wasted at 15 0C.
141
T
S
T
SI
T
max
a) in
^ a.
<
0)
160
120
80
40
V
A
\
\\
\
\\
A
\
N
50
c
I00
e
150* 200
Case Temp C
Fig. 4-8 MULTIPOINT DERATING CURVE FOR IN3263 POWER DIODE
O ccasional l y in the Mil itary Specifications, the derating instruc-
tions are presented as notes rel ative to the maximum ratings. T he sl ash
sheets appended to MI L- S- 1 9 5 0 0 contain numerous exampl es of derating
instructions for discrete semiconductor devices.
4 .1 .2.2 Specific Derating Guidel ines
T his subsection provides specific guidel ines for derating component
parts used in el ectronic equipment. I n general , guidel ines and graphic
presentation of acceptabl e part operation are given for the environmental
cl asses covering ground, airborne and space appl ications.
T hese guidel ines represent a composite summary of derating pol icies
empl oyed presentl y by firms within the el ectronic I ndustry who special ize
in mil itary appl ications. T he derating criteria for resistors, capaci-
tors and semiconductors are presented in graphic format and incl ude
parametric restrictions for both stress ratios and case temperatures.
T he derating criteria for microcircuits, inductive devices, rel ays and
connectors are presented in tabul ar format. T he graphs show three basic
derating regions which are defined as fol l ows:
1 4 2
A A cceptabl ethe most rel iabil ity/cost effective region
providing the optimum margin of safety. Usage of parts
in this region is recommended. No rel iabil ity degradation
is expected.
Q Questionabl e- - the region in which the devices are operated
within their ratings but are not optimum with respect to
rel iabil ity. Long term rel iabil ity can be degraded. T he
designer shoul d consul t with the rel iabil ity or component
engineer regarding part appl ication.
R Restrictedthe region in which the device ratings are
exceeded. Do not use; part overstressed.
I n addition to providing an adequate margin of safety, Region A refl ects
cost/effectiveness precepts. A s a general rul e, the specific derating
guidel ines (Region A ) shoul d not be conservative to the point where costs
rise excessivel y (e.g., higher than necessary part ratings are sel ected).
Neither shoul d the derating criteria be so l oose as to render rel iabl e
part appl ication ineffective. O ptimum derating occurs at or bel ow the
point on the stress/temperature curve where a rapid increase in fail ure
rate is noted for a smal l increase in temperature or stress. T his may be
visual ized by referring to Figure 4 - 5 (when considering a sil icon NPN
transistor) presented in the preceding subsection.
Consider that the transistor is used at 5 5 C ambient temperature
rated for 5 0 0 mW at 25 C and used at two different stress l evel s
4 0 0 mW = 8 0 % and 20 0 mW = 4 0 %. Referring to Figure 4 - 5 , at a stress of 8 0 %
and a temperature of 5 5 C, the fail ure rate A
b
is 0 .3 3 x1 0 " . I t can
al so be seen that 8 0 % stress or 4 0 0 mW is the maximum al l owabl e power
dissipation at 5 5 C for this transistor. I f, however, the transistor is
stressed onl y 4 0 % at 5 5 C, the fail ure rate A , decreases drastical l y to
0 .0 1 0 x1 0 " . A considerabl e rel iabil ity improvement of 3 .3 to 1 has been
achieved.
T abl e 4 - 29 and Figures 4 - 9 through 4 - 1 1 present the derating guide-
l ines for microcircuits. Figures 4 - 1 2 through 4 - 1 6 give the derating
guidel ines for semiconductors. Figure 4 - 1 7 through 4 - 20 show the derating
guidel ines for resistors. Figure 4 - 21 through 4 - 3 0 show the derating
1 4 3
T abl e 4 - 29 MI CRO ELECT RO NI C DEVI CE DERA T I NG CHA RT
1
Power Supply Voltage(s) - Use power supply voltage at parameter
guarantee level which is derated from absolute maximum ratings.
Output Current (Load, Fan-Out) - Derate to 80% of maximum
allowable.
Input Voltage - Logic - Derate to same voltage level as noted
above for supply voltage(s).
Input Voltage - Linear - Derate to 70% of absolute maximum
rating.
T
J
=

T
A
+e
JA
(P
D>
T
C
=
V
e
JC
(r
V
For: Digital Logic Device Application
=
W^PDH
v

(I

xV
j
K
D 2
xv
cc
u
0L
XV
0L
;
where
P
n
is the actual power dissipated in the circuit appl ica-
tion and is the product of the actual measured
cal cul ated vol tage and current.
I
Dn
. is the actual suppl y current drain with inputs in
KUL
l ogic " 0 " state.
I
pnH
is the actual suppl y current drain with inputs in
KUM
l ogic " 1 " state.
V is the actual power suppl y vol tage.
I
n|
is the actual output l ogic " 0 " state sink currents.
V
0 |
is the actual l ogic state " 0 " output vol tage.
For: Linear Device A ppl ication
P
D
=

V
S
XI
IS
+V
;
XI
;
S
where
I
Q<;
is the actual suppl y current ( + ).
1 4 4
V is the actual suppl y vol tage (+ )
GROUND APPLICATION
i .u
.8
I_I_I.6
mmm
_ ,_.
R

.4 \
YJ
=,25T
ft ~V =7E
5 -
2
A
_. ..^
v- At-
A _t-
A I RBO RNE A PPLI CA T I O N
0 4 0 8 0 1 20 1 60
T EMP C
on
Li J
OH
h -
1 .0
.8
J
: .6
.4
.2
R
MM
T
,r
12!
C
q
A V =
75 '
l\
\
v
\
0 4 0 8 0 1 20 1 60
T EMP C
ELECT RI CA L ST RESS
VERSUS T EMPERA T URE
DERA T I NG REGI O NS
A . A cceptabl e
Q. Questionabl e
R. Restricted
SPACE APPLICATION
1.0 ~"
.A
R
.6 L_
- ^ \^2 i
C
2.4 \ QV
fc *V
75
\
.2 V 2.
jr V
x v
0 4 0 8 0 1 20 1 60
T EMP C
Figure 4 - 9 MI CR0 CI RCUI T , MA X O PERA T I NG JUNCT I O N T EMP, 1 25 C
1 4 5
1 .0
GRO UND A PPLI CA T I O N
.8
R
.6
LU
_l
Q
OO
OO A
LU .H
Vl
1 5 0
J
c
OC
\
OO
A Yr
= c
, 1
a o
u
c
.2
1 .0
.8
R
d .6
\
>
LU
_J
Q
V
oo . 4 \V
1 5 ( c
LU
or
F
A T
. ,
= 9 0 * \~
oo
.2
L
\
\
>
S,
0 4 0 8 0 1 20 1 60
T EMP C
0 4 0 8 0 1 20 1 60
T EMP C
1 .0
SPA CE A PPLI CA T I O N
.6
oo
oo
OH
I
oo
.4
.2
R
Q
v = 1 5 oc
V
A = 9 ( c
\
0 4 0 8 0 1 20 1 60
T EMP C
A . A cceptabl e
Q. Questionabl e
R. Restricted
Figure 4 - 1 0 MI CR0 CI RCUI T , MA X O PERA T I NG JUNCT I O N T EMP, 1 5 0 C
1 4 6
GROUND APPLICATION
1 .0
.8
JJ . 6
UJ
i
00 . 4
UJ
OH
H
CO
.2
R
T
l
= 17 5
U
C
q
A
T =
10^ V
4 0 8 0 1 20 1 60
T EMP C
1.0
AIRBORNE APPLICATION
.8
R
LAJ .6
V
17! C
UJ
I Q
co A \
OH
A
V
T
i!
=10! ;c
.2
XJ
4 0 8 0 1 20 1 60
T EMP C
A. Acceptable
Q. Questionabl e
R. Restricted
1 .0
.8
-j
UJ
uj . 6
_
CO
CO
cc . 4
I-
co
.2
R
Q T
,
= 17! i
U
C
A T = 10 fi
0 4 0 8 0 1 20 1 60
T EMP C
Figure 4 - 1 1 MI CR0 CI RCUI T , MA X O PERA T I NG JUNCT I O N T EMP, 1 7 5 C
1 4 7
GRO UND A PPLI CA T I O N A I RBO RNE A PPLI CA T I O N
1 .0
.8
.6
oo
oo
a:
\
oo
.4
.2
R
T
j
= 10 )C
\
A\
Jf
\
c
\
\
40 80 120 160
TEMP C
1 .0
uj . 6
A
OO . 4
LU
a:
OO
.2
R
O\T j=10C C

{**
(
c
L
\
\
-_
0 4 0 8 0 1 20 1 60
T EMP C
1.0
.8
.6
oo
A
a:
oo
.2
R
Q\
T
J1
10C C
A\
Jj
1
# C
0 40 80 120 160
TEMP C
DERA T I NG
A . A cceptabl e
Q. Questionabl e
R. Restricted
NO T ES: Diodes
fi
;
PI V < 8 0 %
I
f
< 7 5 %
T ransistors
l
c - 8 0 %
t A ny Vol tage
< 9 0 %
Figure 4 - 1 2 SEMI CO NDUCT O R, MA X O PERA T I NG JUNCT I O N T EMP, 1 0 0 C
1 4 8
1.0
.8
.6
LxJ
e x . :
.2
R
1
o
ir
j
= 12 5
0
A
LI
\ T
b
*1
40 30 120 160
TENP C
1.0
.8
.6
cc
t
.4
.2
R
. * V-
Yfj
hi ;c
\
tT
A
V
= 7: > TC
\
K
0 40 80 12 0 160
TEMP C
A . A cceptabl e
Q. Questionabl e
R. Restricted
NO T ES: t Diodes
I
f
< 7 5 %
PI V8 0 %
T ransistors
I <.8 0 *
t A ny Vol tage
< 9 0 %
1.0
8
R
LU
T -1 >5
C
C
Q*
a:
A \
1 T
=
75
. 2
8 0 1 20 1 60
T EMP oc
Figure 4 - 1 3 SEMI CO NDUCT O R, MA X O PERA T I NG JUNCT I O N T EMP, 1 25 C
1 4 9
1 .0
.8
UJ . 6
co
co
& .4
CO
.2
R
Q
u
= 15 ( )C
A Vr
r
)0
4 0 8 0 1 20 1 60
T EMP C
1 .0
.6
CO
CO
UJ
A
I
co
.2
R
Q
LLI
150 C
A T
,i1
90
c
c\
0 4 0 8 0 1 20 1 60
T EMP C
1 .0
.8
:.6
CO
CO
LU A
CO
.2
R
\
Q
\h
= 15 o
u
c
A 90
l
c
0 4 0 8 0 1 20 1 60
T EMP C
A . A cceptabl e
0 . Questionabl e
R. Restricted
NO T ES: t Diodes
I
f
< 7 5 %
PI V < 8 0 %
t T ransistors
I < 8 0 %
c
t A ny Vol tage
< 9 0 %
1 5 0
1 .0
.8
.6
in
C X . . 4
.2
|R
T
,
=

17
P
C
Q
A
sf
105 \
1
4 0 8 0 1 20 1 60
T EMP C
1.0
8
R
[- i
UJ
S 6
T
J=
175 Pc
_i
Q

A
Li
iofc
.2

0 4 0 8 0 1 20 1 60
T EMP C
A . A cceptabl e
Q. Questionabl e
R. Restricted
NO T ES: t Diodes
I
f
<_ 7 5 %
PI Vl 8 0 %
t T ransistors
I
c
8 0 %
ff A ny Vol tage
< 9 0 % "
1 .0
.8
^ -i . 6
UJ
.4
.2
R
Q
h'
17 C
A
Tj
109 c^
0 4 0 8 0 1 20 1 60
T EMP C
1 5 1
1 .0
.8
UJ
co
J
on
co
.6
.4
.2
R
i .
=
20 C
D
C
Q
V
1 2C
c
A
4 0 8 0
T EMP C
1 20 1 60
1 .0
.8
.6
oo
LU 4
CO
.2
R
ij
= 20 ( C
Q
V
0 2dC
A
4 0 8 0 1 20 1 60
T EMP C
1 .0
.8
R
LU
>
LU C
= 2 )0
CO
CO Q
LU
T ,
:1 1 )
CO
A
.2
4 0 8 0
T EMP C
1 20 1 60
A . A cceptabl e
0 . Questionabl e
R. Restricted
NO T ES: Diodes
I
f
< 7 5 %
PI V < 8 0 %
T ransistors
I < 8 0 %
c
A ny Vol tage
< 9 0 %
Figure 4 - 1 6 SEMI CO NDUCT O R, MA X O PERA T I NG JUNCT I O N T EMP, 20 0 C
1 5 2
1 .0
.8
_i
UJ
3 .6
CO
CO
^ A
.4
CO
.2
R

Q
,
A
V
0 4 0 8 0 1 20 1 60
T EMP C
1 .0
.8
uj . 6
i
CO
CO
Cd . 4
co
.2
R
q
V
\
\
A
1
\
0 4 0 8 0
T EMP C
1 20 1 60
A . A cceptabl e
Q. Questionabl e
R. Restricted
NO T E: Peak Vol tage and
Current Shal l Not
Exceed 7 5 % of Rated
Val ues
CO
CO
en
co
SPACE APPLICATION
.0
.8
R
.6
Q
\
.4
v
.2
A
>
L
\
1
8 0 1 20 1 60
T EMP C
Figure 4 - 1 7 RESI ST O R, FI XED, CA RBO N CO MPO SI T I O N (RCR)
1 5 3
1.0
GROUND APPLICATION
.8
LxJ
R
B.6 Q
GO
LU
.4
00
A
I
.2
\
4 0 8 0
T EMP C
1 20 1 60
1 .0
.6
GO
GO
J
.4
GO
.2
R
V
Q
\
A
\ ;
\
4 0 8 0
T EMP C
1 20 1 60
I.U
.8
LxJ
S-6
_J
GO
GO
LU A
\-
OO
R

i
Q
V
\
.2 A \
1
0 4 0 8 0 1 20 1 60
T EMP C
A . A cceptabl e
Q. Questionable
R. Restricted
NO T ES: t Peak Power
Not to Ex-
ceed Rated
Power
t A ppl ied Vol -
tage Not to
Exceed 7 5%
of Rating
Figure 4 - 1 8 RESI ST O R, FI XED, MET A LFI LM (RLR, RNR)
1 5 4
1 .0
00
A
u~ ) 4
LU *
co
.2
R
Q
A
4 0 8 0
T EMP C
1 20 1 60
1 .0
^ . 6
CO
co 4
LU '
en
\
.2
R
Q
A
0 4 0 8 0 1 20 1 60
T EMP C
A . A cceptabl e
Q. Questionabl e
R. Restricted
NO T ES: t Peak Power Not
LU
to Exceed Rated
>
LU
Power
-J
CO
A ppl ied Vol tage
CO
LU
Not to Exceed
CCL
7 5 % of Rating
CO
1 .0
, 8
.6
.4
R
Q
A
0 4 0 8 0 1 20 1 60
T EMP C
Figure 4 - 1 9 RESI ST O R, PO WER, WI REWO UND (RER, RWR)
1 5 5
GO
LU
CC
I
GO
f
.8 Q X_ R
~ V
6
s X
5 4
.4 A j

i
t
L
0 4 0 8 0 1 20 1 60
T EMP C
1 , 0
.8
;.6
CO
oo
on
oo
,4
.2
I
R
Q
I
1
1
A
40 80
TEMP C
12 0 160
1 .0
.8
.6
oo
LU . 4
Cd
. 2
R
Q
\
I
\
l
A
0 4 0 8 0 1 20 1 60
T EMP C
A . A cceptabl e
Q. Questionabl e
R. Restricted
NO T ES: t Peak Power Not
to Exceed
Rated Power
A ppl ied Vol tage
Not to Exceed
7 5 % of Rating
Figure 4 - 20 RESI ST O R, PRECI SI O N, WI REBO UND (RBR)
1 5 6
1 .0
I/O . 4
.2
Q
R
A
0 4 0 8 0
T EMP C
1 20 1 60
1 .0
.8
.6
OO
GO
.4
en
00
.2
Q
R
A
4 0 8 0 1 20 1 60
T EMP C
A . A cceptabl e
Q. Questionabl e
R. Restricted
1 .0
.8
S.6
to
en
oo
.4
.2
T EMP C
Figure 4 - 21 CA PA CI T O R, MI CA (CM)
4 0 8 0 1 20 I bO I
1 5 7
.8
[
1
i
UJ
uj .6 \
R
OO
1
^
oo
.4
A
1
oo
.2
0 4 0 8 0 1 20 1 60
T EMP C
.8 Q
_i
tu
S .6
R
_J
uo
v
00
LU A
en -
H A
\
1
oo
1
.2
0 4 0 8 0 1 20 1 60
T EMP C
1 .0
.8
_i
UJ
5 .6
OO
OO
UJ
oo
.2
1
R
V
A )
I
\
'0 80 12 0 ido
A . A cceptabl e
Q. Questionabl e
R. Restricted
T EMP C
Figure 4 - 22 CA PA CI T O R, CERA MI C, T EMP CO MPENSA T I NG
1 5 8
1 .0
.8
.6
00
OO
UJ
on
I
oo
.4
.2
Q

R
\
A
__.,
4 0 8 0 1 20 1 60
T EMP C
1 .0
.3
UJ
>
UJ
OO
oo
L
Cd
h -
OO
.6
.4
.2
Q
R
\
A
4 0 8 0 1 20 1 60
T EMP C
A . A cceptabl e
Q. Questionabl e
R. Restricted
! .U
.8
1,1)
Q
B .6
R
oo
oo
\
oo
A
.2
4 0 8 0
T EMP C
1 20 1 60
Figure 4 - 23 CA PA CI T O R, PA PER- PLA ST I C O R MET A LLI ZED
(CPV, CH) MA X T EMP, 1 25 C
1 5 9
1.0
GROUND APPLICATION
CO
J
Cd
^ -
co
.4
.2
R
C
]
p-
\
V
sj
\
0 4 0 8 0 1 20 1 60
T EMP C
1 .0
.6
CO A
UJ . f
en
oo
.2
R
Q
nv ii MI
FA 1 ^^
0 A 0 80 12 0 160
T EMP C
SPACE APPLICATK
1.0
.8
_i
u
2.6
CO
CO
en
CO
.4
.2
R
I
3
0 4 0 8 0 1 20 1 60
T EMP C
A . A cceptabl e
Q. Questionabl e
R. Restricted
Figure 4 - 24 CA PA CI T O R, A I R T RI MMER
1 60
en
\
n
8
Q
V
R
^
\
4
A
?
.
0 4 0 8 0
T EMP C
1 20 1 60
LU
>
LU
en
.0
8
Q
- u
.6
R
v
4
A
\
?
0 4 0 8 0
T EMP C
1 20 1 60
A . A cceptabl e
Q. Questionabl e
R. Restricted
LU
t/J
LU
en
I
CO
1 .0
.8
.6
.4
.2
Q
R
A
8 0 1 20 1 60
T EMP C
Figure 4 - 25 CA PA CI T O R, CERA MI C, GP, MA X T EMP, 8 5 C
1 61
1 .0
.8
.6
.4
.2
GROUND APPLICATION
Q
R
UJ
>
V
_J
UJ
_J
\
>
UJ
UJ
A
\
oo
oo
t-
\ i
]
on
1
0 4 0 8 0 1 20 1 60
T EMP C
1 .0
.8
.6
, 4
.2
Q
R
\\
1
A
\
\
0 4 0 80 120 160
T EMP C
Q
. O
Q
R
_J
UJ
> 6
Ul *
u
I
oo
.4
\J
a: * ^
I-
oo
A
\
.2
0 4 0 8 0 1 20 1 60
T EMP C
A . A cceptabl e
Q. Questionabl e
R. Restricted
Figure 4 - 26 CA PA CI T O R, CERA MI C, GP, MA X T EMP, 1 25
C
1 62
co
co
on
co
1 .0
.8
i
i
.6
.4
.2
0
R
A
0 4 0 8 0 1 20 1 60
T EMP C
1 .0
. o
.6
co
I/O
oc
\
CO
.4
.z
0
R
\
A
0 4 0 8 0 1 20 1 60
T EMP C
iPA CE A PPLI CA T I O N
A . A cceptabl e
Q. Questionabl e
R. Restricted
1 . u
.8
Q
i
> .6
R
_l
CO
CO
^ A
cc A
CO
A
2
0 40 80 120 160
TEMP C
Figure 4-27 CAPACITOR, PAPER-PLASTIC OR METALLIZED (CPV, CH)
163
1 Hi
GROUND APPLICATION
^
s.
>
sj
w
N
1
L
E
V
E
L

A
Q
R
.4
1
?
A I RBO RNE A PPLI CA T N
0 4 0 8 0
T EMP C
1 20 1 60
1 .0
.8
3 .6
CO
LU
.4
CO
.2
V
L
\
v
N
t
A
q
R
0 4 0 8 0
T EMP C
1 20 1 60
1 .0
.8
! .6
co
A
OH
co
.2
s
w
N
<
N L
S
<
A
Q
R
0 4 0 8 0 1 20 1 60
T EMPC
ELECT RI CA L ST RESS VERSUS
T EMPERA T URE DERA T I NG REGI O NS
A . A cceptabl e
Q. Questionabl e
R. Restricted
NO T E: Peak A C Vol tage Pl us DC
Vol tage Not to Exceed
Rated Vol tage.
Figure 4 - 28 CA PA CI T O R, T A NT A LUM, WET ELECT RO LYT E (CLR)
1 64
1.0
GROUND APPLICATION
^
V
.8
N
v
s
i
LU
UJ . 6
J
Q
R
A
00
W A
CCA
OO
.2
4 0 8 0 1 20 1 60
T EMP C
AIRBORNE APPLICATION
V
_>,
.0
V
LU
5 fi
I _L R
LU . 0
_J
oo
A
A
f .4
oo
.2
0 4 0 8 0 1 20 1 60
T EMP C
T EMPERA T URE DERA T I NG
REGI O NS
A . A cceptabl e
Q. Questionabl e
R. Restricted
NO T ES: Provide Series
Circuit I mpedance
> ^ 3 ohms
t Max Reverse DC
Vol tage
25 C - 5 %
8 5 C - 1 .5 %
1 25 C - 0 .5 %
t No Reverse Rippl e
Permitted
1 .0
.8
.6
oo
oo
LU
Q :
H
oo
.4
.2
rr
V
\
v
\
Q
R
A
-
4 0 8 0 1 20 1 60
T EMP C
Figure 4 - 29 CA PA CI T O R, T A NT A LUM, SO LI D (CSR)
1 65
.8
I
\
Q
L
E
V
E
L

\
R 1
A
\
oo
LU 4
l
00
.2
0 40 80 120 160
TEMP C
LU
OO
00
OO
.8
.6
V
Q
R
\
.4
A \
.2
0 4 0 8 0 1 20 1 60
T EMP C
.8
q
R 1
L
E
V
E
L

00
LU . 4
Cd
l
\
A
N
00
.2
0 4 0 8 0 1 20 1 60
T EMP C
T EMPERA T URE DERA T I NG
REGI O NS
A . A cceptabl e
Q. Questionabl e
R. Restricted
Figure 4 - 3 0 CA PA CI T O R, GLA SS (CY)
1 66
guidel ines for capacitors. T abl es 4 - 3 0 through 4 - 3 2 provide guidel ines
for other parts. Where derating information is graphical l y presented,
the figures show three basic regions of part operation which impact
rel iabil ity.
T abl e 4 - 3 0 DERA T I NG FO R CO I LS, CHO KES A ND T RA NSFO RMERS
I nductor T ype
Maximum Permissibl e
% of Manufacturer's Rating
Current
O perating
Vol tage
Maximum
A ppl i ed
T ransient
(maximum)
Coil , I nductor
Saturabl e Reactor
Coil , Radio Frequency
Fixed
I nductor General
T ransformer, A udio
T ransformer Pul se,
Low Power
T ransformer, Power
T ransformer, Radio
Frequency
T ransformer,
Saturabl e Core
60 %
7 0 %
7 0 %
7 0 %
60 %
7 0 %
60 %
(
60 %
60 %
60 %
60 %
60 %
60 %
60 %
60 %
60 %
9 0 %
9 0 %
9 0 %
9 0 %
7 0 %
9 0 %
9 0 %
9 0 %
1 67
T abl e 4 - 3 1 RELA Y DERA T I NG CHA RT
00
Part
T ype
Stress
Parameter
j % Stress
(A l l owed) Remarks
Rel ay Rated
Contact
Current
5 0 % T he rated contact current for each
contact set shal l be derated by 5 0 %.
Each active contact set must be
cal cul ated separatel y.
a. A ctive means actual l y wired
to serve a circuit function.
b. Each circuit path through the
rel ay constitutes a contact set.
NO T E:
1 . Consideration must be given to the type of l oad to be switched, i.e.,
inductive, capacitive, l amp resistive, or motor when computing
operating current.
2. Rated current means the maximum current for a given type of l oad which
the rel ay wil l make, carry and break for its rated l ife.
3 . A dequate contact protection must be provided where appl icabl e.
4 . Exercise carp in the area of power switching with grounded case rel ays.
T abl e 4 - 3 2 CO NNECT O R DERA T I NG CHA RT
Connector T ype
Stress
Parameter
% Stress
(A l l owed)
R- f Coaxial Current 5 0
Mul tipin Current 5 0
Cabl e Current 5 0
A l l types Vol tage See T abl e Bel ow
for Nonpressured
Systems
Min
A ir
Space
Vol tage at Sea Level
Rated V
(rms)
Working V
A C
DC (rms)
< 0 .0 3 1
0 .0 3 1
0 .0 4 5
0 .0 62
0 .0 7 6
<0 .0 3 1
0 .0 3 1
0 .0 4 5
0 .0 62
0 .0 7 6
< 0 .0 3 1
0 .0 3 1
0 .0 4 5
0 .0 62
0 .0 7 6
60 0 28 0 20 0
1 0 0 0 4 9 0 3 5 0
1 5 0 0 7 0 0 5 0 0
1 8 0 0 8 4 0 60 0
225 0 1 0 5 0 7 5 0
Vol tage at 5 0 , 0 0 0 ft al titude
225 1 0 0 7 5
3 7 5 1 9 0 1 25
5 25 21 0 1 7 5
67 5 3 1 5 225
7 9 0 3 60 3 60
Vol tage at 7 0 , 0 0 0 ft al titude
1 5 0 7 0 5 0
3 0 0 1 25 9 0
3 7 5 1 7 5 1 25
4 5 0 21 0 1 5 0
5 0 0 23 0 1 65
1 69
4 .1 .3 Environmental Resistance
I n order to real ize ful l y the benefits of a rel iabil ity oriented
design, consideration must be given earl y in the design process to the
required environmental resistance of the equipment being designed.
T he environmental resistance, both intrinsic and that provided by
specifical l y directed design features, wil l singul arl y determine the
abil ity of the equipment to withstand the del eterious stresses imposed
by the environment in which the equipment wil l be operated. T he initial
requirement for determining the required environmental resistance is the
identification and detail ed description of the environments in which the
equipment must operate. T he next step is then the determination of the
performance of the components and material s that comprise the equipment
when exposed to the degrading stresses of the environments so identified.
When such performance is inadequate or marginal with regard to the equip-
ment rel iabil ity goal s, corrective measures such as derating, redundancy,
protection from adverse environments, or sel ection of more resistant
material s and components are necessary to ful fil l the rel iabil ity
requirements of the equipment.
4 .1 .3 .1 Environmental Factors
Since rel iabil ity is strongl y dependent upon the operating condi-
tions that are encountered during the entire l ife of the equipment, it
is important that such conditions are accuratel y identified at the
beginning of the design process. Environmental factors which exert a
strong infl uence on equipment rel iabil ity are l isted in T abl e 4 - 3 3 and
discussed on the fol l owing pages.
High temperatures impose a particul arl y severe stress on most
el ectronic components since they can cause not onl y catastrophic fail ure
such as mel ting of sol der joints and burn out of sol id state devices,
but al so sl ow progressive deterioration of component performance l evel s
due primaril y to chemical degradation effects. I t is often stated that
excessive temperature is the primary cause of poor rel iabil ity in
mil itary el ectronic equipment.
1 7 1
T abl e 4 - 3 3 ENVI RO NMENT A L ST RESSES, EFFECT S A ND RELI A BI LI T Y I MPRO VEMENT
T ECHNI QUES I N ELECT RO NI C EQUI PMENT
Environmental
Stress Effects
Rel iabil ity
I mprovement T echniques
High T emperature Parameters of resistance, inductance, capacitance, power factor,
diel ectric constant, etc. wil l vary; insul ation may soften; moving
parts may jam due to expansion; finishes may bl ister; devices
suffer thermal aging; oxidation and other chemical reactions are
enhanced; viscosity reduction and evaporation of l ubricants are
probl ems; structural overl oads may occur due to physical
expansions.
Heat dissipation devices,
cool ing systems, thermal
insul ation, heat- withstanding
material s.
Low T emperature Pl astics and rubber l ose fl exibil ity and become brittl e; el ectrical
constants vary; ice formation occurs when moisture is present;
l ubricants gel and increase viscosity; high heat l osses; finishes'
may crack; structures may be overl oaded due to physical contrac-
tion.
Heating devices, thermal
insul ation, col d- withstanding
material s.
T hermal Shock Material s may be instantaneousl y overstressed causing cracks and
mechanical fail ure; el ectrical properties may be permanentl y
al tered. Crazing, del amination, ruptured seal s.
Combination of techniques for
high and l ow temperatures.
Shock Mechanical structures may be overl oaded causing weakening or
col l apse; items may be ripped from their mounts; mechanical
functions may be impaired.
Strengthened members, reduced
inertia and moments, shock
absorbing mounts.
Vibration Mechanical strength may deteriorate due to fatigue or overstress;
el ectrical signal s may be mechanical l y and erroneousl y modul ated;
material s and structures may be cracked, displ aced, or shaken
l oose from mounts; mechanical functions may be impaired; finishes
may be scoured by other surfaces; wear may be increased.
Stiffening, control of
resonance.
T abl e 4 - 3 3 ENVI RO NMENT A L ST RESSES, EFFECT S A ND RELI A BI LI T Y I MPRO VEMENT
T ECHNI QUES I N ELECT RO NI C EQUI PMENT (Continued)
u>
Environmental
Stress Effects
Rel iabil ity
I mprovement T echniques
Humidity Penetrates porous substances and causes l eakage paths between
el ectrical conductors; causes oxidation which l eads to corrosion;
moisture causes swel l ing in material s such as gaskets; excessive
l oss of humidity causes embrittl ement and granul ation.
Hermetic seal ing, moisture-
resistant material , dehumidi-
fiers, protective coatings.
Sal t A tmosphere
and Spray
Sal t combined with water is a good conductor which can l ower insul a-
tion resistance; causes gal vanic corrosion of metal s; chemical
corrosion of metal s is accel erated.
Nonmetal protective covers,
reduced use of dissimil ar metal s
in contact, hermetic seal ing,
dehumidifiers.
El ectromagnetic
Radiation
Causes spurious and erroneous signal s from el ectrical and el ectronic
equipment and components; may cause compl ete disruption of normal
el ectrical and el ectronic equipment such as communication and
measuring systems.
Shiel ding, material sel ection,
part type sel ection.
Nucl ear/Cosmic
Radiation
Causes heating and thermal aging; can al ter chemical , physical and
el ectrical properties of material s; can produce gases and secondary
radiation; can cause oxidation and discol oration of surfaces; damages
el ectrical and el ectronic components especial l y semiconductors.
Shiel ding, component sel ection,
nucl ear hardening.
Sand and Dust Finel y finished surfaces are scratched and abraded; friction between
surfaces may be increased; l ubricants can be contaminated; cl ogging
of orifices, etc.; material s may be worn, cracked, or chipped;
abrasion, contaminates insul ations, corona paths.
A ir- fil tering, hermetic seal ing.
Low Pressure
(High A l titude)
Structures such as containers, tanks, etc. are overstressed and can be
expl oded or fractured; seal s may l eak; air bubbl es in material s may
expl ode causing damage; internal heating may increase due to l ack of
cool ing medium; insul ations may suffer arcing and breakdown; ozone may
be formed; outgasing is more l ikel y.
I ncreased mechanical strength of
containers, pressurization,
al ternate l iquids (l ow vol atil -
ity), improved insul ation, im-
proved heat transfer methods.
I n present day el ectronic systems design, great emphasis is pl aced
on smal l size and high component part densities. T his general l y requires
a cool ing system to provide a path of l ow thermal resistance from heat-
producing el ements to an ul timate heat sink of reasonabl y l ow temperature.
Sol id state components are general l y rated in terms of maximum
junction temperatures, and the thermal resistances from this point to
either the case or to free air are usual l y specified. T he specification
of maximum ambient temperature for which a component is suitabl e is
general l y not a sufficient method for component sel ection with densel y
packaged parts since the surface temperatures of a particul ar component
can be greatl y infl uenced by heat radiation or heat conduction effects
from other nearby parts. T hese effects can l ead to overheating above
specific maximum safe temperatures even though the ambient temperature
rating appears not to be exceeded. I t is preferabl e, therefore, to
specify thermal environment ratings such as equipment surface tempera-
tures, thermal resistance paths associated with conduction, convection
and radiation effects, and cool ing provisions such as air temperature,
pressure and vel ocity, I n this manner, the true thermal state of the
temperature- sensitive internal el ements can be determined.
Low temperatures experienced by el ectronic equipment can al so cause
rel iabil ity probl ems, T hese probl ems are usual l y associated with mech-
anical el ements of the system and incl ude mechanical stresses produced
by differences in the coefficients of expansion (contraction) of metal l ic
and nonmetal l ic material s, embrittl ement of nonmetal l ic components,
mechanical forces caused by freezing of entrapped moisture, stiffening
of l iquid constituents, etc. T ypical exampl es incl ude cracking of seams,
binding of mechanical l inkages, and excessive viscosity of l ubricants.
A dditional stresses are produced when el ectronic equipment is ex-
posed to sudden changes of temperature or rapidl y changing temperature
cycl ing conditions. T hese conditions generate l arge internal mechanical
stresses in structural el ements particul arl y when dissimil ar material s
are invol ved. Effects of the thermal shock induced stresses incl ude
cracking of seams, del ami nation, l oss of hermeticity, l eakage of fil l
gases, separation of encapsul ating components from components and
encl osure surface l eading to the creation of voids, and distortion of
support members.
1 7 4
A thermal shock test is general l y specified to determine the integ-
rity of sol der joints since such a test creates l arge internal forces
due to differential expansion effects. Such a test has al so been found
to be instrumental in creating segregation effects in sol der al l oys
l eading to the formul ation of l ead- rich zones which are susceptibl e to
cracking effects.
El ectronic equipment is often subjected to environmental shock and
vibration both during normal use and testing. Such environments can
cause physical damage to components and structural members when defl ec-
tions produced cause mechanical stresses which exceed the al l owabl e
working stress of the constituent parts.
T he natural frequencies of subsystems comprising the equipment are
important parameters which must be considered in the design process
since a resonant condition can be produced if a natural frequency is
within the vibration frequency range. T he resonance condition wil l
greatl y ampl ify the defl ection of the subsystem and may increase stresses
beyond the safe l imit.
T he vibration environment can be particul arl y severe for el ectrical
connectors since it may cause rel ative motion between members of the
connector. T his motion in combination with other environment stresses
can produce fret corrosion which generates wear debris and causes l arge
variations in contact resistance.
Humidity and sal t air environments can cause degradation of equip-
ment performance since they promote corrosion effects in metal l ic
components and can foster the creation of gal vanic cel l s particul arl y
when dissimil ar metal s are in contact. A nother del eterious effect of
humidity and sal t air atmospheres is the formation of surface fil ms on
nonmetal l ic parts which cause l eakage paths and degrade the insul ation
and diel ectric properties of these material s. A bsorption of moisture
by insul ating material s can al so cause a significant increase in vol ume
conductivity and dissipation factor of material s so affected.
El ectromagnetic and nucl ear radiation can cause disruption of per-
formance l evel s and, in some cases, permanent damage to exposed equip-
ment. I t is important, therefore, that such effects be considered in
1 7 5
determining the required environmental resistance for el ectronic equip-
ment that must achieve a specified rel iabil ity goal .
El ectromagnetic radiation often produces interference and noise
effects within el ectronic circuitry which can impair the functional per-
formance of the system. Sources of these effects incl ude corona dis-
charges, l ightning discharges, sparking and arcing phenomena. T hese may
be associated with high vol tage transmission l ines, ignition systems,
brush- type motors, and even the equipment itsel f. General l y, the reduc-
tion of interference effects requires incorporation of fil tering and
shiel ding features or the specification of l ess susceptibl e components
and circuitry.
Nucl ear radiation can cause permanent damage by al teration of the
atomic or mol ecul ar structure of diel ectric and semiconductor material s.
High energy radiation can al so cause ionization effects which degrade
the insul ation l evel s of diel ectric material s. T he mitigation of nucl ear
radiation effects typical l y invol ves the use of material s and components
possessing a higher degree of intrinsic radiation resistance and the
incorporation of shiel ding and hardening techniques.
I n addition to the aforementioned stress factors, other environ-
mental factors may require consideration in the design process to assure
that adequate environmental resistance is incorporated into the equip-
ment design. T hese additional factors incl ude:
t Sand and dust
t Fungus
A coustic noise
t El ectric fiel ds
Magnetic fiel ds
Presence of reactive l iquids and gases
Each of these stress factors, if present, requires determination of
its impact on the operational and rel iabil ity characteristics of the
material s and components comprising the equipment being designed, and
the identification of material , component and packaging techniques that
afford the necessary protection against such degrading factors.
1 7 6
I n the environmental stress identification process that precedes
the sel ection of environmental resistance techniques, it is essential
that stresses associated with al l l ife interval s of the equipment be
considered. T his incl udes not onl y the operational and maintenance
environments but al so the preoperational environments when stresses
imposed on the parts during manufacturing assembl y, inspection, testing,
shipping and instal l ation may have significant impact on the eventual
rel iabil ity of the equipment. Stresses imposed during the preoperational
phase are often overl ooked, but they may represent a particul arl y harsh
environment which the equipment must withstand. O ften the shock and
humidity environments to which commercial and mil itary systems are
exposed during shipping and instal l ation are more severe than those it
wil l encounter under normal operating conditions. I t is al so probabl e
that some of the environmental resistance features that are contained
in a system design pertain to conditions that are encountered in the
preoperational phase, and not in conditions that the equipment experi-
ences after being put into operation.
4 .1 , 3 .2 Environmental Resistance Provisions
A fter identification of al l environmental stress factors that wil l
be encountered by a particul ar el ectronic system, a determination is
made of components and el ements of the system which wil l be adversel y
affected and the effects of this degradation on the apportioned rel i-
abil ity goal s. General l y, such a determination wil l not onl y identify
el ements of the proposed design that are total l y unsuitabl e, but equal l y
important, wil l identify tradeoff situations where incorporation of
specific protective features wil l significantl y enhance the achievabl e
rel iabil ity.
I n these cases, the sol ution is the specification of components
having greater inherent resistance to the identified environmental
stresses and the sel ection of particul ar protection techniques for
reducing these stresses to l evel s that produce more favorabl e rel iabil -
ity characteristics.
1 7 7
T hermal Protection
Since excessive temperature is a primary cause of operational and
rel iabil ity degradation, each proposed system design must be eval uated
to establ ish that its thermal performance is consistent with the required
equipment rel iabil ity. T he preferred method for eval uating the thermal
performance of el ectronic equipment (with respect to rel iabil ity) is a
parts stress anal ysis method (per Section 2.3 .1 ) which determines the
maximum safe temperatures for constituent parts. A reduction in the
operating temperature of components is a primary method for achieving
improved rel iabil ity l evel s. T his is general l y possibl e by provision of
a thermal design which reduces heat input to minimal l y achievabl e l evel s
and provides l ow thermal resistance paths from heat- producing el ements
to an ul timate heat sink of reasonabl y l ow temperature. T he thermal
design is often as important as the circuit design in obtaining the
necessary performance and rel iabil ity characteristics of el ectronic
equipment.
T he fail ure rates of el ectronic system components vary significantl y
with temperature. T abl e 4 - 3 4 il l ustrates the rel iabil ity improvement
potential that is associated with the operation of circuit el ements at
reduced temperatures. A consideration of l ife cycl e costs wil l general l y
indicate that the cost of designing and impl ementing adequate thermal
performance into equipment is ful l y recovered by savings in maintenance
costs earl y in the operational l ife of the equipment. A suitabl e thermal
design wil l al so minimize temperature excursions of components when en-
vironmental temperatures or power dissipation vary, resul ting in further
rel iabil ity benefits.
T he part stress anal ysis method for eval uating system thermal per-
formance is based on a determination of the maximum al l owabl e tempera-
ture for each component which is consistent with the equipment rel iabil ity
and the fail ure rate al l ocated to that component. O nce these maximum
al l owabl e temperatures are assigned and the power dissipated by each
component is ascertained, a heat fl ow network can be establ ished from
each component to avail abl e heat sinks or cool ants for anal ysis of the
system thermal performance. I n situations where surface temperatures
must be rel ated to maximum al l owabl e internal temperatures, such as
1 7 8
T abl e 4 - 3 4 RELI A BI LI T Y I MPRO VEMENT PO T ENT I A L
A T REDUCED T EMPERA T URES
Part
Description
Base Fail ure Rates*
(per 1 0
6
hrs)
A t
C
Decrease in
Fail ure Rate
Due to Low T Reduced T emp- C High T emp- C
PNP Sil icon
T ransistors
NPN Sil icon
T ransistors
Gl ass and
Porcel ain
Capacitors
T ransformers
and Coil s
Resistors,
Comp. Carb.
0 .0 0 8 at 4 0
0 .0 0 5 4 at 4 0
0 .0 0 0 9 at 4 0
0 .0 0 1 at 9 0
0 .0 0 0 2 at 4 0
0 .0 63 at 1 60
0 .0 3 3 at 1 60
0 .0 29 at 1 25
0 .0 267 at 8 5
0 .0 0 63 at 9 0
1 20
1 20
8 5
4 5
5 0
8 :1
6:1
3 2:1
27 :1
3 1 :1
T aken from MI L- HDBK- 21 7 B at a 1 0 % stress l evel .
junction temperatures of semiconductor devices, a knowl edge of the
internal thermal resistance of these components is required to cal cul ate
the corresponding surface temperatures for the particul ar operating
conditions of the component.
A step by step procedure for eval uating thermal performance of
proposed designs incl udes the fol l owing activities:
Establ ish the maximum and minimum environmental temperatures
of anticipated heat sinks and cool ants.
Characterize the avail abl e cool ing techniques such as forced
air convection, l iquid or vaporization cool ing.
t Devel op a heat fl ow network using el ectrical anal og techniques
for the conditions of maximum al l owabl e component temperatures
and maximum environmental heat sink or cool ant temperatures;
determine the thermal resistance requirements from parts to
heat sinks.
1 7 9
Sel ect packaging approaches and component pl acements that wil l
ful fil l the thermal resistance requirements in terms of the
avail abl e and permissibl e cool ing techniques.
Determine the suitabil ity of simpl e cool ing techniques such as
free or forced air cool ing for satisfying the heat concentration
and thermal resistance requirements of the proposed design. I f
insufficient, proceed to higher l evel cool ing techniques until
an optimum cool ing method is identified.
t Eval uate the penal ties associated with the sel ected cool ing
method and perform tradeoff anal yses to identify al ternative
approaches and refinements if possibl e.
Further specifics of the parts stress thermal ansl ysis and design
techniques are described in Navel ex Publ ication No. 0 9 67 - 4 3 7 - 7 0 1 0 ,
Jul y 1 9 7 3 , and other references described in this publ ication.
A l though each proposed system design requires a thermal performance
anal ysis based on its specific characteristics, there are a number of
general rul e- of- thumb approaches associated with specific components
that are beneficial for obtaining suitabl e thermal performance. Guide-
l ines to achieve rel iabl e design through temperature reduction of specific
components are itemized in T abl e 4 - 3 5 .
Mechanical Protection
Protection against mechanical abuse environments is general l y
achievabl e by use of suitabl e packaging, mounting and structural tech-
niques. T he rel iabil ity impact of mechanical protection techniques is
general l y singul ar in that these measures do or do not afford the re-
quired protection against the identified mechanical abuse stresses. I n
most cases, tradeoff situations between the l evel of protection and
rel iabil ity improvements are not as pronounced as in the case of thermal
protection. T he one exception may be the case of fatigue damage where
the l evel of protection woul d have a significant impact on rel iabil ity
if in fact fatigue was a primary fail ure mechanism in the normal l ife
of the equipment.
1 8 0
T abl e 4 - 3 5 DESI GN GUI DELI NES T O REDUCE CO MPO NENT O VERHEA T I NG
Semiconductor Devices
a) Minimize thermal contact resistance between device and its
mounting by using l arge area, smooth contacting surfaces
and specifying thermal gaskets or compounds as required.
b) Locate remote from high temperature parts.
c) Use heat sinks with fins positioned vertical l y and in direc-
tion of air or cool ant fl ow. Use painted or coated surfaces
to improve radiation characteristics.
Capacitors
a) Locate remote from heat sources.
b) I nsul ate thermal l y from other heat sources.
Resistors
a) Locate for favorabl e convection.
b) Provide mechanical cl amping or encapsul ating material for
improved heat transfer to heat sinks.
c) Use short l eads whenever possibl e.
T ransformers and I nductors
a) Provide heat conduction paths for transfer of heat from
these devices.
b) Locate favorabl y for convection cool ing.
c) Provide cool ing fins where appropriate.
Printed Wiring Boards
a) Specify l arger area conductors where practicabl e.
b) Segregate heat producing el ements from heat sensitive
components.
c) Use intermediate metal core l ayers in mul ti- l ayer systems
and provide good conduction paths from these l ayers to
support members and intermediate heat sinks.
d) Use protective coatings and encapsul ants for improving heat
transfer to l ower temperature supports and heat sinks.
1 8 1
Shock and Vibration Protection
T he environmental resistance required to protect against specified
shock and vibration stresses is general l y determined by an anal ysis
which eval uates the defl ections and mechanical stresses produced by these
environmental factors. T his general l y invol ves the determination of
natural frequencies and eval uation of the mechanical stresses within
components and material s produced by the shock and vibration environment.
I f the mechanical stresses so produced are bel ow the al l owabl e safe
working stress of the material s invol ved, no direct protection methods
are required. I f, on the other hand, the stresses exceed the safe l evel s,
corrective measures such as stiffening, reduction of inertia and bending
moment effects, and incorporation of further support members are indicated.
I f such approaches do not reduce the stresses bel ow the safe l evel s,
further reduction is usual l y possibl e by the use of shock absorbing
mounts.
Humidity, Sal t A ir, Sand and Dust Protection
I t is often mandatory to provide protection of the system el ements
against dust, dirt, contamination, humidity, sal t spray and other mech-
anical abuse environments of this type. A l though tradeoff situations
general l y do not exist in terms of potential rel iabil ity improvements,
this protection does significantl y impact the operational and rel iabil ity
l evel s of the equipment.
Possibl e protection methods against this cl ass of environmental
stresses incl ude hermetic seal ing, desiccants, and protective coatings.
Hermetic seal ing is often required when components such as sol id state
devices must be operated in a control l ed atmosphere. T he technical con-
siderations invol ved in the sel ection of the hermetic seal system are its
effects on the thermal performance of the system and its resistance to
cracking during thermal shock conditions.
T here are many insul ating compounds that can be appl ied as coatings
on el ectronic component assembl ies. A mong these are epoxies, sil icones,
pol yurethanes, pol ystyrenes and varnishes. General l y, these are sel ected
in accordance with MI L- I - 4 60 5 8 for mil itary appl ications. T echnical
considerations for sel ection of suitabl e protective coatings are insul ation
1 8 2
resistance under the expected humidity and temperature conditions,
dissipation factor, diel ectric constant, mechanical fl exibil ity, resist-
ance to cracking during thermal shock, removal ease for repair work,
ease of appl ication, and its abil ity to prevent the migration of corrosion
products.
Radiation Protection
Radiation protection general l y must be specifical l y designed for
the noise and interference fiel ds against which protection is required.
T his usual l y invol ves the specification of shiel ding and fil tering that
are effective in the frequency range of concern.
Nucl ear radiation protection general l y consists of the use of
specific components having an intrinsic hardness and the incorporation
of shiel ding features that impact the required l evel of hardness to the
system. A gain, the provision of nucl ear protection schemes is usual l y
a go/no- go proposition since few tradeoff situations are apparent.
4 .1 .3 .3 General Packaging Considerations
T he sel ection of a suitabl e packaging method for el ectronic equip-
ment requires consideration of many tradeoff factors in addition to the
environmental protection factors described above. Characteristics that
infl uence the choice of a packaging method incl ude cost, size, produc-
ibil ity, maintainabil ity, repairabil ity and rel iabil ity. I n many cases,
the system requirements are confl icting, and the sel ection process becomes
one of identifying a packaging approach offering the best compromise of
the many divergent requirements.
I n mil itary el ectronic systems, size, weight and rel iabil ity are
prime considerations, and the choice of packaging methods must refl ect
the priority of these factors. System packaging approaches are general l y
concentrated on microel ectronic packaging systems because of the size
reduction and rel iabil ity benefits associated with semiconductor inte-
grated circuit devices. Semiconductor integrated circuits not onl y offer
rel iabil ity improvements because of their inherent properties but al so
because of the reduced number of interconnections that are needed.
Further improvements resul t from the highl y control l ed fabrication
processes and techniques util ized in the manufacture of such devices.
1 8 3
T abl e 4 - 3 6 il l ustrates a general ranking of tradeoffs associated
with el ectronic packaging techniques. For particul ar systems, these
ranking factors wil l vary depending upon the specific requirements of
the system. However, the general order of ranking is bel ieved to be
appropriate for a l arge popul ation of systems, al though l arge variations
wil l occur.
T abl e 4 - 3 6 PA CKA GI NG T RA DE- O FFS
Type of Packaging
Characteristics
Size Cost
Throw
Away
Cost
Relia-
bility
Main-
tenance
Repair
Logistics/
Spares
Soldered Modules on Boards
Welded Modules on Boards
Hybrid Modules
(with integrated circuits)
Hybrid Compartmentalized
Etched Circuits
Pluggable Flat-Pack
Modul es
Flat-Pack Integrated
Circuits Printed Wiring
Board
Welded Flat-Pack IC Stack
Thin-Film Circuits
IC Chips
Large-Seale Integration
(LSI)
MOS Devices
P
P
F
F
F
F
G
G
G
G
G
G
F
P
P
P
P
F
G
P
G
G
G
G
G
F
F
F
F
G
G
P
F
P
P
P
P
P
F
F
F
P
F
F
F
G
G
G
G
G
P
P
P
P
1
p
F
F
F
F
F
F
G
F
F
P
P
P
G = Good
F = Fair
P = Poor
1 8 4
4 .1 .4 Redundancy
T he rel iabil ity of a system can be significantl y enhanced through
the use of redundancy. Redundancy invol ves designing one or more al ter-
nate signal paths into the system through addition of paral l el el ements.
Redundancy has been extensivel y appl ied in airborne systems. For
27
exampl e, the el ectronic mul tipl exing system for the B- l bomber currentl y
uses a redundant design. I n this system, redundant computers control the
main switching buses. Normal l y, one of the two computers is active and
feeds the two main buses which control al l switching functions whil e the
other continuousl y performs the same function and compares its output
with the active computer. I f the active computer mal functions, the stand-
by automatical l y takes over.
A nother exampl e of a redundant configuration is provided by the
28
A WG- 9 weapon control system as used aboard the Grumman F- 1 4 fighter .
I n this system, two major sensors are used to achieve the same goal .
t Pul se Doppl er search, track, acquisition and guidance radar
t Gimbal - mounted infrared search/acquisition sensor.
T he infrared system provides a backup to the radar if the l atter is
inoperabl e due to mal functions or jamming. A dditional l y, it may operate
in a dual mode to augment the radar search vol ume.
T his subsection of the handbook presents data and guidel ines for
the appl ication and eval uation of redundancy. T he categorization of
techniques, their advantages and disadvantages and specific design
exampl es are incl uded. T his treatment of redundancy is not meant to be
exhaustive, but to point out concepts of redundancy important to el ec-
tronic equipment design appl ications and to caution the designer that
appl ications of redundancy are not without drawbacks. For a more detail ed
discussion of redundancy, the reader is referred to the reference sources.
4 .1 .4 .1 General Concepts
A s indicated in Section 2.1 .2, safety and mission rel iabil ity can
be increased through redundancy at the cost of decreasing unschedul ed
maintenance (or serial ) rel iabil ity. Note, however, that the unschedul ed
maintenance rel iabil ity reduction accompanying redundancy may be offset
1 8 5
by also improving reliability through use of component improvement
techniques--such as part screening, derating and design simplification--
as discussed elsewhere in this guide.
Depending on the specific applications, a number of approaches are
available to improve reliability through redundant design. These design
approaches can be classified on the basis of how the redundant elements
are introduced into the circuit to provide a parallel signal path. In
general, there are two (2 ) major classes of redundancy:
(1) Active redundancyExternal components are not required to
perform the function of detection, decision and switching when
an element or path in the structure fails.
(2 ) Standby redundancyExternal elements are required to detect,
make a decision and switch to another element or path as a
replacement for a failed element or path.
Techniques related to each of these two classes are depicted in the
simplified tree-structure shown in Figure 4-31.
Stondby
r-
Non-Operoting Operoting
(7) (8)
Simple Duplex Bimodol
(I) (2 ) (3)
Majority Vote ^"^ Gate Connector
TO
IX
Simple Adaptive
(4) (5)
Fig. 4-31 REDUNDANCY TECH NIQUES
Table 4-37 further defines each of the eight techniques shown in Figure
4-31.
Although not readily apparent, redundancy does not lend itself to
categorization exclusively by element complexity. Although certain of
the configurations described in Table 4-37 are more applicable at the
186
Simple Porallel Redundancy
Duplex Redundancy
3*3Ei
(a) Bimodal Parallel/
Series Redundancy
(b) Bimodal Series/
Parallel Redundancy
I n its simpl est for , redundancy consists of
a simpl e paral l el combination of el ements.
I f any el ement fal l s open, I dentical paths
exist through paral l el redundant el ements.
T his technique is appl ied to redundant l ogic
sections, such as A l and A 2 operating 1 n
paral l el . I t 1 s primaril y used in computer
appl ications where A l and A 2 can be used in
dupl ex or active redundant modes or as a
separate el ement. A n error detector at the
output of each l ogic section detects
noncol ncident outputs and starts a diagnostic
routine to determine and disabl e the faul ty
el ement.
A series connection of paral l el redundant
el ements provides protection against shorts
and opens. Direct short across the network
due to a singl e el ement shorting I s prevented
by a redundant el ement I n series. A n open
across the network is prevented by the
paral l el el ement. Network (a) is useful
when the primary el ement fail ure mode 1 s
open. Network (b) 1 s useful when the
primary el ement fail ure mode is short.
TABLE 4-37 RFDUNDANCY TECHNIQUES
187
Majority Voting Redundancy
| Aj_
| A2
I
1
An
Adapti ve Majority Logic
A.
\
\
A2
\
^^V"A
^fc)
Comp
A3
^^/^s
/
/
A4
/
Gate Connector Redundancy
r
A
i
<
-
Output
Standby Redundancy
J 1
A|
1~r~ ~i
/ ^-
x
Power
Output
-c
-Power
A2
1
Output
Operating Redundancy
X
A3
1
D3
J
I A n j 1 O n
Decision can be buil t I nto the basic paral l el
redundant model by I nputting signal s from
paral l el el ements I nto a voter to compare
each signal with remaining signal s. Val id
decisions are made onl y I f the number of
useful el ements exceeds the fail ed el ements.
T his technique exempl ifies the majority l ogic
configuration discussed previousl y with a
comparator and switching network to switch
out or I nhibit fail ed redundant el ements.
Simil ar to majority voting. Redundant el ements
are general l y binary circuits. O utputs of the
binary el ements are fed to switch- l ike gates
which perform the voting function. T he gates
contain no components whose fail ure woul d
cause the redundant circuit to fal l . A ny
fail ures in the gate connector act as though
the binary el ement were at faul t.
A particul ar redundant el ement of a paral l el
configuration can be switched into an active
circuit by connecting outputs of each el ement
to switch pol es. T wo switching configurations
are possibl e.
1 ) T he el ement may be I sol ated by the switch
until switching I s compl eted and power
appl ied to the el ement in the switching
operation.
2) A l l redundant el ements are continuousl y
connected to the circuit and a singl e
redundant el ement activated by switching
power to it.
I n this appl ication, al l redundant units *
operate simul taneousl y. A sensor on each unit
detects fail ures. When a unit fail s, a switch
at the output transfers to the next unit and
remains there until fail ure.
TABLE 4-37 REDUNDANCY TECHNIQUES (Cont.)
part or circuit l evel as opposed to the equipment l evel , this is not due
to inherent l imitations of the particul ar configuration but rather to
supporting factors such as cost, weight and compl exity.
I n addition to the two major cl asses and rel ated techniques, another
form of redundancy can exist within normal nonredundant design configura-
tions. Paral l el paths within a network often are capabl e of carrying an
added l oad when el ements fail . T his can resul t in a degraded but tol er-
abl e output. I n other words, an el ement fail ure in a paral l el path does
not al ways cause compl ete equipment fail ure but, instead, degrades equip-
ment performance. T he al l owabl e degree of degradation depends on the
number of al ternate paths avail abl e. Where a mission can stil l be accom-
pl ished using an equipment whose output is degraded, the definition of
fail ure can be rel axed to accommodate degradation. Natural l y, l imiting
val ues of degradation must be buil t into the new definition of fail ure.
T his sl ow approach to fail ure, having been termed " graceful degradation" ,
is exempl ified by an array of el ements configured into an antenna or an
array of detectors configured into a receiver. I n either case, individual
el ements may fail , reducing resol ution, but if a minimum number operate,
resol ution remains great enough to identify a target.
T he decision to use redundant design techniques must be based on a
careful anal ysis of the tradeoffs invol ved. Redundancy may prove the
onl y avail abl e method when other techniques of improving rel iabil ity have
been exhausted or when methods of part improvement are shown to be more
costl y than dupl ications. I ts use may offer an advantage when preventive
maintenance is pl anned. T he existence of a redundant equipment can al l ow
for repair with no system downtime. O ccasional l y, situations exist in
which equipments cannot be maintained (e.g., spacecraft). I n such cases,
redundant el ements may prol ong operating time significantl y.
But the appl ication of redundancy is not without penal ties. I t wil l
increase weight, space, compl exity, cost and time to design. A s pre-
viousl y described, the increase in compl exity resul ts in a decrease of
unschedul ed maintenance rel iabil itysafety and mission rel iabil ity is
gained at the expense of serial mean- time- between- fail ure (MT BF).
1 8 9
I n general , the rel iabil ity gain for additional redundant el ements
decreases rapidl y for additions beyond a few paral l el el ements. A s il l us-
trated by Figure 4 - 3 2 for simpl e paral l el redundancy, there is a dimin-
ishing gain in rel iabil ity and MT BF as the number of redundant el ements
is increased. A s shown for the simpl e paral l el case, the greatest gain
achieved through addition of the first redundant el ement is equival ent to
a 5 0 % increase in the system MT BF. I n addition to maintenance cost in-
creases due to repair of the additional el ements, rel iabil ity of certain
redundant configurations may actual l y be l ess. T his is due to the serial
rel iabil ity of switching or other peripheral devices needed to impl ement
the particul ar redundancy configuration (see T abl e 4 - 3 7 ).
T he effectiveness of certain redundancy techniques (especial l y
standby) can be enhanced by repair. Standby redundancy al l ows repair of
the fail ed unit (whil e operation of the good unit continues uninterrupted)
by virtue of the switching function buil t into the standby redundant con-
figuration. T he switchover function can readil y provide an indication
that fail ure has occurred and operation is continuing on the al ternate
channel . With a positive fail ure indication, del ays in repair are mini-
mized. A further advantage of switching is rel ated to buil t- in test (BI T )
objectives. Buil t- in test can be readil y incorporated into a sensing and
switchover network for ease of maintenance purposes.
A n il l ustration of the enhancement of redundancy with repair is
shown in Figure 4 - 3 3 . T he achievement of increased rel iabil ity brought
about by incorporation of redundancy is dependent on effective isol ation
of redundant el ements. I sol ation is necessary to prevent fail ure effects
from adversel y affecting other parts of the redundant network. T he sus-
ceptibil ity of a particul ar redundant design to fail ure propagation may
be assessed by appl ication of fail ure mode effects anal ysis as discussed
in Section 2.3 .2. T he particul ar techniques addressed there offer an
effective method of identifying l ikel y faul t propagation paths.
I nterdependency is most successful l y achieved through standby redun-
dancy, as represented by configurations cl assified as decision with
switching, where the redundant el ement is disconnected until a fail ure
is sensed. Design based on such techniques must provide protection
1 9 0
1.0
.8
= 6
n
o
cc .4
. M'MTBF-y
_L
1 Of 10 Redundant
Elements
1 Of 5
1 Of 4
1 Of 3
1 Of 2
Single Element
M
Time
2M
(a) Simple Active Redundancy For
One Of n Element Required
5 24
CD
2.2
6
2.0
n
0)
o
c
c
E
S
1.8
1.4
1.2
1.0
2 3 4
Degree Of Redundancy (n)
AM
5
.20
.25
(b) Incremental Increase In System MTBF For n Active Elements
Fig. 4-32 DECREASING GAIN IN RELIABILITY AS NUMBER OF
ACTIVE ELEMENTS INCREASES
191
Redundant Element
With Repair
JQ
O
e r
Time
Fig.4-33 RELIABILITY GAIN FOR REPAIR OF SIMPLY
PARALLEL REDUNDANT ELEMENT AT
FAILURE
192
against switching transients and consider effects of switching inter-
ruptions on system performance.
Furthermore, care must be exercised to assure rel iabil ity gains
from redundancy are not offset by increased fail ure rates due to switch-
ing devices, error detectors and other peripheral devices needed to
impl ement the redundancy configurations.
4 .1 .4 .2 Redundancy T echniques
T his section provides further information on the redundancy tech-
niques itemized in Figure 4 - 3 1 and further described in T abl e 4 - 3 7 .
Figures 4 - 3 4 through 4 - 3 8 present bl ock diagrams, mathematical model s,
a pl ot of the rel iabil ity function, appl ications, and advantages and
disadvantages for those techniques defined in T abl e 4 - 3 7 . A s shown in
Figure 4 - 3 1 , active and standby redundancy are major categories or
redundancy techniques. Several different techniques of paral l el redun-
dancy are given, since it is the most widel y used type. Exampl es of
voting and standby redundancy are al so incl uded. Due to the simil arity
between several of the techniques shown in T abl e 4 - 3 7 , several are com-
bined into one figure. I n particul ar, gate connector redundancy and
adaptive majority l ogic have been incl uded as a modification of majority
voting; standby redundancy has been considered to be a modification of
operating redundancy as impl emented by a different switching arrangement.
More detail ed information regarding model s and appl ications of these
special ized techniques is to be found in references 27 , 28 , 29 , 3 0 , 3 1
at the end of Section 4 . A ppl ications of these specific redundancy
techniques to design exampl es may be found in Section 4 .1 .4 .3 .
4 .1 .4 .3 Design Exampl es
T his section presents exampl es of current appl ications of redundancy
to avionics equipment. T he particul ar exampl es discussed are l isted
bel ow:
Simpl e paral l el redundant precision vol tage suppl y
t Quad- redundant computer buil ding bl ock
Majority voter redundant * 8 counter
Standby redundant channel s in an RF receiver.
1 9 3
All Blocks
Are Assumed
To Be
Identical
Reliability
Block Diagram
1 .0
.8
.6
A PPLI CA T I O N
Provides protection against
irreversibl e hardware fail -
ures for continuousl y oper-
ating equipments.
MA T HEMA T I CA L MO DEL
R = l - (l - e"
U
)n
SI MPLI FI ED MO DEL
R = l - (xt)
n
for smal l xt
where
n = number of paral l el
el ements
>>
\\^n5 x = failure rate
o
.4
^\
N
^
v
^n4
^^n2
R= reliability
.2
[" MMTBFY
\Single
^vÊlement
M 2M
Time
RELI A BI LI T Y FUNCT I O N FO R SI MPLE
PA RA LLEL RELI A BI LI T Y
A DVA NT A GES
Simpl icity
t Significant gain in Rel iabil ity
from nonredundant el ement
A ppl icabl e to both anal og and
digital circuitry
DI SA DVA NT A GES
Load sharing must be
considered
Sensitive to vol tage division
across the el ements
Difficul t to prevent fail ure
propagation
May present circuit design
probl ems
Fig. 4 - 3 4 SI MPLE PA RA LLEL REDUNDA NCY
1 9 4
Reliobility
Block Diagram
A PPLI CA T I O N
A ppl icabl e primaril y at the part
l evel where short and open pro-
tection is required.
a) Protects primaril y against the
short fail ure mode.
b) Protects primaril y against the
open fail ure mode.
(b)
m
{All Elements
Shown In
The Block
Diagram Are
Assumed Identical
1.0
.8
I
6
o
a
* .4
\ ^ Series-Parallel
\ \^ Quad Redundancy
\
\
.2
MATH EMATICAL MODEL
a) R = 2e-
2U
-e-
4U
b) R = 4e-
2U
-4e-
3U
+
e-
4U
Parallel -
Series Quad
Redundancy -
M-MTBF-Y
Single Element
M 2M
T ime *
RELI A BI LI T Y FUNCT I O N FO R
BI MO DA L CO NFI GURA T I O NS
A DVA NT A GES
Provides significant gain in
rel iabil ity at the part or stage
l evel for short mission times.
DI SA DVA NT A GES
Difficul t to design.
t Restricted to part and/or
stage appl ications.
Fig. 4 - 3 5 BI MO DA L REDUNDA NCY
1 9 5
Reliability Block Diagram
A PPLI CA T I O N
T his technique is appl icabl e
to digital computer circuits
" * with the objective of pre-
venting incorrect l ogic
el ements from upsetting other
circuits.
(El ements
<A | 9 A
2
1 A re I dentical
1 .0 r
.8 -
.6
o
or
.4 -
.2 -
To Computer Or
External Control
Curve A
:
Reliability Of
Error Detector And Dia-
gnostics Is 1.0.
Curve B Combined Failure
Rate Of Detector 8 Dia-
gnostics Is 0.5 That Of
k
Other Blocks.
RELI A BI LI T Y FUNCT I O N FO R
DUPLEX REDUNDA NCY
A DVA NT A GES
A ppl icabl e to dupl ex, active redundant
modes or separate el ements
Maintains function for n- 1 fail ures
Protects against open and short
fail ure modes and errors
Faul ty units can be repaired without
disrupting the computer
R= P
ED
P
DL
((2P
A
P
Sl -(W
(2P
3
- P^ )
where
P
3
P
G0 1
+ P
G0 2
P
GA ~
P
G0 1
P
G0 2
P
GA
where
ED
DL
SW
= error detector rel i-
abil ity
= diagnostic l ogic
rel iabil ity
= el ement rel iabil ity
= stop switch rel iabil ity
= probabil ity first input
to O R gate gets through
P
rn
o= probabil ity second input
buc
to O R gate gets through
P
GA
=

rel iaDi1 it
y
of

A ND
9
ate
DI SA DVA NT A GES
May require diagnostic
program
I ncreased compl exity due
to sensing and switching
t Storage capacity require-
ments may increase due to
redundant data require-
ments
Fig. 4 - 3 6 DUPLEX REDUNDA NCY
1 9 6
-<=}'
rRedundant
/ Elements Assumed
(Îdentical
M
Time**
Reliability Function For Majority
Voting Redundancy
.001 10 MTBF .01
Time
Reliability For Mission Time Less
Than One MTBF
1
A PPLI CA T I O N
General l y used with l ogic circuitry
for either continuous or intermittent
operation. T his technique with minor
modification, may be put in the form
of adaptive majority l ogic or gate
connector redundancy.
A DVA NT A GES
Can be impl emented to provide
indication of defective el ements
t Can provide a significant gain in
rel iabil ity for short mission
times (l ess than one MT BF)
DI SA DVA NT A GES
Requires voter rel iabil ity
significantl y better than
el ement rel iabil ity
t Lower rel iabil ity for l ong
mission time (greater than
one MT BF)
- Li/"
2n+ 1
)(l - e-
U
)
- xt(2n+ l - i)
SI MPLI FI ED MO DEL
R
. e
V
- 0 (xt)
n+ 1
for smal l A t
where
n = number of redundant el ements
minus minimum number of
el ements required
\ fail ure rate
R = rel iabil ity
\ = fail ure rate of MVT
m
Fig. 4-37 MAJORITY VOTING REDUNDANCY
197
Reliobility Block Diagrom
Al
- A2 - D2 -
A3
Hg)
5
-
L
{Z^}{n}
J
[Redundant
< El ements(A | , . ..A
n
)
VA re I dentical
RELI A BI LI T Y FUNCT I O N FO R O PERA T I NG
REDUNDA NCY WI T H UNI T SELECT I O N
A DVA NT A GES
A ppl icabl e to anal og and digital
circuitry
Effective for intermittent fail ure
modes
A PPLI CA T I O N
T his configuration uses singl e mode
redundancy with a sensor (Dn) on each
unit possessing switching capabil ity
when a fail ure is detected. I t is used
when l ong starting time must be avoided
and onl y singl e output can be tol erated.
T his technique may be reconfigured to a
standby redundancy technique by al tering
the switching arrangement to activate
the el ements as they are switched into
the circuit.
(O perating Redundancy)
-E *1
R = e
A ssuming error detector and
switching rel iabil ity is 1 .0 .
where
n = number of paral l el el ements
x = fail ure rate
R = rel iabil ity
x fail ure rate (A + D )
(Standby Redundancy)
R = e
- Xt
where
K
- X t
(1 - e
S
x = el ement fail ure rate
x
s
= fail ure rate of switching
function
R rel iabil ity
DI SA DVA NT A GES
t Del ay due to sensing and switching
t Redundancy gains are l imited by
fail ure modes of sensing and
switching devices
I ncreased compl exity due to
sensing and switching
Fig. 4 - 3 8
ST A NDBY REDUNDA NCY
1 9 8
I n the fol l owing fourteen pages, a circuit diagram is given for each
exampl e and the specific rel iabil ity model is provides. A graphic
comparison is provided for each exampl e which il l ustrates the rel iabil ity
for both redundant and nonredundant configurations.
1 9 9
EXA MPLE 1
SI MPLE PA RA LLEL REDUNDA NCY
T his exampl e considers appl ication of simpl e paral l el redundancy
at the circuit l evel centered around a precision regul ated vol tage suppl y.
T he circuit diagram for the basic nonredundant configuration pl us part
fail ure rates are shown in Figure 4 - 3 9 .
i
n
WSf
IB
f * ^ ' 1 r
-Li i fr*"V
-V * f
Part
Resistor, carbon composition
Capacitor, solid tantalum
Transformer, power
Transistor, silicon PNP
Transistor, silicon NPN
Diode, general purpose
Diode, zener
Fail ure Rate
n x(x 1 0 "
6
) nx
1 0 0 .0 0 2 0 .0 20
4 0 .0 3 8 0 .1 5 2
1 0 .0 5 6 0 .0 5 6
1 1 .6 1 .60 0
3 0 .9 8 0 .29 4
6 0 .68 0 .4 0 8
2 0 .8 5 1 .7 0 0
Total 4.2 30
Figure 4 - 3 9 PRECI SI O N REGULA T ED VO LT A GE SUPPLY
20 0
For the nonredundant circuit, the total fail ure rate is given by:
x
T otal
=

l

A
parts
= 4 .23 x 1 0 " fail ures/hour
Using an operating time of 20 0 0 hours, the rel iabil ity for the nonredun-
dant configuration is:
R - e"
Xtotal t
= e"
(4 .23 x 1 0 "
6
)(2xl 0
3
)
R = 0.992
Figure 4-40 shows the configuration for the redundant supply. The basic
circuit is shown within the dotted lines in Figure 4-39.
o~
Basic
Circuit
DIC:
Basic
Circuit
Voltage
Supply
Voltage
Supply
Redundant Circuit Configuration Reliability Block Diagram
R- 2i
h
- e"
2Xt
Mathematical Model
Fig. 4 - 4 0 REDUNDA NT REGULA T ED VO LT A GE SUPPLY
201
Using the mathematical model given in Figure 4 - 4 0 , the rel iabil ity of
the redundant configuration is:
R = l - (l - e"
Xt
)
2
R = 0 .9 9 9 9 3
A s indicated previousl y, the time period used is 20 0 0 hours. A
side- by- side comparison of rel iabil ity versus time for both configurations
is given in Figure 4 - 4 1 for mission times above 20 0 0 hours. Figure 4 - 4 1
uses an expanded time axis pl us a l og scal e on the time axis to provide
greater resol ution between the two curves.
1.0 |
^Simple Parallel
.8
^^W^ \ ^r
Redundant Circuit
b
i
l
i
t
y

0
)

Nonredundant' \
a
v A
or
Circuit \
2
i i i i i i i i^
0
4
I0
5
I0
6
Time (Hrs.) Log Scale
Fig. 4-41
RELIABILITY COMPARISON OF SIMPLE REDUNDANT
AND NONREDUNDANT VOLTAGE SUPPLIES
2 02
EXA MPLE 2
BI MO DA L REDUNDA NCY- - QUA D CO NFI GURA T I O N
T his exampl e examines redundancy at the part l evel . T he exampl e
chosen depicts appl ication of a quad- radundant configuration centered
around a transistor and its associated biasing network. T he advantage
of the quad configuration is that, at the part l evel , it protects
against both open and short fail ure modes. A circuit diagram and a l ist
of fail ure rates is given in Figure 4 - 4 2 for the nonredundant circuit.
-' S/W-
7 \ - ww-
Fail ure Rate
Part n A (X 1 0 "
6
) nA
Resistor, carbon composition 4 0 .0 0 2 0 .0 0 8
Capacitor, ceramic 1 0 .0 3 3 0 .0 3 3
T ransistor, NPN sil icon
1 0 .9 8 0 .9 8 0
1 .0 21 x 1 0 "
6
Figure 4 - 4 2 BA SI C T RA NSI ST O R CI RCUI T
For the circuit shown in Figure 4 - 4 2, the total fail ure rate is:
* T ota1
=
s Vrts
=

l
-
m
*
l0
~* fail ures/hour
Using an operating time of 20 0 0 hours, the rel iabil ity of the circuit
is:
20 3
R

=
^total*
u

e
-(1.021xl0"
6
)(2x 10
3
)
R = 0.9980
This circuit finds wide application in computers and other digital equip-
ment. If 2 5 such circuits were to be used within an equipment and all
were required to operate successfully for 2 000 hours, the reliability
could be expressed by
R = (0.9980)
25
R = 0.9512
Figure 4 - 4 3 shows the circuit diagram for the redundant quad con-
figuration. T he rel iabil ity bl ock diagram and mathematical model are
al so incl uded. Since the quad- redundant circuit is used to protect
against short and open fail ure modes, their probabil ity of occurrence
must appear in the mathematical model . However, for purposes of this
exampl e, both shorts and opens wil l be assumed equal l y l ikel y to occur.
T hus, the mathematical model used here (see Figure 4 - 4 3 ) is greatl y
simpl ified in contrast to a model which incl udes different modal
probabil ities.
Design of the quad circuit incl udes the sel ection of three paral l el
resistors in the col l ector circuit as shown in Figure 4 - 4 3 . I f it is
assumed that the predominant fail ure mode of these resistors is open,
the fail ure of any one resistor wil l have a minimal effect on the power
suppl y vol tage. For simpl icity of cal cul ation, the rel iabil ity of these
three resistors has been considered as part of the basic configuration
rather than separate paral l el redundant el ements.
Using the mathematical model given in Figure 4 - 4 3 , the rel iabil ity
of the quad- redundant configuration is:
R = 2e-
Xt
- e-
4 Xt
R = 0 .9 9 9 9 8
20 4
Transistor
Block
Transistor
Block
Transistor
Block
Transistor
Block
Hf
1^-VW-*
[<l~VW III)
Quad Redundant Building Block
R = 2 e
AT
- e
rXt -
0
-4Xt
Mathematical Model
Fig.4-43QUAD REDUNDANT TRANSISTOR CIRCUIT
205
If 25 such circuits are used, the reliability of the aggregate is given
by
R = (0.99998)
25
R = 0.99959
A graphical comparison of these resul ts for a singl e quad circuit
pl us the aggregate of 25 quad circuits is shown in Figure 4 - 4 4 . A s
described in the previous exampl e, the time scal e has been expanded to
show resul ts for operating times greater than 20 0 0 hours. A l og scal e
is used to provide resol ution between the two curves.
1.0
8h
a .6
is
g
4>
.2
10
A
Quad Redundant
Configuration
/
Norr Redundant
Configuration
J I I L J I L
1.0
.8
fi.6
o
a)
* .4
10= IO
e
(a) Single Element
.2
I0
2
Quad Redundant
y Configuration
Non-Redundant
Configuration
J I L
10'
J I I I
10
s
(b) 25 Elements
Fig. 4-44 COMPARISON OF RELIABILITY FOR QUAD RE-
DUNDANT AND NON-REDUNDANT TRANSISTOR
CIRCUIT
206
EXA MPLE 3
MA JO RI T Y VO T E REDUNDA NCY
T his exampl e presents an appl ication of majority voting redundancy.
I t uses a divider l ogic circuit as the vehicl e to show the appl ication
of redundancy. Divider circuits are frequentl y used in timing appl ica-
tions for computers and space systems. Both the divider and voter cir-
cuit are assumed to be packaged within separate integrated circuits.
Figure 4 - 4 5 presents the l ogic diagram for a \ 8 counter circuit.
r"
/ V
r
E 3
r
c
H
c
1
1!

H
1 ' i > \
I t is assumed that the circuit
shown above is avail abl e as a
singl e integrated circuit.
X = 0 .1 4 xl 0 "
6
fail ures/hour
Figure 4 - 4 5 * 8 CO UNT ER CI RCUI T
For an appl ication within an orbiting satel l ite having a mission
l ife of 4 5 0 0 hours (approximatel y six months), the rel iabil ity for the
nonredundant * 8 counter is given by:
R =
e
"
U
=
e
- (0 .1 4 xl 0 "
6
)(4 .5 xl 0
3
)
R = 0 .9 9 4
Figure 4-46 shows the circuit diagram, reliability block diagram
and mathematical model for the redundant majority voting configuration
for the : 8 counter. A two-out-of-three majority voting circuit
possesses the advantage of output selection. This means that any two
2 07
>>< -
no
O
00
+8 Counter
5-8 Counter
+8 Counter
Counter
Counter
Counter
Majority
Vote
Comparator
(2,3)
^WVO
+6V
-O
Redundant Circuit Schematic
Where X
p
* Failure Rate Of A Single
RêV)[e"
3Xpt
+3e"
2X
^l-e"
X
P
,
)J Counter
Mathmatical Model
X
m
Failure Rate Of The
Comparator Network
Fig. 4-46 TWO OUT OF THREE MAJORITY VOTE REDUNDANT +8 COUNTER
of the three i 8 counters need operate correctl y for a proper output.
T he resistor/transistor networks provide for comparison of i 3 counter
outputs. Shoul d the output of any t 8 counter fail to match that of the
remaining, its output woul d be inhibited.
Using the mathematical model shown in the figure, the rel iabil ity
for the majority voting redundant circuit is given by:
R = e
m
- 3 x t - 2xt - A t
8
p
+ 3 e
p
(1 - e
P
where \ is the total fail ure rate of the majority vote/integrated cir-
P _ 6
cuit comparator and is equal to 0 .0 0 7 x1 0 fail ures/hour.
For an operating time of 4 5 0 0 hours,
R = 0 .9 9 9 9
A graphical comparison of these resul ts is shown in Figure 4 - 4 7 for
mission times above 4 5 0 0 hours. Note al so that the time axis has betn
expanded and a l og scal e used to provide resol ution between the two
curves.
1 .0
Majority
Voting
IO
!
I0
6
I0
7
Fig. 4-47 RELIABILITY COMPARISON FOR REDUNDANCY 8
NON-REDUNDANT 8 COUNTER CONFIGURATION
209
EXA MPLE 4
ST A NDBY REDUNDA NCY
T his exampl e shows an appl ication of standby redundancy invol ving
switching. T his exampl e util izes functional R- F channel s as the vehicl e
by which redundancy is appl ied. I n this particul ar appl ication, the
redundant channel s are isol ated at , the power input and at both the signal
input and output. Switching is accompl ished by MO SFET 's driven by shift
register stages of an address/decode circuit using high vol tage ampl i-
3 0
fiers. Each channel within the redundant configuration consists of:
R- F and associated circuitry
t O scil l ator mixer and associated circuitry
t I F and associated circuitry
Detector and associated circuitry
High vol tage ampl ifier
Shift register
t MO SFET 's
Figure 4 - 4 8 presents a diagram for a singl e (nonredundant) R- F receiver
channel pl us fail ure rates for the various functional circuits. T he
total fail ure rate for the singl e channel is:
A
Channel "
z
Circuits
= 5 2.0 x1 0 fail ures/hour
For a 20 0 0 hour operating time, the rel iabil ity is:
D
_ /
X
ch
t
_ - (5 2.O x 1 0 "
6
)(20 0 0 )
K e
e
R = 0 .9 0 1
Figure 4 - 4 9 shows the circuit diagram, rel iabil ity bl ock diagram
and mathematical model for the two channel redundant configuration. T he
additional circuitry needed to impl ement the switching function and
isol ation between channel s are l isted bel ow. Circuit fail ure rates are
al so given:
21 0
Vcc
Input -
-
RF
27 MHz -
osc
Mixer
27.433
MHz
Detect
Output
(20 KHz)
Output
Circuit Failure Rate (x I0"
6
)
RF Amplifier And Associated Circuitry
Oscillator / Mixer And Associated Circuitry
IF Amplifier And Associated Circuitry
Detector And Associated Circuitry
20.5
8.4
16.2
6.9
52.0
Fig. 4-48 NON-REDUNDANT RF AMPLIFIER CHANNEL
*
f\3
Vcc
Input
Vcc
Input
-o-*o-
-o*~o-
o^
1
Channel
I
T
Channel
2
Reliability Block Diagram Simplified Circuit Block Diagram
H V Amp
m
& n
Shift
Register
*#
HV
Amp
Shift
Register
6o
Q O
<D
,J T*
^ ^
tt-
RF
27MHz
"1
*
ocs
Mixer
27.433
MHz
I
Hc=>H
X
H = H
IF
0.455
MHz
T
^
Detect
Output
20 kHz
I
t*-
J l*
RF
27MHz
^h
osc
Mixer
27.433
MHz
>
a
LtM
T
X
HH
IF
0.4 55
MHz
Detect
Output
20kHz
Redundant Circuit Block Diagram
R
-XCH f[,
+
ii
(
,_.-V)]
Mathematical Model
TU,
3
o
Fig. 4-49 STANDBY REDUNDANT TWO CHANNEL RF RECEIVER
Circuit
Shift register
High vol tage ampl ifier
MO SFET output isol ators
n
Fail ure
x(x 1 0 "
Rate
6
)
rU
1 0 .23 0 .23
1 0 .1 5 0 .1 5
3 2.7 0 8 .1 0
T otal 8 .4 8 (xl O "
6
)
Using the mathematical model shown in Figure 4 - 4 9 , the rel iabil ity
for the standby redundant R- F receiver is:
> * [l > <! - ." * * > ]
R = e
R 0 .9 9 4 9
T he resul ts of both redundant and nonredundant configurations are
compared in Figure 4 - 5 0 .
1 .0
.8
-
^ Redundant
R
e
l
i
a
b
i
l
i
t
y

Non- Redundant
\f^Channel
2
Channel -
i i i
,
I P^
I0
2
10=
Fig. 4-50 RELIABILITY COMPARISON OF REDUNDANT 8
NON-REDUNDANT RF RECEIVER CHANNELS
213
4 .1 .5 Design Simpl ification and A nal ysis
A chieving high rel iabil ity in systems and equipment invol ves the
appl ication of specific efforts and anal yses to simpl ify the design to
account for transients and to minimize component aging characteristics.
I n general , simpl ification without the compromise of performance wil l
enhance rel iabil ity. T ransient pickup and component aging wil l cause
unrel iabl e operation and mal function and, when carried to the extreme,
l ead to overstress and fail ure. A ging manifests itsel f by a draft in
component val ues, accompanied by a spread in tol erance l imits. T hese
fail ure characteristics (as described in Section 2 and depicted in
Figure 2- 1 ) must be taken into account during design and, in particul ar,
when attempting to improve rel iabil ity and extend the useful l ife portion
of the equipment.
T he subsections which fol l ow provide detail ed information and
specific guidel ines on these subjects. Subsection 4 .1 .5 .1 covers Design
Simpl ification, 4 .1 .5 .2 covers Degradation A nal ysis and 4 .1 .5 .3 covers
O verstress and T ransient A nal ysis.
3 2
4 .1 .5 .1 Design Simpl ification
Many compl ex el ectronic systems have subsystems or assembl ies that
operate serial l y. Many of their parts and circuits are in series simil ar
to l inks of a chain such that onl y one l ink need fail to stop the system.
T his characteristic, al ong with the increasing trend of compl exity in
new designs, tends to add more and more l inks to the chain, thus greatl y"
increasing the statistical probabil ity of fail ure.
T herefore, one of the steps in achieving rel iabil ity is to simpl ify
the system and its circuits as much as possibl e without sacrificing
performance. However, it shoul d be noted that because of the general
tendency to increase the l oads on the components that remain, there wil l
be a l imiting point to circuit simpl ification. T his l imit is the val ue
of el ectrical stress that shoul d not be exceeded for a given type of
el ectrical component. Limit val ues can be establ ished for various types
of components as determined by their fail ure rates. I n addition, it
shoul d al so be cl ear that the simpl ified circuit must meet performance
criteria under appl ication conditions (e.g., " worst case" ) as described
21 5
l ater in this subsection (paragraph 4 .1 .5 .3 ). During design reviews,
special attention shoul d be given to determine if al l the circuitry is
required in order to perform the intended function.
Design simpl ification and substitution invol ves several techniques:
(1 ) the use of proven circuits with known rel iabil ity, (2) the substitu-
tion of highl y rel iabl e digital circuitry (where feasibl e), (3 ) the use
of high rel iabil ity integrated circuits to repl ace discrete l umped con-
stant circuitry, (4 ) the use of highl y rel iabl e components wherever
individual discrete components must be used, and (5 ) the use of those
designs which minimize the effects of catastrophic fail ure modes.
T he most obvious way to el iminate fail ure modes and mechanisms of
a part is to el iminate the part itsel f. A l though design simpl ification
is, in general , practiced, del iberate attempts to remove parts from
establ ished designs may not be.
For instance, digital design can have extraneous l ogic el ements
incorporated within it. However, minimization techniques, such as by
Bool ean reduction, are wel l establ ished and can be powerful tool s for
incorporating rel iabil ity into a design through simpl ification. For
exampl e, consider the appl ication of Bool ean reduction to a l ogic design
containing superfl uous el ements, as shown in Figure 4 - 5 1 . T he original
l ogic diagram is represented by this figure and the corresponding Bool ean
expression is
D = C n(A UB)Un(BUC)UBn(A UC) (1 )
T wo equival ent reductions are found for this equation. T he sum- of-
products form
D = (A HB)U(A riC)U (BHC) (2)
is the basis for Figure 4 - 5 1 b, which is simpl er than that of Figure
4 - 5 1 a. Stil l simpl er is the product- of- sums form of reduction
D - (A UBUC) fl (UBUC) (3 )
which is shown in Figure 4 - 5 1 c. Simpl ification can al so incl ude the
determination and removal of items that have no functional significance.
21 6
(a) LO GI C DI A GRA M FO R
EQUA T I O N 1
(b) LO GI C DI A GRA M FO R
EQUA T I O N 2
l^h_
O
(c) LO GI C DI A GRA M FO R
EQUA T I O N 3
LEGEND
A , B, C
A , B, C
D
= " A ND" Logical Gate
= " O R" Logical Gate
= Logical I nverter
= I nputs
= I nversions of I nputs
= O utput
Fig. 4 - 5 1 BO O LEA N REDUCT I O N O F LO GI C ELEMENT S
21 7
T he optimization by simpl icity can permit a high degree of rel iabil ity
by making success dependent upon fewer items. T hus, the number of poten-
tial fail ures is reduced. I nasmuch as functioning is now dependent upon
fewer items, care is necessary to insure that unusual performance is not
required of these items. A ny simpl ification wherein the operation of the
remaining parts is not adversel y al tered wil l yiel d a rel iabil ity improve-
ment.
I n addition, efforts shoul d al so be directed toward the reduction of
the critical effects of component fail ures. T he aim here is to reduce
catastrophic fail ures to, at most, a degradation in performance. A s an
exampl e, consider Figure 4 - 5 2, which il l ustrates the design of fil ter
circuits. A l ow- pass design, as shown in Figure 4 - 5 2a, can invol ve
either series inductances or shunt capacitances. T he l atter is to be
avoided if shorting is the predominant fail ure mode pecul iar to the
appl icabl e capacitor types (e.g., sol id tantal um), since a catastrophic
fail ure of the fil ter coul d resul t. Simil arl y, in the high- pass fil ter
of Figure 4 - 5 2b, the use of a shunt inductor is superior to the use of
a series ceramic capacitor, for which an open is the expected fail ure
mode. Here, the sol id tantal um capacitor, if appl icabl e to the el ectrical
design, coul d be a better rel iabil ity risk, since its fail ure woul d onl y
resul t in noise and an incorrect frequency, instead of a compl ete l oss
of signal .
3 3
4 .1 .5 .2 Degradation A nal ysis
T he fail ure rate data which appears in this handbook (and in MI L-
HDBK- 21 7 B) is not based on part changes due to aging. Component parts
such as resistors and capacitors are, however, known to change with age
and stress so that degradation due to aging can represent a significant
fail ure mode in a compl ex, l ong l ife system (see Figure 2- 1 , Section 2).
T wo exampl es of part parameter change due to aging are shown in
Figure 4 - 5 3 a through 4 - 5 3 d. T hese figures show the average change from
initial val ue versus time and the standard deviation of change from
initial val ue versus time for resistance of a resistor type and the
capacitance of a capacitor type. T he resistor data is pl otted for two
stress l evel s whil e the capacitor data is pl otted at rated vol tage. T he
21 8
(a) LO W- PA SS FI LT ER
c^ rv

rww
<
0
Input
Y
i
Y
2
Y
n
Output
o ii < < i o
x
l h
I nput O utput
LEGEND: T - , for i = l , 2, ..., n: Limited to R and C el ements
in various acceptabl e combinations.
(b) HI GH- PA SS FI LT ER
O utput
C
l
C
2
a \( m \(
C
n
K | 11 K
Input f
7
r
O o 1
Z
n
a
Output
0
LEGEND: L, for i = l , 2, ..., n: Limited to Rand L el ements
in various acceptabl e combinations.
Fig. 4 - 5 2 A LT ERNA T I VE FI LT ER DESI GNS
21 9
~ +15
<
_ + 0.5
o
1
5 0
I -0.5
E
o
^ - 1.0
5
- 15
&
o
5
< -2.0
Fig A
5<ft St ress
100' , Seres 1
0.5 1.0 15 2.0 2 5
Times (Hours x |rf)
Average Change From Initial Resistance
For MIL-R-11 Carbon Composition
Resistors At 70*C Ambient And
Various Electrical Stresses
o
o
.35
.30
.25
.20
.15
.10
.05
0 0.5 1.0 15 2.0 2.5
Time (Hours xlO
3
)
Fig B Standard Deviation Of Change From
Initial Resistance For MIL-R-II
Carbon Composition Resistors At 70*C
Ambient And Various Electrical
Stresses.
ioa , Stres i
5 0', Stres i
> 1-0.6
I +0.4
- +0.2
o
-0 2
2
0.4
< -0.6
-0.8
Fig C
) 0.5 1.0 15 20 25
Time (Hours x I0
3
)
Average Change From Initial Capacitance
For MIL-C-20 Temperature Compen-
sating Ceramic Capacitors At Rated
Voltoge And 85*C Ambient
0.7
* 0.6
o
0.5
2
0.4
5 0.3
2 0.2
^ 0.1
0.5 1.0 1.5 2.0
Time (Hours xlO
3
)
2.5
FigD Standard Deviation Of Change From
Initial Capacitance For MIL-C-20
Temperature Compensating Ceramic
Capacitors At Rated Voltage And
85 Ambient
Fig. 4-53 DEGRADATION CHARACTERISTICS DUE TO AGING
220
resistor data was determined from l ife test data representing a total of
1 5 20 tested parts from three manufacturers, whil e the capacitor data
came from l ife test data representing a total of 3 4 0 tested parts from
two manufacturers. A nother type of resistor presentation (Figure 4 - 5 4 )
shows the initial tol erance and nominal val ue for a parameter, and pl ots
the change in these parameters under one specified stress and temperature
condition for a period of time.
T here are basical l y two approaches to reduce part variation due to
aging. T hese are:
(1 ) Control of device changes to hol d them within l imits for a
specified time under stipul ated conditions.
(2) T he use of tol erant circuit design to accommodate drifts
and degradation in time.
I n the first category, as described in Subsection 4 .1 .1 , the technique
that is basical l y used is to precondition the component (burn- in) so
that it undergoes significant change earl y in l ife but then l evel s off
and becomes rel ativel y constant for the remainder of l ife. I n addition,
there is detail ed testing and control of the material s going into the
part, al ong with strict control of processes.
I n the second category, the attempt is made to design circuitry
which is inherentl y tol erant to part parameter change. T wo different
techniques that are practiced here are: (1 ) the use of feedback to
el ectrical l y compensate for parameter variation and thus provide for
performance stabil ity, and (2) the design of circuitry that provides
the minimum required performance, even though the performance may vary
somewhat due to aging. T he l atter approach makes use of anal yses proce-
dures such as
t worst case anal ysis
parameter variation
t statistical design
t transient design
stabil ity anal ysis.
221
.08
.04
0
_-<
N-60 1/32 Watt Dissipation
T I2 5' C
- ^N, *'
Vendor A
8 1.0 1.2 1.4 1.6
Hours x I0
3
1.8 2.0 2.2
<
.12
.08
.04
0
-.04
N-60
T- I25C >
. 1/32 Watt f'
m
Dissipation^ '
s
V''
I 1 l 1 1 I 1 1 1 1
Vendor B
0 .2 .4 .6 .8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
Hours x 10
s
a:
<
5
.20
.10
0
N - 30 1/16 Watt Dissipation
T - 125"C
-.10
i i i i i i i i i i
< D .2 .4 .6 .8 1.0 1.2 1.4 1.6 1.8 2.0 2.
Vendor A
Hours x I0
3
<
.20
10
N 30 1/16 Watt Dissipation
T - I25
-
C ^ -*-- -
*
0
-.10
i i i i i i
1
~ -
1 1
Vendor B
0 .2 .4 .6 .8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
Hours x I0
3
Fig . 4-54 RESISTANCE CHANGE OF 1/8 WATT, FIXED METAL FILM
RESISTORS DURING 2000 HOURS OF OPERATION
(PERCENTAGE CHANGE IN RESISTANCE)
2 2 2
T here are al ternate ways to proceed. O ne way is to view the overal l
circuit specification as a fixed requirement and to then determine the
al l owabl e l imits of each part parameter variation. Each part is then
sel ected accordingl y. T he other way is to examine the amount of parameter
variation expected in each part (incl uding the input) and then to deter-
mine the output under worst case combination, or other type of combina-
tion. T he resul t can then be appraised with regard to determining the
probabil ity of surviving degradation for some specified period of time.
Many of these anal ysis methods and their associated mathematical model s
have been computerized and are avail abl e to perform specific anal yses of
the type mentioned. T abl e 4 - 3 8 , taken from MI L- HDBK- 21 7 A , indicates the
features of some of these computer model s.
I n worst case anal ysis, direct physical dependence shoul d be taken
into account. For exampl e, if a vol tage bus feeds several different
points, the vol tages at each of the several points woul d not be treated
as variabl es independent from each other. Likewise, if temperature
coefficients are taken into account, one part of the system shoul d not
be presumed to be at the hot l imit and the other at the col d l imit at
the same time- - unl ess of course it is physical l y reasonabl e that it be so.
I n the fol l owing discussion, it is assumed that these correl ations are
taken into account wherever possibl e. A yery general boundary condition
for the anal ysis is that the circuit or system shoul d be constructed
according to its specifications and that the anal ysis proceeds from there.
Consider now the absol ute worst case anal ysis. I n the absol ute worst
case anal ysis, the l imits for each independent parameter are set without
regard to other parameters or to its importance in the system. T he
position of the l imits is usual l y set by engineering judgment. I n some
cases, the engineer may perform several anal yses with different l imits
for each case to assess the resul t prior to fixing the l imits.
T here can al so be modified worst case anal yses devel oped because of
the pessimism of the absol ute worst case anal ysis. I t is not worthwhil e
to go into al l of these, but a typical one uses the fol l owing method for
setting the l imits: Critical items are given l imits as in absol ute worst
case anal ysis and the rest of the items are given l imits of their pur-
chase tol erance.
223
T abl e 4 - 3 8 T YPI CA L CI RCUI T A NA LYSI S T ECHNI QUES
A nal ysis
T ype of A nal ysis
Mathematical Model Parts' Data O utput I nformation T ype of Circuits
T echnique Necessary Necessary Received Suitabl e
MA NDEX Worst- Steady state ac and Circuit's simul tan- Nominal val ue and Worst- case val ue of Cl ass A ampl ifiers.
Case Method dc worst- case eous equations or end- of- l ife l imits output variabl e com- power suppl ies, al l
matrix equation pared with al l owabl e
val ue
biasing (dc) circuits,
l ogic circuits, etc.
Moment Method Statistical Circuit's simul tan- Mean (or nominal ) T he mean and variance A ny circuit for which
eous equation or val ue and standard of the distribution a mathematical model
matrix equation deviation or vari-
ance of each input
parameter and cor-
rel ation coeffi-
cients when they
exist
of each output param-
eter
can be derived
Monte Carl o Statistical ; pre- Circuit's simul tan- Compl ete distribu- 20 cel l histogram for A ny circuit for which
Method dicts output vari- eous equation, tion of each I nput each output variabl e a mathematical model
abl e distribution at matrix equation, parameter at a time can be derived
any time; steady transfer function
state ac or dc (any mathematical
(transient may be representation in-
performed if formul a cl uding input
is avail abl e) parameter
VI NI L Method VI NI L Method Piece- wise l inear A ppl ication curves I nput characteristics Digital ; l inear
equival ent circuits over operating and
environmental
ranges al ong with
drift data
(maximum and mini-
mum), transfer char-
acteristics (max. and
min.), output charac-
teristics (max. and
min.)
anal og
Parameter General , determines Circuit's simul tan- A nominal val ue for Fail ure points for A ny steady state ac
Variation al l owabl e parameter eous equation or each parameter and one and two- at- a- time or dc circuit
Method variation before matrix equation a range (in per parameter variation
design fail s to cent) Schmoo pl ot deter-
function. Considers mines safe operating
both one and two- at- envel ope for design
a- time parameter
variation
SPA RC (A EM- 1 , DC anal ysis, ac Equival ent circuits, Nominal (mean);
Minimum f- 3 o);
Sol ution of unknown A l l types, dc, bias,
A EM- 2, A EM- 3 ) anal ysis; transient equations, or in fl oating point switching, nonl inear
System of anal ysis matrices Maximum (+ 3 o) fixed decimal output effects, ac response
Programs and distributed
parameter circuit
servo l oops and feed-
back systems
SCA N DC Linear static, Linear or nonl inear Nominal (mean); Nominal sol utions, A l l circuits that can
Method nonl inear static equations in appro- Minimum (- 3 CT );
Maximum (+ 3 o)
partial derivatives be described by
priate matrix form of unknowns with re- l inear and nonl inear
with reasonabl e es- spect to knowns, equations
timates of val ues of worst case val ues,
the unknowns affects and the probabil ity
by nonl inear equa- of the unknowns be-
tions ing outside of spe-
cified l imits
SCA N A C Linear sinusoidal Simul taneous compl ex Nominal (mean); Famil ies of frequency A ny l inear circuit
Method dynamic anal ysis variabl e equations Minimum {-3a); response curves; sta- that contains fre-
with the real and Maximum (+ 3 o) tistical variation of quency- dependent
the imaginary parts unknowns at any sel - devices and which 1 s
of the equations ected frequency; + 3 o, driven or I s signi-
separated - 3 o and mean of un-
knowns vs frequency
(assumed)
ficantl y anal yzed
with sinusoidal
driving functions
SCA N Linear and nonl inear Simul taneous differ- Nominal parts data; T ime response of A l l circuits for
T ransient transient anal ysis; ential equations al ternate sets of l inear or nonl inear which the transient
Method differential equa- parts' data; parts' systems determining effects
tion sol ution data for the
switched states
can be model ed
224
I n any worst case anal ysis, the val ues of the parameters are adjusted
(within the l imits) so that circuit performance is as high as possibl e,
then readjusted so it is as l ow as possibl e. T he val ues of the parameters
are not necessaril y set at the l imitsthe criterion for their val ue is
to make the circuit performance an extreme. T he probabil ity of this
occurring in practice depends on the l imits which were set by the engineer
at the beginning, on the probabil ity functions of the parameters, and on
the compl exity of the system being considered.
O ne argument in favor of absol ute worst case anal ysis (as opposed
to a statistical anal ysis) is that many digital el ectronic systems have
many simil ar parts, each of which must have such a high probabil ity of
working properl y, that a statistical anal ysis wil l , for practical pur-
poses, turn out to be an absol ute worst case anal ysis, and the absol ute
worst case anal ysis is much simpl er and depends on fewer assumptions.
Computer routines are avail abl e for performing these anal yses on
el ectronic circuits. General l y speaking, the curve of circuit performance
versus each independent parameter is assumed to be monotonic and a num-
erical differentiation is performed at the nominal val ues to see in which
direction the parameter shoul d be moved to make the circuit performance
high or l ow. I t is al so presumed that this direction is independent of
the val ues of any of the other parameters as l ong as they are within
their l imits. I f these assumptions are not true, a much more detail ed
anal ysis of the equations is necessary before worst case can be performed.
Essential l y, this invol ves generation of a response surface for the cir-
cuit performance which accounts for al l circuit parameters.
4 .1 .5 .3 O verstress and T ransient A nal ysis
Semiconductor circuit mal functions can arise from two general
sources: transient circuit disturbances and component burnout. Gener-
al l y, transient upsets are the control l ing factor, because they can
occur at much l ower energy l evel s.
T ransients in circuits can prove troubl esome in many ways. Fl ip-
fl ops and Schmitt triggers can be inadvertentl y triggered, counters can
change count, memory can be al tered due to driving current or direct
magnetic fiel d effect, one- shot mul tivibrators can pul se, the transient
225
can be ampl ified and interpreted as a control signal , switches can change
state, semiconductors can l atch- up in undesired conducting states that
require reset, etc. T he effect can be caused by transients at the input
terminal s, output terminal s, on the suppl y terminal s, or on combinations
of these. T ransient upset effects can be general l y characterized as
fol l ows:
Circuit threshol d regions for upset are very narrow. T hat is,
there is a yery smal l amount of vol tage ampl itude difference
between the l argest signal s which have no probabil ity of causing
upset and the smal l est signal s which wil l certainl y cause upset.
T he dc threshol d for response to a very sl ow input swing is
cal cul abl e from the basic circuit schematic. T his can establ ish
an accurate bound for transients that exceed the dc threshol d for
times l onger than the circuit propagation del ay (a manufacturer's
specification).
t T ransient upsets are remarkabl y independent of the exact wave-
shape, and depend l argel y on the peak val ue of the transient
and the time duration over which the transient exceeds the dc
threshol d. T his waveform independence al l ows rel ativel y easy
experimental determination of circuit behavior with simpl e wave-
forms (square pul se).
T he input l eads (or signal reference l eads) are general l y the
ones most susceptibl e to transient upset.
I t can further be noted that standard circuit handbook data can
often be used to gauge transient upset susceptibil ity. For exampl e,
square pul se triggering vol tage is sometimes given as a function of
pul se duration. A typical pl ot for a l ow l evel integrated circuit is
shown in Figure 4 - 5 5 .
A s indicated above, it is possibl e for semiconductors to l atch up
in undesired conducting states that require reset (power removal ).
T here are various ways in which this can happen. O ne common way is shown
in Figure 4 - 5 6. T his shows an open- base transistor circuit with col l ec-
tor current as a function of col l ector- emitter vol tage. T he l oad l ine
for a particul ar col l ector resistance is shown. T he col l ector current
226
o
o
>
_L -L JL
2 5 50 75
Time(nsec)
Fig. 4-55 SQUARE PULSE TRIGGERING VOLTAGE
FOR TYPICAL LOW LEVEL INTEGRATED CIRCUIT.
VCEO
' CE 'cc
Fig. 4-56 LATCH UP RESPONSE
is normally low (operating point a). H owever, a transient can move the
operating level to point b, where the circuit becomes latched up at a
high current level. The signal required to cause this event can be
determined by noting that the collector-emitter voltage must be driven
above the V(collector-emitter breakdown) voltage.
Another mode of latch-up can occur when a transistor is grown in a
semiconductor substrate, for example, an n-p-n transistor in a doped
p-substrate. Under unusual voltage or gamma radiation stress, the
device can act like an n-p-n-p or SCR device, latching into conduction.
2 2 7
(For this reason, integrated circuits in missil e and aircraft systems
usual l y have diel ectric isol ation rather than junction isol ation.)
O verstress
A l though various system components are susceptibl e to damage, the
most sensitive of these tend to be semiconductor components. T his data
wil l be emphasized first and wil l then be fol l owed by data on resistors
and capacitors. A l so, the transistor data given bel ow are immediatel y
fol l owed by suggestions for transient suppression.
T ransistor O verstress
I n a vul nerabil ity study, conducted by Braddock, Dunn and McDonal d
(BDM) , a considerabl e amount of data on semiconductor fail ure from
overstress was compil ed. T he test procedure was approximatel y as
fol l ows. T he BDM studies used square pul se testing with pul se durations
from 1 0 0 nsec to 20 usec. I n the course of the studies, it was deter-
mined that reverse diode current and reverse base- emitter current had
the l owest fail ure threshol ds, so these were studied rather extensivel y.
For simpl icity, the col l ector was l eft open during transistor testing.
T his restriction did not grossl y affect the resul ts, since col l ector
current is a second- order effect. BDM found that fail ure was al most
al ways due to junction hot spots, al though metal l ization and bond damage
coul d sometimes al so occur. T he criterion for fail ure was a 1 5 % decrease
in 3 or zener vol tage, al though this was not crucial since the difference
between the l evel where sl ight degradation occurred and compl ete fail ure
occurred was onl y about a hal f an order of magnitude. T he 2N2222 was
then extensivel y tested for statistical anal ysis. A fter testing approx-
imatel y 7 0 0 of these devices, it was found that the average power fail ure
l evel was
h o.it"
0
-
4 8
where P is the power (W) and t is the time (sec). T hese data were spread
over about one order of magnitude as indicated in Figure 4 - 5 7 . T here
appeared to be no significant variation due to different manufacturers or
different geometries. Data for other types of transistors are shown in
Figure 4 - 5 8 .
228
IO
4
CM
' I0
3
\
*
>
S io
2
Q
*
o
a.
-^qTTT] 1I I I llll| I I llll| 1I I I 11111 1 II | I 1111 1TTTTTq
T
m
-l4l5C
T
m
575' C
T
m
I4I5C Over 1/10 Area
s. T
m
*675C (Davies 8 -_
Gentry)
J i '"mi i i ii 11 ill i i 111 in ' ""I i MM ml i i 11 mi
IO"
2
0.1 I IO
2
10 IO
2
Time (/xsec)
Fig. 4-57 2N2222 OVERSTRESS FAILURE DATA
IO
4
IO
4
CM
E
i
- ,0
s
l
IO
2
10
x> I i i 11 ~l I i i 1111 r i i i 111 1ii i i in
T
m
-I4l5-C
T
m
-l4l5C Over
1/10 Area
J I I I I I III I I I I Mill I I I I I I III i i i i i in
IO"
2
0.1 I 10
Time (/isec)
IO
2
Fig. 4-58 OVERSTRESS FAILURE DATA FOR EIGHT TRANSISTORS
229
T ransient Suppression for Semiconductors
T here are many techniques avail abl e for transient suppression. Some
of these are il l ustrated in Figure 4 - 5 9 through 4 - 64 , and appl y in the
fol l owing areas:
T ransistors
t SCR's
CMO S
t T T L Protection
Diode Protection
T hese techniques are representative of general l y appl icabl e methods and
are not intended as an exhaustive l ist.
Resistor O verstress
3 5
Sandia Laboratories has performed pul se testing on a l imited
quantity of carbon composition, metal fil m and wire wound resistors.
T he test resul ts are indicative of the transient vul nerabil ity of these
particul ar devices. T he tests indicated that these three types of
resistors were abl e to withstand pul se powers far in excess of their dc
power rating. (T he power ratings of the resistors ran from h watt
carbons to 1 0 watt wire wound.) Wire wound resistors withstood pul se
power of more than 5 0 0 0 times their dc rating, metal fil m resistors more
than 1 0 0 0 times, and carbon composition resistors more than 5 0 0 times
(pul se widths <_ 20 usec).
T he test conditions were approximatel y as fol l ows. High vol tage
pul ses were suppl ied directl y across the resistor and an el ectronic
counter was used to count the number of pul ses appl ied. T he average
power of the pul se was equal to or l ess than the average power rating
of the resistors. T he duty cycl e was l ess than one percent. T he pul se
waveform was rectangul ar, as shown in Figure 4 - 65 . (Pul se waveform was
not al tered in any noticeabl e way during tests.) T est resul ts are shown
in Figures 4 - 66 through 4 - 68 .
T he maximum safe vol tage (E
p
) given therein represents the vol tage
at which the resistor did not change in val ue during a minimum of 1 0 0
pul ses. T he fol l owing exampl es demonstrate possibl e uses of these resul ts,
23 0
C,=t.l/xf
(A) Current Limiting Resistor(R
) And
Transient Suppression Capacitor (Cj)
r-^WV
C|jV
i
D
Z
(C)Transient Limifer(R
B
,D|,D2) And
Transient Suppression Capacitor (C|)
R
R
B
Eq
f
D
Z2
(E) Reverse And Forward Transient
Limiter (Rg,D
Z
|,D
Z
2) And Transient
Capacitor
C|=pl/xf
'VVVl
4 1
(B) Low Gain Filter(Rg.Cg) And Transient
Suppression Capacitor (Ci)
'Z2
F-&T
(
B
WV 1>
D
Z
I$
RorL
=J=>f
(D) Transient Suppression For Base And
Collector (R
B
,D
Z
|,D
Z2
)
r
(F) Complete Transient Protection
(R
B
,D
|>
D
2
,D
Z
,C
|
)
Fig. 4-59 TRANSISTOR PROTECTION
231
SCR
(A) Integrator (Lg,R) Serves To Limit The Initial Surge Current
When The Gate Is Turned On. Diode Dz Protects Against Volt-
age Transients. The PIVof the SCR Should Be Chosen To Pro-
vide Sufficient Anode To Cathode Protection.
A
SCR
(B) Resistor RQ Limits The Gate Current Of The SCR and Diode Dz
Protects The Gate Against Voltage Transients
Fig.4-60 SCR PROTECTION
232
Input
Vz
r
<
30V
I
. *
V
DD
CMOS
-Vss
Output
a) Single Diode Clamps Positive Input Voltage To V
00
And Negative
Input Voltages To V
DD
- 30 Volts Thus Preventing Gate Breakdown
T
+
V
80V
Input
Dz2
30V
I
*S
1.5 K
00
CMOS
t
DZ3
30 V
Output
1C|
-Vss
b) Diode D
Z2
And D
Z3
Clamps Positive Input To V
D0
And Negative
Input To V
ss
Diode D
Z(
And R
s
Provide Time Delay And
Current Limit Action. Capacitor C, Prevents High Frequency
Transient From Entering The Device Through The Power Supply.
Fig . 4-61 CMOS PROTECTION
a) Store Unused Devices In Conductive Foam Or Use Any Method That
Shorts All Leads Together.
b) Use Grounded Soldering Iron.
c) Ground All Test Equipment.
d) All Unused Device Inputs Should Be Connected To V
DD
Or V
ss
.
e) All Low Impedance Equipment Should Be Disconnected From Device
Inputs Before DC Power Supplies Are Turned Off.
Fig .4-62 CMOS HANDLING PRECAUTIONS
233
v
cc
O +
D
i i
r -L
Cl-j- J
M
I
TTI
T
Output
(A) Diode D
(
Presents Input From Becoming Greater Than V
cc
And
Capacitor Cj Absorbs High Frequency Transients On The Power
Supply Line
Input f Output
(B) Diodes D, And Dp Clamp The Positive Input To V
cc
And The Neg-
ative Input To Ground. Diode D Prevents The Output From Going
Below Ground C| Absorbs High Frequency Transients On The Power
Supply Line.
Fig 4 - 63 TTL PROTECTION
234
Z= .Ol/xf
(B) Surge Current Limit Resistor (R
(
) and Transient
Suppression Capacitor (Cj)
Note= The Best Protection For A Diode Is Sufficient
Overrating Of The Reverse Breakdown Voltage
(PIV), Forward Surge Current (l
s
) And Power
Disipation Capability (P)
Fig. 4 -64 DIODE PROTECTION
235
i / rur
r w
1 1
Ep - Peak Pulse Voltage
Q.
J
u
Ip - Peak Pulse Current
PW - Pulse Width
C
c
)
l/PRF - Period Of Pulses
J
Power Of The Pulse Or
Energy Of The Pulse
:
Average Power Of The Pulse
Duty Factor Of The Pulse
Ppulse
8
(Ip) x (Ep)
Ppulse * (Ep)
2
/R
Epulse " (Ppulse) x(PW)
Pavg. (Ppulse) x (PW)/(I/PRF)
DF PW/O/PRF)
Fig. 4-65 PULSE WAVEFORM
236
(0)
(b)
(c)
45 k ^ 10 Watts
O
>
30 k
/ ^** 5 Watts
LU
15 k
Ly 3 Watts
i 1 i 1 i 1 i 1 i
0 10k 2 0k 30k 40k 50k
Resistance (Ohms)
35kV
^10 Watts
to
30 k
o
>
2 0 k
- /
5 Watts
a.
LU
3 Watts
10k
1 i 1 .1.1.
Ik 2 k 3k 4k 5k
Resistance (Ohms)
/I0 Watts
2 5 k
2 0 k
5 Watts
>
15k
10 k
3 Watts
a.
LU
5k
-
i 1 1 . 1 . 1 i
0 2 00 400 600 800 1000
Resistance (Ohms)
Fig 4-66 WIRE-WOUND RESISTORS
237
(a)
50 k
2 Watts
40 k
30 k
1 Watt
o
>
\c
Q-
20 k
10 k
V
1/2 Watt
" . I 1 i 1 i
i.i.
0 0.5M IM I.5M 2M 2.5M
Resistance (Ohms)
(b)
30 k
_ 20 k
10k
I Watt
1/4 Watt
100k 200k 300k 400k 500k
Resistance (Ohms)
(c)
4kV
3 kV
2 kV
Watt
2k 4k 5k 8k 10k
Resistance (Ohms)
Fig. 4-67 METAL FILM RESISTORS
233
(a)
20kV
1 Watt
y^
l5kV
f
CO
1/2 Watt
*o
10 kV
r -
^*
~ f ^^^^^" 1/4 Watt
UJ
r y^
5 kV
i 1 i 1 i 1 i 1 i
0 200k 400k 600k 800k I Meg
Resistance (Ohms)
(b)
CO
4-
20 k
15 k
10 k
5 kV
I Watt
20k 40k 60k 80k 100k
Resistance (Ohms)
Fig4-68 CARBON-COMPOSITION RESISTORS
239
Exampl e 1
Consider an appl ication that requires a resistor to withstand a
pul se of 2 kV at a pul se width of 20 ysec with a resistance val ue of
2.0 Kft From Figures 4 - 66 through 4 - 68 , it is seen that the fol l owing
resistors meet this requirement.
wire wound, 3 W or l arger
metal fil m, 1 W or l arger
t carbon composition, 1 W or l arger.
Exampl e 2
Consider an appl ication that requires a resistor to withstand a
pul se of 1 0 kV at a pul se width of 20 ysec with a resistance val ue of
1 .0 Kn. From Figures 4 - 66 through 4 - 68 , it is seen that the fol l owing
resistors meet this requirement.
wire wound, 3 W or l arger
metal fil m, 1 W or l arger
t carbon composition, 1 W or l arger.
Note that if the pul se width is narrower than 20 psec, the recommended
maximum pul se vol tage may be exceeded. I f, however, the pul se width is
wider than 20 psec, then the pul se vol tage must be reduced. Figure 4 - 69
shows how the pul se width affects the maximum pul se vol tage for one
particul ar case.
Further, it is interesting to note the rel ationship between resistor
survival and pul se width. From Figure 4 - 69 , it is seen that the narrower
the pul se, the l onger the l ife of the resistor. For exampl e, a pul se of
8 0 0 V can open the resistor in l ess than 1 0 pul ses at a pul se width of
1 0 ysec; on the other hand, the resistor remains undamaged at the end of
1 0 0 pul ses for a pul se width of 1 ysec.
Capacitor O verstress
A l though semiconductor devices, such as diodes and transistors,
general l y tend to be the ones most susceptibl e to fail ure from transient
overstress, the overstress mechanism can al so be responsibl e for fail ure
to other devices. T he transient vol tage tol erance and fail ure l evel of
two types of l ow power l ow vol tage capacitors are discussed in this
24 0
900 V
800 V
700 V
o 600 V
J
5 00 V
400 V -
300 V
R = 205-Ohms IRC
MEB Metal Film
10 IO
k
10* 10' I0
:
Number Of Pulses To Open Resistor
Fig.4-69 PULSE WIDTH VS. MAXIMUM PULSE VOLTAGE
section. T he damage fail ure l evel s of these devices are compared to
other typical el ectronic components, as indicated in T abl e 4 - 3 9 .
T he data shown here are based on tests of two types of common l ow
3 6
vol tage capacitors, and were conducted by Harry Diamond Laboratories.
T he devices under test were ceramic disc capacitors and sol id tantal um
el ectrol ytic capacitors. T he test procedure was approximatel y as fol l ows.
T he capacitors were singl e pul se tested and the capacitance, dissipation
factor, and l eakage resistance was measured before and after each pul se
appl ication in order to correl ate the parameter change. T he open circuit
test pul se v/as varied in width from 1 to 3 0 psec, with the ampl itude
varying from the 5 0 V no- fail pul se in the case of the tantal ums in
reverse pol arity, to the 1 0 kV pul se needed to break down the ceramics.
T he rectangul ar pul se was appl ied through both a l ow impedance (1 n) and
a moderate impedance (1 0 0 p.) network in order to eval uate the effect of
24 1
T abl e 4 - 3 9 DA MA GE ENERGI ES
Component Energy (yj)
Point Contact Diodes
1 N8 2A - 2N69 A
I ntegrated Circuits
yA 7 0 9
Low Power T ransistors
2N9 3 0 - 2N1 1 1 6A
High Power T ransistors
2N1 0 3 9 (Ger)
Switching Diodes
1 N9 1 4 - 1 N9 3 3 J
Zener Diodes
1 N7 0 2A
Rectifiers
1 N5 3 7
Sol id T antal um Capacitors
0 .7 - 1 2
1 0
20 - 1 0 0 0
1 0 0 0 and up
7 0 - 1 0 0
1 0 0 0 and up
5 0 0
61 and up
T ypical energy fail ure l evel s of semiconductors compared
to the energy required to damage l ow vol tage tantal um
capacitors. Based on a 1 ysec square damaging pul se.
current l imiting. T he effects of charge rate were al so examined by the
use of ramp testing. (I n ramp testing, the capacitor onl y partial l y
charges during the duration of the pul se.) T he ramp vol tage pul se method
gave more consistent, though essential l y the same, fail ure l evel s, as
indicated in T abl e 4 - 4 0 .
T he test matrices for the ceramic and the sol id tantal um capacitors
are shown in T abl es 4 - 4 0 and 4 - 4 1 , respectivel y. Figure 4 - 7 0 is a pl ot
of the reverse pol arity breakdown energies for two different val ues of
sol id tantal um capacitors.
24 2
T abl e 4 - 4 0 CERA MI C CA PA CI T O RS
Capacitance WVDC Wave Shape
Mean
Breakdown
Vol tage
Standard Deviation
in Breakdown Vol tage
Minimum
Breakdown
Vol tage
5 0 pf 1 0 0 0 rectangul ar 9 67 9 .9 1 69 8 .0 7 3 0 0 .0
ramped 1 0 28 7 .5 1 61 9 .9 7 3 0 0 .0
both 9 9 9 8 .9 1 664 .6 7 3 0 0 .0
1 0 0 0 pf 1 0 0 0 rectangul ar 60 9 7 .2 5 3 8 .9 5 4 7 2
ramped 5 8 9 1 .0 5 4 1 .2 4 9 0 0
both 5 9 7 1 .6 5 4 6.8 4 9 0 0
T abl e 4 - 4 1 SO LI D T A NT A LUM CA PA CI T O RS
Breakdown Vol tage
Pol arity Capacitance WVDC Mean
Standard
Deviation Minimum Pul se Width
Number of
T ested
Devices
Forward 0 .0 0 4 7 pf 3 5 1 5 4 .5 4 3 .1 9 0 .0 2.6 & 4 ps 1 9
Forward 2.2 pf 3 5 1 5 4 .5 4 3 .1 9 0 .0 4 .8 & 3 0 ps 24
Forward 2.2 pf 1 5 1 4 2.6 4 8 .7 68 .0 3 .0 & 3 0 ps 1 7
Reverse 0 .0 0 4 7 pf 3 5 1 0 6.0 1 9 .7 65 .0 1 .0 & 1 0 ps 1 5
Reverse 2.2 pf 3 5 1 0 6.0 1 9 .7 65 .0 3 .0 & 3 0 ps 1 5
Reverse 2.2 pf 1 5 5 3 .7 6.5 4 3 .0 3 0 MS 6
24 3
I0
!
IO<M
la
m
c
l
10
2 _J
10
H 1 I I I III H 1 I I I I 11
2.2/xf
0.0047 fJLf
H 1 I I I III H 1 I I I III H 1 I I I III
10
-i
10 IO
5
Time (^.secs)
Fig 4-70 PLOT OF REVERSE ENERGY FOR FAILURE FOR
THE 35 WVDC SOLID TANTALUM DEVICES
244
I n general , the nonpol ar diel ectric capacitors exhibited vol tage
breakdown at four to six times their dc rated vol tage l evel when sub-
jected to pul se excitation in the microsecond time region. Normal
charging characteristics were seen prior to the point of breakdown. A t
breakdown, the vol tage dropped rapidl y, whil e the current showed a cor-
responding increase. A rcs were often seen. T he resul t of such breakdown
is to reduce the capacitor's l eakage resistance and subsequentl y the
breakdown vol tage l evel , presumabl y by creating tracking paths in the
material or in the encapsul ation. T he extent of the damage depends on
the amount of energy dissipated after the breakdown and on the l ocation
of the breakdown site. I n some instances, a capacitance change was noted,
as wel l as a device fracture.
T he el ectrol ytic capacitors exhibited a broad range of vul nerabil ity
which appears to vary with capacitor val ue, vol tage rating, and the par-
ticul ar construction. T he resul ts on sol id tantal um capacitors showed
rel ativel y l ow damage l evel s. T he l evel s are comparabl e to those for
semiconductor devices. Refer to T abl e 4 - 3 9 for comparison. T he rec-
tangul ar pul se response of the tantal um devices varied with the circuit
l oading. General l y, after the vol tage reached some critical val ue as
shown in Figure 4 - 7 1 , increased conduction through the device was seen.
(Normal charging characteristics were seen prior to this point.) T he
current then increased with time, and correspondingl y the vol tage across
the capacitor decreased with time, until a sharp drop was seen in the
vol tage, which was then accompanied by a sharp rise in the current. When
this behavior was evident in the response, the device coul d al so be ex-
pected to suffer a decrease in l eakage resistance. When the circuit
l oading was of l ow impedance, the response appeared simil ar to the " second
breakdown" effect seen in reversed semiconductor junctions. I n these
cases, the device goes into an aval anche mode, and, after a given amount
of energy is dissipated in the device junction, it then switches to a
second breakdown state. Fail ure occurs rapidl y in this second breakdown
state. Model s have been formul ated for predicting the time at which a
device woul d enter this second breakdown at given power l evel s. T hese
model s are based on l ocal ized heating of portions of the device junction.
When a critical temperature is reached, second breakdown occurs. T he
24 5
(A).0047^f,35WVDC
Normal Polarity
(B)2.2/if, 35WVDC
Reverse Polarity
(C)2.2
M
f,l5WVDC
Normal Polarity
55V
S^ 30V
.
I6us
I9A
u *
o
J \
i
30/xS
Fig 4-7 I CAPACITOR PULSE RESPONSE
246
rel ationship general l y empl oyed for second breakdown prediction is of
the form
P = A J'*
2
or correspondingl y
E A
2
T
2
where P and E are the power and energy, respectivel y, required for fail -
ure at a given rectangul ar pul se width, T . " A " represents a constant
usual l y determined by measurement. T est data indicate a gross dependence
between the square root of pul se width and the energy required for the
initiation of the high current l ow vol tage state. T he reverse pol arity
tends to appear sl ightl y more sensitive than the forward. T he general
response, both forward and reverse, appears simil ar in character for the
tantal um capacitors.
O veral l resul ts of the ceramic and the sol id tantal um tests, as wel l
as other capacitor types, are shown in T abl e 4 - 4 2.
24 7
T abl e 4 - 4 2 FA I LURE LEVELS O F CO MMO N CA PA CI T O RS
Capacitor/Description
Vol tage*
Mean/Min
(vol ts)
Minimum
Pul se Width
(usec)
Energy
Max/Min
(pJ)
Fail ure
0 .5 uf, 1 0 0 Vdc etched
tantal um foil
F- 25 0
R- 25 0
0 .1
0 .1
> 1 3 0 0
> 1 3 0 0
No
No
0 .5 6 pf, 3 5 Vdc sol id
tantal um
F- 8 0
R- 8 0
0 .1
0 .1
> 4 9 0
> 4 9 0
No
No
5 .0 uf, 5 0 Vdc wet
tantal um sl ug
F- 3 2
R- 3 2
0 .1
0 .1
> 1 9 0
> 1 9 0
No
No
5 0 pf, 1 0 0 0 Vdc
ceramic
1 0 0 0 0 /7 3 0 0

Yes
1 0 0 0 pf, 1 0 0 0 Vdc
ceramic
60 0 0 /4 9 0 0

Yes
0 .0 0 4 7 gf, 3 5 Vdc
sol id tantal um
F- 1 5 0 /9 0
R- 1 1 0 /65
0 .25
0 .7
1 , 0 0 0 /8 6
1 , 1 0 0 /61
Yes
Yes
2.2 uf, 3 5 Vdc
sol id tantal um
F- 1 5 0 /9 0
R- 1 1 0 /65
5 .5
1 .2
5 0 , 0 0 0 /3 5 0 0
4 0 , 0 0 0 /3 3 0 0
Yes
Yes
2.2 uf, 1 5 Vdc
sol id tantal um
F- 1 4 0 /68
R- 5 4 /7 3
0 .1
2.0
3 0 , 0 0 0 /1 1 0 0
20 , 0 0 0 /1 20 0
Yes
Yes
1 0 pf 1 0 0 0 8 .0
No
(1 0 pul ses)
4 7 0 0 pf, 5 0 0 Vdc 1 0 0 0 8 .0
No
(1 0 pul ses)
1 uf, 20 0 Vdc 1 0 0 0 8 .0
No
(1 0 pul ses)
0 .0 22 uf, 60 0 Vdc 1 0 0 0 8 .0
No
(1 0 pul ses)
1 0 0 uf, 7 5 Vdc R- 225 0 2.0
No
(1 3 pul ses)
4 0 0 uf, 1 5 Vdc R- 225 0 2.0
No
(3 pul ses)
F: Forward
R: Reverse
24 8
SECT I O N 4 .2
DESI GN T O MI NI MI ZE RELI A BI LI T Y
DEGRA DA T I O N DURI NG PRO DUCT I O N
A ND USE
4 .2.1 Contributions to Rel iabil ity
Degradation
4 .2.2 Design for Ease of I nspection
and Maintenance
4 .2.2.1 Hardware Partitioning
4 .2.2.2 Faul t Diagnosis
4 .2.2.3 Prediction of
I ncipient Fail ures
4 .2 Design to Minimize Rel iabil ity Degradation During Production and Use
A s discussed in Section 1 .2, a rel iabil ity (i.e., MT BF) estimate
computed using MI L- HDBK- 21 7 B prediction techniques wil l refl ect the
rel iabil ity potential of a system or component item during its useful
l ife period. T his estimate depicts the inherent (or potential ) rel i-
abil ity of the design as defined by its engineering documentation, basic
stress/strength design factors and gross appl ication factors. However,
the estimate does not represent operational rel iabil ity unl ess design
fail ures have been el iminated, manufacturing and qual ity defects have
been minimized and operating and maintenance procedures have been opti-
mized. T herefore, to insure high fiel d rel iabil ity, special efforts,
designed specifical l y for the purpose of minimizing rel iabil ity degrada-
tion, must be appl ied during system design and devel opment, production,
operation and maintenance. Lack of effort in these areas can resul t in
a system rel iabil ity as l ow as 1 0 % of its inherent rel iabil ity (see
Subsection 2.2). Furthermore, experience has indicated that the degree
of degradation is directl y rel ated to the l evel of inspectabil ity and
maintainabil ity buil t into the system. T he purpose of this subsection
is to provide information and guidel ines to design for ease of inspec-
tion and maintenance, thus providing the means to minimize production
and use degradation. Subsection 4 .2.1 discusses those factors that
contribute to unrel iabil ity and which can be control l ed during produc-
tion and use. Subsection 4 .2.2 provides design for ease of inspection
and maintenance information and guidel ines.
4 .2.1 Contributions to Rel iabil ity Degradation
T he specific objectives of this subsection are to:
(a) Provide insight into basic fabrication and manufacturing
processes which can be pl anned and traded off during design
to minimize degradation effects.
(b) Establ ish the conceptual framework for viewing fiel d main-
tenance procedures as contributors to operational
unrel iabil ity.
(c) Estimate the advantage of additional process control s, tests
or better inspection.
25 1
T he key to minimizing and control l ing rel iabil ity degradation is to esti-
mate the defects introduced by production and maintenance. T wo types of
defects must be consideredqual ity defects and rel iabil ity defects.
Qual ity defects are defined as those defects which can be l ocated by con-
ventional inspection. Rel iabil ity defects are those defects which require
some stress appl ied over a time interval to devel op into a detectabl e
defect.
A s an exampl e of the two types of defects, consider a resistor with
the l eads bent cl ose to its body. I f the stress imposed during bending
caused the body to chip, this is a qual ity defect. However, had the
stress been inadequate to chip the body, the defect woul d go unnoticed
by conventional inspection. When the body is cycl ed through a tempera-
ture range, smal l cracks can devel op in the body. T his woul d al l ow
moisture and other gases to contaminate the resistive el ement causing
resistance changes. T his is a rel iabil ity defect, R(t). T his defect is
al so a design defect if the design specifications require a tight bend
to fit the component properl y in a board. I f the improper bend is due
to poor workmanship, the defect is cl assified as an induced defect.
T abl e 4 - 4 3 shows some of the processes invol ved in the manufacturing
of an el ectronic assembl y, and identifies some of the associated defects
and resul tant fail ure modes.
T he operation and maintenance of equipment in normal fiel d usage
al so induce defects. I t has been shown that operators in the fiel d wil l
stress systems beyond the predicted l evel s either through negl ect, un-
famil iarity with the equipment, carel essness, or mission constraints.
A l so, maintenance, schedul ed and unschedul ed, degrades rel iabil ity.
During unschedul ed maintenance, good parts are repl aced in an effort to
l ocate the faul ty parts. I n many cases, the good parts are written up
as defective instead of being reinstal l ed. T hese parts often are returned
to depot for repair or discarded, resul ting in a fail ure rate that is
higher than is actual l y occurring. Schedul ed maintenance can al so intro-
duce defects into satisfactory assembl ies. T hese defects are due to:
t Foreign objects l eft in an assembl y
t Bol ts not tightened sufficientl y or overtightened
Dirt injection
25 2
T abl e 4 - 4 3 PRO DUCT I O N PRO CESS A ND A SSO CI A T ED DEFECT S
General
Process
I nduced
Defects
Fail ure
Mode
+ ->
c
< u
!->
M
r-
E
S-
< D
->
C

4->
3
o
S-
+ ->
o
CO
3
u
*r
m
o
c
o.
o
CD
c
.
cu
3
>
C
to
o
Wire Stripping
Sol dering
Lead Cutting
Crimping
Wire Wrapping
Lead Bending
Wire Dress
Nicked Lead
Broken Strands
Short Leads
Long Leads
Excessive Heat
I nsufficient Heat
Excessive Sol der
I nsufficient Sol der
Dul l T ool s (Shock)
Wrong T ool
Wrong T erminal
Low Force
Excessive Force
Broken Wire
Loose Connection
Stress on Case
Vibration Sensitivity
Residual Stress
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
25 3
t Parts repl aced improperl y
t I mproper l ubricant instal l ed.
T hese induced defects and operational stresses, al ong with the
infl uence of the environment, are factors that must be control l ed and
accounted for in the anal ysis of rel iabil ity. I n general , the environ-
mental factor considered in handbook prediction techniques accounts for
the added stress provided by operation within that environment. However,
the environmental stresses imposed during maintenance may be other than
what was anticipated during prediction. For instance, a subassembl y
removed for repair in a desert area may be pl aced in direct sunl ight
whil e awaiting transfer. Component temperatures may exceed those exper-
ienced during normal operation for extended periods, thus reducing their
l ife expectancy. Mechanical stresses imposed on components during
removal , repair and reinsertion may exceed that designed for a given
environment. T herefore, al l maintenance procedures shoul d be eval uated
and control l ed to minimize maintenance induced defects.
Rel iabil ity degradation control invol ves concepts rel ated to inspec-
tionfrequency of, type, l ocation and efficiency. A key facet of
rel iabil ity degradation control is the determination of the efficiency
of inspectionsincoming, production, final and fiel d inspections. I t
shoul d be recognized that no inspection procedure is perfect. T he possi-
bil ity or the probabil ity of an error in an inspection procedure is a
function of a number of factors, some of which are:
(a) Probabil ity that al l component functions are exercised by
the test performed.
(b) Rel iabil ity and cal ibration of test fixture and equipment.
(c) Probabil ity of inspector error.
(d) Compl exity of item inspected.
(e) I nspection instructions, criteria, etc.
T he efficiency of an inspection can be expressed as a probabil ity of
detecting a defect and wil l have a numerical val ue between 0 and 1 . A
perfect or error- free inspection woul d have an associated numeric val ue
of 1 . T he inspection efficiency may al so be expressed as a percentage.
25 4
T he factors which infl uence inspection efficiency can be expressed
as probabil ities which are the tool s for cal cul ating the detection of
a defect. A s an exampl e, assume there are four (4 ) independent factors
which infl uence a particul ar inspection. Further assume that the prob-
abil ity of each factor is (0 .9 ). T hen the probabil ity of inspection
(i.e., inspecting efficiency) is (0 .9 ) or about (0 .66). T hus, even
though the probabil ity of each factor is rel ativel y high, the col l ective
probabil ity or the inspection efficiency is rel ativel y l ow. T his il l us-
trates the difficul ty of obtaining a perfect inspection.
A s previousl y discussed, conventional inspections are designed to
remove qual ity defects; however, since inspections are not perfect, al l
qual ity defects wil l not be removed. Figure 4 - 7 2 is an exampl e of how
inspections can be used to reduce the number of qual ity defects in a
component.
Components
with Defects
Receiving
Part Received [| I nspection
with Defect | ' A ccepts Part
V with Defect
V . " '
K
._ ^
Base qual ity I nspection
defect rate efficiency
do E
x
d
F
= do(l - E
1
)(l - E
2
)(l - E
3
)
where
Defect Not
Detected at
\
Defect Not
Detected a
T

Visu
* ! !\ Final T ests
I nspection \
\
I nspection
efficiency
I nsDection
efficiency
E.
dp = component defect rate after final inspection.
Figure 4 - 7 2 FA ULT T REE DI A GRA M FO R QUA LI T Y DEFECT S
25 5
Even though an individual inspection is not perfect, a sequence of
inspections can insure a smal l number of outgoing defects. T his can be
seen from the above faul t tree diagram which shows that for an outgoing
component to contain a defect, the occurrence of al l four of the fol l owing
events are required.
(a) Part received with a defect
(b) Receiving inspection accepts part with a defect
(c) Defect not detected at in- process inspection
(d) Defect not detected at final test station.
I t shoul d al so be noted that if any of the inspections of the exampl e
were perfect (E = 1 ), there woul d be no outgoing components with defects.
A burn- in or screen test is incl uded in the inspection of many
el ectronic equipments. T his type of test is designed to convert rel i-
abil ity defects which wil l cause premature fail ures in the fiel d into
fail ures in the assembl y pl ant. T his resul ts in a l owered infant mor-
tal ity rate of the system immediatel y after production. T he screen
efficiency, S, is the probabil iy of converting a rel iabil ity defect into
an observabl e fail ure. T he number of rel iabil ity defects converted and
detected is the product of the number of incoming rel iabil ity defects,
the screen efficiency, and the inspection efficiency. I f the screen
efficiency is (0 .9 ) and the inspection is (0 .9 ), then the probabil ity
of converting and detecting a rel iabil ity defect is (0 .8 1 ). T hus, even
with the use of a screen, al l of the induced rel iabil ity defects wil l not
be detected and removed.
T o assess and control the rel iabil ity of a system as it l eaves pro-
duction or a fiel d maintenance activity, val ues for inherent qual ity and
rel iabil ity defect rates, induced qual ity and rel iabil ity defect rates,
and inspection/screening efficiencies must be determined by a process
and inspection anal ysis.
T he process and inspection anal ysis invol ves: (1 ) a determination
of the induced defects (qual ity and l atent rel iabil ity) associated with
each of the more significant steps required in the fabrication of the
system as pl anned- - based on an anal ysis of pl anned inspection criteria
25 6
and historical rejection rates derived from simil ar processes; (2) an
assessment of the total outgoing (from production) defect rate based on
the derived process- induced defects and suppl ied inspection reject rates;
and (3 ) a cal cul ation, based on the ratio of the inherent rel iabil ity to
the outgoing rel iabil ity.
Val ues for process or maintenance induced defect rates can be de-
rived from an eval uation of reject statistics, determined from an eval ua-
tion of stresses appl ied by the manufacturing processes, or can be based
on experience factors with simil ar systems and processes. T he val ues
derived or obtained for reject rates, induced defect rates, and inspec-
tion and screen efficiencies can be combined in a process and inspection
anal ysis fl ow chart which is used to derive a final outgoing defect rate.
T he total defect rate or outgoing rel iabil ity numeric stemming from a
process anal ysis can then be used to determine manufacturing rel iabil ity
degradation factors.
4 .2.2 Design for Ease of I nspection and Maintenance
A s previousl y indicated, achieving high rel iabil ity is directl y
rel ated to the degree of effectiveness of the special features designed
and buil t into a system which woul d make it easy to produce (i.e.,
assembl e and test) and maintain. T hese features must be designed with
the objective of aiding the production inspector or maintenance tech-
nician in recognizing and diagnosing fail ures or weak areas and making a
repair as earl y and as rapidl y as possibl e. Furthermore, the incorpora-
tion of these special features into a system, in addition to improving
rel iabil ity, producibil ity and maintainabil ity, wil l resul t in a reduc-
tion of manufacturing and fiel d support cost.
I n order to effectivel y design for ease of inspection and mainten-
ance, the designer must be compl etel y aware of basic probl ems and
marginal or difficul t areas rel ated to assembl y and maintenance. He
must be aware of possibl e equipment fail ure modes connected with these
probl em areas, and he must be compl etel y famil iar with the production
and maintenance environment. T he designer must recognize that production
probl ems are potential maintenance probl ems, e.g., if assembl y is diffi-
cul t under factory conditions, it woul d be virtual l y impossibl e under
fiel d conditions.
25 7
A chieving ease of inspection and maintenance requires designing
special means into the system for: (1 ) identifying fail ure and/or
potential (or marginal ) fail ures, and (2) facil itating faul t diagnosis
(e.g., access to fail ed units and removal and repl acement of fail ed
units). T abl e 4 - 4 4 presents a simpl ified l ist of activities and devel op-
ment guidel ines that wil l aid in assuring impl ementation of these
features.
A l though impl ementing these features invol ves essential l y al l
aspects of equipment devel opment, concepts rel ative to hardware parti-
tioning (i.e., packaging, modul arity, etc.), faul t diagnosis and detec-
tion of incipient fail ures are considered key el ements. T he fol l owing
subsection provides information about and guidel ines for these three
el ements.
4 .2.2.1 Hardware Partitioning
Hardware partitioning is the process of dividing the system into
physical l y and functional l y distinct units to facil itate faul t isol a-
tion, removal and repl acement. Partitioning enabl es equipment units,
assembl ies and subassembl ies to be designed as discrete items or modul es.
Modul arization affects both maintainabil ity and producibil ity as
indicated in Figure 4 - 7 3 .
I MPRO VED MA I NT A I NA BI LI T Y
I sol ation T ime
Skil l Requirements
Speed of Repl acement
I nterchangeabl e ity
Repair qual ity
r
MO DULA RI ZA T I O N
DESI GN GUI DELI NES
8 Uniform sizes and shapes
t Guide pins and keyed
connectors
t Ease of test/checkout
Quick disconnect
I^ JP* -
t Decrease number of
functions
I MPRO VED
PRO DUCI -
-f tJUH J
Figure 4 - 7 3 MO DULA RI ZA T I O N DESI GN
25 8
T abl e 4 - 4 4 EA SE O F MA I NT ENA NCE GUI DELI NES
Fail ure diagnosis, identification and repl acement are
facil itated by:
t Using modul ar design techniques
Use of special buil t- in circuits for faul t detection,
error warning l ights, etc.
Designing for repl acement at higher l evel s
Using increased skil l l evel technicians
I ncreasing depth of penetration of l ocal ization features
Util izing test indications which are l ess time consuming
and/or l ess difficul t to interpret
t Designing for minimum diagnostic strategies
t Making accessibl e and obvious both the purpose of the
test points and their rel ationship to the item tested
I mproving qual ity of technical manual s or maintenance aids
t Designing access for ease of entry
Reducing number of access barriers
Reducing need for isol ation access by bringing test
point, control s and displ ays out to accessibl e l ocations
1 1 Reducing number of interconnections per repl aceabl e item
Using pl ug- in el ements
Reducing requirements for special tool s.
25 9
Modulari zati on i s ach i eved th rough f uncti onal desi gn wh i ch encom-
passes th e packagi ng of components and subassembli es perf ormi ng si mi lar
f uncti ons i n self -contai ned uni ts, th us f aci li tati ng testi ng and mai n-
tenance.
T h e appli cati on of modular desi gn allows th e i solati on of f aults
to a uni t wh i ch may be removed f rom th e equi pment f or on-si te repai r,
sh i pment to a repai r depot or th rowaway. T h e equi pment may be i mmed-
i ately put back i nto operati on by replacement of a spare modules, mi ni -
mi zi ng on-li ne mai ntenance acti on. Locali zati on of components i nto
modules eli mi nates long path s and crossovers, as i llustrated i n F i gure
4-74. T h i s f urth er enh ances ease of mai ntenance by si mpli f yi ng th e
traci ng of si gnal path s wh en locati ng and i solati ng a f ai lure.
USE T H IS
Module Modul e 2
NO T T HI S
Fig. 4-74 DESIGN FOR FUNCTIONAL MODULARIZATION
2 60
A n exampl e of modul arization currentl y used in airborne systems
design is the l ine repl aceabl e unit (LRU). T he LRU concept al l ows the
rapid removal and repl acement of l arge equipment modul es or subsystems
on the fl ight l ine for maintenance at a repair station. T he appl ication
of this concept al l ows reduction of faul t isol ation time, reduction of
on- l ine maintenance personnel skil l requirements and provides for con-
sistent qual ity of repair.
I f the modul e is inexpensive and not used in great numbers, there
is a strong l ikel ihood of adopting a throwaway maintenance concept for
the modul e. T his is a l ogical concl usion of a cost of ownership anal ysis
(CO O ) (see Section 4 .3 ) indicating that repair costs are greater than
the cost of a new unit. T he l ogistics of modul e repl acement are directl y
rel ated to the initial design decisions on size and compl exity of modul es.
Repair of equipment can be accompl ished by repl acement of a modul e after
faul t isol ation is accompl ished by some portabl e test equipment or buil t-
in test, but the repair of a modul e general l y requires jigs, fixtures,
power suppl ies, etc.
T his equipment is ordinaril y found at the production pl ant to enabl e
rework of these modul es. However, it is general l y too expensive for
fiel d appl ication. A l ong with the training and technical orders required
for fiel d repair of a modul e, there are the cost factors which must be
considered. Further detail s on the l ogistical aspects can be obtained
from the A PLCM/A FSCM 8 0 0 - 4 manual on O ptimum Repair Level A nal ysis (O RLA ).
Based on costs and l ogistics, a design tradeoff must be made, in
the concept formul ation stage, to design smal l inexpensive modul es which
wil l be designated throwaway or to design l arger modul es for a possibl e
economy of equipment repair. I t is crucial that these decisions be made
earl y in the concept phase where changes l east affect program costs.
A n equipment which impl ements the throwaway concept of modul ar
design possesses several advantages. T hrowaway modul es al l ow savings in
repair time, tool s, facil ities and manpower. T hey al so al l ow improved
standardization and interchangeabil ity of modul es and assembl ies. T hrow-
away modul es al so impose several penal ties. T hey increase suppl y burdens
because nodul es must al ways be on hand. Simil arl y, redesign or retrofit
of manufactured units becomes difficul t since modul es cannot be readil y
modified.
261
I f a modul e can be cost effectivel y thrown away, the troubl e shooting
and repair aids in the modul e can be el iminated, providing the modul e can
stil l be readil y isol ated. I n this case, it shoul d be remembered that an
expensive part shoul d not be discarded with an inexpensive but fail ure
prone part. I n the case of an inexpensive modul e containing an expensive
part (3 0 % of modul e cost), a pl ug- in connection al l owing sal vage of the
expensive part may be considered.
4 .2.2.2 Faul t Diagnosis
I t must be emphasized that a system's ease of maintenance depends
on those design features which impact the abil ity to diagnose fail ure
rapidl y and accuratel y. Repair cannot begin until the fail ure is iden-
tified, l ocated and isol ated. Consideration of faul t diagnostics during
equipment design can significantl y increase ease of maintenance by
reducing diagnostic time and, therefore, equipment downtime. Design
factors contributing to rapid faul t diagnosis are:
Buil t- in T est Provisions
Maintenance Support
Special provisions must be designed into the system that wil l provide
the means to assess the condition of internal LRU's, assembl ies, or
modul es, for the prupose of l ocating fail ures. Such provisions can have
a wide range of compl exity, depending on the needs and constraints of
the specific system. Some systems may simpl y provide test points to
interface with external support equipment. O ther systems may incorporate
Buil t- in- T est- Equipment (BI T E) or sophisticated Buil t- in- T est (BI T ) which
operate under computer control and provide compl ete indication of fail ure.
Buil t- in test provisions obviousl y infl uence inspection and main-
tenance cost. From the maintenance viewpoint, maximizing faul t isol ation
is the most desirabl e approach. However, a number of difficul ties arise.
Buil t- in test provisions add cost to the equipment's devel opment. T hus,
the extent of the provisions must be determined through tradeoff studies
concerning maintenance needs and total cost of ownership. T he tradeoff
between acquisition costs and potential maintenance savings must be eval -
uated to determine the impact. O ther factors may infl uence the decision,
such as: short downtime requirement, critical ity of the item, or per-
sonnel requirements.
262
I ncorporating test points into the system invol ves considering
number, type, l ocation and arrangement. T he physical l ocation of the
test points has a marked effect on the qual ity of inspection and main-
tenance. General l y, test points shoul d be l ocated near the signal
source, since the nature of a signal may be such that it does not travel
wel l without being al tered in the process of transmission. T his consid-
eration is particul arl y pertinent in those cases where the waveshape
of the signal is critical and wil l tend to change in transmission to a
test point. T he designer shoul d keep in mind that the technician needs
onl y an indication that refl ects an out- of- tol erance condition of the
true signal . I f these indications are documented during engineering
tests, they wil l provide adequate mal function indicators for fiel d use.
Particul ar care shoul d be taken to make test points accessibl e.
I deal l y, internal test points shoul d be cl ustered around the portion of
the unit that wil l be most accessibl e when instal l ed. T here shoul d be
onl y one adjustment control associated with each test point and it shoul d
be easil y and rel iabl y operated.
T est points shoul d be grouped or arrayed on a central panel to facil -
itate checking and troubl eshooting. T he test points shoul d be grouped in
an orderl y fashion which is convenient for sequential checking. T he
specific test points to be empl oyed in an el ectronic system depend on
the operational and tactical demand pl aced on the system design, and the
special needs of a particul ar service. T he number and type of test
points shoul d be compatibl e with test instrumentation (buil t- in or other-
wise) that is avail abl e at the pl ace of system use, or at the maintenance
or repair activity.
T he functional l ocation of test points shoul d be fixed by determining
from the manufacturing inspection requirements and the maintenance proce-
during what signal s must be avail abl e to the technician and at what points
they must be avail abl e. T est points shoul d make avail abl e those signal s
that the procedures indicate the technician must have in order to inspect
and maintain the system. T heir l ocation must be pl anned into the system
for maximum effectiveness.
263
A test point (which may be nothing more than a bare wire) shoul d be
provided at the input and output for each l ine repl aceabl e unit. O ne
convenient way to provide these test points is to mount components on
one side of a board and wiring on the other side with el ectrical connec-
tion through the board. T he advantage of having test points al one on a
fl at surface rather than in among the parts is that ful l identifying
information for each test point can be stamped on the surface without
being obscured by the parts.
I t shoul d not be necessary to remove any assembl y from a major com-
ponent to inspect or troubl eshoot that assembl y. T his may require
special test points on the major components or assembl ies- . But test
equipment and bench mockup access to the outputs and inputs of each l ine
repl aceabl e unit shoul d be provided through the normal interconnecting
pl ugs wherever possibl e. Design guidel ines for test points in el ectronic
equipment are l isted in T abl e 4 - 4 5 .
T he decision to incl ude BI T E/BI T must be based on a tradeoff between
basic maintenance factors and other system parameters and constraints.
Buil t- in test capabil ities have three uses at fiel d l evel :
Warning that subsystem has become inoperative
t Generating fail ure signal s to reconfigure system
Faul t isol ation to a repl aceabl e el ement.
T he difficul ties of appl ying BI T E/BI T are:
Changes in hardware (modifications or additions to the system)
require BI T hardware/software modifications.
t I nformation transfer between systems with BI T is greater than
without BI T .
t Systems BI T is normal l y designed by system integrators who are
not as famil iar with the system as the original designers.
Central ized BI T requires increased data input and more
el aborate l ogic.
264
T abl e 4 - 4 5 DESI GN GUI DELI NES FO R T EST PO I NT S
1 . T est points shoul d be provided for the input and output
of each l ine repl aceabl e or repairabl e assembl y, circuit,
item or unit; these points shoul d be immediatel y avail abl e.
2. Ground points shoul d be provided as necessary, particul arl y
when a painted surface woul d otherwise prevent good el ec-
trical contact.
3 . Vol tage dividers shoul d be incorporated at test points for
vol tage in excess of 3 0 0 vol ts.
4 . T est points and their associated l abel s and control s shoul d
face the technician for best visibil ity, consider use of
col or coded test points for each of l ocation.
5 . Combine test points, where feasibl e, into cl usters for
mul tipronged connectors, particul arl y where simil ar
cl usters occur frequentl y.
6. A rrange test points in a test panel or other surfaces
according to the fol l owing criteria, l isted in order of
priority:
a) T he type of test equipment to be empl oyed at each point
b) T he type of connector used and the cl earance it requires
c) T he function to which each point is rel ated
d) T he test routines in which each point wil l be used
e) T he order in which each wil l be used,
7 . Label each test point with the tol erance l imits of the signal ,
and a number, l etter or other symbol keyed to the maintenance
instructions.
8 . Locate routine test points so that they can be used without
removal of cabinet cover or chassis.
9 . Label each test point with the in- tol erance signal .
265
I n general , buil t- in tests perform faul t isol ation by appl ying a
signal to a circuit and measuring its response by primary measurements
such as vol taqe l evel s, distortion, noise, etc. Meters or go/no- go test
equipment are buil t into the circuit so that a minimum of external test
equipment need be connected to test the circuit performance. Checkout
is normal l y performed manual l y by appl ying stimul us and observing the
response of the circuit by BI T E. T he output can be fed to a computer
which determines if al l measured parameters are within l imits. T he com-
puter can al so generate the necessary test signal s. BI T E, in addition
to reducing the mean time to repair a fail ure (MT T R), al so l owers the
skil l l evel needed to maintain equipment because faul t isol ation is
performed by a computer and the technician need onl y repl ace the com-
ponent identified by the computer.
T o determine BI T E sophistication, it is necessary to define the
requirements for MT T R, number of parameters tested, critical ity of mal -
function, and l evel of maintenance personnel . For instance, aircraft
operating in battl e conditions pose severe restraints on the time per-
mitted for a system check. I n a combat situation, aircraft are recycl ed
as rapidl y as possibl e because of the l imited time between missions and
shortened prefl ight checkout. T herefore, the MT T R shoul d be minimal ,
e.g., one hour or l ess. Due to the compl exity of the avionics equipment,
many parameters need to be tested to insure mission success. Even with
skil l ed technicians, the time required to remove panel s to get at test
points is prohibitive. T herefore, some form of BI T E is necessary, and
the more compl ete the testing performed, the higher the l ikel ihood of
finding critical mal functions. I f the aircraft were to have a computer
on board, the computer coul d cycl e the avionics through a compl ete test
whil e returning from a mission when the computer burden is l ow. A l l
necessary parameters coul d either be printed out for a semiskil l ed
technician to eval uate for conformance to specification, or the computer
coul d perform this function as wel l as identify any defective avionics
modul es.
A n exampl e with opposing requirements is a central communication
network having redundant equipment. I n this case, a few vol tage current
and/or power meters l ocated at the output of l arge subassembl ies in the
network BI T E woul d al l ow an operator to isol ate a mal functioning
266
subassembl y quickl y. T he backup unit woul d be switched on and, once the
defective subassembl y is disconnected, the defective component can be
identified and repaired at a l ess demanding pace. T he degree of BI T E
used in this exampl e woul d depend upon the skil l l evel of the technician.
A yery important consideration when impl ementing BI T E is the manner
in which it affects the circuit. I deal l y, it shoul d l ook l ike an open
circuit at al l times under al l fail ure modes in the control circuit. I n
this way, the buil t- in test provision wil l not decrease the circuit rel i-
abil ity. Since this is not al ways possibl e or practical , its l oading
effects shoul d be eval uated in the operation of a circuit. Circuit oper-
ation shoul d be studied to determine if there is another l ocation in the
circuit where a simil ar measurement might provide as much and possibl y
more information with l ess l oading. A fail ure mode and effect study
shoul d be performed on the BI T E to determine the impact of various fail -
ures on the operation of the circuit under test. T hose fail ure modes
causing l owered performance of the circuit under test shoul d be el iminated
by a different test technique or by improving rel iabil ity using techniques
described in Section 4 .1 of this handbook.
T he system to be maintained shoul d be ful l y described by the designer,
Schematic diagrams of new or unusual circuits shoul d be provided. Equip-
ments to be tested shoul d be broken down into functional bl ock diagrams,
and engineering sketches and diagrams shoul d be provided to identify
modul es and test points. Modul es and test points shoul d be l abel ed or
coded to facil itate identification from documentation. T he testing pro-
cedure shoul d be documented in a cl ear, concise manner and expected signal
l evel s and waveforms adequatel y indicated.
T he designer shoul d al so prepare a technical description of proposed
test or support equipment which must be avail abl e to maintain the equip-
ment. I f the test or support equipment is government furnished, the
nomencl ature of the equipment shoul d be identified. However, if the
test or support equipment for maintaining the equipment is commercial ,
the designer shoul d l ist the name of the suppl ier and catal og number of
the commercial l y avail abl e equipment. A statement shoul d be furnished,
and preferred and al ternate devices shoul d be indicated if there is more
than one suitabl e test or support equipment avail abl e. I t shoul d be
stated whether the proposed test is buil t into the equipment.
267
4 .2.2.3 Prediction of I ncipient Fail ure
O ften, components require many hours of operation before they degrade
to the point that the circuit in which they are instal l ed ceases to oper-
ate adequatel y. For the components degrading at a sl ow rate, l ife prog-
nosis, or fail ure prediction, al l ows schedul ing of preventive maintenance
in a timel y manner for most efficient use of maintenance personnel , in-
creased MT BF, and maximum equipment avail abil ity. However, the penal ty
that must be paid for these advantages is more frequent status measure-
ments invol ving detail ed data on the signal l evel s present throughout a
circuit. T his data is compared with predetermined data l imits to val idate
circuit fail ure or proper operation. Data taken for l ife prognosis must
be stored for comparison to future data. By comparing data from several
such groups, data degradation trends can be identified, the degraded part
l ocated, and the expected l ifetime predicted. T he cl assic way of obtain-
ing data, i.e., a technician taking data at many l ocations in the circuit,
is expensive and prohibitivel y time consuming. T he current approach,
which expedites data col l ection, is to use Buil t- in- T est Equipment, BI T E,
which simpl ifies data taking or Buil t- in- T ests, BI T , which can obtain
these data under computer control . A nother approach that can be useful
is to measure secondary effects, such as component temperature and el ec-
tric and magnetic fiel d gradients, around a circuit board or subassembl y.
Secondary effects are defined as those effects which are not pro-
duced sol el y from the signal processing. Exampl es of such effects are:
the heating of a component due to current fl ow rectification, or mixing
of an ac signal (s) at the junction of a bipol ar transistor due to its
nonl inear characteristics, and odor emitted from a component due to
current fl ow. A broad background in physical effects associated with
component operation physics, as wel l as state- of- the- art detection tech-
niques, are needed in order to ful l y expl oit secondary effects. T his
section wil l provide onl y an insight into this subject since a compl ete
discussion is beyond the scope of this handbook. Some references for
both mechanical and el ectrical systems are provided at the concl usion.
Secondary effects can be subdivided into passive or active cate-
gories. Passive effects were used as exampl es in the preceding paragraph,
i.e., a sensor monitors the effects of the operating system without
268
providing any stimul us other than what is normal l y present. T he second
exampl e coul d al so be an active technique if an external RF fiel d were
imposed on a bipol ar transistor. T he nonl inear conductivity woul d cause
a signal to be reradiated from the transistor with an A M component pro-
portional to the signal being processed by the transistor. A n active
effect is, therefore, one util izing external stimul us. Secondary effects
can be further categorized into chemical , mechanical and el ectromagnetic.
T he fiel ds covered in each of these categories are presented in T abl e
4 - 4 6.
T he feasibil ity of sensing secondary effects has been demonstrated
and is appl ied with varying degrees of success through the industry.
Secondary effects sensing has not been widel y accepted because the signal s
obtained from them are compl ex and difficul t to interpret. I n general ,
the secondary effect created by a component is not uniquel y characterized
by a singl e response in the el ectromagnetic, mechanical or chemical
domain and, therefore, requires the use of different types of sensors for
any inspection.
T he secondary effects may best be described as " signatures" . T his
signature may be characterized in the time domain, the frequency domain,
or in the case of chemical signatures, the mol ecul ar weight, partition
coefficients, or size distribution. T he environment must al so be con-
sidered as having a signature characterized in terms of a particul ar
sensory system.
Normal signatures as wel l as signatures of an incipient or actual
fail ure may vary sl ightl y from equipment to equipment because of nominal
differences in components and assembl y. Fail ure signatures may, in some
cases, tend to be masked by variations in the environmental signatures.
T here are several possibl e ways that the environmental factors may be
negated. T oe unit under test can be pl aced in a control l ed environment
or otherwise shiel ded from its effects. I mproved sensors can, with
spatial resol ution, improve the signal to environment ratio by cancel l ing
the environmental signature. T he improvements in data processors (mini-
computers, digital fast Fourier transform, etc.) make it possibl e to sub-
tract steady- state environmental contributions if they remain constant or
change sl owl y.
269
T abl e 4 - 4 6 CA USE A ND EFFECT O F SECO NDA RY EFFECT S
Secondary Effect
Sensed
Source of
Effect
El ectrical
I nfrared
Microwave
High Frequency
El ectric Fiel d
Magnetic Fiel d
Mechanical
Noise
Heat
Chemical
O dors
Particl es
Power Dissipation
T ransistor heating
Resistor heating
Displ ay heating
Capacitor heating
Connector heating
Poor connector
Noisy transistors
T ransistor nonl inearity
O scil l ating current in coil s
Poor connection
I nsufficient bypass cap
A C and DC vol tage gradients
A C and DC currents
Conductor vibration
Poor el ectrical connection (arcing)|
Loose component
Power dissipation components
Poor connection
Friction
O verheating
O verheating
A rcing
A rcing
27 0
Secondary effect monitoring meets the ideal criteria for BI T E/BI T
sensors because they do not l oad the circuit under test, and, if they
shoul d fail , the operation of the circuit is unaffected. T he sensors
are, in general , more expensive than BI T E/BI T but they can suppl y sup-
pl emental diagnostic data which might otherwise be difficul t to obtain
by conventional BI T E techniques.
27 1
SECT I O N 4 .3
DESI GN T O CO ST
4 .3 .1 Design to Cost O verview
4 .3 .2 Defining Cost and Rel iabil ity T argets
4 .3 .2.1 Concept and Val idation Phase
4 .3 .2.2 Devel opment and Production
Phase
4 .3 .2.3 Bal anced Design Management
4 .3 .3 Meeting Cost and Rel iabil ity T argets
4 .3 Design to Cost
Currentl y, design to cost goal s are used in contracts to seek the
best bal ance between performance and acquisition cost in most defense
systems programs. T he decision to emphasize cost goal s was made in the
l ight of the hard real ities of l ikel y future l evel s of DoD budgets and
4 8
the ever increasing unit acquisition, manpower and support cost. A l -
though design to cost is not a unique concept, it does represent a
constraint to add to the task of designing equipment which wil l meet
performance, rel iabil ity, maintainabil ity, and now, cost goal s. O f
course, the true objective of the design effort is to achieve a bal anced
design that wil l meet al l requirements. I n this section of the handbook,
we wil l treat the seemingl y simpl e task of achieving the " bal anced"
design. Specifical l y, we wil l discuss:
(a) T he " design- to- cost" phil osophy,
(b) Procedures for al l ocating broad contractual goal s to the
subsystem and component l evel , and
(c) T echniques which can be used to meet cost goal s.
4 .3 .1 Design to Cost O verview
A n understanding of the rational e and background for the design to
cost phil osophy wil l aid in the appl ication of these principl es. Design
to cost evol ved after studies of past program cost trends reveal ed that
the mil itary woul d not be abl e to repl ace equipment at the same rate at
which present equipment was becoming obsol ete. A cl earer understanding
of the dil emma is possibl e by reviewing the DoD resource al l ocation
process.
DoD Resource A l l ocation Process
DoD pl anners did not see a real growth in the portion of the federal
budget al l ocated for mil itary needs. A fixed infl ow of funds is shown
in Figure 4 - 7 5 . Due to the increased compl exity of today's equipment,
a l arger portion of the budget was projected to be al l ocated to:
1 ) operating and maintenance needs, and 2) manpower requirements. T he .
procurement budget for new repl acement equipment was expected to remain
constant, at best. I t was obvious that steps woul d have to be taken to
restrict cost (in most cases, unit production cost) to past l evel s of
27 5
Support
Costs
Strategic Tactical
nance Ordnance Tanks
Government
Spending
Defense
Budget
Procurement
Budget
Manpower
Costs
Other
Ships
l
Aircraft
i
Navy Marines A rmy
Fig. 4 - 7 5 T HE DO D RESO URCE A LLO CA T I O N PRO CESS
equipment unit cost in order to provide equival ent force structures.
Design to cost was instituted precisel y to achieve this end. I t was al so
intended to sl ow the trend toward increased performance without regard
to cost, rel iabil ity and compl exity of the new equipment.
Design to cost coul d take different emphases dependent on the type
4 4
of devel opment program. Four programs with varying design to cost
emphasis are defined in T abl e 4 - 4 7 . A s seen in the tabl e, " Design- to-
Unit- Production- Cost" (DT UPC) is emphasized in most major mil itary
programs. DT UPC can determine the number of aircraft or equipment the
mil itary coul d " afford" .
T abl e 4 - 4 7 T YPES O F DESI GN- T O - CO ST PRO GRA MS
Design to Cost
Programs
Program
Characteristics
Program
Exampl es
Production Unit
Price
Large Quantity
Procurements
t
t
Cl ose Support
A ircraft A - 1 0
Lightweight
Fighter
T otal Program t Compl ex Equipment A WA CS
Costs
t Smal l Buys
t High Devel opment
Cost
A dvanced A irborne
Command Post
Production Unit
and I nstal l ation
Cost
Cost
t Large Quantity
Procurement of
Subsystems
t
t
t
t
A irborne Radar
A vionics Equipment
T A CA N
Gyroscope
Devel opment and
O perating Costs
Facil ities and
Construction
Programs
t Ground Radar
I nstal l ations
Despite the emphasis on unit production cost in contractual require-
ments, the overriding objective is to minimize the l ife.cycl e costs-
design to unit production cost is onl y an aid in the process. A major
component of Hfe cycl e cost is support cost. A quick review of Figure
4 - 7 5 il l ustrates the importance of minimizing support cost. I f support
27 7
costs are compromised when meeting DT UPC goal s, future funds for equipment
procurement are further reduced.
What this means is that during design one must strive for a bal anced
design which wil l :
(a) Maximize performance within unit cost goal s, and
(b) Minimize support cost, to minimize l ife cycl e costs.
A design that minimizes support cost invol ves the appl ication of rel i-
abil ity discipl ines during the design phase. T he practitioner who em-
braces rel iabil ity fundamental s in equipment design is actual l y incorpor-
ating sound economic principl es which wil l l ead to the l owest cost to
the owner.
Figure 4 - 7 6 il l ustrates the rel ationship between objectives of a
design program. I n the past, the emphasis on performance woul d often
become overriding, to the detriment of rel iabil ity and cost considera-
tions. Design engineers must now bal ance performance, rel iabil ity and
unit production goal s equal l y against the overal l objective of minimizing
l ife cycl e costs.
T o meet this need, attention is focused on structuring a bal anced
design approach derived from a l ife cycl e cost model that is composed
of, and governed by, submodel s which cal cul ate R&M and cost variabl es.
Figure 4 - 7 7 presents an overview of the methodol ogy within this frame-
work. T he figure shows the l ife cycl e cost model as the vehicl e by
which estimates for operation, performance, R
9
M, and cost are traded
off to obtain " design to" target goal s which col l ectivel y represent a
bal anced design. T his l ife cycl e cost model incl udes submodel s
which are representative of acquisition costs and l ogistics support
costs, subject to the constraints of functional objectives and minimal
performance requirements.
Life cycl e cost represents al l costs incurred from the point at
which the decision is made to acquire a system, through operational l ife
and eventual disposal of the system. A variety of anal ytical approaches
can be used as inputs to the establ ishment of an optimum l ife cycl e cost
model . T he total l ife cycl e cost model is thus composed of subsets
of cost model s which are then exercised during tradeoff studies. T hese
27 8
ro
Trades
Low Reliability
o Better Performance
Old
New
Fig. 4-76 TRADE RELATIONS BETWEEN PROGRAM OBJECTIVES
(BALANCED DESIGN)
I\5
o
Initial
Values
MTBF
MTTR
i
Operational Design
Requirements Constraints
Mission Size
Operational Weight '
Modes Power |
1 i !
Design Balancing
Activities
R8M
Models
Life Cycle
Cost Model
"Design To"
Targets <
R, M a C
4
\\ \\
R, M ac
Values (Status)
Acquisition
Cost Model
Logistics
Support
Cost
Model
i

i i I i I
i
l r N
nance I
Management
Tracking Prodi
Cost
jction Desi
Cost
gn Maint
Cost
Par
Tes
ts Redundant
ting Design
Bread-
board
Tests
ORLA
Bite
Age
L .
Fig. 4-77 RSM AND COST METHODS
cost model s and cost estimating rel ationships range from simpl e informal
rel ationships to compl ex mathematical statements derived from empirical
data.
A total l ife cycl e cost (LCC) is represented by costs col l ected in
two areas: (1 ) system acquisition costs, and (2) l ogistics and support
costs. I n simpl e mathematical terms, the above can be stated by:
LCC = A C + LSC
where
LCC = l ife cycl e cost
A C = acquisition cost
LSC = l ogistic support cost
Some of the major el ements comprising these cost categories are shown
bel ow:
A cquisition (A C)
Design and devel opment
- Basic engineering
- T est and eval uation
- Experimental tool ing
- System management
Manufacturing and qual ity engineering
Fabrication
Production tool ing
Qual ity control
T est equipment
Facil ities
I nitial spares
T raining
28 1
Logistics and Support (LSC)
Spares
Personnel and training
O verhaul and l ower echel on maintenance facil ities
A erospace ground equipment (A GE)
Logistics factors
LCC model s have been formul ated which establ ish rel ationships to
control l abl e A C and LSC characteristics. T o obtain A C cost estimates for
desian and devel opment, detail ed engineering costs as wel l as statistical
cost rel ationships (parametric sensitivity anal yses) shoul d be compil ed
and/or establ ished. O btaining this information necessitates a firm under-
standing of the equipment, its devel opment and production processes, and
a historical data base on simil ar type equipment. A few specific ap-
proaches which shoul d be undertaken are: rel ating costs to measurements
of technol ogy over a given period of time, and using trend l ine parameters
devel oped from the historical data base of simil ar equipments. T he tech-
nol ogical advance sought through the new equipment and the al l otted
devel opment time can be used for gross estimating purposes.
I n further estimating A C costs, production cost information is re-
quired. Production costs, in general , incl ude material , l abor, G&A ,
overhead, profit, capital ization for production, handl ing and transporta-
tion. Specific factors that comprise production costs are:
Recurring Production Costs
Fabrication
A ssembl y
T est
Manufacturing support
Qual ity control
Engineering support
Nonrecurring Costs
Manufacturing engineering
System integration
Engineering changes
Qual ity assurance
28 2
First articl e tests
T est equipment
T ool ing
Facil ities
Documentation
Program Management
Pl anning
A dministration
Control
I t shoul d be noted that R&M can have a significant impact on pro-
duction costs. Redundant systems can add to both system weight and cost.
Use of establ ished rel iabil ity components (per appropriate MI L- SPECS)
and stringent qual ity control during production (e.g., equipment screen-
ing tests pl us extensive subassembl y testing) can al so increase produc-
tion cost. High qual ity parts which increase the design safety factors
may be costl y to procure and may al so increase inspection costs. T he
cost factors associated with production test fail ures can be minimized
if fail ure modes are el iminated during design, and if rel iabil ity defects
are uncovered earl y in the production cycl e. T he factors that woul d
reduce production costs, as rel iabil ity requirements are increased,
incl ude rework, material review board action (MRB), scrap rate and QC
inspection.
T he most compl ex cost estimating rel ationships are found in the
l ogistics support cost area (LSC). For exampl e, a l ogistics support
cost model devel oped by the A ir Force defines this factor in terms of
eight equations as fol l ows:
(1 ) I nitial and pipel ine spares cost
(2) Repl acement spares cost
(3 ) O n- equipment maintenance cost
(4 ) O ff- equipment maintenance cost
(5 ) I nventory entry and suppl y management cost
(6) Support equipment cost
(7 ) Cost of personnel training and training equipment
(8 ) Cost of management and technical data.
28 3
T he factors, el ements and terms of these equations identify an incurred
cost, time or expended resource in mil itary fiel d operations. T he initial
and pipel ine spares cost il l ustrates the compl exity and detail of the
model .
T his cost factor is defined in terms of (a) number of Line Repl ace-
abl e or Repairabl e Units (LRU's) in the subsystem, (b) expected peak force
fl ying hour/month, (c) fraction of maintenance actions for which the LRU
or SRU (Smal l Repl aceabl e Unit) can be repaired in pl ace, (d) mean fl ying
time between maintenance actions, (e) average base repair time, (f) frac-
tion of removal s returned to depot for repair, (g) expected total force
fl ying hours over l ife cycl e, (h) expected unit cost at the time of
initial provisioning, (i) fraction of removal s expected to be scrapped.
Simil ar rel ationships exist for the other l ogistic cost factors.
A review of l ogistics support cost factors indicate that they are
driven by system R&M characteristics. For exampl e, when considering
maintenance costs, the rel iabil ity of the system and its components, in
terms of unschedul ed maintenance frequencies and MT BF, directl y impacts
the frequency of repair and/or overhaul of fail ed components. A l so, the
higher the rel iabil ity, the l ower the number of fiel d modifications
required and the l ower the cost, incl uding retrofit. Significant R&M
expenditures during the devel opment phase can be cost justified if
improved fiel d R&M performance and l ower operating and maintenance wil l
resul t from the R&M efforts.
I n the A ir Force LSC model , the functional modul es of a system are
cal l ed LRU's and the submodul es are cal l ed SRU's. Whil e the definitions
of the LRU and SRU may differ somewhat, the definition as functional
modul es and submodul es can be consistentl y appl ied.
T he model provides costs per LRU and SRU and subtotal s by equation,
as wel l as total s and percentages by cost equation. I t al so l ists the
l ogistic support costs for each A GE item required to support the system.
I n addition, it separates fixed l ogistic support costs from costs sensi-
tive to maintenance frequency. T hus, the model can determine the anti-
cipated support costs of a given system configuration.
28 4
T he model can determine the cost area which has the greatest impact
on the overal l cost. I t can be used as a tool to optimize system cost- -
eval uating potential al ternatives that meet design requirements. I t can
be used for parametric sensitivity anal ysis, determining the effects of
varying parameter val ues on the cost of an LRU, SRU and total system,
and aiding the identification and eval uation of risk and uncertainty
factors. I t can be used as a means of eval uating cost and performance
target goal s and as a vehicl e to budget total cost of ownership by cate-
gories of costs on a continuing basis. Final l y, it can be used to estab-
l ish the discipl ine data bases that can be used for cost eval uation of
other design configurations, as wel l as tracking the sensitive discipl ine
parameters during the design to cost and bal anced design phases.
4 .3 .2 Defining Cost and Rel iabil ity T argets
A ful l design to cost effort begins with the " requirements" process
and continues through production. T he appl ication of design to cost
goal s in DoD contracts becomes firmer as the project approaches its pro-
duction phase. T abl e 4 - 4 8 l ists contract cost factors in a design to
4 4
cost effort during the program phases.
4 .3 .2.1 Concept and Val idation Phase
During the conceptual phase, production costs, key support cost
factors and equipment quantity rel ationships are derived and compared
with " avail abl e" resources. T hese factors are iterated as primary
parameters during the formul ation of numerous essential performance
requirements for the new system.
Resul ting from this process are performance and rel iabil ity bands
and a target unit production cost. T he establ ished cost goal s can be
val idated and refined for use as primary design parameters, equal to
performance in priority during ful l scal e devel opment.
T he tradeoff process during the concept and val idation phases
incl udes:
unit cost versus rel iabil ity
unit cost versus performance
rel iabil ity versus performance.
28 5
T abl e 4 - 4 8 HYPO T HET I CA L DESI GN T O CO ST PRO GRA M
ro
CD
Program Phase/
Cost Governing Factor
Concept and
Val idation
Ful l Scal e
Devel opment Production
1 . Specification and
Request for Proposal
Limited number of
critical characteristics.
A dditional goal s or
features in terms of
priorities.
Minimum performance
features; no " how to"
specifications.
Minimum use of mil itary
specifications.
2. Cost Goal Variabl e (but defined)
budgetary estimate.
I ncreasingl y firm cost.
Possibl e production
price option.
Firm cost.
3 . Cost Goal
(support)
Life cycl e cost or
approximation (rel i-
abil ity or maintain-
abil ity). Life cycl e
cost may be source
sel ection criterion.
Same as concept or
val idation, but firmer
base.
Perhaps warranty.
4 . Contract Cost type. Cost type with possibl e
production options.
Fixed price.
5 . I ncentives Performance, rel iabil ity,
maintainabil ity, l ife
cycl e cost and, in some
cases, production unit
cost.
Production unit cost,
1 ife cycl e cost.
Profit. Production
unit cost goal .
Possibl e maintenance
warranty. Val ue
engineering.
I ssues of primary consideration during the tradeoff process are:
off- the- shel f requirements versus performance; compl exity versus rel i-
abil ity; redundancy versus weight and vol ume penal ties; and many others.
T he " design to" concept has, as a fundamental phil osophy, the notion
that tradeoffs can be made within the bal anced design framework of the
design to cost structure. Defining the l imits for tradeoff of R&M
parameters is of a critical importance. T he unit production price l imits
the cost of spares, the amount of buil t- in test equipment (BI T E), and
the l evel of functional rel iabil ity that can be designed into the system
to meet the operational avail abil ity requirement. T he operational
scenario, al ong with unit l evel rel iabil ity, defines the expected number
of system faul ts which wil l have to be serviced within the defined owner-
ship costs. Required system avail abil ity further constrains rel iabil ity
and establ ishes the maintenance and suppl y considerations that wil l have
to be designed into the system. A l l these factors, and more, enter into
the initial design trades if affordabl e systems are to be acquired. By
setting a unit production price and designing to it, the BI T E, redundancy,
and maintenance concepts that can be util ized are automatical l y l imited.
T he offsetting factors must be spares and manpower or avail abil ity.
A l though onl y l imited data is avail abl e in the earl y phases of the
l ife cycl e, the design to cost goal , as wel l as the minimal acceptabl e
performance requirements, shoul d be estimated as earl y as possibl e in
the conceptual phase (through LCC studies as previousl y described).
T hese estimates wil l have the primary purpose of providing visibil ity
to management so that the design configuration may be adjusted to provide
the most cost effective minimum within the constraints imposed and the
bal ancing objectives for performance, rel iabil ity, etc.
A s was mentioned previousl y, tradeoffs woul d have to be made over
the l ife cycl e of the system. T he cost tradeoffs during the conceptual
and earl y devel opment phases wil l be made at a gross parametric l evel
and wil l depend primaril y on the contractor's historical support data.
During these phases, operating and support costs, and research and
devel opment costs shoul d be verified to support system design. However,
this cannot be a true val idation but onl y a verification of the cost
driving parameters. For the most part, the significant factors wil l be
rel iabil ity, modul arization, faul t isol ation, sparing and manning.
28 7
Updated data banks must be used for estimating such parameters as
unschedul ed and schedul ed maintenance manhours, A GE util ization and
adequacy, technical manual adequacy, spare parts util ization, and diag-
nostic testing and training. During the devel opment phase, submodul e
al ternatives are stil l being considered and many of the required data
el ements are onl y estimates. T hat point at which a prototype is designed
is the first point at which accurate modul e/submodul e l ogistic and support
cost estimates can be made. T rade- offs which shoul d be made during this
phase incl ude test equipment versus maintenance manhours, rel iabil ity
growth program costs versus spares requirements, maintenance manhours
versus transportation and inventory cost to maintain spares pipel ines.
Cost targeting must be expanded to incl ude requirements on the number of
operating and maintenance personnel permitted, support equipment costs,
the number of l ine items permitted to be entered into inventory, and on-
equipment faul t detection and isol ation.
T hroughout the entire l ife cycl e in which the design to cost method-
ol ogy is empl oyed, the fol l owing two questions must be addressed:
(1 ) I s the l atest design iteration meeting the performance and
cost goal s?
(2) Do al ternative designs exist which further minimize the cost
of ownership and enhance the performance characteristics?
O nce a design has been chosen, tradeoff anal yses woul d then be very
detail ed and l imited to such things as changes in part qual ity, redun-
dancy, rel iabil ity goal s for particul ar components and producibil ity
methods. T hus, it is imperative that the initial anal yses focus atten-
tion on high cost areas and devel op al ternatives to reduce the cost.
Figures 4 - 7 8 and 4 - 7 9 il l ustrate the rel ationship between rel iabil ity,
maintainabil ity and cost. Figure 4 - 7 8 shows that as a system is made
more rel iabl e, everything el se being equal , the operation costs wil l de-
crease since there are fewer fail ures. A t the same time, acquisition
costs (both devel opment and production) must be increased to attain the
increased rel iabil ity. A t some point, each acquisition dol l ar spent on
increasing rel iabil ity wil l resul t in exactl y a dol l ar saved in operating
costs. T his point represents the rel iabil ity for which total costs are
minimum. Note that there are steps in attaining rel iabil ity which are of
28 8
Life Cycle Cost
Minimum
Life Cycle
Cost
oo
t
o
u
I v Development
I (Cost
Acquisition
Cost
Operating
Cost
Optimum Reliability/Cost Ratio
Minimum Reliability
Reliability
Fig. 4-78 COST VERSUS RELIABILITY
Total Cost
O
U
Acquisition Cost
Operating Cost
Maintainability
MTTR
Fig. 4-79 COST VERSUS MAINTAINABILITY
290
varying difficul ty and cost. T he cheapest increase in rel iabil ity woul d
be taken first and the most expensive l ast. T herefore, the cost of
rel iabil ity must be an upward increasing sl ope.
Essential to effective tradeoff studies is the definition of each
step and the devel opment of accurate rel iabil ity/cost curves for equip-
ment that shows the sensitivity and breakpoints of critical rel iabil ity
factors. I t is the objective of earl y trade studies to define a band
of acceptabl e performance and cost goal s. Figure 4 - 7 8 il l ustrates a
method of defining the minimum rel iabil ity and the maximum unit produc-
tion cost based on the minimum ownership cost principl es. We assume
devel opment cost is fixed over a l imited range of MT BF. T he right side
of the acceptabl e bound shown in the figure is constrained by the maxi-
mum unit production cost, and al so resul ts in a new optimum total cost.
T he l eft side bound defines minimum rel iabil ity l evel s. T he maximum
unit production cost shoul d be based on true affordabil ity considerations,
and traded and verified during the devel opment and production phases of
the program.
Like rel iabil ity, increasing maintainabil ity causes increased ac-
quisition costs and reduced operating costs. Maintainabil ity is general l y
measured in Mean- T ime- T o- Repair (MT T R); the l ess time required to repair
an item (the smal l er MT T R), the more maintainabl e the item. I f one takes
the reciprocal of MT T R to obtain a variabl e which increases with main-
tainabil ity and with cost of attainment of acquisition, exactl y the same
type of curves are obtained as for rel iabil ity (Figure 4 - 7 9 ).
Rel ationships can be derived to determine cost variations with equip-
ment performance assuming various technol ogies and rel iabil ity and
maintainabil ity approaches. Rel ationships can al so be derived defining
how rel iabil ity and maintainabil ity vary with performance (or with com-
pl exity, which is in turn dependent on performance) with cost hel d
constant. T he resul tant rel iabil ity and maintainabil ity for any given
performance can be referred to as the basel ine rel iabil ity and basel ine
maintainabil ity.
29 1
T he concept of avail abil ity is of val ue, in this context, for R&M
tradeoff studies. A vail abil ity is the abil ity of an item, under the
combined aspects of its rel iabil ity and maintenance, to perform its
required function at a stated instant in time.
A vail abil ity invol ves the appl ication of both rel iabil ity and main-
tainabil ity, ie.., MT BF and MT T R, and is expressed mathematical l y as
MT BF
A =
MT BF+ MT T R
A n avail abil ity assessment provides a measure of total equipment perfor-
mance. Equipment can be designed and buil t to have a high MT BF with
respect to MT T R, or ease of maintenance can be designed into the equip-
ment that woul d resul t in short maintenance time el ements and a l ow MT T R
with respect to MT BF. Frequentl y, the most practical way to achieve a
high probabil ity of equipment performance is to suppl ement the design for
rel iabil ity with a design for efficient and rapid repair and a high degree
of maintainabil ity. Quantifying these R&M factors in terms of avail abil -
ity provides an insight into the effectiveness of the equipment and
demonstrates numerical l y the impact of significant system R&M el ements.
I ncl uded in this insight is the effectiveness of the R&M design and
support factors.
T he tradeoffs between rel iabil ity and maintainabil ity must al so be
considered. For this purpose, additional rel ationships are derived which
state how rel ative cost changes as rel iabil ity or maintainabil ity is
varied from the basel ine. Figure 4 - 8 0 provides an exampl e of the rel i-
abil ity/maintainabil ity tradeoff process using the avail abil ity concept
described previousl y. T his figure can be interpreted as a resul tant
cost al l ocation approach for optimizing MT BF and MT T R. T he isocost and
isoavail abil ity curves shown here define the appropriate mix of MT BF and
MT T R to optimize cost. Note that the optimum R&M approach occurs at the
point of contact between the isoavail abil ity and isocost curves. T he
actual isocurves for specific equipment can be generated using computer-
ized cal cul ation procedures in conjunction with the rel iabil ity, main-
tainabil ity, cost and avail abil ity model s previous described.
29 2
Isoavailobility Curves
MTTR
Fig. 4-80 OPTIMUM COST ALLOCATION APPROACH
293
4 .3 .2.2 Devel opment and Production Phase
A s the program progresses through advanced and ful l scal e devel op-
ment, some cost (production and support) and performance tradeoff fl ex-
ibil ity is needed to permit the devel opment of acceptabl e systems within
the cost constraints. For this purpose, design to cost programs feature
these characteristics:
(a) End- item minimum performance goal s or specifications (to al l ow
tradeoff fl exibil ity) are used rather than detail design
specifications for systems, subsystems and components.
(b) T rade- off decision threshol ds for program managers are estab-
l ished to cl arify their authority to make tradeoffs within
the overal l cost, schedul e and performance requirements of the
program, and
(c) Sufficient devel opment time and resources are al l ocated to
iterate designs to reduce future costs.
T he iterative design process is an essential ingredient of effective
4 6
design to cost program impl ementation. Figure 4 - 8 1 il l ustrates several
phases in a design program with the emphasis on: 1 ) al l ocation of cost
goal s to the subsystem and component l evel , 2) estimates of subsystem
costs with comparison to target figures, and 3 ) real l ocation or redesign
to achieve total target cost goal s. T he process continues throughout
the program's l ife cycl e, incl uding the preproduction and production
phase.
T he initial cost goal al l ocation is devel oped by Program Management.
T he objective of the al l ocation process is to devel op cost goal s that
are under the designer's control . T his means that nonrecurring costs,
such as G&A , fee and devel opment cost, must be segregated from the
essential remaining costs that are within the designer's control . T he
principal recurring costs (material , direct l abor and support l abor) are
shown in Figure 4 - 8 2. T hese costs are further categorized by functions
or subsystems to establ ish a cost matrix that can be used as a Design
UPC worksheet. A n exampl e of a prel iminary Design UPC worksheet is shown
in T abl e 4 - 4 9 . T he initial al l ocation of system cost is based on an
estimate of the rel ative compl exity of each individual subsystem. Note
29 4
Phase I
Preliminory
Design
Define Top
Target Cost
Contract
T
Generate Target
Cost Breakdown
By Assembly
Material and Labor
Progrom Manager
Define Preliminary
Design
Technical Director
Phose in
Pilot
Production
To Design
Change *
Compare
Actuals To
Estimates
Production
1
Generate All
Cost Estimates
Production
1
Resolve Target
To Estimate
Deltas
Progrom Manoger
Establish Design
To Cost Target
Program Manager
3
"Processes" {How To)
Design Definition
To Meet Cost
Estimates
Production
Obtain
Hardware
Production
Assemble 8 Test
Hardware
Production
Determine
Element Cost
Production
1
Phose n
Design
Spec Change
rnrrortive Action
(internal or Consumer)
From
Phase I
Design
Budget
Target Cost
Technical Director
Design Changes
Technical Director
1
_E
Design Product
To Cost Target
Technical Director
Estimate
Costs
Production
Compare
Estimates To
Targets
Technical Directory
To
Phase n
Design
Approve Design
Program Manager
Chief Engineer
To Phase m
Pilot Production
From Phase n
Design
To
Phose ISO
Production
From Phase IE
Pilot Production
Phose IE
Assemble 8 Test
To Allowable Cost
Production
Monitor Cost
Production
To Design
Change
Compare Actual
Costs To
Allowable Cost
Production
Release Hardware
To Customer
Fig.4 - 8 1 DESI GN T O CO ST PRO GRA M PHA SES (Ref 4 6)
Price Goal
(Contract)
LBMB
(Prog. Mgr.)
(Functional Mgr.s) (Tech. Dir.)
Non-
recurring +N
Recurring
/
Material
/
Labor
/
/
Material
/
/
/
/
/
/
/
Electronic
(El. D.E.)
/
/
/
L
Basic Level I
Functions
(Systems Eng.)
G 8 A +Fee
(Div. Mgt.)
(Des. Process Eng.)
Direct
Labor
Support
Labor
UPC Goal
Fig . 4-82 DESIGN TO TARGET COST MODEL
296
T abl e 4 - 4 9 PRELI MI NA RY DESI GN UPC WO RKSHEET - PHA SE 1
4 6
Dev i ce Computer
Labor Rates June 1 9 7 5
Quant ity_ 4 0
Date December 1
t
1 9 7 4
Production Rate 3 /Month
T op T arget $ 4 0 , 0 0 0
Lot Quantity 3
Function
Percent
Compl exity
60 %
Material
T ar. Est.
3 0 %
Direct Labor
T ar. Est.
1 0 5
Support
T ar.
Labor
Est.
1 0 0 %
T otal
T ar. Est.
Memory 22$ 4 .5 3 .2 1 .1 8 .8
CPU 25 * 7 .4 1 .9 0 .7 1 0 .0
Chassis 20 3 .6 3 .3 1 .1 8 .0
Power Suppl y 4 $ 4 .0 0 .4 0 .2 1 .6
Final A ssembl y 3 *

0 .9 0 .3 1 .2
Unit T est 1 4 $

4 .1 1 .5 5 .6
I /O 1 2$ 3 .9 0 .7 0 .2 4 .8
T otal 1 0 0 ? 20 .4 1 4 .5 5 .1 4 0 .0
" SHO ULD CO ST "
that the estimate is based on a known total :
production quantity,
production rate, and
cost rel ated to a specified base year,
Historical data is used to make an initial estimate of the distri-
bution of cost between material , direct and support l abor. A fter pre-
l iminary design data is generated, production cost estimates are generated
and the data compared with target val ues. T abl e 4 - 5 0 compares the esti-
mates with target costs and shows adjusted target cost where deviation
against the target woul d not be reduced by further design change. T o
meet total contract cost goal s, it was decided (in this exampl e) to reduce
nonrecurring product design costs.
T he subsystem can now be further defined by the components, chassis,
connectors and cabl es that make up these subsystems. I n the same manner
as described above, target costs can be al l ocated to the component l evel
and firm costs can be estimated and compared with the target val ues. T he
costs are shown in the Work Breakdown Structure (WBS) in Figure 4 - 8 3 .
T he WBS is a useful method of al l ocating both cost goal s and task assign-
ments to individual designers. T abl e 4 - 5 1 l ists target val ues for sub-
assembl ies; the procedure for al l ocating, estimating and resol ving devia-
tion from target cost is the same as previousl y discussed. A t this point,
it is possibl e to improve the accuracy of the estimates and set standard
hours for assembl y and test of the individual subsystems. Standard hours
can be estimated by production personnel , given the production rate and
total quantities.
I t shoul d be noted that tradeoffs can be made between support cost
and component types, as wel l as assembl y time, to achieve the overal l
target cost goal . Methods for estimating and sel ecting the l owest cost
sol ution is the subject of Section 4 .3 .3 .
I n the previous exampl e, it was simpl e to rel ate the subassembl y's
performance function to its cost. I n many cases, it is difficul t to
separate cost and function, since a particul ar performance function is
shared by several assembl ies. Since cost and rel iabil ity estimates can
be more easil y estimated against subassembl ies (using rel iabil ity work-
sheets as described in Section 4 .1 ), it is useful to empl oy a function
29 8
T abl e 4 - 5 0 PRELI MI NA RY DESI GN UPC WO RKSHEET (CO MPLET ED)PHA SE 1
4 6
Device Computer Production Rate 3 /Month
Labor Rate June, 1 9 7 5
Quantity 4 0
T op T arget
Lot Quanti 1
$ 4 0 , 0 0 0
:y 3
Date December 1 , 1 9 7 4
Function
Percent
Compl exity
60 %
Material
T ar. Est.
3 0 %
Direct Labor
T ar. Est.
1 0 % 1 0 0 %
Support Labor T otal
T ar. Est. T ar. Est.
A djusted
T arget
Memory 22? 4 .5 5 .0 3 .2 4 .0 1 .1 1 .4 8 .8 1 0 .4 9 .0
CPU 25 ? 7 .4 7 .3 1 .9 2.3 0 .7 1 .0 1 0 .0 1 0 .6 1 0 .6
Chassis 20 ? 3 .6 4 .2 3 .3 3 .6 1 .1 1 .3 8 .0 9 .1 8 .9
Power Suppl y 4 ? 1 .0 1 .3 0 .4 0 .9 0 .2 0 .9 1 .6 3 .1 2.6
Final A ssembl y 3 *

0 .9 1 .4 0 .3 0 .6 1 .2 2.0 2.0
Unit T est 1 4 ?

4 .1 3 .6 1 .5 1 .0 5 .6 4 .6 4 .6
I /O 1 2? 3 .9 3 .8 0 .7 1 .2 0 .2 0 .6 4 .8 5 .6 5 .6
T otal 1 0 0 ? 20 .4 21 .6 1 4 .5 1 7 .0 5 .1 6.8 4 0 .0 4 5 .4 4 3 .3
o
o
Computer
T 43.3
E 43.36
I
Memory
T 9.0
E 13.75
CPU
T 10.6
E 8.3
As
Connectors
0.4
0.38
Cables
0.5
0.5 5
Stack
JT 8.1
JE 12.83
Planes
T 7.5
E 11.91
KeepS Subst
T 0.6
E
Compon.
Chassis
8.9
74
Main SCR
Cold Plates
Connectors
Filter Box
r
Power Sup.
2.6
2.8
1 Fin* ]l Assy. |
T 3.0
E 1.5
A,
+ 15 V
+5 V
-10V
PCB's
Unit Test
4.6
E 3.8
X
-
I/O
T 5.6
E 5.8
As
Transform
Compon.
Chassis
T
1 E
Conn a Comp.
Struct
Fig.4 - 8 3 WO RK BREA KDO WN ST RUCT URE (Ref 4 6 )
T abl e 4 - 5 1 UNI T PRO DUCT CO ST MA T RI X
4 6
CO
o
Product Line
Cuni j. )u l er
UPCT (LBMB)
Production
Date
Rev. No.
$ 9 . O K
Device Rate
Page of
Cum. A ve. Quantity
Lot Size
Subsystem
Standard
Hours
Mater
$ K
ial
Direct
Labor
$ K
Support
Labor
$ K
T otal
$ K
1 .0 Memory T ar. Est. T ar. Est. T ar. Est. T ar. Est. T ar. Est.
1 .1 Stack 9 1 .0 24 3 .0 4 .3 4 .8 2.5 3 6.7 6 1 .27 1 .27 8 .1 1 2.8 3
1 .2 Cabl es 4 .4 4 .6 0 .3 0 0 .3 3 0 .1 2 0 .1 4 0 .0 8 0 .0 8 0 .5 0 0 .5 5
1 .3 Connectors 5 .1 5 .4 0 .20 0 .1 7 0 .1 4 9 .1 5 0 .0 6 0 .0 6 0 .4 0 0 .3 8
T otal 1 0 0 .0 25 3 .0 4 .8 5 .3 0 2.7 9 7 .0 5 1 .4 1 1 .4 1 9 .0 1 3 .7 6
versus subassembl y worksheet of the type shown in T abl e 4 - 5 2. Estimates
of the fraction of the subassembl y that performs a specific function are
determined by the designer. Using known part counts for the subassembl y,
it is possibl e to estimate the number of components required to perform
a particul ar function. Both l abor and material cost to perform the
function can now be estimated as shown in Figure 4 - 8 4 . T he rel iabil ity
or fail ure rate associated with the performance of the function can al so
be estimated using part count or rel iabil ity stress worksheets. T he need
for the performance function can then be scrutinized in l ight of the
knowl edge of the cost of the function and unrel iabil ity associated with
the design. T rade- offs can be made with ful l knowl edge of the cost to
incl ude a specific function in the system.
4 .3 .2.3 Bal anced Design Management
A s previousl y indicated, an effective mil itary system must seek a
bal ance between performance, R&M and cost. T he bal ancing must be done
on a tentative basis, such that the bounds for al l parameters can change.
A bal anced design management technique must be structured which provides
visibil ity into system costs and shows how they rel ate to performance
and R&M requirements. T he management technique must provide a means of
ascertaining whether the design configuration can be establ ished within
the " design to" goal s and, if not, to give warning of this in time to
permit corrective action. I n addition, the bal anced design methodol ogy
must maintain a historical record of al l parameters associated with the
design configurations.
A concept presentl y being used in the design stage of ongoing pro-
grams invol ves the formation of a bal anced design team, composed of
representatives from the mil itary program office and contractors. T his
team participates in reviewing ongoing designs and pl anned production
processes in order to provide information and al ternatives that woul d
enhance performance and/or reduce cost. During earl y system devel opment,
conceptual cost of ownership studies were used to derive target " design
to" goal s covering the bal ancing parameters, and were assigned to each
equipment item. T hese target goal s were then used as the basis for
bal ancing each design parameter.
3 0 2
Elec. Piece Part
Count Per System
o
>

#5 Enclose LRU
(Chassis Misc.
Hdwr)
# 3 Interface
Circuit (Mother)
#2 Maintain Min.
Sol. Volt. (BUS)
#1 Convert a Reg.
Cir. Volt (P/S)
w

d ) Monitor Thrust
Pressure a
Denote Fail
c) Command/SO
Valve Closure
c
x

3
*

O

5

1

-

Q

a
.

a,e) Interpret a
Validate Input
Com.
r
o

p

c
_

o

-
n

m

1
0

/

"

/

"
O
S

/

a
/

s

/

2

/

P

0
0

C
T

.

x
-

o

i

-
i

c

T
3

3
2
3

b

8
0
9
1

-
1

6
7

o

a

o

-
2

6
0
6

o

o

-
3

6
1

b

-
4

2
7
3

o

b

o

-
5

1
4
2

b

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6

1
4
4

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0
1

-
7

8
4

o

8

-
8

1
5
8

b

-
9

4
3

b

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1
0

3
0

b

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I
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1
7
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b

-
1
2

1
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8
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b

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1
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4

o

-
1
5

6

6

-
1
6

1
2

b

-
1
7

8
8

b

-
1
8

7
6

b

-
1
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2
0

5

3
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8
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4
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/
4
3
/
4
6
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3

E
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l

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a
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t
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t
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;
0

LRU UPC
Material Labor
1-
Design-to-Cost Overbuy Support
1
Direct
Total
(Labor Breakdown/
Material Breakdown)
o
*
Assembly
1
Test
Functional
Electronics
Interconnects
Circuit Boards
Mechanical
Equipment
Piece
Parts
Cards 8 Co. Conn.
Mother BD.
Harness
Conn. 8
Misc. Inter.
Final
Assembly
Card
Test
Engineering Support 8
Acceptance Test
Procedure
Fig 4-84 LRU-UNIT PRODUCTION COST

T o assure that the team has the proper data, in the proper format
at the proper time, a management information system (MI S) containing
each discipl ine's data banks (e.g., R^ , M, etc.) can be devel oped as
part of the program.
T he MI S serves as a record keeper and processor for al l data rel ated
to bal ancing a system design. I t serves as a vehicl e for providing
effective technical interface, as wel l as pertinent reports, to mil itary
personnel concerned with bal ancing design parameters. T herefore, the
primary purpose of the MI S is to facil itate proper bal ance of pertinent
system parameters, such as cost, performance, rel iabil ity, maintainabil ity
and producibil ity. T he actual bal anced design is accompl ished through
an iterative process which resul ts in a continuous update of the esti-
mated val ue of each system parameter. T hus, a higher degree of confidence
can be given to the acquisition cost, l ogistics support cost, and cost of
ownership as the system is devel oped. I n addition, it provides visibil ity
to al l the " design to" goal s. O utputs of the MI S are avail abl e at each
significant mil estone (e.g., design reviews). T hus, the MI S al l ows the
" bal anced design" team to fl ag areas that may require further design
effort to reduce costs or enhance rel iabil ity, performance, etc.
Figure 4 - 8 5 contains a conceptual diagram of the MI S record form.
Each data el ement in the structure is representative of a functional
unit of the system (i.e., SRU) and is rel ated to its succeeding l evel
(i.e., LRU). T his type of arrangement provides a comparison of target
val ues to estimated val ues.
A tol erance band is displ ayed in terms of " greater than" or " l ess
than" goal s. T hese tol erances indicate the maximum band of acceptabl e
fl uctuations of the system parameter val ues. Exampl es of the bal ancing
parameters and the data el ements to be stored in the MI S are: cost
(material , acquisition, LSC), rel iabil ity (MT BF, parts count), maintain-
abil ity (faul t detection, on- l ine and off- l ine, BI T E, MT T R, A GE), pro-
ducibil ity (percent subcontracted, percent LSI , discrete circuits, etc.),
configuration (weight, power, vol ume), and survivabil ity (EMP, nucl ear
hardening).
3 0 5
System
Acquisition Cost
Reliability
Maintainability
Performance
Acquisition Cost
Reliability
Maintainability
Performance
Acquisition Cost
Developement Cost
Cost of Ownership
Reliability
Maintainability
Performance
Acquisition Cost
Reliability
Maintainability
Performance
Acquisition Cost
Reliability
Moinfainobility
Performance
Fig 4-85 MIS RECORD FORMAT
A l though the comparisons to be made within the bal anced design are
rel ativel y few and simpl e, great quantities of data must be processed
and disseminated. T he MI S is both economical l y and technical l y suited
for computer processing. A computerized version al l ows for a greater
degree of fl exibil ity and responsiveness.
Because of continual iteration of the design during system devel op-
ment, many computer runs are performed to eval uate and revise the bal anc-
ing parameters. Preformatted keypunch cards and MA CRO S (open subroutines
which al l ow the programmer to al ter input parameters and have several
executions during a singl e computer run) assure rapid computer processing.
T he MI S was structured such that parameters outside of the target
goal tol erance band are fl agged. T hese fl agged val ues are used by the
" bal anced design" teams for anal yses/tradeoffs. T hese val ues are used
with the previous data to derive new targets, new design configurations,
etc. T he general fl ow of information rel ated to the function of the MI S
through the bal anced design process is depicted in Figure 4 - 8 6.
T he MI S, therefore, facil itates the bal ancing of the system param-
eters (cost, rel iabil ity, maintainabil ity, survivabil ity, design configur-
ation, performance and producibil ity). T he bal ancing is accompl ished
through an iterative process where the various parameters are continuousl y
monitored and updated. Hence, the MI S provides the vehicl e for both
col l ecting and disseminating parameter val ues at each iteration. T hus,
a historical record of the design process for an LRU, SRU or any param-
eter is retrievabl e at any point in time.
4 .3 .3 Meeting Cost and Rel iabil ity T argets
T he previous section described methods of defining, al l ocating, and
managing cost and rel iabil ity goal s. T he handbook woul d not be compl ete
if it did not provide guidance to enabl e a designer to meet the defined
cost and rel iabil ity targets. Meeting cost constraints is the subject
of this section and wil l be treated at two l evel s: 1 ) the broad system
trades made during the earl y concept and val idation phase, and 2) detail ed
cost tradeoff invol ving component sel ection.
3 0 7
R
Specs
M
Specs
Producibility
Specs
GO
O
00
Cost
Specs
LRU/SRU
Design
R
Predicted
M
Predicted
L S Cost
Predicted
Data
Entered
in MIS
Acquisition
Cost
Predicted
Performance
Predicted
MIS
Output
Balanced
Design
Team
USAF
Review
Decision
Review
Analyses/
Tradeoffs
Fig 4 -86 MIS INFORMATION FLOW
Concept and Val idation Phase
T he B- l offers an excel l ent exampl e of the appl ication of design- to-
cost principl es. A s original l y conceived, the el ectronics for this air-
craft woul d cost $ 1 0 - 1 2 mil l ion per aircraft, weigh about six tons and
woul d consume 1 0 0 kW of power. A l though it was acknowl edged that B- l
mission needs are compl ex, it was fel t that the requirements coul d be
met at l ower cost, by appl ying " design- to- cost" principl es. T he end
resul t of the cost cutting effort was to remove three tons of el ectronic
4 5
equipment and an expectation of improvement of the fiel d rel iabil ity.
For exampl e, the B- l wil l now have two good inertial navigators on board
for l ess than the price of one more precise navigator and the radar wil l
cost l ess than hal f of that original l y proposed. T he " design- to- cost"
principl es used to achieve these resul ts from the B- l can be general ized
4 5
for most other aircraft programs. T hey are:
(1 ) Review of al l requirements for avionics against both the
specific designs needed and against the cost of the design.
(2) When stated requirements drive costs undul y, other means
shoul d be sought to satisfy the requirements.
(3 ) Equipment of proven and rel iabl e performance shoul d be
sel ected in preference to starting compl etel y new designs,
even if the ol der equipment needs modification to adapt
and fit.
(4 ) A ppl y standardization principl es whenever possibl e.
(5 ) Bal ance, and if necessary change, operational procedures if
simpl er, l ess costl y equipment can be found to do the job.
(6) A l l ocate and define cost goal s for individual subsystems of
the avionics compl ements.
(7 ) El iminate, or put into a phase of intensive advance devel op-
ment, high risk equipment to prove and reduce cost.
(8 ) Segregate equipment by function (e.g., offensive and defensive
subsystems) to reduce compl exity and to increase fl exibil ity
of the computer software.
3 0 9
(9) Use standard (of f -th e-sh elf ) equi pment wh ere possi ble. H old
i ndustri al competi ti on to select equi pment.
T h e above li st i s by no means complete and only outli nes a common-
sense approach to equi pment selecti on i n th e early ph ase of th e desi gn.
T he role of th e desi gner duri ng th i s ph ase i s to provi de cost and reli -
abi li ty data usi ng li mi ted detai l desi gn i nf ormati on. One of h i s ef f orts
i s to i denti f y costly processes or h i gh ski ll levels and manpower cost
associ ated wi th alternati ve desi gn requi rements. T h e desi gner must be
aware of th e li mi ts of avai lable tech nology and be ex peri enced enough to
relate past problem areas to th e proposed desi gn requi rements. As th e
desi gn i s i terated and better def i ned, th e cost reli abi li ty trade-of f s
can be more mech ani zed and better def i ned.
T h e nex t secti on descri bes th e procedures necessary to perf orm
detai led trade-of f at th e component and system level.
Development and Producti on Ph ase
T h e cost of unreli abi li ty i s usually measured i n terms of th e added
repai r and replacement cost accrued i n th e f i eld resulti ng f rom a f ai lure
of a component. T h i s cost can be compared wi th th e i ncremental uni t cost
of a component of h i gh er reli abi li ty. If th e added component cost i s less
th an th e savi ngs resulti ng f rom reduced f i eld f ai lures, th e h i gh reli abi l-
i ty component sh ould be selected. Reli abi li ty parameters can be used to
esti mate th e ex pected cost of f i eld f ai lures. Alth ough appli cati on of
th e pri nci ples outli ned above sh ould yi eld a desi gn wh i ch mi ni mi zes
ownersh i p costs, th e resultant desi gn may not meet th e program " desi gn-
to-cost" goals. In addi ti on, component costs are not th e only contri buti on
to uni t producti on cost. H i gh reli abi li ty requi rements can of ten add to
th e labor cost by requi ri ng h i gh er labor ski ll levels. On th e oth er h and,
low reli abi li ty components can i ncrease uni t producti on cost by requi ri ng
added quali ty support labor, i ncrease system test ti me and scrap rate,
and i ncrease th e probabi li ty of h i gh er cost platf orm and/or oth er veri f i ca-
47
ti on test f ai lures. ' T h e added costs wi ll eventually be ch arged th rough
vari ance and overh ead accounts to uni t producti on cost.
T h e deci si on to select alternati ve h i gh reli abi li ty equi pment can be
based on th e f ollowi ng equali ty. If th e ch ange i n component cost and labor
310
requirements are l ess than the added support costs, expected test fail ure
costs and expected fiel d fail ure costs,
A Component Cost + A Labor Cost <A I nspection Cost
+ A Expected in Process Fail ure T est Cost+ A Expected Fiel d
Fail ure Cost
then sel ect the high rel iabil ity equipment.
T he general formul a to be used for the sel ection of individual com-
ponents or a compl ete system is more formal l y given bel ow:
n
CQ < Q I (A P(f)
i
xC.) + QxA P(f)xC
f
i= l
where
A C = average added cost of a high rel iabil ity part over a
standard part (both parts and l abor)
0 = quantity of parts per system
A P(f). added fail ure probabil ity of l ow rel iabil ity fail ure
over a standard part during the i* h test phase
n = number of test phases
C. = cost of fail ure during the i
tn
test phase
A P(f) = probabil ity of fail ure in the fiel d A P(f)
m
A A T
C\p = cost of fiel d fail ures.
Sel ection of equipment that satisfies the inequal ity wil l resul t in the
l owest ownership cost. I f the second term on the right of the equation
is disregarded (i.e., expected fiel d fail ure costs) and the inequal ity
is satisfied, l owest unit production cost wil l be attained.
Fiel d Cost Versus Component Cost
T he simpl est comparison that a designer can make is between unit
component cost and fiel d fail ure costs. T he underl ying assumption in
this approach is that the added fabrication l abor costs incurred by
sel ecting the high rel iabil ity design is offset by the saving resul ting
from a reduction of test rel ated fail ures. With the understanding of
the assumptions, the rul e is appl ied as fol l ows:
3 1 1
(a) Estimate the (inherent) fail ure rate (A ) of each al ternative
design (use stress derating tabl es and formul as as described
in MI L- HDBK- 21 7 B- - see Section 2).
(b) Estimate the useful l ife of the system (T ).
(c) Estimate the cost (C) to service each fail ure in the fiel d.
T he expected cost of fiel d fail ures is:
E(Cost) = A T . C
T abl e 4 - 5 3 l ists the parameters and costs of three al ternate transistor
4 8
designs. T he fail ure rate (A ) was estimated using the fol l owing
formul a:
A =
x
b
(^
E
^
Q
Vs2
)
where A . is the base fail ure rate adjustment factor shown in the tabl e.
A djustment factors are l isted in T abl e 4 - 5 3 . Val ues were obtained from
MI L- HDBK- 21 7 B using avail abl e design data. Note the change in total cost
of the transistors as the equipment's l ife increases.
T he effect of adding a component to a circuit can al so be eval uated
using the approach. T he procedure and input data are used to compute the
fail ure rates (T abl e 4 - 5 4 ) so that two total rel iabil ity costs are com-
puted with and without cl amping diodes in the circuit. T he estimated
cost in these il l ustrations does not represent total fiel d fail ure cost,
but represents onl y those factors over which the designer has direct
control .
StandardizationCosts and Savings
Component standardization can reduce the unit production cost of the
system as wel l as devel opment cost. Standardization al l ows quantity dis-
counts in the purchase of components and can significantl y reduce docu-
mentation cost during devel opment.
A rel iabil ity study of two radar systems (A PQ- 1 20 and A PQ- 1 1 3 )
found the program which emphasized standardization (A PQ- 1 1 3 ) util ized
one- third fewer piece part drawings and 28 0 0 fewer piece parts to achieve
basical l y the same functions that the A PQ- 1 20 provides. Comparisons of
part standardization are shown by part type in Figure 4 - 8 7 . T his chart
3 1 2
T abl e 4 - 5 3 SELECT I NG T HE O PT I MUM T RA NSI ST O R
4 8
*
u>
Computati ons
T ransi stor #1
Wi th out H eat Si nk
T ransi stor #1
Wi th H eat Si nk
T ransi stor #2
Wi th out H eat Si nk
T V Envi ronmental F actor (Aj) 25 25 25
T T
Q
Q uali ty F actor 0. 4 0. 4 0. 4
T T . Appli cati on F actor 1. 5 1. 5 1. 5
T T
S2
V oltage Stress 0. 75 0. 75 0. 48
x . Base F ai lure Rate (x 10'
6
h rs) 0. 06 3 0. 016 0. 010
x F ai lures per 10 h rs 0. 709 0. 18 0 .1 1
MT BF (Mean T i me Between F ai lures) 1,410,437 5 ,5 5 5 ,5 5 5 9,090,909
Percent F ai lures/Year 1. 22% 0. 31% 0. 19%
F i eld Cost/1 Year 30. 8 * 7. 9* 5 . 0*
F i eld Cost/2 Years 6 1. 6 * 15 . 8 * 9. 0*
Standard Cost/Year 25 . 0* 33. 0* 4 0 .0 *
T otal Cost/Year 5 5 . 8 * 40. 9* 45 . 0*
T otal Cost/2 Years 8 6 . 6 * 48 . 8 * 49. 0*
T abl e 4 - 5 4 CO MPA RI SO N FO R DESI GN T O A DD A DI O DE
4 8
I
Computation Without Diode With Diode
T V Environmental Factor (A
F
) 25 25
T T
Q
Qual ity Factor 0 .4 0 .4
T T . A ppl ication Factor 0 .5 0 .5
T T
S2
Vol tage Stress Factor 0 .7 5 0 .4 8
x
b
Base Fail ure Rate (x 1 0 hrs) 0 .0 63 0 .0 63
A (Fail ures per 1 0 hrs) 0 .7 0 9 0 .4 5 4
MT BF (Mean T ime Between Fail ure) 1 , 4 1 0 , 4 3 7 2, 20 2, 64 3
Percent Fail ures/Year 0 .4 68 % 0 .3 0 %
I nitial Part Cost 4 0 .5 <t 4 5 .0 *
Warranty Cost/Year 1 1 .9 * 7 .6*
Standard Cost/Year 4 0 .0 <t 4 5 .0 *
T otal Cost/Year 5 1 .9 5 2.6<t
100"
80--
*0
O
c
60--
I 40
20
j
E
3
APQ 113
Cost Savings^
APQ 120
APQ !!3
-800
-600
--400
o
o
-200 ~
in
a>
c
>
o
en
--o
o
o
Res
'200
Fig. 4-87 PART STANDARDIZATION-COST SAVINGS ( Ref 47)
shows the percent of total part popul ation of a generic part type as a
function of the number of different part drawings util ized. Figure 4 - 8 8
shows an estimate of initial potential cost savings avail abl e through
parts standardization based on a cost of $ 5 0 0 0 to make and rel ease a part
drawing. T he savings avail abl e through pool ed- buy purchase agreements
woul d provide additional cost savings and resul ts in reduced unit produc-
tion cost.
Standardization is appl ied through the use of a Preferred Parts
List (PPL) distributed to the designer. A l though the PPL shoul d be
compil ed with preference given to components of high known rel iabil ity,
standardization can l ead to a compromise of rel iabil ity. Listed in
T abl e 4 - 5 5 is the MT T F of five vacuum tube designs at five different
vibration l evel s.
T abl e 4 - 5 5 MT T F O F A LT ERNA T I VE T UBE DESI GNS
4 9
Probabil ities 0 .1 0 0 .20 0 .4 0 0 .1 0 0 .20 % of T ubes Used
States of Nature N
l
Vibrat
N
2
ion Level
N
3
N
4
N
5
Expected
Val ue (EV)
S, Present Desi gn 20 0 20 0 20 0 20 0 20 0 20 0
S2 Design 2 1 8 0 1 8 0 260 1 8 0 1 8 0 21 2
(Singl e Best)
S
3
Design 3 24 0 220 20 0 1 8 0 1 8 0 20 2
S- Design 4 1 8 0 20 0 20 0 21 0 24 0 20 7
Sr Design 5 1 8 5 1 7 5 1 65 1 5 5 1 4 5 Dominated
T he highest rel iabil ity can be achieved by sel ecting the tube that
performs best at the specified vibration l evel . Since onl y one tube can
be produced economical l y, tube design 2 shoul d be sel ected and wil l pro-
duce the highest l evel of rel iabil ity at al l vibration l evel s. T he tabl e
il l ustrates the appl ication of principl es of decision theory to product
design. Reference 4 9 offers a more compl ete discussion of decision
theory.
3 1 6
APQ 120-
APQ 113-
Tota!
Parts
-13553
10704
20 30 40 50
Cumulative Number of Different Drawings
60
398 '605
Fig.4-88 DRAWING STANDARDIZATION COMPARISON
COMPOSITE OF ALL DRAWINGS (Ret 47)
Component Cost Versus Expected Cost of Fail ure During System T est
A system wil l be subjected to several phases of test during its
production. T hese can incl ude:
I ncoming T est
I n- Process T est
Rel iabil ity A cceptance T est (RA T )
Pl atform T est
T he cost of fail ure during test increases as the system progresses to a
higher assembl y l evel . T abl e 4 - 5 6 l ists estimated fail ure probabil ities
for both high and l ow rel iabil ity components, based on the A PQ- 1 1 3 system
4 7
devel opment experience. T o decide whether the added cost of the high
rel iabil ity components is paid for during the system test phase, the
fol l owing inequal ity is tested.
n
A C- Q<Q I A P.(f)- C
i
'
i= l
where
A C = the average additional cost per component = $ 1 .0 0
Q = Quantity of Parts/System = 1 0 , 7 0 0
T herefore,
A C- Q = $ 1 0 , 7 0 0
A P. and C. are given in T abl e 4 - 5 6.
Q[(P
1
(HR)- P
1
(S)).C
1
+ (P
2
(HR)- P
2
(S)).C
2
+ 0 .3 0 (P
3
(HR)- P
3
(S)).C3 + (P
4
(HR)- P
4
(S)).C
4
1
= 10,700($0.384+$0.48+$0.015 +$0.5 0)
= $14,75 8
T he added expected cost of test fail ure is greater than the increased
cost of the component; therefore, the high rel iabil ity components wil l
resul t in the l owest unit production cost.
3 1 8
T abl e 4 - 5 6 A PQ- 1 1 3 PRO DUCT I O N T EST FA I LURE EXPERI ENCE
4 7
P^ S) P^ HR) C
i
% Fail ures % Fail ures Cost
T est Phase Std. Parts High Rel . Parts of Fail ure
I ncoming 3 .0 % 0 .6 % $ 1 6
I n- Process 0 .4 % 0 .0 8 % $ 1 5 0
RA T * 0 .0 2% 0 .0 0 3 % $ 3 0 0
Pl atform 0 .0 3 % 0 .0 1 % $ 2, 5 0 0
3 0 % of systems presented to RA T .
Estimates of both fail ure probabil ities and cost of fail ure wil l
vary with the type of system being devel oped, and the manufacturer must
devel op data from his test experience. I f the costs of test fail ure are
correctl y accounted for, high rel iabil ity parts can be justified and
resul t in l ower production cost in many system production programs.
T he fail ure probabil ities in T abl e 4 - 5 6 incl ude both inherent
rel iabil ity fail ures and infant mortal ity type fail ures. I f a screening
program is introduced into the production program, the cost of burn- in
5 0
can be directl y compared to reductions in other product and QC costs.
Figure 4 - 8 9 il l ustrates the impact of a burn- in program on production
and QC costs.
A cost eval uation of product environmental screening of the A PQ- 1 1 3
Radar was performed in Reference 4 7 . T ypical burn- in costs were compared
with the cost of pl atform fail ure. T o quote from the study, " T he product
environmental screening investment woul d have been compl etel y amortized
if onl y 24 percent of the factory burn- in precipitated fail ures had
escaped to fail at the fiel d pl atform l evel . A ctual l y, it was found
that 4 0 to 8 0 percent of the LRU's tested, fail ed burn- in, most occurring
during the first temperature cycl e." Without burn- in tests, the majority
of these fail ures woul d have been detected during pl atform testing.
3 1 9
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5

Bal anced Design- - Meeting System Requirements
A methodol ogy has been establ ished to eval uate the rel iabil ity of
a design in terms of
(a) System Fiel d Fail ure Costs, and
(b) T otal Unit Production Costs.
A strong case has been establ ished that high rel iabil ity components and
rel iabil ity provisioning can reduce production costs. I t is al so con-
ceded that, often, rel iabil ity and unit cost goal s can be in confl ict and
a designer must bal ance his design to meet both of the contractual re-
quirements. T o achieve a total bal anced system design, a cost versus
rel iabil ity tradeoff must be performed. T he exampl e and methodol ogy
presented were original l y described in Reference 5 1 .
T hree component groups are defined, each having three l evel s of
rel iabil ity. T abl e 4 - 5 7 l ists both costs and fail ure rates for each
group and rel iabil ity l evel for equipment under consideration for a
Missil e I nterface Unit, proposed for use in a manned bomber.
T he component groups categorized by the various degrees of rel iabil ity
yiel d 1 8 combinations shown in T abl e 4 - 5 8 . For exampl e, point 4 is com-
puted in the fol l owing manner:
1 0
6
MT BF

=
29 .0 + 3 .5 + 0 .1 8 + 3 3 .0
MT BF = 1 5 , 225 hours
Cost = 11,65 0+ 1,5 60 ($0.5 4)
Cost = $12,984
A l l computed points can be displ ayed in a scatter pl ot as shown in
Figure 4 - 9 0 .
A rel iabil ity requirement of 1 9 , 0 0 0 hours is shown as a horizontal
l ine in the figure. Using point # 1 as a reference, equipment rel iabil ity
must be increased to one of the al ternate configurations. A l ine to
point 9 , or condition (2, 2, 1 ), exhibits a 1 9 , 4 9 3 hour MT BF at the l owest
cost of $ 1 2, 7 7 6 per unit.
3 21
T abl e 4 - 5 7 CO ST /RELI A BI LI T Y WO RKI NG DA T A '
4 8
CO
Component
Group
Quantity
(Q)
MI L- ST D
Fail ure
Rate f.
(Per 1 0

hrs)
Med. Rel .
Fail ure
Rate
Cost of
Med. Rel .
(Per Comp)
High Rel .
Fail ure
Rate
Cost of
High Rel .
(Per Comp)
1 . I ntegrated
Circuits
5 25 29 .0 1 4 .5 $ 0 .5 4 3 .63 $ 3 .0 0
2. Semiconductors 1 5 60 7 .1 3 .5 0 .5 4 0 .8 9 2.5 0
3 . Resistors 28 0 0 .3

0 .1 8 1 .7 5
4 . O ther Part T ypes
3 3 .0

T otal Fail ure Rate
Equival ent MT BF
T otal Cost Based on
MI L- ST D parts
= 69 .4
= 1 4 , 4 0 9
= $ 1 1 , 65 0
T abl e 4 - 5 8 CO ST S A ND MT BF FO R A LL CO MBI NA T I O NS
O F RELI A BI LI T Y SCREENS
5 1
Point
Number
Rel iabil ity Level (see Legend)
T otal
Cost
(Dol l ars)
MT BF
(Hours)
Sl ope
(from Pt. # 1 )
I ntegrated
Circuits
Semi-
conductors Resistors
1 1 1 1 1 1 65 0 1 4 4 0 9 0 .0 5 0 8
2 1 1 3 1 21 4 2 1 4 4 3 4 0 .0 5 0 8
3 1 2 1 1 24 9 2 1 5 1 9 7 0 .9 3 5 8
4 1 2 3 1 29 8 4 1 5 225 0 .61 1 7
5 1 3 1 1 25 5 0 1 5 8 25 0 .3 63 1
6 1 3 3 1 60 4 2 1 5 8 5 5 0 .3 29 3
7 2 1 1 1 1 9 3 4 1 8 21 4 1 3 .4 24 0
8 2 1 3 1 24 25 1 8 25 4 4 .9 60 5
9 2 2 1 1 27 7 6 1 9 4 9 3 4 .5 1 5 5
1 0 2 2 3 1 3 268 1 9 5 3 8 3 .1 7 1 1
1 1 2 3 1 1 5 8 3 4 20 5 8 8 1 .4 65 0
1 2 2 3 3 1 63 25 20 3 8 8 1 .3 21 7
1 3 3 1 1 1 3 225 227 1 1 5 .27 1 5
1 4 3 1 3 1 3 7 1 7 227 7 3 4 .0 4 7 2
1 5 3 2 1 1 4 0 67 24 7 3 4 4 .27 1 1
1 6 3 2 3 1 4 5 5 9 24 8 0 7 3 .5 7 4 4
1 7 3 3 1 1 7 1 25 28 4 4 1 2.1 9 7 6
1 8 3 3 3 1 7 61 7 265 25 2.0 3 0 6
LEGEND
1 - Mil itary
2 - Screened MI L- ST D's
3 - High Rel iabil ity
3 23
CO
ro
28+
= 26
o
X
24-
* 22
S 20
O
P 18+
CD 16
14
II
9 10
15 16
o 0
(3,2,1) (3,2,3)
13 14
1,1,1)^,1,3)
,7 18
e
(3,3,1)
(3
3
,3)
II 12
o 0
(2,3,1) (2,3,3)
3 4
? o
(1,2,1) (1,2,3)
(l,T,l) (1,1,3)
Reliability Requirement
5
s
(1,3,1) (1,3,3)
13 14 15 16
Cost (Thousands of Dollars)
17 18
Fig. 4-90 PREDICTED MTBF VS. COST (Ref. 51)
I n making cost- rel iabil ity tradeoffs, al l possibl e combinations
of screening techniques on al l component part types shoul d be considered.
T here may be parts not yet computed which exceed the requirements at
l ess cost.
T he scatter pl ot is an excel l ent method of visual izing possibl e
combinations of part and screen types. I f the anal ysis indicates that
no combination of screens wil l meet both cost and rel iabil ity criteria,
redesign may be necessary. T he design wil l be iterated and reeval uated
as described in Section 4 .3 .2.
3 25
REFERENCES
PA RT SELECT I O N A ND CO NT RO L
1 . MI L- ST D- 7 4 9 B, Preparation and Submission of Data for A pproval of
Nonstandard Parts, A ugust 1 9 69 .
2. MI L- ST D- 8 9 1 B, Contractor Parts Control and Standardization
Program, A pril 1 9 7 4 .
3 . MI L- ST D- 1 5 62, Lists of Standard Microcircuits, November 1 9 7 4 .
4 . MI L- ST D- 7 0 1 J, Lists of Standard Semiconductor Devices, January 1 9 7 4 .
5 . MI L- ST D- 1 9 9 B, Resistors, Sel ection and Use of, June 1 9 7 4 .
6. MI L- ST D- 1 9 8 C, Capacitors, Sel ection and Use of, December 1 9 7 1 .
7 . MI L- ST D- 20 2E, T est Methods for El ectronic and El ectrical Component
Parts, A pril 1 9 7 3 .
8 . MI L- ST D- 7 5 0 , T est Methods for Semiconductor Devices, February 1 9 7 0 .
9 . MI L- M- 3 8 5 1 0 , Microcircuits, General Specifications for, O ctober
1 9 7 3 .
1 0 . MI L- HDBK- 1 7 5 , Microel ectronic Device Data Handbook, May 1 9 68 .
1 1 . MI L- S- 1 9 5 0 0 E, Semiconductor Devices, General Specifications for,
March 1 9 7 4 .
1 2. MI L- ST D- 1 28 6, T ransformers, I nductors and Coil s, Sel ection and Use
of, June 1 9 7 0 .
1 3 . MI L- ST D- 1 3 4 6, Rel ays, Sel ection and A ppl ication of, June 1 9 69 .
1 4 . MI L- ST D- 1 1 3 2, Switches and A ssociated Hardware, Sel ection and Use
of June 1 9 68 .
1 5 . MI L- ST D- 8 8 3 , T est Methods and Procedures of Microel ectronics,
May 1 9 68 .
1 6. MI L- ST D- 1 3 27 , Fl anges, Coaxial and Waveguide; and Coupl ing
A ssembl ies, Sel ection of, January 1 9 68 .
1 7 . MI L- ST D- 1 3 28 , Coupl ers, Directional (Coaxial Line, Waveguide and
Printed Circuit), Sel ection of, May 1 9 7 4 .
1 8 . MI L- ST D- 1 3 29 , Switches, RF Coaxial , Sel ection of, February 1 9 65 .
1 9 . MI L- ST D- 4 5 4 , Standard General Requirements for El ectronic
Equipment, A ugust 1 9 7 3 .
3 27
20 . MI L- ST D- 20 0 , El ectron T ubes, Sel ection of, November 1 9 68 .
21 . J. Vaccaro, " Semiconductor Rel iabil ity with the U.S. DoD, "
Proceedings of the I EEE, February 1 9 7 4 .
DERA T I NG
22. MI L- ST D- 21 7 B, Rel iabil ity Prediction of El ectronic Equipment,
September 1 9 7 4 .
23 . MI L- M- 1 9 5 0 0 E, Semiconductor Devices, General Specification for,
March 1 9 7 4 .
ENVI RO NMENT A L RESI ST A NCE
24 . MI L- ST D- 21 7 B, Rel iabil ity Prediction of El ectronic Equipment,
September 1 9 7 4 .
25 . MI L- I - 4 60 5 8 C, I nsul ating Compound, El ectrical (for coating printed
circuit assembl ies), February 1 9 7 4 .
26. Rel iabil ity/Design HandbookT hermal A ppl ication, Naval ex Publ ication
No. 0 9 67 - 4 3 7 - 7 0 1 0 , Jul y 1 9 7 3 .
REDUNDA NCY
27 . Kl ass, P.J., " Mul tipl ex System to be T ested on B- l , " A viation Week
and Space T echnol ogy, March 5 , 1 9 7 3 , p. 3 8 .
28 . Mil l er, B., " A WG- 9 Provides Mul titarget Capabil ity, " A viation Week
and Space T echnol ogy, March 1 2, 1 9 7 3 , p. 4 0 .
29 . Fasano, R.M., Lemack, A .G., " A Quad Configuration- - Rel iabil ity and
Design A spects, " Proceedings of the 8 th National Symposium on
Rel iabil ity and Qual ity Control , Washington, D.C., January 1 9 62.
3 0 . Barrett, L.S., " Rel iabil ity Design and A ppl ication Considerations
for Cl assical and Current Redundancy Schemes, " Lockheed Missil es
and Space Company, I nc., Sunnyval e, Cal ifornia, September 3 0 , 1 9 7 3 .
3 1 . A nderson, J.E., Macri, F.J., " Mul tipl e Redundancy A ppl ications in a
Computer, " 1 9 67 A nnual Symposium on Rel iabil ity, Washington, D.C.,
January 1 9 67 .
3 28
DESI GN SI MPLI FI CA T I O N A ND A NA LYSI S
3 2. Chamow, M.F., Smith, W.M., " Some Precepts of Rel iabl e El ectronic
Design, " Proceedings of 1 9 66 Rel iabil ity and Maintainabil ity
Symposium, pp. 269 - 27 5 .
3 3 . MI L- HDBK- 21 7 A , Rel iabil ity Stress and Fail ure Rate Data for El ec-
tronic Equipment, 1 December 1 9 65 , pp. 9 - 1 to 9 - 1 0 .
3 4 . " El ectromagnetic Pul se Handbook for Missil es and A ircraft in Fl ight, "
pp. 3 1 1 - 3 1 6, Sandia Laboratories, A l buquerque, New Mexico, September
1 9 7 2, SC- M- 7 1 - 0 3 4 6.
3 5 . Lennos, C.R., " Experimental Resul ts of T esting Resistors Under Pul se
Conditions, " Sandia Laboratories, A l buquerque, New Mexico, 1 9 67 .
3 6. Case, C. and Mil etta, J., " Capacitor Fail ure Due to High Level
El ectrical T ransients, " Harry Diamond Laboratories, T echnical Note
to be publ ished, circa 1 9 7 4 .
DESI GN T O MI NI MI ZE RELI A BI LI T Y DEGRA DA T I O N DURI NG PRO DUCT I O N A ND USE
3 7 . Standard Workmanship Manual , 0 A M0 0 1 , Singer A erospace and Marine
Systems, June 1 9 7 1 .
3 8 . Standard Printed Wiring Practices, ESP1 8 , T he Singer Company,
Kearfott Division, O ctober 1 9 7 1 .
3 9 . Rel iabil ity and Maintainabil ity Pl anning Guide for A rmy A viation
Systems and Components, U.S. A rmy A viation Systems Command, A VSCO M
Pamphl et No. 7 0 2, Jul y 1 9 7 4 .
4 0 . Engineering Design Handbook, Maintainabil ity Guide for Design,
A rmy Material Command, A D 7 5 4 - 20 2, O ctober 1 9 7 2.
4 1 . Maintainabil ity Principl es and Practices, Bl anchard, B.S.,
Lawery, E.E., McGraw- Hil l Book Company, New York, 1 9 69 .
4 2. I nvestigation of Secondary Effects for the Checkout of Nonel ectronic
Systems, A ir Force A ero Propul sion Laboratories Research and T ech-
nol ogy Division, A FA PL- T R- 65 - 5 7 , A ugust 1 9 65 .
4 3 . Secondary Effect T echnique Study, U.S. A rmy A rmament Command, FCF-
1 3 - 7 4 , June 1 9 7 4 .
3 29
DESI GN T O CO ST
4 4 . Gansl er, J.S. and Sutherl and, G.W. (DoD), " A Design to Cost O verview, "
Defense Management Journal , September 1 9 7 4 .
4 5 . McCol l , D.R.S. (Deputy for A dvance T echnol ogy - SA FRD), Remarks
Before the Windy City O l d Crows A ssociation, Chicago, I l l inois,
September 1 9 , 1 9 7 4 .
4 6. Unit Product Cost System, Honeywel l A erospace Division, St. Peters-
burg, Fl orida, 1 9 7 2.
4 7 . Research Study of Radar Rel iabil ity and I ts I mpact on Life Cycl e
Costs for the A PQ- 1 1 3 , - 1 1 4 , - 1 20 and - 1 4 4 Radar Systems, T echnical
Report under Contract No. F3 3 61 5 - 7 2- C- 1 3 5 4 , General El ectric Company,
Utica, New York, A ugust 1 9 7 2.
4 8 . Deger, E. and Jobe, T ., " For the Real Cost of a Design Factor in
Rel iabil ity, " (RCA Corporation, Consumer El ectronics, I ndianapol is,
I ndiana), El ectronics, A ugust 3 0 , 1 9 7 3 , pp. 8 3 - 8 9 .
4 9 . Starr, M.K., Graduate School of Business, Col umbia University,
Product Design and Decision T heory, Prentice- Hal l , I nc., Engl ewood
Cl iffs, New Jersey, 1 9 63 .
5 0 . Jones, E.R. (Wakefiel d Engineering, I nc.), A Guide to Component
Burn- I n- T echnol ogy, Wakefiel d Engineering, I nc. Report, 1 9 7 2.
5 1 . Benware, L.T . (I BM El ectronics Systems Center, O wego, New York),
" Cost Versus Rel iabil ity T rade- off, " Proceedings of the 1 9 67 A nnual
Symposium on Rel iabil ity, Washington, D.C., January 1 9 67 .
3 3 0
A PPENDI X A
DEFI NI T I O NS, A BBREVI A T I O NS A ND SYMBO LS
DEFI NI T I O NS
A cceptabl e Qual ity Level (A QL)
T he qual ity standard associated with a given producer's risk which
is prescribed by the customer or qual ity engineer for the products
on order. I t is usual l y expressed in terms of percent defective
per hundred units.
A vail abil ity
T he abil ity of an item, under the combined aspects of its rel iabil -
ity and maintenance, to perform its required function at a stated
instant in time.
Burn- I n
T he operation of items prior to their ul timate appl ication intended
to stabil ize their characteristics and to identify earl y fail ures.
Characteristic, O perating
T he curve which describes the probabil ity of acceptance of a l ot
for various val ues of process average.
Defect
A characteristic which does not conform to appl icabl e specification
requirements and which adversel y affects or potential l y affects the
qual ity of a device.
Degradation
A gradual deterioration in performance as a function of time.
Demonstrated
T hat which has been proven by the use of concrete evidence gathered
under specified conditions.
Derating
T he intentional reduction of stress/strength ratio in the appl ica-
tion of an item, usual l y for the purpose of reducing the occurrence
of stress rel ated fail ures.
Downtime
T he period of time during which an item is not in a condition to
perform its intended function.
Effectiveness
T he capabil ity of the system or device to perform its function.
Engineering, Human
T he science of studying the man- machine rel ationships in order to
minimize the effects of human error and fatigue and thereby provide
a more rel iabl e operating system.
3 3 3
DEFI NI T I O NS contd.
Engineering Qual ity
T he science of establ ishing qual ity acceptance and eval uation
criteria such as acceptance sampl ing pl ans, control charts, cl assi-
fication of defects, and tests.
Engineering, Rel iabil ity
T he science of incl uding those factors in the basic design which wil l
assure the required degree of rel iabil ity.
Fail ure
T he termination of the abil ity of an item to perform its required
function.
Fail ure A nal ysis
T he l ogical , systematic examination of an item or its diagrams(s)
to identify and anal yze the probabil ity, causes, and consequences
of potential and real fail ures.
Fail ure, Catastrophic
Fail ures that are both sudden and compl ete.
Fail ure, Random
A ny fail ure whose cause and/or mechanism make its time of occurrence
unpredictabl e, but which is predictabl e onl y in a probabil istic or
statistical sense.
Fail ure, Wearout
A fail ure that occurs as a resul t of deterioration processes or
mechanical wear and whose probabil ity of occurrence increases with
time.
Fail ure Law, Exponential
T he exponential fail ure l aw states that the probabil ity of survival
P
s
of an equipment operating for a time T is a function of the mean
l ife, m, or of fail ure rate x, as expressed by the fol l owing
formul as:
P - e"
T /M
P = e"
xT
Fail ure Rate (x)
T he number of fail ures of an item per unit measure of l ife (cycl es,
time, etc.). During" the useful l ife period, the fail ure rate, X,
is considered constant.
3 3 4
Faul t
A n attribute which adversel y affects the rel iabil ity of a device.
Forced Defect
See T EST - T O - FA I LURE
Freedom, Degrees O f
T he number of observations that are free to vary at random, regard-
l ess of the restrictions imposed by the statistics describing the
distribution.
Hazard Rate (Z(t))
A t a particul ar time, the rate of change of the number of items that
have fail ed divided by the number of items surviving.
I tem
I tem denotes any l evel of hardware assembl y; i.e., system, subsystem,
equipment, components, part, etc.
Human Factors
A body of scientific facts about human characteristics. T he term
covers biomedical and psychosocial considerations in the areas of
human engineering, personnel sel ection, training, l ife support, job
performance aid. and human performance eval uation.
Maintainabil ity
A characteristic of design and instal l ation which is expressed as
the probabil ity that an item wil l be retained in or restored to a
specified condition within a given period of time, when the mainten-
ance is performed in accordance with prescribed procedures and
resources.
Maintenance
A l l actions necessary for retaining an item in or restoring it to a
specified condition.
Maintenance, Corrective
T he actions performed, as a resul t of fail ure, to restore an item
to a specified condition.
Maintenance, Preventive
T he actions performed in an attempt to retain an item in a specified
condition by providing systematic inspection, detection and preven-
tion of incipient fail ure.
3 3 5
Man- Function
T he function al l ocated to the human component of a system.
Mean- Mai ntenance- T ime
T he total preventive and corrective maintenance time divided by the
number of preventive and corrective maintenance actions during a
specified period of time.
Mean- T ime- Between- Fai1 ures (MT BF)
For a particul ar interval , the total functioning l ife of a popul ation
of an item divided by the total number of fail ures within the popu-
l ation during the measurement invol ved.
Mean- T ime- Between- Maintenance (MT BM)
T he mean of the distribution of the time interval s between mainten-
ance actions (either preventive, corrective, or both).
Mean- T ime- T o- Repair
T he total corrective maintenance time divided by the total number
of corrective maintenance actions during a given period of time.
Qual ity
A measure of the degree to which a device conforms to appl icabl e
specification and workmanship standards.
Qual ity, A verage O utgoing
T he ul timate average qual ity of products shipped to the customer
which are the resul t of the composite techniques of sampl ing and
screening.
Randomness
T he occurrence of an event in accordance with the l aws of chance.
Redundancy
I n an item, the existence of more than one means of performing its
function.
Redundancy, A ctive
T hat redundancy wherein al l redundant items are operating simul tane-
ousl y rather than being switched on when needed.
3 3 6
Redundancy, Standby
T hat redundancy wherein the al ternative means of performing the
function is inoperative until needed, and is switched on upon
fail ure of the primary means of performing the function.
Rel iabil ity
T he characteristic of an item expressed by the probabil ity that it
wil l peform a required function under stated condition for a stated
period of time.
Growth T esting
T he improvement process during which hardware rel iabil ity increases
to an acceptabl e l evel .
Rel iabil ity, I nherent
T he potential rel iabil ity of an item present in its design.
Rel iabil ity, I ntrinsic
T he probabil ity that a device wil l perform its specified function,
determined on the basis of a statistical anal ysis of the fail ure
rates and other characteristics of the parts and components which
comprise the device.
Repair
See MA I NT ENA NCE, CO RRECT I VE
Repl aceabil ity
A measure of the degree to which repl acement of an item wil l be
accompl ished within a given time under specified conditions.
Risk
T he probabil ity of rendering the wrong decision based on pessimistic
data or anal ysis.
Safety
T he conservation of human l ife and its effectiveness, and the pre-
vention of damage to items, consistent with mission requirements.
Screening
T he process of performing 1 0 0 percent inspection on product l ots
and removing the defective units from the l ots.
Screening T est
A test or combination of tests, intended to remove unsatisfactory
items or those l ikel y to exhibit earl y fail ures.
3 3 7
Step Stress T est
A test consisting of several stress l evel s appl ied sequential l y for
periods of equal duration to a sampl e. During each period, a stated
stress l evel is appl ied and the stress l evel is increased from one
step to the next.
Storage Life (Shel f Life)
T he l ength of time an item can be stored under specified conditions
and stil l meet specified requirements.
Stress, Component
T he stresses on component parts during testing or usage which affect
the fail ure rate and hence, the rel iabil ity of the parts. Vol tage,
power, temperature, and thermal environmental stress are incl uded.
Survivabil ity
T he measure of the degree to which an item wil l withstand hostil e
man- made environment and not suffer abortive impairment of its
abil ity to accompl ish its designated mission.
System Effectiveness
A measure of the degree to which an item can be expected to achieve
a set of specific mission requirements, and which may be expressed
as a function of avail abil ity, dependabil ity and capabil ity.
T est- T o- Fail ure
T he practice of inducing increased el ectrical and mechanical stresses
in order to determine the maximum capabil ity of a device so that con-
servative usage in subsequent appl ications wil l thereby increase its
l ife through the derating determined by these tests.
T ime, Mission
T hat el ement of Uptime during which the item is performing its
designated mission.
T ime, Up (Uptime)
T hat el ement of active time during which an item is either al ert,
reacting or performing a mission.
T ime, Down (Downtime)
T hat el ement of time during which the item is not in condition to
perform its intended function.
Uptime Ratio
T he quotient of uptime divided by Uptime pl us Downtime.
3 3 8
Wearout
T he process of attrition which resul ts in an crease of hazard rate
with increasing age (cycl es, time, mil es, events, etc., as appl ic-
abl e for the item).
3 3 9
A BBREVI A T I O NS A ND SYMBO LS
A C A cquisition Cost
A FCM A ir Force Logistics Command Manual
A FSCM A ir Force Systems Command Manual
A GE A erospace Ground Equipment
A QL A cceptabl e Qual ity Level
A WA CS A irborne Warning and Control System
BI T Buil t- in- T est
BI T E Buil t- in- T est Equipment
CMO S Compl imentary Metal O xide Semiconductor
CO O Cost of O wnership
DT UPC Design to Unit Production Cost
EA R El ectronical l y A gil e Radar
ECA P El ectronic Circuit A nal ysis Program
EO M Ease of Maintenance
FMEA Fail ure Mode and Effects A nal ysis
FT A Faul t T ree A nal ysis
G & A General and A dministrative
LCC Life Cycl e Cost
LRU Line Repl aceabl e Unit
LSI Large Scal e I ntegration
LSC Logistic Support Cost
MI S Management I nformation System
MO S Metal O xide Semiconductor
MRB Material Review Board
MT BF Mean- T ime- Between- Fail ures
3 4 1
A BBREVI A T I O NS A ND SYMBO LS contd.
MT BMA Mean- T ime- Between- Maintenance A ctions
MT T F Mean- T ime- T o- Fai1 ure
MT T R Mean- T ime- T o- Repair
O RLA O ptimum Repair Level A nal ysis
PPL Preferred Parts List
PPM Parts Per Mil l ion
QC Qual ity Control
RA C Rel iabil ity A nal ysis Center
RA DC Rome A ir Devel opment Center
RFP Request for Proposal
RO M Read O nl y Memory
RPM Rel iabil ity Pl anning and Management
SRU Smal l Repl aceabl e Unit
T
B
Burn- I n- T ime
T T L T ransistor- T ransistor Logic
T
W
Wearout T ime
T WT T ravel ing Wave T ube
UPC Unit Production Cost
WBS Work Breakdown Strucutre
z(t) Hazard Rate
A Fail ure Rate
3 4 2
A PPENDI X B
BI BLI O GRA PHY (A NNO T A T ED)
Reference Documents: T he fol l owing documents provide additional or
supporting information. A synopsis of each document is presented as
it appears in the text. (NO T E: T he l atest issue of a document shoul d
be used when seeking reference information.)
T he objective of this book is to devel op rel iabil ity concepts and
methods in a l ogical way, from simpl e components to compl ex systems,
to give the reader a thorough understanding of the subject, and to
show him how to sol ve rel iabil ity probl ems by anal ysis, design, and
testing. T here is an abundance of useful rel iabil ity formul as in
the book which wil l hel p the reader predict system rel iabil ity,
establ ish rel iabil ity goal s, and determine the procedures necessary
to acnieve them. A l so incl uded is a quantitative treatment of sys-
tem maintainabil ity, avail abil ity, and safety and outl ined methods
which have to be fol l owed.
2. Mil itary Standardization Handbook 21 7 B, Rel iabil ity Prediction of
El ectronic Equipment, Sept. 1 9 7 4 .
T his document, which is a revision of MI L- HDBK- 21 7 , provides two
methods of rel iabil ity prediction: a) Parts Stress A nal ysis, and
b) Parts Count. T he part fail ure rate model s have been brought up
to date and model s added for newer parts. Mathematical expressions
for part fail ure rates are provided for use in computer programming.
T abl es, rather than curves, are used for base fail ure rates to im-
prove ease of manual appl ication of the prediction methods. T hese
prediction methods wil l be continual l y updated as new information
becomes avail abl e. T his Handbook incl udes information rel ating to
Part Stress A nal ysis Prediction in the areas of: a) Microel ectronic
Devices, b) Discrete Semiconductors, c) T ubes, El ectronic Vacuum,
d) Lasers, e) Resistors, f) I nductive Devices, h) Rotating Devices,
i) Rel ays, j) Switches, k) Connectors, 1 ) Wire and Printed Wiring
Boards, and m) Miscel l aneous Parts. A l so covered is Parts Count
Rel iabil ity Prediction. A ppendices deal ing with System Rel iabil ity
Model ing and A pproximation for Rel iabil ity Cal cul ation, and a com-
prehensive bibl iography are al so incl uded.
T his Handbook is oriented toward rel iabil ity prediction of mil itary
el ectronic equipment; it provides a common basis for predicting
and comparing predictions on mil itary contracts and proposal s. I t
is not a compl ete guide to rel iabil ity engineering.
3 . Myers, R., Wong, K., and Gordy, H., Rel iabil ity Engineering for
for El ectronic Systems, John Wil ey and Sons, New York, 1 9 64 .
T his book represents an introductory treatment of rel iabil ity engi-
neering as appl ied to el ectronic systems. Suitabl e for use as a
text book for students or research workers, the subject matter covers
fundamental concepts drawn from probabil ity and statistics and appl ies
them to rel iabil ity engineering. Simpl e probl ems and references are
provided at the end of each chapter.
3 4 5
4 . Vaccaro, J., and Gorton, H. (RA DC and Battel l e Memorial I nstitute),
Rel iabil ity Physics Notebook, RA DC- T R- 65 - 3 3 0 , A D 624 - 7 69 , O ctober, 1 9 65 .
T he purpose of this Notebook is to make avail abl e to the el ectronics
rel iabil ity engineer current state- of- the- art information rel ating to
what may be termed the rel iabil ity physics of sol id state el ectronic
parts. I t expl ains techniques and procedures for obtaining pertinent
data on specific part types and methods of util izing the data in
accel erated testing, screening, and rel iabil ity prediction programs.
Consideration is l argel y l imited to degradation and fail ure mechanisms
which remain after gross mechanical and qual ity defects have been
screened out. A brief section on sil icon integrated circuits is
incl uded.
5 . Mil itary Standard 7 8 5 A , Rel iabil ity Program for Systems and Equipment
Devel opment and Production, March, 1 9 69 .
Establ ishes uniform criteria for rel iabil ity programs and provides
guidel ines for the preparation of rel iabil ity program pl ans. Lists
detail ed requirements as Program El ements incl uding: (a) Rel iabil ity
Management (Rel iabil ity O rganization, Management and Control , Sub-
contractor and Suppl ier Rel iabil ity Program, Program Review,
(b) Rel iabil ity Design and Eval uation (Design T echniques Rel iabil ity
(haiiure uata LuiieuLiuri nridiybib emu uur restive HULIUN, ranure
Summaries), (e) Production Rel iabil ity (T ransition from Devel opment,
Reprocurement), (f) Status Reports.
6. A nderson, R., Kos, D., and Schil l er, J. , (I I T RI ) Rel iabil ity and
Maintainabil ity Pl anning Guide for A rmy A viation Systems and
Components, R & M Division, Directorate for Product A ssurance,
U.S. A rmy A viation Systems Command, St. Louis, Missouri, Jul y 1 9 7 4 .
T his guidebook serves as a management tool to use in pl anning,
managing and monitoring R&M programs for aviation systems. I t
provides specific guidel ines for structuring work efforts, al l ocating
resources and eval uating al l l ife cycl e R&M activities.
7 . Study of Rel iabil ity Prediction T echniques for Conceptual Phases of
" Devel opment, Final Report, Rome A ir Devel opment Center, RA DC- T R- 7 4 -
23 b, O ctober 1 9 7 4 .
T his report presents the resul ts of a study to devel op a rel iabil ity
prediction technique to estimate system compl exity for appl ication
during the earl y conceptual phases of system devel opment. T he pre-
diction technique is based on system performance data derived from
design specifications, detail ed parts summaries, and detail ed hand-
book predictions using MI L- HDBK- 21 7 A on existing systems.
3 4 6
8 . Sel b;/, J. and Mil l er, S., (General El ectric), " Rel iabil ity
Pl anning and Management - RPM" , Symposium for Rel iabil ity and
Maintainabil ity T echnol ogy for Mechanical Systems, Washington,
A O A , A pril , 1 9 7 2.
T his paper presents a new approach to the rel iabil ity pl anning and
management of compl ex weapon systems. RPM is essential l y a manage-
ment tool for briding the gap between stated rel iabil ity require-
ments and impl ementation pl anning. T he RPM methodol ogy, equal l y
usabl e by buyer and contractor, is appl icabl e to establ ishing pl ans
projecting effort, eval uating proposal s and monitoring contract
performance.
Costs for the A PQ- 1 1 3 , - 1 1 4 , - 1 20 , and - 1 4 4 Radar Systems, General
El ectric Company, A erospace El ectronic Systems Department, Utica,
New York, A ugust, 1 9 7 2.
T he purpose of this study was to provide insight into Rel iabil ity
Worth through quantifying the rel ative val ues of rel iabil ity
activities and their impact on l ife- cycl e- costs. T he study is based
on data obtained and anal yzed for the A PQ- 1 20 and the A PQ- 1 1 3 , - 1 1 4 ,
and - 1 4 4 Radar Systems. I n- service rel iabil ity performance data
was gathered and anal yzed for both radar famil ies, the objective
being to correl ate differences in performance with the equipment
rel iabil ity requirements and programs structured. T he rel iabil ity
discipl ines and methodol ogies appl ied to these radar programs were
anal yzed with emphasis pl aced on providing measurabl e quantified
anal ysis and concl usions. Recommendations are provided, based on
concl usions derived from study findings, rel ative to rel iabil ity
contracting practices, prerel ease discipl ines and testing programs.
1 0 . Rel iabil ity and Maintainabil ity Management Guide, A ir Force Systems
Command, A FSCP 8 0 0 Series, 1 9 7 4 .
T his pamphl et expl ains how to insure appropriate l evel s of rel iabil -
ity and maintainabil ity (R&M) over the l ife cycl e of systems and
equipments through effective management actions by staff, program
office and contractor personnel .
1 1 . Mil itary- Standard- 7 8 1 B, Rel iabil ity T ests: Exponential Distribution,
1 9 67 .
O utl ines test l evel s and test pl ans for rel iabil ity qual ification
(demonstration), rel iabil ity production acceptance (sampl ing) tests,
and for l ongevity tests. (T he test pl ans are based upon the expon-
ential , or Poisson distribution, and are intended for the testing
of equipment.) Provides uniformity in R testing by: (a) Facil itating
the preparation of Mil itary Specs and Standards through the estab-
l ishment of standard test l evel s and test pl ans; (b) restricting
the variety of rel iabil ity tests so that those conducting tests can
establ ish facil ities; (c) Facil itating the determination of more
real istic correl ation factors between test and operational rel i-
abil ity; and (d) facil itating the direct comparison of MT BF test
resul ts through the establ ishment of uniform test l evel s and pl ans.
I ncl udes graphic exampl es and exampl es of records and reports.
3 4 7
1 2. Kil patrick, P.S., Mitchel l , P.D., Scal es. E.A ., A ircraft A vionics
T rade- off Study, Vol . I I , Final Report, A D 9 1 5 - 8 8 1 L, September, 1 9 7 3 .
T he objective of this study was to define and eval uate modul ar
avionics concepts and to provide data for an orderl y time- phased
transition to these concepts. T his document presents the resul ts
from the avionics requirements definition task. T he general objec-
tives of this task were to define future avionics requirements and
trends across a spectrum of A ir Force operations so that the subse-
quent tradeoffs woul d have a meaningful basis.
1 3 . Mil l er, B., " A WG- 9 Provides Mul ti- T arget Capabil ity" , A viation Week
and Space T echnol ogy, March 1 2, 1 9 7 3 .
Presents capabil ities of the A WG- 9 weapon control system and how it
wil l aid the Navy in maintaining the rigid quantitative rel iabil ity
requirements on the Navy's Grumman F- 1 4 fighter.
1 4 . Ul samer, E., " How Computers Wil l Fl y T ommorrow's A irpl anes, "
A ir Force Magazine, Jul y, 1 9 7 2.
T his articl e discusses the A ir Force's concept of the " digital air-
pl ane, " and presents the advantages of such a system.
1 5 . Kl ass, P.J., " USA F Weighing Standardized Modul es, " A viation Week
and Space T echnol ogy, September 1 6, 1 9 7 4 .
Discusses the success of the Navy's attempt at circuit- modul e stand-
ardization through their Standard Hardware Program (SHP), and how it
might affect the USA F to consider a simil ar program for future air-
borne avionics.
1 6. MI L- ST D- 7 4 9 B, Preparation and Submission of Data for A pproval of Non-
standa rd Parts, A ugust, 1 9 69 .
T his standard establ ishes uniform procedures for the preparation and
submission of data for approval of nonstandard parts prior to use in
mil itary equipment.
1 7 . MI L- ST D- 8 9 1 B, Contractor Parts Control and Standardization Program,
A pril , 1 9 7 4 .
T his standard establ ishes the criteria and guidel ines for the prepar-
ation and impl ementation of a pl anned contractor parts control and
standardization program. I ncl udes (a) Reference Documents;
(b) Definitions; (c) General Requirements; (d) Detail Requirements;
(e) Equipment Performance; (f) Data and graphics designating parts
sel ected for proposed and additional program preferred parts l ists.
1 8 . MI L- ST D- 1 5 62, Lists of Standard Microcircuits, November, 1 9 7 4 .
T he purpose of this standard is to provide equipment designers and
manufacturers with l ists of microcircuits considered to be most
acceptabl e for mil itary appl ications and to control and minimize
the variety of microcircuits used by mil itary activities in order
to facil itate effective l ogistic support of equipment in the fiel d;
to maximize economic support of and to concentrate improvement on,
production of the microcircuits l isted in this standard.
3 4 8
1 9 . MI L- ST D- 7 0 1 J, Lists of Standard Semiconductor Devices,
January, 1 9 7 4 .
T his standard provides device characteristics, ratings and other
parameters of standard semiconductors. I t is intended to guide
designers in the sel ection process for noncritical appl ications
where an establ ished device can be used.
20 . MI L- ST D- 1 9 9 B, Resistors, Sel ection and Use O f, June, 1 9 7 4 .
T he purpose of this standard is to provide the equipment designer
with a sel ection of standard resistors for use in most mil itary
appl ications; to control and minimize the variety of resistors
used in mil itary equipment in order to facil itate l ogistic support
of the equipment in the fiel d; and to outl ine criteria pertaining
to the use, choice, and appl ication of resistors in mil itary
equipment.
21 . MI L- ST D- 1 9 8 C, Capacitors, Sel ection and Use of, December, 1 9 7 1 .
T his standard provides the equipment designer with a sel ection
of standard capacitors for use in most mil itary appl ications;
control s and minimizes the variety of capacitors used in mil itary
equipment in order to facil itate l ogistic support of the equip-
ment in the fiel d; and outl ines criteria pertaining to the use,
choice, and appl ication of capacitors in mil itary equipment.
22. MI L- ST D- 20 2E, T est Methods for El ectronic and El ectrical Component
Parts, A pril , 1 9 7 3 .
T his standard establ ishes uniform methods for testing el ectronic
and el ectrical component parts, incl uding basic environmental tests
to determine resistance to del eterious effects of natural el ements
and conditions surrounding mil itary operations, and physical and
el ectrical tests. T his standard is intended to appl y onl y to smal l
parts, such as transformers and inductors, weighing up to 3 0 0 pounds
or naving a root- mean- square test vol tage up to 5 0 , 0 0 0 vol ts unl ess
otherwise specifical l y invoked.
23 . MI L- ST D- 7 5 0 , T est Methods for Semiconductor Devices, February, 1 9 7 0
T his standard is intended to appl y onl y to semiconductor devices
(i.e., transistors, Diodes, vol tage regul ators, rectifiers and
tunnel 1 diodes). T he test methods described have been prepared
to serve several purposes incl uding control of l aboratory conditions,
control uniform methods and format of resul ts.
24 . MI L- M- 3 8 5 1 0 , Microcircuits, General Specification For, O ctober, 1 9 7 3 .
T his specification and its suppl ementary sl ash sheets provide data
and sel ection guidel ines for microcircuits. I t is intended to aid
designers in sel ection and appl ication of standard monol ithic I C
types.
3 4 9
25 . MI L- HDBK- 1 7 5 , Microel ectronic Device Data Handbook, May 1 9 68
T his handbook is intended as a quick- reference document for use by
design engineers, technicians, parts special ists, and by contractors.
T he text is addressed to readers with l ittl e or no experience in
microel ectronics. I t is intended to provide general guidance for
empl oying the technol ogy. Sol utions to the specific probl ems of
equipment design must be considered in the context of cost, schedul e,
environments, and the other constraints of a particul ar appl ication
and are therefore beyond the scope of this handbook. T he handbook
does provide general information that wil l be of substantial assis-
tance in the sol ution of specific probl ems.
26. MI L- S- 1 9 5 0 0 E, Semiconductor Devices, General Specification For,
March, 1 9 7 4 .
T his specification covers the general requirements for semiconductor
devices used in mil itary equipment. Specific requirements for a
particul ar type of semiconductor device are l isted in the appl icabl e
detail specification, which is incl uded within the specification
as sl ash sheets.
27 . MI L- ST D- 1 28 6, T ransformers, I nductors and Coil s, Sel ection and Use
O f, June, 1 9 7 0 .
T his standard provides guidel ines for sel ection and appl ication of
inductive devices. Data and information covering cl asses of insu-
l ators, power ratings, etc. is provided to aid designers in sel ecting
suitabl e devices.
28 . MI L- ST D- 1 3 4 6, Rel ays, Sel ection and A ppl ication O f, June, 1 9 69 .
T his standard provides guidel ines for the sel ection and appl ication
of rel ays. I ncl uded is information on types, styl es, contact ratings
and other data for rel iabl e rel ay appl ication.
29 . MI L- ST D- 1 1 3 2, Switches and A ssociated Hardware, Sel ection and Use
O f, June, 1 9 68 .
Simil ar to MI L- ST D- 1 3 4 6, this standard provides data and information
rel ative to switches. A ppl ication guidel ines, data and notes are
provided to aid designers in proper sel ection.
3 0 . MI L- ST D- 8 8 3 , T est Methods and Procedures for Microel ectronics,
May, 1 9 68 .
T he purpose of this standard is to establ ish uniform methods and
procedures for testing microel ectronic devices, incl uding basic
environmental tests to determine resistance to del eterious effects
of natural el ements and conditions surrounding mil itary and space
operations, and physical and el ectrical tests. For the purpose
of this standard, the term " devices" incl udes such items as mono-
l ithic, mul ti- chips, " fil m, and hybrid microcircuits, microcircuit
arrays, and the el ements from which the circuits and arrays are
formed. T his standard is intended to appl y onl y to microel ectronic
devices.
3 5 0
T his document incl udes a) referenced documents, b) abbreviations,
symbol s and definitions, c) general requirements, d) detail
requirements, and test methods rel ating to: Environmental T ests,
Mechanical T ests, El ectrical T ests (digital ), El ectrical T ests
(l inear), and T est Procedures.
3 1 . MI L- 1 - 4 60 5 8 , I nsul ating Compound, El ectrical (for coating printed
circuit assembl ies), February 1 9 7 4 .
T his specification l ists the properties, characteristics and
qual ities of insul ating compounds and material s used to seal
printed circuit boards from moisture entrapment, corrosion or
other harmful environmental effects.
3 2. Kl ass, P.J., " Mul tipl ex Systems to be T ested on B- l , " A viation
Week and Space T echnol ogy, March 5 , 1 9 7 3 , p. 3 8 .
Presents the El ectrical (function) Mul tipl exing System (E Mux),
which performs el ectrical functions of the on/off switching type.
3 3 . Fasano, R.M., Lemack, A .G., " A Quad ConfigurationRel iabil ity and
Design A spects, " Proceedings of the 8 th National Symposium on
Rel iabil ity and Qual ity Control , January 1 9 62.
Primaril y discusses the rel iabil ity design aspects and l imitations
of el ectronic circuits in which a particul ar type of component
redundancy cal l ed QUA Ding is used. Proposes that a nonredundant
and a QUA D redundant circuit are anal yzed to establ ish the mag-
nitude of the increased rel iabil ity, effects on l oading, power,
terminal suppl ies, transient aspects, etc.
3 4 . Barrett, L.S., Rel iabil ity Design and A ppl ication Considerations
for Cl assical and Current Redundancy Schemes, Lockheed Missil es
and Space Company, I nc., Sunnyval e, Cal ifornia, September 3 0 ,
1 9 7 3 .
T his report presents a summarization of the rel iabil ity, appl ica-
tion, and design aspects of both cl assical and state- of- the- art
redundancy methodol ogy and, in addition, some of the more attrac-
tive redundancy techniques currentl y being investigated or
devel oped.
3 5 . A nderson, J.E. and Macri, F.J., " Mul tipl e Redundancy, A ppl ications
in a Computer, "
T his paper presents a computer design in which the sel ected form
of redundancy was a resul t of various tradeoff studies performed
to yiel d the optimum overal l design. T he units are the Launch
Vehicl e Digital Computer and Data A dapter (LVDC/LVDA ).
3 6. Chamow, M.F. and Smith, W.M., " Some Precepts of Rel iabl e El ectronic
Design, " Proceedings of 1 9 66 Rel iabil ity and Maintainabil ity
Symposiurn, pp. 269 - 27 5 .
Presents precepts for rel iabl e design. T he guidel ines given are
practical and are derived from actual experience.
3 5 1
3 7 . MI L- HDBK- 21 7 A Rel iabil ity Stress and Fail ure Rate Data for
El ectronic Equipment, December 1 , 1 9 65 , pp. 9 - 1 to 9 - 1 0 .
T his handbook provides essential fail ure rate data for el ectronic
parts and indicates how MI L- ST D- 7 5 6 may be impl emented using this
data. T he handbook was designed to improve prediction accuracy
A ppl ication K factors are incl uded to account for the severity of
the use environment.,
3 8 . El ectromagnetic Pul se Handbook for Missil es and A ircraft in Fl ight,
SC- M- 7 1 - 0 3 4 6, Sanaia Laboratories, A l buquerque, September, 1 9 7 2,
pp. 3 1 1 - 3 1 6
T he objective of this handbook is to provide for anal ysis by break-
ing down the EMP response of an infl ight missil e or aircraft, and
al so to provide avail abl e quantitative data (both experimental l y
and theoretical l y derived) on each of the constituent parts of the
response.
3 9 . C.R. Lennox, Experimental Resul ts of T esting Resistors Under Pul se
Conditions, Sandia Laboratories, A l buquerque, 1 9 67
0
Presents resul ts of tests performed on three types of resistors;
those being wirewound, metal fil m and carbon composition; al so
describes testing equipment.
4 0 . C. Case and J. Mil etta, Capacitor Fail ure Due to High Level
El ectrical T ransients, Harry Diamond Laboratories, T echnical
Note circa 1 9 7 4
0
T his report preserts the resul ts of tests conducted on sol id tanta-
l um capacitors of l ow dc vol tage rating which have demonstrated
fail ure energy l evel s for those type of capacitors comparabl e to
the fail ure l evel s of l ow power discrete semiconductor devices and
smal l - scal e integrated circuits, and describes the fail ure character-
istics of the sol id tantal um devices and other typical capacitor
types T hese capacitor fail ure l evel s are compared to typical
fail ure l evel s of semiconductor devices.
4 1 . Standard Workmanship Manual , 0 A M0 0 1 , Singer A erospace & Marine
Systems, June 1 9 7 1
0
T his manual serves as a compil ation of acceptabl e Workmanship
methods, procedures, practices and aids for use in the manufacture
of el ectronic products
4 2. Standard Printed Wiring Practices, ESP1 8 , T he Singer Company
Kearfoot Division, O ctober, 1 9 7 1
T he purpose of this document is to insure that al l printed wiring
designs represent the highest qual ity consistent with current
economical l y sound manufacturing procedures
3 5 2
4 3 Engineering Design Handbook, Maintainabil ity Guide for Design,
A rmy Materiel Command, O ctober, 1 9 7 2 A D7 5 4 - 20 2.
T he objective of this hardbook is to infl uence design so that
equipment can be (1 ) serviced efficientl y and effectivel y if
servicing is required, and repaired efficientl y and effectivel y
if it shoul d fail , (2) operabl e for the period of intended l ife
without fail ing and without servicing, if possibl e T his hand-
book embraces information on the extent and nature of the
Maintainance Probl ems as it exists today and the principl es and
techniques that, if incl uded in future design, wil l reduce this
probl em
0
4 4 o Maintainabil ity Principl es and Practices, B
0
Sc Bl anchard and
E E. Lowery, McGraw- Hil l Book Company, New York, 1 9 69 .
T his bcok is an introduction to maintainabil ity engineering
I ts focus throughout is on the principl es and practices of
organization, pl anning, actuation, and control of a company
maintainabil ity program. T his book is primaril y designed for
use in courses at either the undergraduate or graduate l evel .
4 5 . I nvestigation of Secondary Effects for the Checkout of
Nonel ectronic Systems, A ir Force A ero Propul sion Laboratories
Research and T echnol ogy Division, A FA PL- T R- 65 - 5 7 , A ugust, 1 9 65 .
T he main objectives of this investigation was to demonstrate
the feasibil ity of sensing secondary phenomena of nonel ectronic
system operation and to obtain information concerning the status
of the system or its components T he primary emphasis has been
on secondary effects not requiring the physical dismantl ing of
the system under test and not currentl y empl oyed in existing
checkout operations, ,
4 6. Secondary Effect T echnique Study, U.So A rmy A rmament Command,
FCM3 - 7 4 , June, 1 5 7 4 .
T he object of this program was to identify and devel op secondary
effect detection techrique concepts for use with the MA I D- T ECH
Progranio T he purpose of these techniques is to simpl ify checkout
procedures and to provide information that cannot be easil y obtained
through primary measurements.,
4 7 o Gansl er, J
C
S
U
and Sutherl and, G.W. (DoD), A Design to Cost O verview
Defense Management Journal , September, 1 9 7 4
T his articl e presents a phil osophy of design- to- cost, appl icabl e
to the DoD. T he need for principl es, commercial practice, l ife
cycl e cost considerations, characteristic features, appl ication,
and the rel ationship to DoD decision process are covered, as wel l
as the chal l enge to DoD and the defense industry. A l so presented
is a hypothetical design to cost program.,
3 5 3
4 8 . McCol l , DnR.S. (Deputy for A dvanced T echnol ogy- SA FRD),
Remarks Be- fcre the Windy City O l d Crows A ssn., Chicago, I l l inois,
September 1 9 , 1 9 7 4 .
T his paper presents the matter of increasing compl exity of weapons
and their higher costs, and the effect this has on purchasing
equipment. Pointed out is the design to cost approaches taken by
the A ir Force to al l eviate this major probl em.
4 9 . Unit Product Cost System, Honeywel l A erospace Division,
St. Petersburg, Fl orida,
T his pamphl et provides informative data rel ated to a Unit Product
Cost System T he design is broken down into four phases, those
being: Phase I - Prel iminery Design, Phase I I - Design, Phase I l l -
Pil ot Production, and Phase I V- Production. T he data is presented
in the form of diagrams, fl ow charts and work sheets.
5 0 . Deger, E. and Jobe, T ., (RCA Corporation, Consumer El ectronics,
I ndianapol is, I N.), T or the Real Cost of a Design, Factor in
Rel iabil ity" , El ectronics, A ugust 3 0 , 1 9 7 3 .
Presents a method of figuring total rel iabil ity costs into design
tredeoffSo I ncl udes information on the economics of rel iabil ity,
rel iabil ity data sources, a guide to transistor rel iabil ity, adding
components for l ower total cost, guidel ines in actual practice,
rel iabil ity compared to modul ar design, and presentl y used rel i-
abil ity data.
5 1 . Starr, M
0
K. (Graduate School of Business, Col umbia University),
Product Design and Decision T heory, Prentice- Hal l , I nc.,
Engl ewood Cl iffs, N.J., 1 9 63 .
T his booK attempts to expl ain the nature of decision theory and how
it can be util ized to improve design decisions. Many different kinds
cf design situations are presented, but the surface of possibil ities
has onl y been scratched. Extensive detail has been avoided in pre-
senting the exampl es for l ack of space T his book has been pl anned
so that, al l members of the design team as wel l as students of
engineering, production, marketing, and management can obtain a
different pcint of view about the product design probl em.
5 2o Jones, E
0
R
0
(Wakefiel d Eng
u
I nc.), A Guide to Compcnent Burn- in
T echnol ogy, Wakefiel d Engineering, I nc
u
, 1 9 7 2.
T he purpose of this bookl et is to hel p expl ain why and how reduction
in fail ures is accompl ished and how this accompl ishment rel ates to
test time, costs and certain procedural considerations.
5 3 . " Cost Versus Rel iabil ity T rade- O ff" , Proceedings of the 1 9 67 A nnual
Symposium on Rel iabil ity, Washington, D.C., January 1 9 67 .
Presents a technique for achieving a higher required rel iabil ity at
minimum possibl e cost.
3 5 4
A PPENDI X C
CO MPA RA T I VE FA I LURE RA T ES
FO R MO NO LI T HI C MI CRO CI RCUI T S
(Standard T ypes from MI L- ST D- 1 5 62)
Each device type is defined in the
appropriate sl ash sheets
of MI L- M- 3 8 5 1 0 )
T T L and NA ND Gates, I nverters and Buffers
GO
en
Commercial or
Generic Number
Specification
MI L- M- 3 8 5 1 0 /
Device
T ype Circuit Description
F/1 0
b
hrs
5 4 0 0 1 0 4 Quad, 2- input NA ND gate 0 .0 60 *
5 4 H0 0 23 0 4 Quad, 2- input (high speed) NA ND gate 0 .0 64
5 4 L0 0 20 0 4 Quad, 2- input (l ow power) NA ND gate 0 .0 68
5 4 S0 0 7 0 0 1 Quad, 2- input (Schottky) NA ND gate 0 .0 64
5 4 0 1 1 0 7 Quad, 2- input NA ND gate (open col l ector output) 0 .0 5 6
5 4 L0 1 20 0 6 Quad, 2- input NA ND gate (open col l ector output)(l ow power) 0 .0 5 2
5 4 H0 1 23 0 6 Quad, 2- input NA ND gate (open col l ector output)(high speed) 0 .0 5 2
5 4 0 3 1 0 9 Quad, 2- input, open col l ector NA ND gate 0 .0 5 6
5 4 L0 3 20 0 6 Quad, 2- input, open col l ector (l ow power) NA ND gate 0 .0 5 2
5 4 S0 3 7 0 0 2 Quad, 2- input, open col l ector (Schottky) NA ND gate 0 .0 5 6
5 4 0 4 1 0 5 Hex inverter 0 .0 7 2
5 4 H0 4 23 0 5 Hex inverter (high speed) 0 .0 7 6
5 4 L0 4 20 0 5 Hex inverter (l ow power) 0 .0 7 2
5 4 S0 4 7 0 0 3 Hex inverter (Schottky) 0 .0 7 6
5 4 0 5 1 0 8 Hex inverter, open col l ector 0 .0 64
5 4 S0 5 7 0 0 4 Hex inverter, open col l ector (Schottky) 0 .0 64
5 4 0 6 8 0 1 I nverter/buffer driver, 3 0 - vol t output 0 .0 7 2
5 4 0 7 8 0 3 Buffer driver, 3 0 - vol t output 0 .0 64
5 4 0 8 1 6 0 1 Quad, 2- input A ND gate 0 .0 64
5 4 0 9 1 6 0 2 Quad, 2- input, open col l ector A ND gate 0 .0 60
A ssumption, stress
of this appendix.
l evel s and other ground rul es used to cal cul ate the fail ure rates are given at the end
T T L and NA ND Gates, I nverters and Buffers (Cont'd)
00
Commercial or
Generic Number
Specification
MI L- M- 3 8 5 1 0 /
Device
F/1 0
6
hrs
5 4 1 0 1 0 3 T ripl e, 3 - input NA ND gate 0 .0 5 6
5 4 H1 0 23 0 3 T ripl e, 3 - input (high speed) NA ND gate 0 .0 60
5 4 L1 0 20 0 3 T ripl e, 3 - input (l ow power) NA ND gate 0 .0 5 6
5 4 S1 0 7 0 0 5 T ripl e, 3 - input (Schottky) NA ND gate 0 .0 60
5 4 1 2 1 0 6 T ripl e, 3 - input, open col l ector NA ND gate 0 .0 5 2
5 4 20 1 0 2 Dual , 4 - input NA ND gate 0 .0 5 2
5 4 H20 23 0 2 Dual , 4 - input (high speed) NA ND gate 0 .0 5 2
5 4 L20 20 0 2 Dual , 4 - input (l ow power) NA ND gate 0 .0 5 2
5 4 S20 7 0 0 6 Dual , 4 - input (Schottky) NA ND gate 0 .0 5 2
5 4 H22 23 0 7 Dual , 4 - input NA ND gate (open col l ector output)(high speed) 0 .0 4 4
5 4 S22 7 0 0 7 Dual , 4 - input NA ND gate (open col l ector output)(Schottky) 0 .0 4 4
5 4 3 0 1 0 1 Singl e, 8 - input NA ND gate 0 .0 3 2
4 3 H3 0 23 0 1 Singl e, 8 - input (high speed) NA ND gate 0 .0 4 4
5 4 L3 0 20 0 1 Singl e, 8 - input (l ow power) NA ND gate 0 .0 3 2
5 4 S3 0 7 0 0 3 Singl e, 8 - input (Schottky) NA ND gate 0 .0 4 4
5 4 3 7 3 0 2 Quad, 2- input NA ND buffer 0 .0 60
5 4 3 8 3 0 3 Quad, 2- input (open col l ector) NA ND buffer 0 .0 5 2
5 4 4 0 3 0 1 Dual , 4 - input NA ND buffer 0 .0 60
5 4 H4 0 24 0 1 Dual , 4 - input (high speed) NA ND buffer 0 .0 5 2
5 4 S4 0 7 2 0 1 Dual , 4 - input (Schottky) NA ND buffer 0 .0 5 2
TTL or NOR Gates
en
Commercial or
Generic Number
Specification
MI L- M- 3 8 5 1 0 /
Dev i ce
F/1 0
6
hrs
5 4 0 2 4 0 1 Quad, 2- input NO R gate 0 .0 64
5 4 L0 2 27 0 1 Quad, 2- input NO R gate (l ow power) 0 .0 68
5 4 S0 2 7 3 0 1 Quad, 2- input NO R gate (Schottky) 0 .0 7 2
5 4 23 4 0 2 Dual , 4 - input with strobe and expandabl e input NO R gate 0 .0 60
5 4 25 4 0 3 Dual , 4 - input NO R gate with strobe 0 .0 60
5 4 27 4 0 4 T ripl e, 3 - input NO R gate 0 .0 64
5 4 5 0 5 0 1 Expandabl e, dual 2- wide, 2- input A ND- O R invert gate 0 .0 5 2
5 4 H5 0 4 0 0 1 Expandabl e, dual 2- wide, 2- input A ND- O R invert gate (hi- spd) 0 .0 5 6
5 4 5 1 5 0 2 Dual , 2- wide, 2- input A ND- O R invert gate 0 .0 5 2
5 4 L5 1 4 1 0 1 Dual , 2- wide, 2- input A ND- O R invert gate (l ow power) 0 .0 5 2
5 4 H5 1 4 0 0 2 Dual , 2- wide, 2- input A ND- O R invert gate (high speed) 0 .0 5 2
5 4 S5 1 7 4 0 1 Dual , 2- wide, 2- input A ND- O R invert gate (Schottky) 0 .0 5 6
5 4 5 3 5 0 3 Expandabl e, 4 - wide, 2- input A ND- O R invert gate 0 .0 5 2
5 4 H5 3 4 0 0 3 Expandabl e, 4 - wide, 2- input A ND- O R invert gate (high speed) 0 .0 5 2
5 4 5 4 5 0 4 4 - wide, 2- input A ND- O R invert gate 0 .0 5 2
5 4 H5 4 4 0 0 4 4 - wide, 2- input A ND- O R invert gate (high speed) 0 .0 5 2
5 4 L5 4 4 1 0 2 4 - wide, 2- input A ND- O R invert gate (l ow power) 0 .0 5 2
5 4 H5 5 4 0 0 5 Expandabl e, 2- wide, 4 - input A ND- O R invert gate (high speed) 0 .0 4 4
5 4 L5 5 4 1 0 3 Expandabl e, 2- wide, 4 - input A ND- O R invert gate (l ow power) 0 .0 4 4
5 4 S64 7 4 0 2 4 - 2- 3 - 2 input A ND- O R invert gate 0 .0 5 2
T T L or NO R Gates (Cont'd)
Commercial or
Generic Number
Specification
MI L- M- 3 8 5 1 0 /
Device
F/1 0
6
hrs
5 4 S65
5 4 8 6
5 4 L8 6
7 4
7
26
0 3
0 1
0 1
4 - 2- 3 - 2 input, open col l ector A ND- O R invert gate (Schottky)
Quad, 2- input, excl usive- O R gate
Quad, 2- input, excl usive- O R gate (l ow power)
0 .0 5 2
0 .0 8 4
0 .0 4 4
TTL Adders
CO
CTi
O
5 4 8 2 6 0 1 2- bit, ful l adder 0 .0 4 4
5 4 8 3 6 0 2 4 - bit, ful l adder 0 .1 1 2
9 3 0 4 6 0 3 Dual , ful l adder 0 .0 9 2
TTL ALU
9 3 4 1 1 1 0 1 A LU/function generator 0 .1 8 0
9 3 4 2 1 1 0 2 Lookahead carry generator 0 .0 9 2
5 4 1 8 1 1 1 0 1 A LU/function generator 0 .1 8 0
5 4 1 8 2 1 1 0 2 Lookahead carry generator 0 .0 9 2
TTL Flip-Flops, Multivibrators and Latches
Commercial or
Generic Number
Specification
MI L- M- 3 8 5 1 0 /
Device
F/1 0
6
hrs
5 4 7 0 2 0 6 Singl e, edge- triggered J- K fl ip- fl op 0 .0 68
5 4 7 2 2 0 1 Singl e, J- K master sl ave fl ip- fl op 0 .0 64
5 4 H7 2 22 0 1 Singl e, J- K master sl ave fl ip- fl op (high speed) 0 .0 60
5 4 L7 2 21 0 2 Singl e, J- K master sl ave fl ip- fl op (l ow power) 0 .0 64
5 4 7 3 2 0 2 Dual , J- K master sl ave, no preset fl ip- fl op 0 .0 8 4
5 4 H7 3 22 0 2 Dual , J- K master sl ave, no preset fl ip- fl op (high speed) 0 .0 8 4
5 4 L7 3 21 0 3 Dual , J- K master sl ave, no preset fl ip- fl op (l ow power) 0 .0 8 4
5 4 7 4 2 0 5 Dual , D- type, edge triggered fl ip- fl op 0 .0 7 2
5 4 H7 4 22 0 3 Dual , D- type, edge triggered fl ip- fl op (high speed) 0 .0 8 8
5 4 L7 4 21 0 5 Dual , D- type, edge triggered fl ip- fl op (l ow power) 0 .0 7 6
5 4 S7 4 7 1 0 1 Dual , D- type, edge triggered fl ip- fl op (Schottky) 0 .0 8 4
5 4 7 5 1 5 0 1 4 - bit, bistabl e l atch, compl ementary outputs 0 .0 9 2
5 4 7 6 2 0 4 Dual , J- K, master- sl ave fl ip- fl op 0 .0 8 4
5 4 H7 6 22 0 4 Dual , J- K, master sl ave fl ip- fl op (high speed) 0 .0 7 6
5 4 7 7 1 5 0 2 4 - bit l atch 0 .0 8 4
5 4 L7 8 21 0 4 Dual , J- K, master sl ave fl ip- fl op (l ow power) 0 .0 8 4
5 4 7 9 2 0 7 Dual , D- type, edge triggered, buffered output fl ip- fl op 0 .0 8 4
5 4 H1 0 1 22 0 5 Singl e, edge triggered, J- K fl ip- fl op (high speed) 0 .0 7 2
5 4 H1 0 3 22 0 6 Dual , J- K edge triggered fl ip- fl op (high speed) 0 .0 9 2
5 4 S1 1 2 7 1 0 2 Dual , J- K edge triggered fl ip- fl op (Schottky) 0 .0 8 4
TTL Flip-Flops, Multivibrators and Latches (Cont' d)
crv
r\3
Commercial or
Generic Number
Specification
MI L- M- 3 8 5 1 0 /
Device
F/1 0
6
hrs
5 4 S1 1 3 7 1 0 3 Dual , J- K edge triggered fl ip- fl op (Schottky 0 .0 8 4
5 4 S1 1 4 7 1 0 4 Dual , J- K edge triggered fl ip- fl op (Schottky) 0 .0 8 4
5 4 1 1 6 1 5 0 3 Dual , 4 - bit l atch 0 .0 9 2
5 4 1 21 1 2 0 1 Singl e monostabl e mul tivibrator 0 .0 68
5 4 1 22 1 2 0 2 Singl e, retriggerabl e with cl ear monostabl e mul tivibrator 0 .0 68
5 4 1 23 1 2 0 3 Dual , retriggerabl e with cl ear monostabl e mul tivibrator 0 .0 9 2
5 4 1 7 4 1 7 0 1
Hex, D- type, positive- edge fl ip- fl op triggered with cl ear
and singl e outputs
0 .1 5 2
5 4 S1 7 4 7 1 0 5
Hex, D- type, positive- edge fl ip- fl op triggered with cl ear
and singl e outputs (Schottky)
, 0 .1 5 2
5 4 1 7 5 1 7 0 2
Quad, D- type, positive- edge fl ip- fl op triggered with cl ear
and compl ementary outputs
0 .1 20
5 4 S1 7 5 7 1 0 6
Quad, D- type, positive- edge fl ip- fl op triggered with cl ear
and compl ementary outputs (Schottky)
0 .1 1 2
9 3 0 8 1 5 0 3 Dual , 4 - bit l atch 0 .0 9 2
9 3 1 4 1 5 0 4 4 - bit, master reset l atch 0 .1 0 0
T T L Shift Registers
en
Commercial or Specification Device F/1 0
6
Generic Number MI L- M- 3 8 5 1 0 / T ype Circuit Description hrs
5 4 9 5 9 0 1 4 - bit, right shift, l eft shift 0 .1 0 0
5 4 L9 5 28 0 1 4 - bit, right shift, l eft shift (l ow power) 0 .1 0 0
5 4 9 6 9 0 2 5 - bit 0 .1 0 8
5 4 1 64 9 0 3 8 - bit, paral l el - out, serial 0 .1 1 2
5 4 L1 64 28 0 2 8 - bit, paral l el - out, serial (l ow power) 0 .1 1 2
5 4 1 65 9 0 4 8 - bit, paral l el l oad 0 .1 20
5 4 1 9 4 9 0 5 4 - bit, bidirectional 0 .1 20
5 4 1 9 5 9 0 6 4 - bit, paral l el access 0 .1 1 2
7 6L7 0 28 0 5 8 - bit, paral l el - out, serial (l ow power) 0 .1 20
9 3 L0 0 28 0 4 4 - bit (l ow power) 0 .1 0 0
9 3 L28 28 0 3 Dual , 8 - bit (l ow power) 0 .0 9 2
T T L Decoders
5 4 4 2 1 0 0 1 BCD to decimal 0 .1 0 0
5 4 L4 2 29 0 1 BCD to decimal (l ow power) 0 .1 0 0
5 4 4 3 1 0 0 2 Excess- 3 to decimal 0 .1 0 0
5 4 L4 3 29 0 2 Excess- 3 to decimal (l ow power) 0 .1 0 0
5 4 4 4 1 0 0 3 Excess- 3 gray- to- decimal 0 .1 0 0
5 4 L1 4 29 0 3 Excess- 3 gray- to- decimal (l ow power) 0 .1 0 0
5 4 4 5 1 0 0 4 BCD to decimal decoder/driver (open col l ector) 0 .1 0 0
5 4 4 6 1 0 0 6 BCD to 7 - segment decoder/driver (open col l ector) 0 .1 0 0
5 4 L4 6 29 0 4 BCD to 7 - segment decoder/driver (open col l ector)(l ow power) 0 .1 0 0
5 4 4 8 1 0 0 8 BCD to 7 - segment decoder/driver 0 .1 0 0
5 4 4 9 1 0 0 9 BCD to 7 - segment decoder/driver (open col l ector) 0 .0 9 2
T T L Counters
CO
Commercial or Specification Device F/1 0
6
Generic Number MI L- M- 3 8 5 1 0 / T ype Circuit Description hrs
5 4 9 0 1 3 0 7 High speed 0 .1 0 0
5 4 L9 0 25 0 1 High speed decade (l ow power) 0 .1 20
5 4 9 2 1 3 0 1 Divide- by- 1 2 0 .0 8 8
5 4 9 3 1 3 0 2 4 - bit binary 0 .0 9 2
5 4 L9 3 25 0 2 4 - bit binary (l ow power) 0 .0 8 8
5 4 1 62 1 3 0 5 Synchronous 4 - bit decade (synchronous cl ear) 0 .1 20
5 4 1 63 1 3 0 4 Synchronous 4 - bit binary (synchronous cl ear) 0 .1 20
5 4 1 9 2 1 3 0 8 Synchronous 4 - bit up/down decade 0 .1 5 2
5 4 1 9 3 1 3 0 9 Synchronous 4 - bit up/down binary 0 .1 4 0
T T L Data Sel ectors/Mul tipl exers
5 4 1 5 0 1 4
-= -=
0 1 1 6- input with enabl e 0 .1 0 8
5 4 1 5 3 1 4 0 3 Dual , 4 - input with enabl e 0 .1 0 0
9 3 0 9 1 4 0 4 Dual , 4 - input without enabl e 0 .0 68
9 3 1 2 1 4 0 2 8 - input with enabl e 0 .0 8 4
9 3 22 1 4 0 5 Quad, 2- input with enabl e 0 .0 8 4
CMO S NA ND Gates, Buffers, I nverters, and A ND- 0 R Sel ect Gates
4 0 0 7 A 5 3 0 1 Dual , compl ementary pair pl us inverter 0 .0 4 4
4 0 1 1 A 5 0 0 1 Quad, 2- input NA ND gate 0 .0 5 6
4 0 1 2A 5 0 0 2 Dual , 4 - input NA ND gate 0 .0 5 6
4 0 1 9 A 5 3 0 2 Quad, A ND- O R sel ect gate 0 .0 7 2
4 0 23 A 5 0 0 3 T ripl e, 3 - input NA ND gate 0 .0 64
4 0 4 9 A 5 5 0 3 I nverting hex buffer 0 .0 5 2
4 0 5 0 A 5 5 0 4 Non- inverting hex buffer 0 .0 68
CMOS Flip-Flops
Commercial or
Generic Number
Specification
MI L- M- 3 8 5 1 0 /
Device
F/1 0
b
hrs
4 0 1 3 A
4 0 27 A
5 1
5 1
0 1
0 2
Dual , D- type, edge triggered
Dual , J- K, master sl ave
0 .1 0 4
0 .1 1 2
CMO S NO R Gates
CO
en
4 0 0 0 A 5 2 0 1 Dual , 3 - input pl us inverter 0 .0 5 6
4 0 0 1 A 5 2 0 2 Quad, 2- input 0 .0 5 6
4 0 0 2A 5 2 0 3 Dual , 4 - input 0 .0 5 6
4 0 25 A 5 2 0 4 T ripl e, 3 - input 0 .0 64
CMO S A dders
4 0 0 8 A 5 4 0 1 4 - bit ful l adder 0 .1 5 2
CMO S Counters/Dividers
4 0 1 7 A 5 6 0 1 Decade counter/divider 0 .23 2
4 0 1 8 A 5 6 0 2 Presettabl e divide- by- N counter 0 .25 6
4 0 20 A 5 6 0 3 1 4 - stage rippl e- carry binary counter/divider 0 .3 4 4
4 0 22A 5 6 0 4 Divide- by- S counter/divider 0 .20 0
4 0 24 A 5 6 0 5 7 - stage binary counter 0 .20 0
CMO S Static Shift Registers
Commercial or
Generic Number
Specification
MI L- M0 3 8 5 1 0
Device
F/1 0
6
hrs
4 0 0 6A
4 0 1 4 A
4 0 1 5 A
4 0 21 A
4 0 3 1 A
5 7
5 7
5 7
5 7
5 7
0 1
0 2
0 3
0 4
0 5
Dual , 4 - stage/dual 5 - stage
8 - stage synchronous paral l el or serial input/serial output
Dual , 4 - stage serial input/paral l el output
8 - stage asynchronous paral l el input/serial output
64 - stage
0 .3 20
0 .25 6
0 .25 6
0 .25 6
0 .23 2
[
HYPR0 M 5 1 2
Programmabl e RO M
512 -bit 0.2 80
00
CT>
Bipol ar O perational A mpl ifiers
7 4 1 1 0 1 0 1 Singl e, internal l y compensated 0 .1 4 4
7 4 7 1 0 1 0 2 Dual , internal l y compensated 0 .1 3 6
LM1 0 1 A 1 0 1 0 3 Singl e, external l y compensated 0 .1 20
LM1 0 SA 1 0 1 0 4 Singl e, external l y compensated 0 .1 5 2
LM1 0 2 1 0 6 0 1 Vol tage fol l ower 0 .1 1 2
LM1 1 0 1 0 6 0 2 Vol tage fol l ower, high speed 0 .1 1 2
Bipol ar Vol tage Regul ators
7 23
LM1 0 9
1 0 2
1 0 7
0 1
0 1
Precision
5 - vol t
0 .1 1 2
0 .1 1 2
Bipol ar Vol tage Comparators
Commercial or
Generic Number
Specification
MI L- M- 3 8 5 1 0 /
Device
F/1 0
6
hrs
7 1 0
7 1 1
LM1 0 6
LMl l l
1 0 3
1 0 3
1 0 3
1 0 3
0 1
0 2
0 3
0 4
Singl e, differential
Dual channel , differential
Singl e, comparator/buffer
Precision, comparator/buffer
0 .1 20
0 .1 1 2
0 .0 9 6
0 .1 20
Bipol ar Line Drivers and Receivers
5 5 1 0 7 1 0 4 0 1 Dual , l ine receiver 0 .1 4 4
5 5 1 0 8 1 0 4 0 2 Dual , l ine receiver, open col l ector output 0 .1 3 6
5 5 1 1 3 1 0 4 0 5 Dual , differential l ine driver (3 - state output) 0 .1 8 4
5 5 1 1 4 1 0 4 0 3 Dual , differential l ine driver (2- state output) 0 .20 8
5 5 1 1 5 1 0 4 0 4 Dual , differential l ine receiver 0 .1 7 6
9 61 4 1 0 4 0 3 Dual , differential l ine driver (2- state output) 0 .20 8
9 61 5 1 0 4 0 4 Dual , differential l ine receiver 0 .1 7 6
ECL NO R Gates
1 0 5 0 1 60 0 1 Quad, 0 T /N0 R with strobe 0 .0 8 0
1 0 5 0 2 60 0 2 T ripl e, NO R, singl e 0 R/N0 R 0 .0 8 0
1 0 5 0 5 60 0 3 T ripl e, 2- 3 - 2 0 R/N0 R 0 .0 8 0
1 0 5 0 6 60 0 4 T ripl e, 3 - 4 - 3 NO R 0 .0 7 6
1 0 5 0 7 60 0 5 T ripl e, excl usive 0 R/N0 R 0 .0 8 8
1 0 5 0 9 60 0 6 Dual , 4 - 5 0 R/N0 R 0 .0 7 2
CMOS
CO
00
Generic Number
Mi 1 i tary
Number T abl e Circuit Description F/1 0
6
4 0 0 0 A /0 5 20 1 I I - B Dual , 3 - input pl us inverter NO R gates 0 .0 5 6
4 0 0 1 A /0 5 20 2 I I - B Quad, 2- input NO R gates 0 .0 5 6
4 0 0 2A /0 5 20 3 I I - B Dual , 4 - input NO R gates 0 .0 5 6
4 0 0 6A /0 5 7 0 1 I I - E Dual , 4 - stage/dual 5 - stage static shift register 0 .3 20
4 0 0 7 A /0 5 3 0 1 I I Dual , compl ementary pair pl us inverter 0 .0 4 4
4 0 0 8 A /0 5 4 0 1 I I - C 4 - bit ful l adder 0 .1 5 2
4 0 1 1 A /0 5 0 0 1 I I Quad, 2- input NA ND gate 0 .0 5 6
4 0 1 2A /0 5 0 0 2 I I Dual , 4 - input NA ND gate 0 .0 5 6
4 0 1 3 A /0 5 1 0 1 I I - A Dual , D- type, edge triggered fl ip- fl op 0 .1 0 4
4 0 1 4 A /0 5 7 0 2 I I - E
8 - stage, synchronous paral l el or serial input/serial output
static shift register
0 .25 6
4 0 1 5 A /0 5 7 0 3 I I - E
Dual , 4 - stage serial input/paral l el output static shift
register
0 .25 6
4 0 1 7 A /0 5 60 1 I I - D Decade counter/divider 0 .23 2
4 0 1 8 A /0 5 60 2 I I - D Presettabl e divide- by- N counter 0 .25 6
4 0 1 9 A /0 5 3 0 2 I I Quad, A ND- O R sel ect gate 0 .0 7 2
4 0 20 A /0 5 60 3 I I - D 1 4 - stage rippl e- carry binary counter/divider 0 .3 4 4
4 0 21 A /0 5 7 0 4 I I - E
8 - stage asynchronous paral l el input/serial output static
shift register
0 .25 6
4 0 22A /0 5 60 4 I I - D Divide- by- S counter/divider 0 .20 0
4 0 23 A /0 5 0 0 3 I I T ripl e, 3 - input NA ND gate 0 .0 64
CMOS (Cont'd)
Generic Number
Mil itary
6
4 0 24 A /0 5 60 5 I I - D 7 - stage binary counter 0 .20 0
4 0 24 A /0 5 20 4 I I - B T ripl e, 3 - input NO R gates 0 .0 64
4 0 27 A /0 5 1 0 2 I I - A Dual , J- K, master- sl ave fl ip- fl op 0 .1 1 2
4 0 3 1 A /0 5 7 0 5 I I - E 64 - stage static shift register 0 .23 2
4 0 1 9 A /0 5 5 0 3 I I I nverting hex buffer 0 .0 5 2
4 0 5 0 A /0 5 5 0 1 I I Non- inverting hex buffer 0 .0 68
ECL
CO
en
wo
1 0 5 0 1 /0 60 0 1 V Quad, 0 R/N0 R with strobe 0 .0 8 0
1 0 5 0 2 /0 60 0 2 V T ripl e, NO R, singl e 0 R/N0 R, singl e 0 T /N0 R gate 0 .0 8 0
1 0 5 0 5 /0 60 0 3 V T ripl e, 2- 3 - 2 0 R/N0 R gate 0 .0 8 0
1 0 5 0 6 /0 60 0 4 V T ripl e, 3 - 4 - 3 NO R gate 0 .0 7 6
1 0 5 0 7 /0 60 0 5 V T ripl e, excl usive 0 R/N0 R gate 0 .0 8 8
1 0 5 0 9 /0 60 0 6 V Dual , 4 - 5 0 R/N0 R gate 0 .0 7 2
Linear Devices
o
Generic Number
Mil itary
6
7 1 0 /1 0 3 0 1 I V- B Singl e, differential vol tage comparator 0 .1 20
7 1 1 /1 0 3 0 2 I V- B Dual channel , differential vol tage comparator 0 .1 1 2
7 23 /1 0 20 1 I V- A Precision vol tage regul ator 0 .1 1 2
7 4 1 /1 0 1 0 1 I V Singl e, internal l y compensated operational ampl ifier 0 .1 4 4
7 4 7 /1 0 1 0 2 I V Dual , internal l y compensated operational ampl ifier 0 .1 24
5 5 1 0 7 /1 0 4 0 1 I V- C Dual , l ine receiver 0 .1 4 4
5 5 1 0 8 /1 0 4 0 2 I V- C Dual , l ine receiver, open col l ector output 0 .1 4 4
5 5 1 1 3 /1 0 4 0 5 I V- C Dual , differential l ine driver 0 .1 8 4
5 5 1 1 4 /1 0 4 0 3 I V- C Dual , differential l ine driver (2- state output) 0 .20 8
5 5 1 1 5 /1 0 4 0 4 I V- C Dual , differential l ine receiver 0 .1 7 6
9 61 4 /1 0 4 0 3 I V- C Dual , differential l ine driver 0 .20 8
9 61 5 /1 0 4 0 4 I V- C Dual , differential l ine receiver 0 .1 7 6
LM1 0 1 A /1 0 1 0 3 I V Singl e, external l y compensated operational ampl ifier 0 .1 20
LM1 0 2 /1 0 60 1 I V Vol tage fol l ower operational ampl ifier 0 .1 1 2
LM1 0 6 /1 0 3 0 3 I V- B Singl e, comparator/buffer vol tage 0 .0 9 6
LM1 0 8 A /1 0 1 0 4 I V Singl e, external l y compensated operational ampl ifier 0 .1 5 2
LM1 0 9 A /1 0 7 0 1 I V- A 5 - vol t vol tage regul ator 0 .1 1 2
LM1 1 0 /1 0 60 2 I V Vol tage fol l ower, high speed operational ampl ifier 0 .1 1 2
LM1 1 1 /1 0 3 0 4 I V- B Precision, comparator/buffer vol tage comparator 0 .1 20
TTL
CO
T T L
Medium Speed/Power
T T L
Low Power
T T L
High Speed
T T L
Schottky Circuit Description F/1 0
6
5 4 0 0
/0 0 1 0 4
I
5 4 L0 0
/0 20 0 4
I
5 4 H0 0
/0 23 0 4
I
5 4 S0 0
/0 7 0 0 1
I
Quad, 2- input NA ND gate 0 .0 60
5 4 0 1
/0 0 1 0 7
I
5 4 L0 1
/0 20 0 6
I
5 4 H0 1
/0 23 0 6
I
Quad, 2- input NA ND gate (open col l ector
output)
0 .5 6
5 4 0 2
/0 0 4 0 1
I - B
5 4 L0 2
/0 27 0 1
I - B
5 4 S0 2
/0 7 3 0 1
I - B
Quad, 2- input NO R gate 0 .0 64
5 4 0 3
/0 0 1 0 9
I
5 4 L0 3
/0 20 0 6
I
5 4 S0 3
/0 7 0 0 2
I
Quad, 2- input, open col l ector NA ND gate 0 .0 5 6
5 4 0 1
/0 0 1 0 5
I
5 4 L0 4
/0 23 0 5
I
5 4 H0 4
/0 7 0 0 5
I
5 4 S0 4
/0 7 0 0 3
I
Hex inverter 0 .0 7 2
5 4 0 5
/0 0 1 0 8
I
5 4 S0 5
/0 7 0 0 4
I
Hex inverter, open col l ector 0 .0 64
5 4 0 6
/0 0 5 0 1
I
I nverter/buffer driver, 3 0 vol t output 0 .0 7 2
5 4 0 7
/0 0 8 0 3
I
Buffer driver, 3 0 - vol t output 0 .0 64
5 4 0 8
/0 1 60 1
I
Quad, 2- input A ND gate 0 .0 64
TTL (Cont'd)
T T L
Medium Speed/Power
T T L
Low Power
T T L
High Speed
T T L
6
5 4 0 9
/0 1 60 2
I
Quad, 2- input, open col l ector A ND gate 0 .0 60
5 4 1 0
/0 0 1 0 3
I
5 4 L1 0
/0 20 0 3
I
5 4 H1 0
/0 23 0 3
I
5 4 S1 0
/0 7 0 0 5
I
T ripl e, 3 - input NA ND gate 0 .0 5 6
5 4 1 2
/0 0 1 0 6
I
T ripl e, 3 - input, open col l ector NA ND gate 0 .0 5 2
5 4 20
/0 0 1 0 2
I
5 4 L20
/0 20 0 2
I
5 4 H20
/0 23 0 2
I
5 4 S20
/0 7 0 0 6
I
Dual , 4 - input NA ND gate 0 .0 5 2
5 4 H22
/0 23 0 7
I
5 4 S22
/0 7 0 0 7
I
Dual , 4 - input NA ND gate (open col l ector
output)
0 .0 4 4
5 4 23
/0 0 4 0 2
I - B
Dual , 4 - input with strobe and expandabl e
input NO R gate
0 .0 60
5 4 25
/0 0 4 0 3
I - B
Dual , 4 - input NO R gate with strobe 0 .0 60
5 4 27
/0 0 4 0 4
I - B
T ripl e, 3 - input NO R gate 0 .0 64
5 4 3 0
/0 0 1 0 1
I
5 4 L3 0
/0 20 0 1
I
5 4 H3 0
/0 23 0 1
I
5 4 S3 0
/0 7 0 0 8
I
Singl e, 8 - input NA ND gate 0 .0 3 2
TTL (Cont'd)
CO
T T L
Medium Speed/Power
T T L
Low Power
T T L
High Speed
T T L
6
5 4 3 7
/0 0 3 0 2
I
Quad, 2- input NA ND buffer 0 .0 60
5 4 3 8
/0 0 3 0 3
I
Quad, 2- input (open col l ector) NA ND buffer 0 .0 5 2
5 4 4 0
/0 0 3 0 1
I
5 4 H4 0
/0 24 0 1
I
5 4 S4 0
/0 7 20 1
I
Dual , 4 - input NA ND buffer 0 .0 60
5 4 4 2
/0 1 0 0 1
I - F
5 4 L4 2
/0 29 0 1
I - F
BCD to decimal decoder 0 .1 0 0
5 4 4 3
/0 1 0 0 2
I - F
5 4 L4 3
/0 29 0 2
I - F
Excess - 3 to decimal decoder 0 .1 0 0
5 4 4 4
/0 1 0 0 3
I - F
5 4 L4 4
/0 29 0 3
I - F
Excess - 3 gray- to- decimal decoder 0 .1 0 0
5 4 4 5
/0 1 0 0 4
I - F
BCD to decimal decoder/driver
(open col l ector)
0 .1 0 0
5 4 4 6
/0 1 0 0 6
I - F
5 4 L4 6
/0 29 0 4
I - F
BCD to 7 segment decoder/driver
(open col l ector)
0 .1 0 0
5 4 4 8
/0 1 0 0 8
I - F
BCD to 7 segment decoder/driver 0 .1 0 0
TTL (Cont'd)
CO
T T L
Medium Speed/Power
T T L
Low Power
T T L
High Speed
T T L
6
5 4 4 9
/0 1 0 0 9
I - F
BCD to 7 segment decoder/driver
(open col l ector)
0 .0 9 2
5 4 5 0
/0 0 5 0 1
I - B
5 4 H5 0
/0 4 0 0 1
I - B
Expandabl e, dual 2- wide, 2- input A ND- O R
invert gate
0 .0 5 2
5 4 5 1
/0 0 5 0 2
I - B
5 4 L5 1
/0 4 1 0 1
I - B
5 4 H5 1
/0 4 0 0 2
I - B
5 4 S5 1
/0 7 4 0 1
I - B
Dual , 2- wide, 2- input A ND- O R invert gate 0 .0 5 2
5 4 5 3
/0 0 5 0 3
I - B
5 4 H5 3
/0 4 0 0 3
I - B
Expandabl e, 4 - wide, 2- input A ND- O R invert
gate
0 .0 5 2
5 4 5 4
/0 0 5 0 4
I - B
5 4 L5 4
/0 4 1 0 2
I - B
5 4 H5 4
/0 4 0 0 4
I - B
4 - wide, 2- input A ND- O R invert gate 0 .0 5 2
5 4 L5 5
/0 4 1 0 3
I - B
5 4 H5 5
/0 4 0 0 5
I - B
Expandabl e, 2- wide, 4 - input A ND/O R invert
gate
0 .0 4 4
5 4 S64
/0 7 4 0 2
I - B
4 - 2- 3 - 2 input A ND- O R invert gate 0 .0 5 2
5 4 S65
/0 7 4 0 3
I - B
4 - 2- 3 - 2 input, open col l ector A ND- O R
invert gate
0 .0 5 2
5 4 7 0
/0 0 20 6
I - A
Singl e, edge- triggered J- K fl ip- fl op 0 .0 68
TTL (Cont'd)
CO
en
T T L
Medium Speed/Power
T T L
Low Power
T T L
High Speed
T T L
6
5 4 7 2
/0 0 20 1
I - A
5 4 L7 2
/0 21 0 2
I - A
5 4 H7 2
/0 220 1
I - A
Singl e, J- K master- sl ave fl ip- fl op 0 .0 64
5 4 7 3
/0 0 20 2
I - A
5 4 L7 3
/0 21 0 3
I - A
5 4 H7 3
/0 220 2
I - A
Dual , J- K, master- sl ave, no preset fl ip- fl op 0 .0 8 4
5 4 7 4
/0 0 20 5
I - A
5 4 L7 4
/0 21 0 5
I - A
5 4 H7 4
/0 220 3
I - A
5 4 S7 4
/0 7 1 0 1
I - A
Dual , D- type, edge- triggered fl ip- fl op 0 .0 7 2
5 4 7 5
/0 1 5 0 1
I - A
4 - bit, bistabl e l atch, compl ementary outputs 0 .0 9 2
5 4 7 6
/0 0 20 4
I - A
5 4 H7 6
/0 220 4
I - A
Dual , J- K, master- sl ave fl ip- fl op 0 .0 8 4
5 4 7 7
/0 1 5 0 2
I - A
4 - bit l atch 0 .0 8 4
. 5 4 L7 8
/0 21 0 4
I - A
Dual , J- K, master- sl ave fl ip- fl op 0 .0 8 4
5 4 7 9
/0 0 20 7
I - A
Dual , D- type, edge triggered buffered
output fl ip- fl op
0 .0 8 4
5 4 8 2
/0 0 60 1
I - C
2- bit, ful l adder 0 .0 4 4
TTL (Cont'd)
CO
T T L
Medium Speed/Power
T T L
Low Power
T T L
High Speed
T T L
6
5 4 8 3
/0 0 60 2
I - C
4 - bit, ful l adder 0 .1 1 2
5 4 8 6
/0 0 7 0 1
I - B
5 4 L8 6
/0 260 1
I - B
Quad, 2- input, excl usive- O R gate 0 .0 8 4
5 4 9 0
/0 1 3 0 7
I - G
5 4 L9 0
/0 25 0 1
I - G
High- speed decade counter 0 .1 0 0
5 4 9 2
/0 1 3 0 1
1 - 6
Divide- by- 1 2 counter 0 .0 8 8
5 4 9 3
/0 1 3 0 2
I - G
5 4 L9 3
/0 25 0 2
I - G
4 - bit binary counter 0 .0 9 2
5 4 9 5
/0 0 9 0 1
I - E
5 4 L9 5
/0 28 0 1
I - E
4 - bit, right shift, l eft shift register 0 .1 0 0
5 4 9 6
/0 0 9 0 2
I - E
5 - bit shift register 0 .1 0 8
5 4 H1 0 1
/0 220 5
I - A
Singl e, edge- triggered J- K fl ip- fl op 0 .0 8 4
5 4 H1 0 3
/0 220 6
I - A
Dual , J- K edge- triggered fl ip- fl op 0 .0 7 2
TTL (Cont'd)
u>
T T L
Medium Speed/Power
T T L
Low Power
T T L
High Speed
T T L
6
5 4 S1 1 2
/0 7 1 0 2
I - A
5 4 S1 1 3
/0 7 1 0 3
I - A
5 4 S1 1 4
/0 7 1 0 4
I - A
5 4 1 1 6
/0 1 5 0 3
I - A
Dual , 4 - bit l atch 0 .0 9 2
5 4 1 21
/0 1 20 1
I - A
Singl e, monostabl e mul tivibrator 0 .0 68
5 4 1 22
/0 1 20 2
I - A
Singl e, retriggerabl e with cl ear monostabl e
mul tivibrator
0 .0 68
5 4 1 23
/0 1 20 3
I - A
Dual , retriggerabl e with cl ear monostabl e
mul tivibrator
0 .0 9 2
5 4 1 5 0
/0 1 4 0 1
I - H
.
1 6- input with enabl e data sel ector/
mul tipl exer
0 .1 0 8
5 4 1 5 3
/0 1 4 0 3
I - H
Dual , 4 - input with enabl e data sel ector/
mul tipl exer
0 .1 0 0
TTL (Cont'd)
CO
00
T T L
Medium Speed/Power
T T L
Low Power
T T L
High Speed
T T L
Schottky
i
Circuit Description F/1 0
6
5 4 1 62
/0 1 3 0 5
I - G
Synchronous 4 - bit decade (synchronous
cl ear) counter
0 .1 20
5 4 1 63
/0 1 3 0 4
I - G
Synchronous 4 - bit binary (synchronous
cl ear) counter
0 .1 20
5 4 1 64
/0 0 9 0 3
I - E
5 4 L64
/0 28 0 2
I - E
8 - bit, paral l el - out, serial shift register 0 .1 1 2
5 4 1 65
/0 0 9 0 4
I - E
8 - bit, paral l el l oad shift register 0 .1 20
5 4 1 7 4
/0 1 7 0 1
I - A
5 4 S1 7 4
/0 7 1 0 5
I - A
Hex, D- type, positive- edge fl ip- fl op
triggered with cl ear and singl e outputs
0 .1 20
5 4 1 7 5
/0 1 7 0 2
I - A
5 4 S1 7 5
/0 7 1 0 6
I - A
Quad, D- type, positive- edge fl ip- fl op
triggered with cl ear and compl ementary
outputs
0 .1 20
5 4 1 8 1
/0 1 1 0 1
I - D
A LU/function generator | 0 .1 8 0
5 4 1 8 2
/0 1 1 0 2
I - D
Lookahead carry generator 0 .0 9 2
5 4 1 9 2
/0 1 3 0 8
I - G
Synchronous 4 - bit up/down decade counter 0 .1 5 2
TTL (Cont'd)
CO
VO
T T L
Medium Speed/Power
T T L
Low Power
T T L
High Speed
T T L
6
5 4 1 9 3
/0 1 3 0 9
I - G
Synchronous 4 - bit up/down binary counter 0 .1 4 0
5 4 1 9 4
/0 0 9 0 5
I - E
4 - bit, bidirectional shift register 0 .1 20
5 4 1 9 5
/0 0 9 0 6
I - E
4 - bit, paral l el access shift register 0 .1 1 2
7 6L7 0
/0 28 0 5
I - E
8 - bit, paral l el - out, serial shift register 0 .1 20
9 3 L0 0
/0 28 0 4
I - E
4 - bit shift register 0 .1 0 0
9 3 0 4
/0 0 60 3
I - C
Dual , ful l adder 0 .0 9 2
9 3 0 8
/0 1 5 0 3
I - A
Dual , 4 - bit l atch 0 .0 9 2
9 3 0 9
/0 1 4 0 4
I - H
Dual , 4 - input without enabl e data
seiector/mul ti piexer
0 .0 68
9 3 1 2
/0 1 4 0 2
I - H
8 - input with enabl e data sel ector/
mul tipl exer
0 .0 8 4
TTL (Cont'd)
CO
CD
O
T T L
Medium Speed/Power
T T L
Low Power
T T L
High Speed
T T L
6
9 3 1 4
/0 1 5 0 4
I - A
4 - bit, master reset l atch 0 .1 0 0
9 3 22
/0 1 4 0 5
I - H
Quad, 2- input with enabl e data
sel ector/mul tipl exer
0 .0 8 4

9 3 L28
/0 28 0 3
I - E
Dual , 8 - bit shift register 0 .0 9 2
9 3 4 1
/0 1 1 0 1
I - D
A LU/function generator 0 .1 8 0
9 3 4 2
/0 1 1 0 2
I - D
Lookahead carry generator 0 .0 9 2
1 1
Memory Devices
Generic Number
Mil itary
6
HYPR0 M.5 1 2 /20 1 0 1 I I I 5 1 2- bit PRO M 0 .28 0
A ssumption for Fail ure Rate Cal cul ations
T he fol l owing assumptions were made in fail ure rate
computations.
1 . I T Q = 2, 7 T * = 4 , *
L
= 1 , T
A
= 25 C
2. Where the number of transistors (NT ) < 1 20 ,
T j = 1 0 C+ T
A
; and where N
T
> 1 20 , T j = 25 C+ T
A
.
Hence, T T - T val ues are T T
T
= 0 .1 7 and 0 .3 5 ;
ir
T
= 0 .24 and 0 .8 2, respectivel y.
T
2
3 . Where more than one circuit configuration exists,
worst case compl exity was used.
*
iTr = Airborne Inhabited Environment
381
A PPENDI X D
CHA RA CT ERI ST I CS A ND FA I LURE RA T ES
O F ST A NDA RD ELECT RO N T UBES
T abl e I T UBES A PPRO VED FO R USE I N MI LI T A RY EQUI PMENT
Cathode Ray- El ectrostatic Defl ection and Focus
T ype
No.
I P
mA
mA dc
Maximum
Maximum
A node
Vol tage
Ebl Vdc
Maximum
gi
Cutoff
V
MI L- E- 1 /
Specification
Sheet No.
F/1 0
6
hrs
1 DP7 220 * 3 0 0 9 5 1 20 4 1 5
1 DP1 1 220 * 3 0 0 9 5 1 20 4 1 5
3 A CP1 A 660 1 5 0 0 - 7 5 3 1 1 1 5
3 A CP7 A 660 1 5 0 0 - 7 5 3 1 1 1 5
3 A DP2 660 * 1 1 0 0 - 8 7 9 7 4 1 5
3 A DP7 660 * 1 1 0 0 - 8 7 9 7 4 1 5
3 A DP1 1 660 * 1 1 0 0 - 8 7 9 7 4 1 5
3 SP1 660 1 1 0 0 - 1 0 1 5 0 2 1 5
3 WP1 660 1 1 0 0 - 7 5 267 1 5
4 MP1 660 * 1 1 0 0 - 8 7 1 29 6 1 5
5 A DP1 660 1 1 0 0 - 5 6 68 9 1 5
5 A DP7 660 1 1 0 0 - 7 5 68 9 1 5
5 A FP1 660 1 7 5 0 - 7 5 1 0 4 8 1 5
5 A FP7 660 1 7 5 0 - 7 5 1 0 4 8 1 5
5 A QP7 660 1 65 0 - 7 9 1 1 3 3 1 5
5 BFP7 660 1 5 5 0 - 65 1 20 5 1 5
5 BHP2A 660 8 8 0 - 8 0 1 3 9 5 1 5
6DP7 1 9 8 0 1 5 5 0 - 1 24 1 0 7 9 1 5
7 A EP7 660 1 3 7 5 - 7 5 9 4 9 1 5
7 A GP1 9 660 3 5 0 0 - 1 7 5 1 1 7 8 1 5
7 A KP25 660 27 5 0 - 1 20 1 21 9 1 5
7 BSP7 3 1 0 1 65 0 - 7 2 1 4 5 5 1 5
7 YP2 660 1 65 0 - 9 0 4 22 1 5
1 2A KP7 660 3 3 0 0 - 24 0 1 1 22 1 5
1 2A T P28 1 9 8 0 20 0 0 - 8 6 1 4 0 0 1 5
3 8 5
Cathode Ray- Magnetic Defl ection, El ectrostatic and Magnetic Focus
T ype
No.
Focus
T ype
I f
mA
Max
Maximum
A node
Vol tage
Ebl Vdc
Maximum
Grid
Cutoff
Eel Vdc
MI L- E- 1 /
Specification
Sheet No.
F/1 0
6
hrs
5 A HP7 A El ec 660 1 1 0 0 - 7 7 9 7 2 1 5
5 FP7 A Mag 660 8 8 0 0 - 7 0 1 3 9 2 1 5
5 FP1 4 A Mag 660 8 8 0 0 - 7 0 1 3 9 2 1 5
7 A BP7 A El ec 660 1 1 0 0 - 7 7 8 66 1 5
7 MP7 Mag 660 8 8 0 0 - 63 67 1 5
1 0 KP7 A Mag 660 1 1 0 0 0 - 63 1 1 62 1 5
1 0 WP7 El ec 660 9 0 0 - 7 7 1 0 0 5 1 5
1 2A BP7 A El ec 660 1 1 0 0
1 261 1 5
22CP7 A Mag 660 1 8 0 0 0 - 7 7 1 0 7 2 1 5
22CP25 A Mag 660 1 8 0 0 0 - 7 7 1 0 7 2 1 5
I mage Converters
T ype
No.
Eb
Vdc
Max
ib
A dc
Max
I b
A dc
Max
A l titude
ft
MI L- E- 1 /
Specification
Sheet No.
F/1 0
6
hrs
69 1 4
69 29
1 6, 0 0 0
1 2, 0 0 0
3 .5
3 .5
0 .3 5
0 .3 5
1 0 , 0 0 0
1 0 , 0 0 0
1 0 4 9
1 5 8 3
20
20
T ravel ing Wave
T ype
No.
Frequency
Range
GHz Function
Power
O utput
MI L- E- 1 /
Specification
Sheet No.
F/1 0
6
hrs
8 1 7 5
8 3 62
8 3 64
2.9 to 3 .1
5 .4 to 5 .9
5 .4 to 5 .9
A mpl ifier
A mpl ifier
A mpl ifier
1 kW
5 0 W
20 0 mW
1 623
1 65 3
1 65 4
3 0
3 0
3 0
3 8 6
Pl anar and Pencil
T ype
No.
Design Function
Pp
W
Fl
MHz
MI L- E- 1 /
Specification
Sheet No.
F/1 0
6
hrs
629 9 Pl anar triode
ceramic- metal
2.0 3 , 0 0 0 4 8 4 1 0 0
7 5 5 4 Pencil triode
ceramic- metal
Cl ass C
ampl ifier
2.5 5 5 0 1 3 25 1 0 0
64 4 2 Pl anar triode
ceramic- metal
O scil l ator
or ampl ifier
8 .0 2, 5 0 0 1 0 5 5 1 0 0
7 8 1 5 Pl anar triode
ceramic- metal
A node, grid
pul sed
oscil l ator
or ampl ifier
1 0 3 , 0 0 0 1 4 29 1 0 0
7 28 9 Pl anar triode CW
oscil l ator
1 0 0 2, 5 0 0 1 1 20 1 0 0
Pul se Modul ators (gas)
T ype
No.
epx
kV
ib
a
I b
A dc xl 0
y
MI L- E- 1 /
Specification
Sheet No. F/1 0
6
hrs
7 621 8 9 0 0 .1 0 0 2.7 1 4 28 1 0
7 7 8 2 1 2 3 5 0 0 .2 4 .0 1 63 6 1 0
7 665 1 6 3 5 0 0 .5 0 5 .0 1 4 8 5 1 0
7 620 20 5 0 0 0 .5 1 0 1 61 2 1 0
8 3 5 4 25 1 , 0 0 0 2.2 25 1 3 61 1 0
7 3 9 0 3 3 2, 0 0 0 4 .0 3 0 1 3 61 1 0
Vidicons
T ype
No.
Cutoff
Vdc max
Center Resol ution
(l ines)
min
MI L- E- 1 /
Specification
Sheet No. F/1 0
6
hrs
7 0 3 8
7 263 A
7 7 3 5 A
- 9 5
- 9 5
- 9 5
65 0
65 0
65 0
1 5 3 4
1 29 4
1 4 1 0
20
20
20
3 8 7
Kl ystrons
T ype
No.
Center
Frequency
MHz
Power
O utput
N
Frequency
Range
MHz
Duty
MI L- E- 1 /
Spec.
Sheet No.
F/1 0
6
hrs CW Pul se
A mpl ifiers
1 0 8 8 25 K 9 60 to 1 21 5 X 1 1 1 2 20 0 8 4 9 3
8 23 7 3 0 4 0 67 20 29 8 0 to 3 1 0 0 X 1 5 8 9 20 0
8 1 9 6 3 5 0 0 3 .5 M 3 4 0 0 to 3 60 0 X 1 5 20 20 0
8 3 1 5 5 64 2 3 0 0 5 3 8 5 to 5 9 0 0 X 1 29 0 20 0
8 3 61 5 65 0 3 M 5 4 0 0 to 5 9 0 0 X 1 228 20 0
8 4 0 4 5 65 7 2 5 3 8 5 to 5 9 3 0 X 1 28 9 20 0
O scil l ator
1 8 0 0 0 .0 5 7 8 5 to 28 20 X X 60 2 3 0 5 8 3 7
6BM6A 21 7 5 0 .0 5 5 5 0 to 3 8 0 0 X 7 4 6 3 0
61 3 3 261 3 0 .0 9 5 1 5 0 0 to 3 7 5 0 X X 20 0 3 0
2K22 4 5 7 5 0 .1 0 0 4 24 0 to 4 9 1 0 X 1 63 8 3 0
7 4 7 1 5 65 0 0 .0 3 5 5 0 0 to 5 8 0 0 X 1 28 3 3 0
VA - 220 B 7 27 5 1 .0 7 1 25 to 7 4 25 X 1 63 1 3 0
2K4 8 7 5 0 0 0 .0 2 4 0 0 0 to 1 1 0 0 0 X 3 7 4 3 0
63 9 0 8 8 8 2 0 .0 4 5 67 0 0 to 1 1 0 65 X X 8 4 0 3 0
69 4 0 9 0 8 0 0 .0 2 8 5 0 0 to 9 660 X 1 229 3 0
67 8 1 9 27 5 0 .0 4 0 8 5 0 0 to 1 0 0 0 0 X 1 1 8 0 3 0
7 5 1 1 9 5 0 0 0 .0 20 8 5 0 0 to 1 0 5 0 0 X 1 1 1 9 3 0
8 23 0 1 3 3 0 0 1 5 1 3 29 5 to 1 3 3 0 5 X 1 3 4 0 3 0
8 4 0 7 1 3 4 5 0 0 .1 4 0 1 24 0 0 to 1 4 5 0 0 X 1 5 7 1 3 0
8 1 8 2 69 7 5 0 0 .0 1 5 68 7 5 0 to 7 0 7 5 0 X 1 4 25 3 0
Power T riodes
T ype
No. Function
Pp
W
Fl
MHz
MI L- E- 1 /
Specification
Sheet No.
F/1 0
6
hrs
8 1 61 C T el egraphy 4 , 0 0 0 1 1 0 1 61 9 7 5
3 8 8
Power T etrodes
T ype
No. Function
Pp
W
Fl
MHz
MI L- E- 1 /
Specification
Sheet No.
F/1 0
6
hrs
68 1 6 C T el egraphy 1 1 5 1 , 21 2 1 23 9 1 0 0
68 8 4 C T el egraphy 1 1 5 1 , 21 5 1 23 9 1 0 0
7 5 8 0 W Cl ass A B1 25 0 3 0 1 3 8 5 1 0 0
8 621 Cl ass A B1 25 0 1 5 8 0 1 0 0
8 24 5 /
4 CX25 0 K
C Pul sed 25 0 1 , 5 0 0 1 5 0 6 1 0 0
8 1 67 Cl ass A B1 3 0 0 5 0 0 1 3 1 3 1 0 0
8 3 21 Cl ass A B1 3 5 0 1 63 4 1 0 0
8 3 22 Cl ass A B1 3 5 0 1 63 4 1 0 0
8 65 1
4 CX3 0 0 Y
C T el egraphy 4 0 0 1 1 0 1 5 4 1 1 0 0
628 3 C T el egraphy 4 8 0 9 0 0 1 3 1 4 ' 1 0 0
8 5 0 0 C T el egraphy 4 8 0 9 0 0 1 3 1 4 1 0 0
7 65 0
Linear RF
Power A mpl ifier
60 0 1 , 21 5 1 5 5 2 1 0 0
7 65 1
Pul sed
RF A mpl ifier
60 0 1 , 21 5 1 5 5 3 1 0 0
8 1 68 /
4 CX1 0 0 0 A
Cl ass A B1 or A B 1 , 0 0 0 1 1 0 1 5 69 1 0 0
8 660
4 CX1 5 0 0 B
Cl ass B or A B 1 , 5 0 0 3 0 1 64 8 1 0 0
8 1 7 0 W C T el egraphy 5 , 0 0 0 1 0 0 1 4 27 1 0 0
69 5 2
A node Pul sed
A mpl ifier;
Cl ass B
8 , 0 0 0 5 5 0 1 1 0 6 1 0 0
61 66A /
7 0 0 7
C T el egraphy 1 2, 0 0 0 220 1 5 4 3 1 0 0
20 4 1
Screen and Grid
Pul sed A mpl ifier;
Cl ass B
20 , 0 0 0 5 7 5 1 3 8 3 1 0 0
3 8 9
Graphic I ndicators
T ype
No.
I onization
Vol tage
Vdc
Cathode Current
(I ndividual )
mA
Character
Displ ay
MI L- E- 1 /
Specification
Sheet No.
F/1 0
6
hrs
68 4 4 A 1 7 0 4 .0 Numeral 1 266 1 5
7 0 0 9 1 7 0 2.0 Numeral 1 5 0 0 1 5
7 9 7 7 1 7 0 2.0 Numeral 1 4 9 7 1 5
8 4 21 1 7 0 3 .5 Numeral 1 4 5 4 1 5
8 4 22 1 7 0 3 .5 Numeral 1 5 1 9 1 5
8 4 23 1 7 0 4 .5 Numeral 1 5 1 8 1 5
Receiving T riodes
T ype
No.
Ef
V
Max
I f
mA
Max
Mu
Max
l b
mA dc
Max
MI L- E- 1 /
Specification
Sheet No. F/1 0
6
hrs
6C4 WA 6.9 1 60 1 8 .5 1 4 .5 8 5 7 5
1 2A T 7 WC 1 3 .9 1 5 8 7 0 .0 1 4 .0 1 0 9 7 5
5 67 0 W 6.9 3 7 0 4 4 .0 1 0 .5 5 5
5 7 0 3 WB 6.9 21 0 28 .5 1 1 .5 1 0 7 0 5
5 7 1 8 6.6 1 60 3 1 .0 1 1 .0 1 7 2 5
5 7 1 9 6.6 1 60 8 0 .0 0 .9 1 7 3 5
5 7 4 4 WB 6.9 21 0 8 0 .0 5 .2 1 0 7 3 5
5 7 5 1 1 3 .8 1 9 0 8 5 .0 1 .8 1 0 5
5 8 1 4 A 1 3 .8 1 9 0 1 8 .5 1 4 .5 1 2 5
60 1 2W 6.6 3 20 4 0 .0 8 .5 1 8 8 5
61 1 1 WA 6.6 3 20 23 .0 1 1 .0 1 27 0 5
61 1 2 6.6 3 20 8 0 .0 1 .1 0 1 9 0 5
65 3 3 WA 6.9 21 0 60 .0 1 .25 1 1 0 4 5
7 0 7 7 6.6 25 8 1 1 5 .0 8 .8 1 20 3 5
7 5 8 6 6.9 1 4 5 4 2.0 1 2.5 1 3 9 7 5
8 0 8 5 6.9 1 4 5 1 0 0 .0 1 2.0 1 4 9 1 5
8 5 3 2W 6.3 4 25 65 .0 1 8 .0 1 5 27 5
3 9 0
Receiving T etrodes and Pentodes
T ype
No. Cutoff
Ef
V
Max
I f
A mps
Max
l b
mA dc
Max
MI L- E- 1 /
Specification
Sheet No.
F/1 0
6
hrs
6A 1 1 0 WA
6A U6WC
5 0 5 4 W
5 7 0 2WB
5 7 4 9 W
5 8 4 0 W
5 8 9 4
5 8 9 9
7 5 8 7
Sharp
Sharp
Sharp
Sharp
Remote
Sharp
Semi -
Remote
Sharp
6.9
6.9
6.9
6.9
6.9
6.6
1 3 .8
6.6
6.9
0 .4 8 0
0 .3 25
0 .1 9 0
0 .21 0
0 .3 25
0 .1 60
2, 0
0 .1 60
0 .1 60
1 2.5
1 3 .5
1 1 .0
9 .5
1 3 .5
9 .5
2x 1 1 0
9 .2
1 1 .8
1 1 3 0
9 5 2
4
1 0 69
8
1 65 6
1 5 2
9 7
1 4 3 4
5
5
5
5
5
5
5
5
5
Receiving Mixers and Converters
T ype
No.
Ef
V
Max
I f
mA
Max
l b
mA dc
Max
MI L- E- 1 /
Specification
Sheet No. F/1 0
6
hrs
5 63 6 6.6 1 60 6.9 1 68 1 0
5 7 25 W 6.9 1 9 0 9 .0 6 1 0
5 7 5 0 6.9 3 25 3 .5 9 1 0
5 7 8 4 WB 6.9 21 0 7 .1 1 0 9 6 1 0
3 9 1
Receiving Power O utput T riodes
T ype
No.
Ef
V
Max
I f
mA
Max
Mu
Max
l b
mA dc
Max
MI L- E- 1 /
Specification
Sheet No. F/1 0
6
hrs
5 68 7 WB
60 8 0 WC
1 3 .2
6.6
4 7 0
265 0
21 .0
2.5
4 5
1 5 0
7 7 9
1 65 5
5
5
Receiving Power O utput Pentodes
T ype
No.
A mpl ifier
Description
Ef
V
Max
I f
mA
Max
l b
mA dc
Max
MI L- E- 1 /
Specification
Sheet No.
F/1 0
6
hrs
6A N5 WA Video 6.9 4 8 0 4 3 8 3 9 5
6L6WGB Beam Power 6.9 9 60 8 0 1 9 7 5
5 63 9
Video
RF
6.6 4 8 0 28 1 5 9 5
5 68 6 Beam Power 6.9 3 8 0 4 4 1 7 1 5
5 9 0 2 Beam Power 6.6 4 8 0 3 7 1 7 5 5
60 0 5 W Beam Power 6.9 4 8 0 5 7 1 3 5
60 9 4 Beam Power 6.6 64 0 5 7 8 21 5
61 4 6W Beam Power 1 0 % 1 3 25 1 4 0 1 5 0 2 5
63 8 4 Beam Power 6.9 1 260 8 8 1 0 22 5
3 9 2

Radc RDH-376

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