Design Technique for Interpolated Flash ADC

H. Tang
1
, H. Zhao
1
, S. Fan
2
, X. Wang
1
, L. Lin
1
, Q. Fang
1
, J. Liu
1
, A. Wang
1*
and B. Zhao
2
1
Dept. of Electrical Engineering, University of California, Riverside, CA, 92521, USA, aw@ee.ucr.edu
2
Fairchild Semiconductor, Inc., Irvine, CA, USA
Abstract
Analog-to-digital conversion plays an essential role in all
kinds of electronics systems, including signal processing,
communications and storage. In particular, interpolated
flash ADC has been widely used in high-speed systems
requiring very high sampling speed. Obviously, practical
ADC design is very challenging, which has been
dominated by experiences and trial-and-error skills. This
is true to flash ADC designs too where circuit designers
have often been puzzled by complex factors between
ADC chip performance and its architecture, circuit,
device and technological details. As system performance
continues advance and market demands intensify rapidly,
it is imperative for designers to make quick and rational
decisions in ADC designs to balance various design
factors. This paper reports a comprehensive design
matrix analysis and quantitative design approach for
capacitive interpolated flash ADCs aiming to address the
design challenges. It describes quantitatively the
complex relationship among critical factors including
ADC speed, interpolation, stage number, pre-amplifier
bandwidth, transistor parasitic effects, transistor size and
technology parameters, etc. The quantitative design
technique intends to enable designers to make rapid and
predictive decisions in flash ADC designs to achieve
both trade-offs and performance optimization in practice.
Design examples in 90/130nm CMOS are presented.
1. Introduction
ADC has become a basic building block for most
electronics systems. Among all kinds of ADCs, low to
medium resolution, very high speed flash ADCs
(sampling rate over Gsps) have applications in UWB
systems, disk drivers and optical communications.
Moderate resolution and relatively high speed flash
ADCs are used in CCD image systems, digital video
(e.g., HDTV), xDSL, cable modems and fast Ethernet,
etc [1]. In principle, an m-bit flash ADC consists of 2
m
-1
comparators and a resistor ladder with 2
m
equal segments.
However, due to the massive parallelism or lack of
front-end sampling, the number of comparators in flash
ADCs will grow exponentially with the resolution bits
that result in huge chip size, high power consumption
and large input capacitance, etc [2]. Hence, interpolation
technique has been widely used to resolve the above
problems for flash ADCs. The main idea of interpolation
is to increase the resolution by interpolating the output
voltages between adjacent preamplifiers.
In practical flash ADC designs, it is very important to
fully understand the influences of interpolation on the
performance of the whole flash ADC chips. This means a
quantitative matrix and clear mapping between the ADC
chip specs (e.g., resolution, sampling speed, size and
power dissipation) and low level factors, such as, process
parameters, device parameters, block circuit parameters,
topologies and architectures, are required. However,
such a quantitative flash ADC design methodology does
not exist yet, although there were some discussions on
design trade-offs [3, 4]. Consequently, practical flash
ADC design is still experience-based.
In this paper, we present a new quantitative design
matrix analysis technique for capacitive interpolated
flash ADC design, which provides an accurate and quick
bottom-up design method for flash ADC design
optimization. After introduction, Section 2 discusses the
details for the new design methodology and Section 3
presents design verification, followed by conclusions.
2. Interpolated Flash ADC Design Matrix
For a single-pole amplifier system, the frequency
response can be expressed by,
( )
1
V
L
A
H
j
e
e e
=
+
(1)
where A
V
is the large open-loop gain,
1
L
out out
R C
e = , R
out
and C
out
are the output resistance and capacitance
respectively. As the gain drops by -3dB, e.g., to
( )
1
2
V
H A e = , the bandwidth of the amplifier is,
3
1
dB L
out out
R C
e e

= = (2)
For a multi-stage (n stages) cascaded amplifier system,
assuming each stage is identical, the overall frequency
response is obtained as,
( ) ( ) ( ) ( ) | |
1 1
1,
1
n
n
V
n
L
A
H H H H
j
e e e e
e e
= = =
+
| |
|
\ .
(3)
978-1-4244-5798-4/10/$26.00 2010 IEEE
Let ( )
1,
1
1 2
n
n V
V
L
A
H A
j
e
e e
= =
+
| |
|
\ .
, one gets the
overall n-staged network bandwidth as,
1 1
3 , 1, 1, 3
2 1 2 1
n n
dB total L dB
e e e

= = (4)
This readily shows that the overall bandwidth of the
multi-stage cascaded amplifiers shrinks monolithically.
Next to consider the ADC bandwidth variation. A typical
structure of an interpolated flash ADC core is shown in
Figure 1 with the interpolation factor of two.
Figure 1 Interpolated flash ADC core structure.
This interpolated flash ADC consists of pre-amplifier
stages and the comparator stage. The number of the
pre-amplifier stages varies depending on the ADC bit
resolutions and its interpolation factors. Normally, higher
resolution results in more stages, while a larger
interpolation factor reduces the stage numbers. Detailed
structure for a practical capacitive interpolated flash
ADC is depicted in Figures 2 and 3. Figure 2 gives
pre-amplifier influences on the whole multi-stage
interpolated flash ADC, which consists of edge
pre-amplifiers and interpolated pre-amplifiers. As
discussed before, the cascaded pre-amplifier network,
used for interpolation, will reduce the overall ADC
bandwidth because of increase of the number of stages.
On the other hand, it is realized that the pre-amplifiers at
different locations have different loading effects of
capacitance and resistance. Obviously, each interpolated
pre-amplifier is loaded by three succeeding pre-amps (in
practical design a sampling capacitor is applied to the
pre-amplifier); while each edge pre-amplifier has a
lighter load coming from two succeeding pre-amplifiers.
Thus, it is easy to understand that the middle
interpolation pre-amplifiers will definitely have larger
time constants and hence narrower bandwidth. Therefore,
considering the two factors together, the interpolation
multi-stage pre-amplifier chain with largest load in the
middle has the slowest signal path and hence determines
the flash ADC sampling speed, as illustrated in Figure 3.
Note that the last stage comparators have little impact on
the ADC speed, because these comparators are normally
dynamic latches, which can compare signals at a very
high speed and are much faster than pre-amplifiers.
Therefore, ADC speed bottleneck is with pre-amplifiers.
Figure 2 ADC interpolation Figure 3 Middle path
has different paths. is the slowest channel.
Figure 4 shows the equivalent loading circuit for an
example interpolated pre-amplifier loaded by three
sampling capacitors and three succeeding pre-amplifiers.
Figure 4 Equivalent loading of an interpolated pre-amp.
R
out
and C
p
are the output resistance and the parasitic
capacitance of the interpolated pre-amplifier respectively,
where C
p
includes parasitic C
dg
, C
ds
, C
dd
, C
db
. C
s
is the
sampling capacitance used in ADC design. C
m
is the
Miller capacitance and C
gs
is the gate-source capacitance
of the succeeding pre-amplifier. All the pre-amplifiers
are identical. The load resistance is obviously R
out
and
the load capacitance is calculated by,
( )
( )
, ,
, ,
3 //
3 // 1
L central p s m gs in
p s V gd in gs in
C C C C C
C C A C C
= + +
( = + + +

(5)
The bandwidth of the interpolated pre-amplifier is
obtained as ( )
-3dB, central ,
1
out L central
R C e = . Apply it into
Equation (4), one can get the overall frequency
bandwidth for the capacitive interpolated flash ADC as,
( ) | |
1
3 ,
,
2 1
3 //
n
dB ADC
out p s m gs in
R C C C C
e

=
+ +
(6)
From Equation (6), it is obvious that that the overall
bandwidth for a capacitive interpolated flash ADC can
be substantially reduced by both the multi-stage
interpolation and the relatively heavier load of the
interpolated pre-amplifiers, which leads to a reduced
ADC sampling rate. The previous analysis provides a
clear illustration on the impacts of capacitive
interpolation on the flash ADC bandwidth, both
qualitatively and quantitatively.
The flash ADC sampling rate analysis is provided as
following. For a single one-pole amplifier, from previous
frequency response analysis, it comes that,
( )
( )
1
t
o V in
v t A v e
t

= (7)
where is the time constant given by
L L
R C t = , A
V
is
the low frequency amplifier gain, R
L
and C
L
are the load
resistance and capacitance of the amplifier, respectively.
It is understood that the time required to amplify input
signals to a certain output magnitude depends strongly
on the difference of the input signals. For an ADC chip,
the worst case is when the difference between the input
and one of the reference is 1/2 LSB, being the minimum
input signal difference, which take a longer time to
determine the outputs of two relative thermometer codes.
On the other hand, for an ADC chip, the output of a
pre-amplifier will be sent to a latched comparator, which
requires the output signal to be large enough in order to
be sensed by the latched comparator for accurate signal
comparison. Thus, the following can be obtained,
1
1 1
1
2 2
t
n
V L n
A LSB e v
t

= A
| |
|
\ .

(8)
where
L
v A is the minimum voltage signal required by a
latched comparator, n is the number of pre-amplifier
stages, ( ) Full Scale 2
n
LSB = , t is the overall
pre-amplifier time constant. ( )
1
1 2
n n
V
A

is the
smallest gain that amplifies the input signal, because
each interpolated signal from the second stage is only
amplified by
1
2
V
A . Therefore, the slowest response
time becomes,
1 1
ln ln
2 2 2
1 1
FS
s n n n
L L
n n
V V
t
v v
A LSB A
t t = =
A A


| | | |
| |
| |
| |
| |
\ . \ .
(9)
In addition, 2 1 2
s s s
t T f = = holds, where t
s
is the
response time of the overall cascaded pre-amplifier
chain, T
s
is the clock period and f
s
is generally defined
as sampling speed for the ADC. Thus, the sampling
rate for a flash ADC is given as,
3
1
=
2
1
ln
2 2
1
FS
dB
s
s
n n
L
n
V
f
f
t
v
A
t

| |
|
|
|
|
\ .
(10)
where f
-3dB
is the overall frequency bandwidth (Hz) of
the cascaded interpolation pre-amplifier chain.
Overall parameter mapping for a flash ADC chip is
discussed below. From previous analysis, the sampling
speed for a flash ADC can be derived as,
1
3 , central
,
2 1
1
ln
2 2
1
FS
n
dB
speed ADC
n n
L
n
V
f
f
v
A
t

=
A

| |
|
|
|
|
\ .
(11)
where f
speed,ADC
is the overall ADC sampling speed, n is
number of stages, f
-3dB,all
is the overall bandwidth of all
the pre-amplifiers and f
-3dB,central
is the bandwidth of the
individual interpolation pre-amplifier block circuit.
Equation (11) depicts that the sampling speed for a
capacitive interpolated flash ADC is quantitatively
related to its internal interpolation pre-amplifier
bandwidth, interpolation factor, resolution bit number
and the number of stages selected. The new quantitative
relation serves to provide a useful design guideline for
IC designers to rapidly and accurately design capacitive
interpolated flash ADC for proper design trade-offs and
whole-chip ADC performance optimization.
3. Design Verification
A 4-bit interpolation flash ADC designed a foundry
0.13m CMOS is used to validate the new ADC design
matrix technique. The individual interpolation
pre-amplifier bandwidth is derived as given in Figure 5.
Figure 5 Pre-amplifier bandwidth in 0.13m CMOS.
The bandwidth is about 1.4GHz for a stage number of 4.
Apply it to Equation (11), overall ADC speed becomes,
1
4
,
2 1 1.4
1.22
1
ln
2 2
1
FS
speed ADC
n n
L
n
V
f GSps
v
A
t
= =
A

| |
|
|
|
|
\ .
(12)
Hence, theoretical peak speed is 1.22Gsps for this 4-bit
ADC, which matches reasonably well with the actually
designed maximum sampling rate of 1Gsps using our
new ADC design method, as shown in Figure 6. The new
design matrix technique was also validated by designing
another 4-bit interpolated flash ADC in a 90nm CMOS,
for which the theoretically calculated peak speed is
2.8Gsps in comparison with a maximum sampling rate
of about 2.3Gsps using our design technique. These two
practical ADC design examples serve to verify our new
ADC design matrix technique, which would enable
designers to rapidly design and optimize a flash ADC
with different levels of factors considered to achieve
overall ADC performance optimization in practices.
Figure 6 4bits 1Gsps flash ADC simulation design.
4. Conclusion
This paper provides a practical design matrix analysis
technique for designing interpolated flash ADCs, which
includes quantitative analysis of influences of process,
device, circuit and structural parameters on whole-chip
ADC performance. The quantitative mapping between
ADC performance specs and design parameters, such as,
interpolation factor, number of stages, pre-amplifier
bandwidth, loading effects, transistor size, technology
parameters, etc., will enable IC designers to conduct
quick and rational flash ADC design with optimal design
balance and chip performance. The design technique was
validated by two 4-bit flash ADCs in commercial
0.13m and 90nm CMOS technologies.
References
[1] M. Gustavsson, J. Jacob Wikner and N. Tan, CMOS
Data Converters for Communications, Kluwer
Academic Publishers, 2000.
[2] D. Hoeschele, Analog-to-Digital and
Digital-to-Analog Techniques, Wiley & Sons, 1994.
[3] A. Ismail and M. Elmasry, Analysis of the flash
ADC bandwidth-accuracy trade-off in
deep-submicron CMOS technologies, IEEE Trans.
Circuit and Systems-II, pp. 1001-1005, 2008.
[4] J. Vandenbussche, et al., Systematic design of a 200
MS/s 8-bit interpolating A/D converter, Proc. IEEE
DATE, pp. 357-361, 2002.