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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010

A Fully-Integrated 77-GHz FMCW Radar Transceiver

in 65-nm CMOS Technology
Jri Lee, Member, IEEE, Yi-An Li, Meng-Hsiung Hung, and Shih-Jou Huang

AbstractA fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed. Utilizing
synthesizer as the FMCW generator, the transa fractionalmitter linearly modulates the carrier frequency across a range
of 700 MHz. The receiver together with an external baseband
processor detects the distance and relative speed by conducting
an FFT-based algorithm. Millimeter-wave PA and LNA are
incorporated on chip, providing sufficient gain, bandwidth, and
sensitivity. Fabricated in 65-nm CMOS technology, this prototype
provides a maximum detectable distance of 106 meters for a
mid-size car while consuming 243 mW from a 1.2-V supply.
Index Terms77 GHz, fast Fourier transform (FFT), fracsynthesizer, frequency modulated continuous-wave
tional(FMCW) radar, low-noise amplifier (LNA), power amplifier (PA).

I. INTRODUCTION

HE emerging automotive radar systems have been developed over the past years to create a more secure and more
comfortable driving environment. Up to now, quite a few standards have been established for different applications (Fig. 1).
m) radars are adopted to proFor example, short-range (
vide parking assistance or to prevent side-crash, which utilizes
pulse-based modulation with a wide bandwidth of 7 GHz. Because of the short distance, it must provide a wide azimuth
and a fine resolution (
cm) [1]. Used in the
angle
Stop-and-Go system,1 the mid-range radars usually operate at
24-GHz band to cover a distance of 1040 m with an angle of
30 60 [2], [3]. The 77-GHz band, on the other hand, has been
dedicated to long-range radars, e.g., the adaptive cruise control
(ACC) system, which basically detects the distance and the relative speed of the vehicles in front so as to perform a real-time response by means of the braking system or other protective mechanism. It must cover a range up to 100150 meters [4]. At the
speed of 110 km/h, saving one second response time is equivalent to extending over 30 meters for braking. With proper operation, such an anti-collision system can reduce a great amount
of casualties in traffic accident.
The 77-GHz radar presents significant advantages over
microwave (e.g., 24-GHz) radars. The more compact size
Manuscript received April 06, 2010; revised June 29, 2010; accepted August
12, 2010. Date of publication October 28, 2010; date of current version December 03, 2010. This paper was approved by Guest Editor Ranjit Gharpurey.
The authors are with the Electrical Engineering Department, National Taiwan
University, Taipei, Taiwan (e-mail: jrilee@cc.ee.ntu.edu.tw).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2010.2075250
1A cruise control system that could maintain a safe driving distance from the
vehicle ahead while in heavy traffic.

(especially in antenna design) makes it suitable for further

integration. The associated narrow-beamwidth requirement
fits in with long-distance applications. For example, high-gain
narrow-beamwidth antennas such as horn or dish can be used.
Also, as compared with the laser radar, which is subject to
disturbance by rain or mist, millimeter wave reveals better
environmental resistance. However, even with modern technology, 77-GHz radar systems are still very expensive and can
only be applied to luxury cars. It is because in conventional
approaches, engineers need to collect individual mm-wave
circuits and put them together as a module, rather than realizing a fully-integrated circuit in one chip. It inevitably suffers
from high cost and low yield. Today, the trend to popularize
this high-end technique puts more pressure on cost reduction.
Research on 77-GHz automotive radars has been extensively
conducted over the past years. For example, [5] and [6] provide single-chip transceivers and transceiver arrays in SiGe
BiCMOS technology, respectively, and 77-GHz transceivers are
also demonstrated in CMOS [7], [8]. Even so, highly-integrated
77-GHz radar transceivers have never been realized in CMOS
before. Unlike compound technologies, CMOS manifests itself
in its low cost, high yield, and potential of highly integration,
and it is of course desirable to implement long range radar
transceivers in CMOS. In this paper, we propose a solution
that integrates the whole transceiver in single chip, which
along with antennas and baseband processor forms a complete
system. It substantially reduces the cost and increases the
reliability. Note that [9] only accomplishes the transmit part
. Whole-system
assembly requires much more effort than building up blocks.
Before looking at design details, we need to evaluate the challenges of realizing such a high-frequency system. It is wellknown that the returned power loss of a radar system is given
by

(1)
denote the transmitted and received power,
where
the gain of antennas, the radar cross section, the wavelength, and the distance [10]. At 77 GHz, the reflected wave
would be attenuated by approximately 150 dB at a distance of
100 meters. Here, the radar cross section is defined as
(2)
where
denotes the incident power density measured at the
the scattered power density seen at a distance
target, and

0018-9200/$26.00 2010 IEEE

LEE et al.: A FULLY-INTEGRATED 77-GHz FMCW RADAR TRANSCEIVER IN 65-nm CMOS TECHNOLOGY

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Fig. 1. Classification of automotive radar systems.

away from the target. For a mid-size automotive,

m [11]. In the receive side, the lowest detectable power level
can be expressed as [10]
(3)
denotes the overall receiver noise figure and
the fast Fourier transform (FFT) resolution bandwidth. Here we assume the intermediate frequency (IF) of the
FMCW radar is calculated by doing FFT. In radar systems, a
detectable signal needs to present a signal-to-noise ratio (SNR)
higher than 16 dB [10]. Considering 1-kHz FFT bandwidth,
, obtained
and approximately 28-dB total noise figure (
from simulation), we can calculate the minimum detectable
dBm. Compared with standard
power level as around
2.4-GHz transceivers (e.g., Bluetooth [12], which have RF
dBm), the receiver here must deal with
input sensitivity of
even weaker signals. Meanwhile, to reach a longer distance, it
as much as possible, which in
is desirable to suppress
turn requires a high-gain low-noise amplifier (LNA).
To estimate the minimum required output power in the
, we have
transmit side
where

(4)
represents the receiver (Rx) sensitivity,
the
where
antenna gain. Suppose each antenna contributes 20-dBi gain, we
obtain that the power amplifier (PA) in the transmitter (Tx) must
deliver at least 10 dBm of power for a 100-m ranging distance. In
other words, high output power PA and high-gain antennas are
essential. The 20-dBi antenna gain can be achieved by some specific structures. So far, horn and dish antennas still prove to be
the most suitable structures because they concentrate radiation
energy efficiently. As will be discussed in Section VI, planar antennas such as patch arrays may achieve similar performance as
well. The interconnection between chip and antenna is another
issue, since the signal at 77 GHz can get attenuated significantly
by travelling through only a small piece of wire. In our prototype, the lengths of the bonding wires are minimized to about
250300 m.
In advanced CMOS technologies, the millimeter-wave (mmwave) PA and LNA designs become applicable. However, the

Fig. 2. Performance analysis of CMOS mm-wave circuits: (a) P

power gain and (c) noise figure of LNAs.

of PAs, (b)

design margins are still quite small. To be more specific, we

can analyze the performance of state-of-the-art PAs and LNAs,
, for PAs) and
and predict their output saturation power (
power gain (for LNAs) at 77 GHz by regression. As illustrated
in Fig. 2(a) and (b), they are approximately 7.5 dBm and 11 dB.
of at
For the radar to function properly, we need a PA with
-dB gain and
-dB NF.
least 10 dBm and an LNA with
Thus, it is necessary to adopt modern mm-wave circuit designs
so as to achieve the required performance. Block optimization
and integration technique are equally important. Similarly, the
noise figure of LNAs must be kept below 10 dB as the intersection point is about 7.5 dB [Fig. 2(c)]. Note that the down-conversion mixer and IF amplifier contribute significant noise figure as
well.
In architecture level, conventional structures tend to use an
integer- phase-locked loop (PLL) with a programmable direct digital frequency synthesizer (DDFS) as the reference input
[27]. The frequency modulation is accomplished by changing
. This approach, however, suffers from
the input reference
severe power and area penalties, primarily because the DDFS
may need high-resolution digital-to-analog converters (DACs)
and large read-only memory (ROM) tables to achieve fine frequency tuning. The linearity of modulated frequency is determined by that of the DDFS, which may undergo inaccuracy
of frequency chirping. In our design, we remove the DDFS
entirely and incorporate a fractional- PLL instead. The frequency modulation is therefore achieved by changing the divide modulus. We integrate the FMCW generator and the radio
frequency (RF) front-end in one chip, and have it co-designed
with the interconnection to antennas. Together with signal processor realized in a field programmable gate array (FPGA), the
FMCW radar system is capable of detecting multiple objects
and exhibiting their positions and speeds in real time.
This paper is organized as follows. Section II briefly describes
the FMCW radar theory. Section III presents the transceiver
architecture, revealing system level considerations. Section IV

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Fig. 3. FMCW radar operation for (a) general case, (b) longest distance, (c) highest speed.

Fig. 4. (a) FMCW radar system architecture, (b) triangular frequency modulation, (c) loop bandwidth selection.

discusses building block designs, and a complete testing result is

summarized in Section V. Consideration for future work is discussed in Section VI. Finally, Section VII concludes this work.
II. FMCW RADAR
An FMCW radar transmits a continuous wave, which is triangularly modulated in frequency, and receives the wave reflected
from objects. As can be illustrated in Fig. 3(a), for a moving
target, the received frequency would be shifted (i.e., Doppler
and
shift), resulting in two different offset frequencies
for the falling and rising ramps. Denoting the modulation range
and period as and , respectively, we can derive the distance
and the relative velocity
as

(5)
(6)

where represents the center frequency and the speed of light.

In this design, we have
MHz, and
msec,
of approximately
leading to a ranging resolution
and
are obtained by counting
21.4 cm. Here, we assume
period. Since
their cycles, which must be integers in each
the detectable offset frequencies need to be counted at least once
(and
) is
in each ramp, we conclude that the minimum
. By the same token, the lowest difference beequal to
is equal to
tween the two offset frequencies
kHz. It translates to a speed resolution of
, which
is equal to 4.7 km/h. For automotive application, these resolutions are sufficient in most cases.
It is also interesting to look into the maximum ranging limits
of such an FMCW radar. For a stationary object standing very
far away from the detector, the two sawtooth waveforms become
apart from each other. This extreme case is shown in Fig. 3(b),
. Such a condition corresponds to a diswhere
tance of
km, given that the very unstable
and
(only appear for a very short period of time) can
be obtained. Similarly, the maximum detectable speed can be
calculated as illustrated in Fig. 3(c). Here, one of the offset frequencies drops to zero under this circumstance. The maximum
, which is
detectable speed is therefore given by
m, the highest detectable
a function of distance . For
speed is about 2182 km/h. Since we are looking at distance and
speed 23 orders less than the extreme cases, the FMCW operation here is quite robust.
III. TRANSCEIVER ARCHITECTURE
The transceiver architecture is illustrated in Fig. 4(a). It contains an RF front-end (PA, LNA, and mixer), two high-gain antennas, an FMCW generator (basically a fractional- synthesizer), and an FPGA-based signal processor. By tuning the divide modulus, the full-rate VCO delivers FMCW carrier signal
around 77 GHz directly to the PA, the mixer, and the first divider. One important advantage of this structure is that it requires no frequency doublers or triplers, simplifying the circuit
design by eliminating lots of mm-wave blocks. The reference
is set to about 700 MHz, created by an external
clock

LEE et al.: A FULLY-INTEGRATED 77-GHz FMCW RADAR TRANSCEIVER IN 65-nm CMOS TECHNOLOGY

PLL with a crystal oscillator (50 MHz) for simple implementation. If necessary, this low-speed PLL can be further integrated
into the transceiver. A 16-bit - modulator produces a 3-bit
modulation signal for the
divider, which follows the
2nd divider. Note that the power consumption of this architecture is at least 2 orders less than that of the DDFS version. The
full-rate clock is amplified by the PA and coupled to the antenna
directly.
In the receiver path, another antenna captures the reflected
signal. After the LNA and mixer, we obtain the IF signal and
have it digitized by means of an external analog-to-digital converter (ADC) before sending it to the digital signal processor
(DSP). The ADC provides 12-bit output with sampling rate of
3 MSample/s. Again, if necessary, it can be easily included in
the main chip. Since the IF is quite low, the ADC power consumption can be kept less than 1 mW [28]. An FFT algorithm is
implemented in the FPGA to calculate the distance and speed,
which can track up to 5 objects simultaneously. In order to
achieve the best frequency resolution, the FFT sampling time
to fully utilize the information for
should be as large as
and
interval. However,
IF frequency estimation at each
since the number of FFT points are usually a power of 2, the
FFT sampling time here may be slightly smaller than
if the sample rate is pre-selected. In this design, we choose a
2048-point FFT with 3-MSample/s sampling rate, leading to an
FFT sampling time as

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Fig. 5. (a) VCO and its tuning range, (b) 1st frequency divider stage.

(7)
Equation (7) corresponds to 1.46-kHz frequency resolution.
It is also important to look at the modulation mechanism. As
shown in Fig. 4(b), the ramp is composed of 8192 steps with
. Note that
stepping rate of about 10.9 MHz
output, which
the stepping is accomplished by using the
facilitates the synchronization between DSP (in FPGA) and the
modulation logics (on chip). The - resolution is thus given
by

Fig. 6. 38.5-GHz frequency divider.

IV. BUILDING BLOCKS

In this section, we introduce circuit details of building blocks
and their design considerations.
A. VCO and Frequency Dividers

(8)
In other words, each step corresponds to 2 LSBs. The loop bandwidth of the frequency synthesizer is of great concern as well. In
order to achieve a linear triangular profile with steep turn-around
points, the bandwidth must be much greater than the modulation
frequency, which is 0.67 kHz, and less than the stepping rate,
which is 10.9 MHz [Fig. 4(c)]. In this design, the loop bandwidth is set to be 1 MHz as an optimal value.
Other issues may affect the transceiver performance and need
and
to be considered carefully. For example, to extract
correctly, the logics on the board and the chip must be synchronized by the same reset and clock signals. Adaptability is imporhad better be made
tant as well. Parameters such as and
programmable to meet different standards.

Fig. 5(a) depicts the 77-GHz VCO design. It is implemented

as a standard
tank structure with thick-oxide (5.6-nm) varactors to suppress the leakage. Simulation suggests a tuning range
of about 1 GHz. To drive a large loading of 66 fF for the divider,
the PA, and the mixer at 77 GHz, we employ a pseudo-differenas a buffer. It is also possible
tial tuned amplifier pair
to incorporate a cascode structure to further isolate the VCO.
However, in such a low-supply design, the buffers output swing
would be somewhat degraded, if another deck of devices were
added. The parasitic capacitance introduced at internal nodes
would cause significant loss as well.
The first divider stage is realized as a direct injection-locked
topology [Fig. 5(b)], where the injection signal is ac-coupled to
. The bias voltage
affects the lock
the gate of the switch
range significantly. Higher
produces a larger lock range by
degrading the tank , which in turn decreases the output swing.
As can be clearly shown in Fig. 5(b), with input swing of 800
V, where the equivalent
mV , the divider fails for

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010

Fig. 7. (a) Prescaler design, (b)

42=3 cell, (c) CML-to-CMOS converter.

tank loss exceeds

. Here, we choose
V to
arrive at a lock range of 4 GHz with sufficient design margin.
Note that injection-locked dividers present much less kickback
than their static counterparts.
The second divider is implemented as a static topology with
current-mode logic (CML) structure, class-AB biasing, and inductive peaking (Fig. 6) [29]. Simulation shows that for input
dBm, single-endedly), the lock range
swing of 260 mV (
is approximately equal to 26 GHz. The peaking inductors only
give a mild bandwidth boost and contribute negligible influence
prescaler is illuson the static dividers behavior. The
trated in Fig. 7(a), which follows the design in [30]. Four
cells are placed in cascade. This structure provides a simple yet
robust operation. With the 4th control bit set to 1, the division
.
range is given by
Different types of latches2 are employed to minimize its power
consumption while achieving high speed. Here, we map the
so as to tune the
3-bit - output to the control bits
divide modulus from 24 to 31 (the average divide ratio is about
cell in Fig. 7(b).
27.5). For completeness, we plot the
Once again, class-AB biasing technique [29] is applied to the
first cell to help driving large loading at higher speed (19.25
GHz). A differential CML-to-CMOS converter is required between the 2nd and the 3rd cells, which is illustrated in Fig. 7(c).
Note that we take advantage of the available differential clocks
to relax the heavy loading. That is, both of the pseudo-differenand
in the 3rd cell are used to drive two latches
tial inputs
for each. In 65-nm CMOS technology, the converter presents a
-dB bandwidth of 10.5 GHz while consuming only 2.2 mW
of power.
B. LNA and PA
The LNA is realized as three identical gain stages [Fig. 8(a)].
Here, each stage contains a cascode structure, and conjugate
matching networks are placed between stages. The on-chip
2CML

and true-single-phase clock (TSPC).

Fig. 8. (a) Low-noise amplifier, (b) improvement of double-shield ground.

transmission line design is not trivial at such a high frequency.

For example, coppers skin depth is equal to 0.25 m at 77
GHz, whereas the thickness of M1 in 65-nm CMOS is only
0.18 m. To prevent significant leakage to the substrate, we
put two layers of metal as the ground plane. Here, M1 and
M2 are shunt through vias to form a thicker ground plane
with no penetrating slot [31]. As demonstrated in Fig. 8(b),
the LNA gain and noise figure are improved by at least 2 to
and
4 dB by using this double-layered ground. Also,
are laid out with shared junction [32] to minimize the parasitic
capacitance of the internal node. The layout for
and
is
illustrated in Fig. 8(a) as well. Note that if source degeneration
were used, the gain would be degraded by 23 dB. Since the
receivers noise figure is primarily determined by the mixer and
IF amplifier, it is good to keep the LNA in high gain region.
The PA design is depicted in Fig. 9(a). It is a 5-stage structure
in cascade with conjugate matching in between. Each stage is
made of a single-stage class-A amplifier. Here, to improve stability, it is desirable to add local bypass, e.g., a capacitor, to the
supply. However, this bypass capacitor can never be large (usually 12 pF) since it has to accommodate limited space between
stages. As a result, the bypass impedance raises up to a higher

LEE et al.: A FULLY-INTEGRATED 77-GHz FMCW RADAR TRANSCEIVER IN 65-nm CMOS TECHNOLOGY

Fig. 9. (a) Power amplifier, (b) impedance jZ j and Q of bypass network as a

function of frequency with parasitics considered.

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Fig. 10. (a) Mixer, (b) IF amplifier, (c) 16-bit 6-1 modulator.

value at low frequencies, possibly introducing more noise coupling or even oscillation.
To reduce the impedance and quality factor at low frequenbranch [33]. The
cies, we can introduce an additional
overall impedance seen looking into the - - network
is now given by

(9)
pF,
pF, and
,
In our design,
arriving at a zero at 1.6 GHz and two poles at dc and 8.2 GHz,
respectively. Similarly, the equivalent of this bypass network
is defined as

(10)
which must be low enough for any frequency. However, (9) and
(10) are over simplified as they contain no parasitics. Fig. 9(b)
reveals the simulated results with parasitic inductance and resistance taken into account. Note that we can not use - solely,
otherwise the PAs gain will be degraded significantly (owing to
). Simulation suggests that this PA presents a gain higher than
13 dB. The degeneration transmission lines are used here to improve stability and wideband matching.
C. Mixer, IF Amplifier, and -

Modulator

The mixer design is shown in Fig. 10(a). In order to conform

and
to the 1.2-V supply and ensure abrupt switching on
, we separate the gain and switching stages [34], i.e., a tuned
amplifier couples its output to the common-source node of the
- . A single-balanced structure is used to
switching pair
reduce the LO port loading. Since IF is less than LO frequency
by approximately 5 orders of magnitude, the LO feedthrough
can easily be eliminated. Note that if a double-balanced mixer
were used, the LO port would present capacitive loading twice
as large to the VCO and its buffer. Most RF current flows into

Fig. 11. (a) Die photograph, (b) testing setup.

rather than the tail current , since

the switching pair
the latter presents an output impedance much greater than the
impedance seen upwards. Parasitic capacitance associated with
node is absorbed as part of the matching network. The mixer
gain is estimated to be 5 dB.
The down-converted IF signal needs to be enlarged to at least
5 mV before it can be processed by the ADC. The IF amplifier
is composed of 3 differential pairs and an offset compensation
unit loaded to the first stage, which could neutralize any possible
offset up to 300 mV [Fig. 10(b)]. Although the offset cancellation in this prototype is designed for manual tuning,3 it could be
easily modified as an automatic calibration scheme [35], [36].
The IF amplifier is capable of providing 16-dB gain.
The 16-bit - modulator is illustrated in Fig. 10(c).
Adopting standard MASH 1-1-1 structure [37], this modulator
is inherently stable. All the blocks are operated in pure digital
(averagely equal to
) is promode. The 3-bit output
duced by the -times carry overflow of the first accumulator
cycles. Note that the carries of the second and the
in every
third accumulators do not affect the output average value due
. Integrated with modulation
to the differentiators
control logics, the adders, delay cells, and other digital blocks
are synthesized by Design Compiler and are placed-and-routed
3In real measurement, the observed offset is very small and we do not need
to tune it out manually.

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Fig. 12. Spectra of 77-GHz synthesizer: (a) integer- , (b) fractional- operation. (c) Phase noise plots under integer- operation, (d) spread spectrum
under frequency modulation.

Fig. 13. FMCW modulation profile and accuracy.

by Astro [38]. Guard rings made of n-well and p diffusion

layer are placed around the - modulator to isolate the
created digital noise.
V. EXPERIMENTAL RESULTS
The transceiver chip has been fabricated in 65-nm CMOS
technology. Fig. 11(a) shows the die photo, which measures
0.95 1.1 mm . The circuit (FPGA not included) consumes a
total power of 243 mW, of which 73 mW dissipates in the frequency synthesizer, 115 mW in PA, 30 mW in LNA, and 25
mW in the mixer and buffers. The testing setup is also shown
in Fig. 11(b). An external PLL (CDCE62002) [39] provides the
700 MHz reference clock, and an ADC (ADS7882) [39] digitizes the IF signal. Both of them can be further merged into the
transceiver in future design. A low-cost FPGA evaluation board
(Altera DE0 Board) [40] has been used for FFT calculation. The
radar transceiver as well as individual building blocks are tested
on a probe station. A fully-assembled module has also been implemented, whose link budget is degraded by about 12 dB due
to bonding wire loss and mismatch loss especially at transmitter
output. We here summarize the measurement results obtained
from probing as follows.
Fig. 12(a) and (b) reveal the output spectra of the 77-GHz
synthesizer under integer- and fractional- operation, suggesting phase noise of
and
dBc/Hz at 1-MHz
dBc and the
offset, respectively. The reference spurs are
dBc. Note that these spikes have little infractional spurs
fluence on the radar performance, because the fractional spurs
vary all the time due to the modulated carrier frequency. In other
words, after averaging no stationary spur can be created to cause
false alarm. Phase noise plots are also depicted in Fig. 12(c).
Here, the phase noise of the full-rate clock is not directly available due to our limited equipment [29]. We instead plot the
phase noise of the divided-by-4 output along with that of the
700-MHz reference. The 19-GHz output reveals phase noise of
dBc/Hz at 1-MHz offset, demonstrating that the first two

Fig. 14. LNA measurement: (a) S-parameters, (b) noise figure.

Fig. 15. PA measurement: (a) S-parameters, (b) large signal performance.

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Fig. 16. (a) IF spectrum while detecting an object 102-m away, (b) link budget.

TABLE I
PERFORMANCE SUMMARY

divider stages contribute negligible noise. It also follows the reference profile tightly until 100 kHz offset. The integrated jitter
from 100 Hz to 1 GHz is equal to 293 fs. The output spectrum under modulation is shown in Fig. 12(d), which presents a
spreading range of 700 MHz.
By using a standalone synthesizer, we can even record the triangular frequency profile as shown in Fig. 13. The root-meansquare (rms) frequency error including the turn-around points
is less than 300 kHz, which is superior to that of conventional
DDFS-based transceivers by at least 1 order [27]. Note that
the standalone synthesizer provides slightly lower modulation
range , which is approximately 500 MHz.
To verify the performance of each block, we have also tested
the LNA and PA individually. Here, both small- and large-signal
measurements are conducted. The LNA achieves 17.5-dB gain,
-dBm
, and
-dBm
at 77 GHz.
7.4-dB NF,
Fig. 14 depicts the LNA S-parameter and NF around the band

of interest. The PA reveals a peak gain of 13.7 dB, with a -dB

bandwidth of 21.5 GHz,
of 6.7 dBm,
of 10.5 dBm
and maximum PAE of 8.4% (Fig. 15).
Fig. 16(a) shows the IF spectrum while detecting an object
about 0.4 0.6 m at 102 meters away. We can see an IF line of
dBm at about 635 kHz. Note that the undesired spur caused
by stepping does not appear, since we choose a low IF and a
high modulating resolution. It serves as another advantage as
compared with other FMCW designs [27]. The link budget is illustrated in Fig. 16(b). For a mid-size car, the longest detectable
distance is about 110 meters, which matches our measurement
dBm,
closely. Furthermore, the noise floor at the IF is about
which implies that the total NF of the receiver is about 30 dB.
We have also verified the accuracy of this radar system, and
shown in Fig. 17(a) and (b) are the results for distance and
speed. A picture of this out-door measurement is also shown
in Fig. 17(c). A mid-size car with cross-section area of 30 m

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Fig. 19. Photos of the 77-GHz radar system with integrated transceiver (chip)
and on-board antennas.
Fig. 17. Accuracy for (a) distance, (b) velocity measurements, (c) picture of
measurement setup.

Fig. 18. (a) 8 8 patch array antenna, (b) its gain and bandwidth, (c) radiation
pattern E- and H-planes.

serves as a target, and accurate speed meters as well as longrange measuring tapes are used. The maximum detectable is
106 meters. Note that the rms error is less than the resolution in
both cases here, demonstrating the accuracy of this work. Table I
summarizes the overall performance, and compares this work
with some other FMCW radar transceivers and front-ends previously published. Other 77-GHz circuits such as [42] and [43]
can also be found in the literature.
VI. FUTURE WORK
The antenna is of great importance in a radar system and is
worthy of further modification. As discussed in Section I, in
order to reach a long distance, we need high-gain antennas such
as horn or dish to concentrate the radiation energy. In such cases,
signal at 77 GHz must be transformed from coplanar waveguide to rectangular waveguide mode, and vice versa. All of the

mm-wave components (antennas, adaptors, etc) are very costly

because they require delicate manufacture techniques and precise mechanical placement.
A low-cost solution may be found if we use a patch antenna
array. It is well known that a large antenna array could get a
high gain by focusing the radiation energy. As demonstrated
in Fig. 18, we design an 8 8 patch array on a commercially-available PC board, RO4003C [41], which occupies an
.
area of approximately 2.3 2.5 cm on a board with
Tree-structure corporate feeding paths guarantee that the overall
radiation is constructive. Using 8 8 elements, we can achieve
-dBi gain and
-GHz bandwidth [Fig. 18(b)], quite
close to the requirement of automotive FMCW radar systems.
The radiation patterns for E- and H-planes are also shown in
Fig. 18(c), revealing beamwidth of 10 and 9 , respectively. A
radar module incorporates 8 8 patch antenna arrays has been
demonstrated in Fig. 19, which achieves a ranging distance of
at least 40 meters in preliminary test. It is absolutely possible
to extend this distance to over 100 meters by modifying the RF
front-ends as well as the DSP baseband.
VII. CONCLUSION
A fully-integrated 77-GHz FMCW radar transceiver has been
proposed in this paper. Utilizing fractional- synthesizer as an
FMCW engine, we substantially reduce the complexity of the
circuit and board designs. Significant power and area can be
saved by this architecture, leading to a low-cost solution. Millimeter-wave front-end realized in CMOS technology has been
demonstrated as well. With baseband processors and high-gain
antennas included, this work provides a complete realization example, which reveals promising potential for future automotive
applications.
ACKNOWLEDGMENT
The authors thank the TSMC University Shuttle Program for
chip fabrication.

LEE et al.: A FULLY-INTEGRATED 77-GHz FMCW RADAR TRANSCEIVER IN 65-nm CMOS TECHNOLOGY

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+14 5

+6

Jri Lee (S03M04) received the B.Sc. degree in

electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, in 1995, and the M.S. and
Ph.D. degrees in electrical engineering from the University of California, Los Angeles (UCLA), both in
2003.
After two years of military service (19951997),
he was with Academia Sinica, Taipei, Taiwan from
1997 to 1998, and subsequently Intel Corporation
from 2000 to 2002. He joined National Taiwan
University (NTU) since 2004, where he is currently
an Associate Professor of electrical engineering. His current research interests
include high-speed wireless and wireline transceivers, phase-locked loops, and
data converters.
Prof. Lee received the Beatrice Winner Award for Editorial Excellence at the
2007 ISSCC, the Takuo Sugano Award for Outstanding Far-East Paper at the
2008 ISSCC, the best technical paper award from Y. Z. Hsu memorial foundation in 2008, the T. Y. Wu memorial award from national science council
(NSC), Taiwan in 2008, the Young Scientist Research Award from Academia
Sinica in 2009, and the Outstanding Young Electrical Engineer award in 2009.
He has also received NTU outstanding teaching award in 2007, 2008, and 2009.
He has served as a Guest Editor of the IEEE Journal of Solid-State Circuits in
2008 and a tutorial Lecturer at the 2009 ISSCC. He is now serving in the Technical Program Committees of the International Solid-State Circuits Conference
(ISSCC), Symposium on VLSI Circuits, and Asian Solid-State Circuits Conference (A-SSCC).

2756

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010

Yi-An Li was born in Taichung, Taiwan, in 1986. He

received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei,
Taiwan, in 2008 and 2010, respectively.
His research interests include phase-locked loops
and frequency synthesizers.

Meng-Hsiung Hung was born in Tainan, Taiwan,

in 1986. He received the B.S. degree in electrical
engineering from National Tsing-Hua University,
Hsinchu, Taiwan, in 2008, and the M.S. degree
in electrical engineering from National Taiwan
University, Taipei, Taiwan, in 2010.
His research interests focus on millimeter-wave
front-end circuits including antenna.

Shih-Jou Huang was born in Tainan, Taiwan, in

1986. He received the B.S. degree in electrical
engineering from National Tsing-Hua University,
Hsinchu, Taiwan, in 2008. He is currently working
toward the Ph.D. degree at National Taiwan University.
His research interests focus on millimeter-wave
wireless transceivers.