1

Fault Resistance, Location and Inception Angle

Effects on DC Offset of the Fault Currents
F. B. Costa, B. A. Souza, N. S. D. Brito, W. C. Santos
AbstractShort circuits in ac power systems produce fault
currents usually composed by a fundamental power-frequency
component of constant value, an exponentially decaying dc
component (dc offset), some harmonic components and fault-
induced noises according to the fault inception angle, resistance
and location. Protective relays require an accurate representation
of the primary fault current in the secondary one of the current
transformers. However, secondary fault currents usually present
distortion due to current transformer saturation. dc offset has
far more inuence on current transformer saturation than the
magnitude of the ac fault current and remanent ux in the
transformer core. In this framework, dc offset is the main cause
of disfunction in the protection relay. This paper investigates the
effects of fault inception angle, resistance and location on dc
offset of fault currents.
Index TermsDecaying dc current, power system protection,
transmission lines.
I. INTRODUCTION
S
Udden short circuits in ac power systems produce fault
currents which can have a substantial proportion of unidi-
rectional current (dc offset) depending on the fault inception
angle, resistance and location [1]. It is well known that line
relays can overreach in the presence of dc offset in fault
current waveforms. For line relaying purpose, the decaying
dc components must be removed from these waveforms. In
addition, dc offset may produce saturation in the current
transforms (CTs) of the protective relays sensing the faults.
Power system protection typically utilizes distance relays
to protect transmission lines. The lters of these relays must
decompose the signals in order to estimate the fundamental
frequency components as quickly and accurately as possible
for fault detection and location purpose. Conventional Discrete
Fourier Transform (DFT) is the most widely used lter algo-
rithm well suitable for estimating the accurate fundamental
phasors in measurements which only contain fundamental fre-
quency and integer harmonic frequency components. However,
fault currents usually contain decaying dc components which
are composed by noninteger harmonic components. In this
way, conventional DFT algorithms do not have the ability to
lter out dc offset [2].
In order to overcome the above problems, many methods
have been proposed to remove dc offset in faulted signals. [3]
has proposed a digital mimic ltering technique to remove dc
offset. [4], [5] have proposed a new DFT-based algorithm to
complectly remove the decaying dc components. A DFT-based
adaptive mimic phasor estimator to remove dc offset has also
This work was supported by Brazilian National Research Council (CNPq).
The authors are with Department of Electrical Engineering at Federal
University of Campina Grande, 882 Aprgio Veloso Av, Bodocong o, Camp-
ina Grande - PB, CEP:58.109-970, Brazil. E-mail: {abc, benemar, nu-
bia}@ee.ufcg.edu.br.
been proposed [6]. Recently, the wavelet transform (WT) has
been used to predict and remove dc offset in fault currents [7].
With regard to the CT saturation, the application of protec-
tive relays to the power system require an accurate representa-
tion of the primary fault currents in the secondary one of the
CT. However, the secondary fault currents can be signicantly
distorted. The dc offset has far more inuence on CT saturation
than the magnitude of the ac fault current [8].
Several methods for compensating the distortion in the
secondary fault currents have been presented. [1] has proposed
an analog circuit to be connected to the secondary circuit of the
CT and to use it to generate a dc offset equal and opposite to
that seen in the primary current. [9], [10], [11] have proposed
digital algorithms for compensating the secondary current.
Articial Neural Network (ANN)-based approach [12] and
WT-based method [13] for correcting the distorted secondary
current have also been reported.
As aforementioned, dc offset in fault currents is the main
cause of disfunction of protective relay. Several papers have
presented techniques for compensating or extinguishing this
component. It is important to investigate the nature and effects
of dc offset according to fault and system parameters. The
purpose of this paper is to provide complete information re-
garding dc offset according to fault inception angle, resistance
and location.
II. FAULT CURRENT COMPONENTS
Fig. 1 depicts a part of a normalized fault current of an ac-
tual transmission-line fault. Current waveform characteristics
before, during, and after a fault may be signicantly different.
In this way, the current waveforms related to a fault should be
divided into three intervals: pre-fault time, fault clearing time,
and post-fault time.
Fig. 1. Actual fault current of a single-phase fault.
2
A. Pre-fault Time
Pre-fault time corresponds to steady-state operation of the
power system and the currents in this interval are usually
composed by a power-frequency component of constant value,
some harmonic components and noises.
B. Fault Clearing Time
Fault current waveforms at fault clearing time contain two
types of components, viz. alternating (ac) and unidirectional
(dc) quantities [1]. Fault currents in most transmission and
distribution networks may be adequately represented by a
power-frequency component of constant value, an exponen-
tially decaying dc component and fault-induced noises [1],
[14]. This decaying dc component will be kindly dealt with
in this paper.
C. Post-fault Time
Post-fault time contains the current values after fault clear-
ance. It is well known that CT saturates due to the primary
fault current. In this way, the secondary fault current may not
have its current zero at the same time as the primary fault
current. Therefore, when the primary current is interrupted by
a circuit breaker at current zero, the secondary fault current
may be a nonzero value, resulting in a decaying dc current
similar to that shown in Fig. 1 [15]. This dc offset will decay as
a function of the time constant of the transformers secondary
circuit.
The actual fault currents after fault clearance are usually
composed by a dc offset (long decaying dc time constant
and low magnitude) and high frequency noises due to the
transducer errors.
III. FAULT PARAMETER EFFECTS
In order to identify some fault parameter effects, the sim-
plied single-phase short transmission line model depicted in
Fig. 2 was used. A short transmission line can be modelled as
a serie resistance and inductance (R + jwL) [16]. The local
end of the transmission line is represented by a source and the
remote end is modelled as a constant impedance r
2
+jwl
2
. The
fault is modelled as a constant resistance and an ideal switch
S. This switch is closed to simulate the fault at discrete time
k
o
. The fault location is given by 0 x 1 and x=1-x.
In an interconnected power system with several supply
sources the fault currents may have an unidirectional compo-
nent dened by various time constants. However, the addressed
fault parameter effects in accordance with the circuit showed
in Fig. 2 can be extended to circuits with more supply points.
Fig. 2. Single-phase short distance fault line model.
The impedance Z denotes the equivalent impedance of the
circuit before fault inception with modulus and phase given
by:
|Z| =

(R + r
2
)
2
+ w
2
(L + l
2
)
2
, (1)
= tg
1
w(L + l
2
)
R + r
2
. (2)
For ease of description, the switch will be closed on sample
k=k
o
and the voltage phase angle is set to be +
o
. The
local voltage v
A
(k) is represented by a sinusoidal function, as
follows:
v
A
(k) = V
A
sin

w(k k
o
)
f
s
+
o
+

. (3)
Before fault inception (k < k
o
), the switch is opened and
the current in steady-state normal system operation is given
by:
i
A
(k) =
V
A
|Z|
sin

w(k k
o
)
f
s
+
o

. (4)
Fig. 3 depicts the equivalent circuit after fault inception (k
k
o
). The impedance Z
f
=R
f
(r)+jwL
f
(r) is a function of the
fault resistance r as follows:
|Z
f
| =

R
f
(r)
2
+ w
2
L
f
(r)
2
, (5)

f
= tg
1
wL
f
(r)
R
f
(r)
, (6)
where
R
f
(r) = xR + r
r + r
2
+ xR
(r + r
2
+ xR)
2
+ w
2
(l
2
+ xL)
2
r
2
, (7)
L
f
(r) = xL +
(l
2
+ xL)
(r + r
2
+ xR)
2
+ w
2
(l
2
+ xL)
2
r
2
. (8)
The time constante of the system is now:

f
=
L
f
(r)
R
f
(r)
, (9)
Fig. 3. Equivalent circuit after fault inception.
Neglecting all harmonic components and fault-induced
noises, the current at local end after fault inception (k k
o
)
might be expressed by two components: alternating (ac) and
unidirectional (dc), as follows:
i
A
(k) = i
ac
(k) + i
dc
(k), (10)
i
ac
(k) =
V
A
|Z
f
|
sin

w(k k
o
)
f
s
+
o
+
f

, (11)
i
dc
(k) = I
o
e

(kko)
f
s

f
, (12)
where f
s
is the sampling rate and I
o
is the dc offset value at
fault inception (I
o
=i
dc
(k
o
)), expressed as follows:
3
I
o
=
V
A
|Z|
sin(
o
)
V
A
|Z
f
|
sin(
o
+
f
). (13)
The rst term of Eq. (10) is related to a new steady-state
operation after fault inception. The second term is nonperi-
odic and decays exponentially with a time constant
f
. This
nonperiodic term is called dc offset.
Rearranging the Eq. (13), yields:
I
o
= V
A
|Z Z
f
|
|Z|.|Z
f
|
sin(
o
), (14)
where
= tan
1

|Z|sin(
f
)
|Z
f
| |Z|cos(
f
)

. (15)
According to Eqs. (12) and (13), the dc offset depends
of various parameters: fault location (x.R and x.L), system
loading (r
2
and l
2
), fault resistance (r) and the fault inception
angle (
o
). The effects of these parameters on dc offset will
be addressed in the further subsections.
In order to demonstrate the fault parameter effects, two test
cases based on the circuit depicted in Fig. 2 are used. The
sampling rate is f
s
=15360 Hz and the fundamental frequency
is f=60 Hz. In this way, one cycle of power-frequency k
has 256 samples. The rated voltage is V
1
=120 V; the load
impedance parameters are: r
2
= 50 and l
2
= 150mH. Two
different transmission line parameters are used, as follows:
1) Circuit 1: R = 2 and L = 66.66mH.
2) Circuit 2: R = 2 and L = 20mH.
The switch S is initially opened. After two cycles, the
switch is closed. The total simulation time was set to be 8
cycles. All of the simulation were performed by MATLAB

according to the dened equations in this section.

A. Fault Inception Angle Effects
In order to identify the fault inception effects on decaying
dc current the fault resistance was neglected (r=0) and the
fault was applied at middle of the transmission line (x=0.5).
These parameters will be dealt with in the remainder of this
paper.
Disregarding the fault resistance, some equations are sim-
plied, as follows:
lim
r0
R
f
(r) = xR (16)
lim
r0
L
f
(r) = xL. (17)
In this way,
|Z
f
| = x

R
2
+ w
2
L
2
, (18)

f
= tg
1
wL
R
, (19)

f
=
L
R
, (20)
The circuit parameter values of each conguration are:
1) Circuit 1:
xR = 1, r
2
= 50, r = 0, xL = 33.33mH, l
2
=
150mH, |Z| = 96.83, = 57.52
o
, |Z
f
| = 12.60,

f
= 85.45
o
,
f
= 33.33ms (2 cycles).
2) Circuit 2:
xR = 1, r
2
= 50, r = 0, xL = 10mH, l
2
=
150mH, |Z| = 82.53, = 50.94
o
, |Z
f
| = 3.90,

f
= 75.14
o
,
f
= 10.00ms.
After two cycles of steady-state simulation (2k = 512
samples), the switch was closed on k
o
= 2k. The time in
this point was set to be the reference. In this way,
o
indicates
the fault inception angle on the current. According to Eqs. 4
and 10, the current related to each conguration with the fault
inception angle
o
= 0
o
is the follows
1
:
1) Circuit 1:
i
A
(k) =

1.2sin(1.4(k k
o
)) , if k < k
o
9.5sin(1.4(k k
o
) 27.9
o
) + 4.46e
kok
511.9
2) Circuit 2:
i
A
(k) =

1.5sin(1.4(k k
o
)) , if k < k
o
30.8sin(1.4(k k
o
) 24.2
o
) + 12.61e
k
o
k
153.6
According to the previous considerations, the dc offset
depends of the fault inception angle. Fig. 4 depicts the fault
currents for each circuit with
o
= 0
o
. In fact, the effects of
the decaying dc current could be seen on the current in both
analyzed circuit 1 and 2.
Fig. 4. Fault current with fault inception angle
o
=0
o
and zero fault
resistance: a) circuit 1; b) circuit 2.
According to the fault parameters, a fault in a generic circuit
may produce a current without dc offset (I
o
=0). From Eq. 14,
I
o
=0 whether:

o
= n, (21)
with n={0,1,2,...}. For instance, the decaying dc current in the
assessed circuits is null if n=0. In this way:
1) Circuit 1:
o
=31.87
o
.
2) Circuit 2:
o
=25.36
o
.
Fig. 5 depicts the fault currents for both circuit 1 and 2 with
fault inception angle
o
=31.87
o
and
o
=25.36
o
, respectively.
In fact, there is no decaying dc offset for these phase current
angles.
1
P.S.: Phase angles of all trigonometric functions in this paper are in degree.
In this way, w(k k
o
)/f
s
rad = (k k
o
)/128 rad = 1.4(k k
o
) degree.
4
Fig. 5. Fault current without DC offset: a) circuit 1; b) circuit 2.
The decaying dc current is maximum in circuit 1 and
2 when the fault inception angle is
o
=31.87
o
+90
o
and

o
=25.36
o
+90
o
, respectively. The voltage and current related
to circuit 1 and 2 congurations with fault inception angle of

o
=121.87
o
and
o
=115.36
o
, respectively, are the follows:
1) Circuit 1:
v
A
(k) = 120sin(1.4(k k
o
) + 179.39
o
),
i
A
(k) =

1.2sin(1.4(k k
o
) + 121.87
o
) , if k < k
o
9.5sin(1.4(k k
o
) + 93.94
o
) 8.44e
kok
511.9
2) Circuit 2:
v
A
(k) = 120sin(1.4(k k
o
) + 166.30
o
),
i
A
(k) =

1.5sin(1.4(k k
o
) + 115.36
o
) , if k < k
o
30.8sin(1.4(k k
o
) 91.16
o
) 29.45e
kok
153.6
Fig. 6 depicts the voltage and the fault current of the
circuit 1, with the fault inception angle
o
=121.87
o
. These
signals related to circuit 2 regarding
o
=115.36
o
are depicted
in Fig. 7. The maximum dc offset magnitude occurs in a
specic fault inception angle according to system parameters
and fault resistance and location. In the used model (Fig. 2),
the maximum dc offset does not occur on maximum voltage
(Figs. 6 and 7).
Fig. 8 depicts the decaying dc currents of the circuit 1 with

o
=0
o
(Fig. 4 (a)) and
o
=121.87
o
(Fig. 6 (a)).
Fig. 6. Signals regarding to a fault inception angle in circuit 1 that results
in maximum DC offset: a) voltage; b) fault current.
Fig. 7. Signals regarding to a fault inception angle in circuit 1 that results
in maximum DC offset: a) voltage; b) fault current.
Fig. 8. Decaying dc current of the circuit 1 relate to the fault inception
angle: a) o=0
o
; b) o=121.87
o
.
The decaying dc time constant (
f
) dened in Eq. 9 is a
constant according to the fault inception angle. Considering a
xed current sample k
x
, the component e
(k
x
k
o
)/f
s

f
from
Eq. (12) is a constant and the dc offset is in accordance with
the fault inception angle as follows:
i
dc
(
o
) = C
1
sin(
o
), (22)
where
C
1
= V
|Z Z
f
|
|Z|.|Z
f
|
e
(k
x
k
o
)/f
s

f
. (23)
With regard to circuit 1, three distinctive samples were
evaluated to investigate the fault inception angle effects on
the decaying dc current: k
x
= {k
o
, k
o
+k/2, k
o
+k}. The
dc offset for each evaluated instant is the follows:
i
dc
(
o
) = 5.0sin(
o
31.87
o
), for k
x
= k
o
.
i
dc
(
o
) = 3.9sin(
o
31.87
o
), for k
x
= k
o
+k/2.
i
dc
(
o
) = 3.0sin(
o
31.87
o
), for k
x
= k
o
+k.
Fig. 9 depicts the fault inception angle effects on dc offset
of the fault current for those distinctive samples after fault
inception according to the previous equations.
The dc offset magnitude of the fault current with both xed
system and constant fault impedance is affected by the fault
inception angle according to a sinusoidal function. On the
other hand, decaying dc time constant is not affected by fault
inception angle.
5
Fig. 9. Fault inception angle effects on decaying DC component.
In order to evaluate the fault inception angle effects on CT
saturation and fault diagnostic method, only the angles laying
on the range 0
o
to 180
o
are necessary. In fact, the angle values

o
and
o
+180
o
provide the same effects with decaying dc in
opposite directions.
B. Fault Resistance Effects
In order to quantify the inuence of the fault resistance on
dc offset, the fault resistance values laying on the range 0 to
1k were investigate. For ease of description, the fault was
applied at middle of the transmission line (x=0.5).
Fig. 10 depicts the decaying dc time constant
f
as a
function of the fault resistance for both circuit 1 and 2, with

o
=0
o
. Under low fault resistance inuence,
f
is almost
constant and depends of the system conguration and fault
location. However, for increasing of the fault resistance the
decaying dc time constant is noticeably affected. The decaying
dc time constant is very fast (almost zero) for high fault
impedances without circuit conguration distinction.
Fig. 10. Fault resistance effects on decaying dc time constant.
Fig. 11 depicts the decaying dc magnitude as a function
of the fault resistance for some fault inception angles. The
dc offset values were computed at the fault inception instant
(k=k
o
i
dc
(k
o
)=I
0
).
Fig. 11. Fault resistance effects on dc offset: (a) circuit 1; (b) circuit 2.
According to Fig. 11, the dc offset magnitude is almost
constant for low fault resistance and their values depend of the
fault inception angle, fault location, and system conguration.
On the other hand, the dc offset magnitude tends to zero for
high fault resistance.
With regard to circuit 1, as aforementioned,
o
=31.87
o
de-
notes the fault inception angle in which the dc offset is null for
zero fault resistance. As a matter of fact, I
o
0 on low fault
resistances for this angle (Fig. 11(a)). However, increasing
fault resistance the dc offset values increase and after decrease
to zero. On the other side,
o
=121.87
o
=90
o
+31.87
o
denotes
the fault inception angle in which the decaying dc component
is maximum for zero fault resistance (Fig. 9). In this case, I
o
value decreases for increasing of fault resistance (Fig. 11(a)).
Similar features can be seen in Fig. 11(b), but the high fault
resistance region ranges with the system conguration.
Fig. 12 depicts the fault resistance effects on the fault
current of the circuit 1 with
o
=121.87
o
, applied on the middle
of the line with various fault resistances (r=1, 10 and 100
). The decaying dc components of these fault currents are
depicted in Fig. 13.
The fault resistance noticeably affects the dc offset magni-
tude and decaying dc time constant. The increasing of the fault
resistance damps the dc component effects. According to Fig.
9, the dc offset in the circuit 1 is maximum for
o
=121.87
o
.
However, for this phase angle the dc offset is vary damping
for r=100 with fault located on the middle of the line.
Fig. 12. Fault current of the circuit 1 with fault inception angle
o
=121.87
o
,
applied on the middle of the line with fault resistance of: (a) 1; (b) 10;
c) 100.
Fig. 13. Decaying dc current of the circuit 1 with fault inception angle

o
=121.87
o
, applied on the middle of the line with various fault resistances.
With regard to circuit 1, as aforementioned,
o
=121.87
o
denotes the fault inception angle in which the dc offset
magnitude is maximum for zero fault resistance. However,
increasing the fault resistance value the dc offset magnitude
will present its maximum value at another fault inception
angle. Fig. 14 depicts the fault inception angle versus the
fault resistance in order to produce the maximum dc offset
magnitude in both circuit 1 and 2.
6
Fig. 14. Fault inception angle at the current to produces the maximum dc
offset according to fault resistance.
According to Fig. 14, the point on current waveform in
which the hardest dc offset occurs changes with the fault
resistance. Analogous results can be expected in the voltage.
Fig. 15 shows the frequency analysis of two decaying
dc components according to the fault resistances r=1 and
r=10. The noticeable frequency components lie on the
low frequency spectrum and the respective modulus are in
accordance to the fault resistance.
Fig. 15. Frequency analysis of the decaying dc current of the circuit 1 with
fault inception angle
o
=121.87
o
, applied on the middle of the line with fault
resistance: (a) 1; (b) 10.
C. Fault Location Effects
In order to quantify the inuence of the fault location on
dc offset, short-circuits were applied from 10% of the line
length near the source until the line remote end. In other words,
0.1 x 1.0.
Fig. 16 depicts the dc offset values of the circuit 1 as a
function of the fault location for some fault resistances and

o
=121.87
o
. The current values were computed at the fault
inception instant k=k
o
i
T
(k
o
)=I
0
.
Fig. 16. Fault location effects on transient current of the circuit 1.
According to Fig. 16, the dc offset is damped with the
increasing of the fault location. The decaying dc component is
hardly affected with faults located near the monitoring point.
IV. CONCLUSIONS
Considering both xed system and constant fault im-
pedance, the dc offset magnitude of a fault current is affected
by the fault inception angle according to a sinusoidal function.
On the other hand, decaying dc time constant is not affected
by the fault inception angle.
Under low fault resistance inuence, the decaying dc time
constant depends of both the system conguration and the fault
location. In this situation, the dc offset magnitude depends
of the system conguration, fault location and fault inception
angle. On the other hand, under high fault impedances, the
decaying dc time constant is very fast and the dc offset
magnitude is very damped. In addition, The point on voltage
and current waveforms in which the hardest dc offset occurs
changes with the fault resistance.
The inuence of fault location was also quantied. The dc
offset is damped with fault located from away of monitoring
point. On the other hand, the decaying dc component is hardly
affected with fault located near the monitoring point.
The frequency analysis of the decaying dc components
states that the noticeable frequency components lie on the low
frequency spectrum.
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